sdhci_pci.c revision 318495
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci_pci.c 318495 2017-05-18 20:46:27Z marius $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/kernel.h> 33#include <sys/lock.h> 34#include <sys/module.h> 35#include <sys/mutex.h> 36#include <sys/resource.h> 37#include <sys/rman.h> 38#include <sys/sysctl.h> 39#include <sys/taskqueue.h> 40 41#include <dev/pci/pcireg.h> 42#include <dev/pci/pcivar.h> 43 44#include <machine/bus.h> 45#include <machine/resource.h> 46 47#include <dev/mmc/bridge.h> 48 49#include <dev/sdhci/sdhci.h> 50 51#include "mmcbr_if.h" 52#include "sdhci_if.h" 53 54/* 55 * PCI registers 56 */ 57#define PCI_SDHCI_IFPIO 0x00 58#define PCI_SDHCI_IFDMA 0x01 59#define PCI_SDHCI_IFVENDOR 0x02 60 61#define PCI_SLOT_INFO 0x40 /* 8 bits */ 62#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 63#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 64 65/* 66 * RICOH specific PCI registers 67 */ 68#define SDHC_PCI_MODE_KEY 0xf9 69#define SDHC_PCI_MODE 0x150 70#define SDHC_PCI_MODE_SD20 0x10 71#define SDHC_PCI_BASE_FREQ_KEY 0xfc 72#define SDHC_PCI_BASE_FREQ 0xe1 73 74static const struct sdhci_device { 75 uint32_t model; 76 uint16_t subvendor; 77 const char *desc; 78 u_int quirks; 79} sdhci_devices[] = { 80 { 0x08221180, 0xffff, "RICOH R5C822 SD", 81 SDHCI_QUIRK_FORCE_DMA }, 82 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 83 SDHCI_QUIRK_FORCE_DMA | 84 SDHCI_QUIRK_LOWER_FREQUENCY }, 85 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 86 SDHCI_QUIRK_LOWER_FREQUENCY }, 87 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 88 SDHCI_QUIRK_FORCE_DMA }, 89 { 0x05501524, 0xffff, "ENE CB712 SD", 90 SDHCI_QUIRK_BROKEN_TIMINGS }, 91 { 0x05511524, 0xffff, "ENE CB712 SD 2", 92 SDHCI_QUIRK_BROKEN_TIMINGS }, 93 { 0x07501524, 0xffff, "ENE CB714 SD", 94 SDHCI_QUIRK_RESET_ON_IOS | 95 SDHCI_QUIRK_BROKEN_TIMINGS }, 96 { 0x07511524, 0xffff, "ENE CB714 SD 2", 97 SDHCI_QUIRK_RESET_ON_IOS | 98 SDHCI_QUIRK_BROKEN_TIMINGS }, 99 { 0x410111ab, 0xffff, "Marvell CaFe SD", 100 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 101 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 102 SDHCI_QUIRK_32BIT_DMA_SIZE | 103 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 104 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 105 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 106 { 0x0f148086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 107 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 108 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 109 SDHCI_QUIRK_WAIT_WHILE_BUSY | 110 SDHCI_QUIRK_MMC_DDR52 | 111 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 112 SDHCI_QUIRK_PRESET_VALUE_BROKEN}, 113 { 0x0f158086, 0xffff, "Intel Bay Trail SDXC Controller", 114 SDHCI_QUIRK_WAIT_WHILE_BUSY | 115 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 116 { 0x0f508086, 0xffff, "Intel Bay Trail eMMC 4.5 Controller", 117 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 118 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 119 SDHCI_QUIRK_WAIT_WHILE_BUSY | 120 SDHCI_QUIRK_MMC_DDR52 | 121 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 122 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 123 { 0x22948086, 0xffff, "Intel Braswell eMMC 4.5.1 Controller", 124 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 125 SDHCI_QUIRK_DATA_TIMEOUT_1MHZ | 126 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 127 SDHCI_QUIRK_WAIT_WHILE_BUSY | 128 SDHCI_QUIRK_MMC_DDR52 | 129 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 130 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 131 { 0x22968086, 0xffff, "Intel Braswell SDXC Controller", 132 SDHCI_QUIRK_WAIT_WHILE_BUSY | 133 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 134 { 0x5aca8086, 0xffff, "Intel Apollo Lake SDXC Controller", 135 SDHCI_QUIRK_WAIT_WHILE_BUSY | 136 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 137 { 0x5acc8086, 0xffff, "Intel Apollo Lake eMMC 5.0 Controller", 138 SDHCI_QUIRK_ALL_SLOTS_NON_REMOVABLE | 139 SDHCI_QUIRK_INTEL_POWER_UP_RESET | 140 SDHCI_QUIRK_WAIT_WHILE_BUSY | 141 SDHCI_QUIRK_MMC_DDR52 | 142 SDHCI_QUIRK_CAPS_BIT63_FOR_MMC_HS400 | 143 SDHCI_QUIRK_PRESET_VALUE_BROKEN }, 144 { 0, 0xffff, NULL, 145 0 } 146}; 147 148struct sdhci_pci_softc { 149 u_int quirks; /* Chip specific quirks */ 150 struct resource *irq_res; /* IRQ resource */ 151 void *intrhand; /* Interrupt handle */ 152 153 int num_slots; /* Number of slots on this controller */ 154 struct sdhci_slot slots[6]; 155 struct resource *mem_res[6]; /* Memory resource */ 156 uint8_t cfg_freq; /* Saved frequency */ 157 uint8_t cfg_mode; /* Saved mode */ 158}; 159 160static int sdhci_enable_msi = 1; 161TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi); 162SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 163 0, "Enable MSI interrupts"); 164 165static uint8_t 166sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 167{ 168 struct sdhci_pci_softc *sc = device_get_softc(dev); 169 170 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 171 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 172 return bus_read_1(sc->mem_res[slot->num], off); 173} 174 175static void 176sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot __unused, 177 bus_size_t off, uint8_t val) 178{ 179 struct sdhci_pci_softc *sc = device_get_softc(dev); 180 181 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 182 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 183 bus_write_1(sc->mem_res[slot->num], off, val); 184} 185 186static uint16_t 187sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 188{ 189 struct sdhci_pci_softc *sc = device_get_softc(dev); 190 191 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 192 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 193 return bus_read_2(sc->mem_res[slot->num], off); 194} 195 196static void 197sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot __unused, 198 bus_size_t off, uint16_t val) 199{ 200 struct sdhci_pci_softc *sc = device_get_softc(dev); 201 202 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 203 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 204 bus_write_2(sc->mem_res[slot->num], off, val); 205} 206 207static uint32_t 208sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot __unused, bus_size_t off) 209{ 210 struct sdhci_pci_softc *sc = device_get_softc(dev); 211 212 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 213 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 214 return bus_read_4(sc->mem_res[slot->num], off); 215} 216 217static void 218sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot __unused, 219 bus_size_t off, uint32_t val) 220{ 221 struct sdhci_pci_softc *sc = device_get_softc(dev); 222 223 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 224 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 225 bus_write_4(sc->mem_res[slot->num], off, val); 226} 227 228static void 229sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot __unused, 230 bus_size_t off, uint32_t *data, bus_size_t count) 231{ 232 struct sdhci_pci_softc *sc = device_get_softc(dev); 233 234 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 235} 236 237static void 238sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot __unused, 239 bus_size_t off, uint32_t *data, bus_size_t count) 240{ 241 struct sdhci_pci_softc *sc = device_get_softc(dev); 242 243 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 244} 245 246static void sdhci_pci_intr(void *arg); 247 248static void 249sdhci_lower_frequency(device_t dev) 250{ 251 struct sdhci_pci_softc *sc = device_get_softc(dev); 252 253 /* 254 * Enable SD2.0 mode. 255 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 256 */ 257 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 258 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 259 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 260 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 261 262 /* 263 * Some SD/MMC cards don't work with the default base 264 * clock frequency of 200 MHz. Lower it to 50 MHz. 265 */ 266 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 267 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 268 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 269 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 270} 271 272static void 273sdhci_restore_frequency(device_t dev) 274{ 275 struct sdhci_pci_softc *sc = device_get_softc(dev); 276 277 /* Restore mode. */ 278 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 279 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 280 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 281 282 /* Restore frequency. */ 283 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 284 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 285 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 286} 287 288static int 289sdhci_pci_probe(device_t dev) 290{ 291 uint32_t model; 292 uint16_t subvendor; 293 uint8_t class, subclass; 294 int i, result; 295 296 model = (uint32_t)pci_get_device(dev) << 16; 297 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 298 subvendor = pci_get_subvendor(dev); 299 class = pci_get_class(dev); 300 subclass = pci_get_subclass(dev); 301 302 result = ENXIO; 303 for (i = 0; sdhci_devices[i].model != 0; i++) { 304 if (sdhci_devices[i].model == model && 305 (sdhci_devices[i].subvendor == 0xffff || 306 sdhci_devices[i].subvendor == subvendor)) { 307 device_set_desc(dev, sdhci_devices[i].desc); 308 result = BUS_PROBE_DEFAULT; 309 break; 310 } 311 } 312 if (result == ENXIO && class == PCIC_BASEPERIPH && 313 subclass == PCIS_BASEPERIPH_SDHC) { 314 device_set_desc(dev, "Generic SD HCI"); 315 result = BUS_PROBE_GENERIC; 316 } 317 318 return (result); 319} 320 321static int 322sdhci_pci_attach(device_t dev) 323{ 324 struct sdhci_pci_softc *sc = device_get_softc(dev); 325 struct sdhci_slot *slot; 326 uint32_t model; 327 uint16_t subvendor; 328 int bar, err, rid, slots, i; 329 330 model = (uint32_t)pci_get_device(dev) << 16; 331 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 332 subvendor = pci_get_subvendor(dev); 333 /* Apply chip specific quirks. */ 334 for (i = 0; sdhci_devices[i].model != 0; i++) { 335 if (sdhci_devices[i].model == model && 336 (sdhci_devices[i].subvendor == 0xffff || 337 sdhci_devices[i].subvendor == subvendor)) { 338 sc->quirks = sdhci_devices[i].quirks; 339 break; 340 } 341 } 342 sc->quirks &= ~sdhci_quirk_clear; 343 sc->quirks |= sdhci_quirk_set; 344 /* Some controllers need to be bumped into the right mode. */ 345 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 346 sdhci_lower_frequency(dev); 347 /* Read slots info from PCI registers. */ 348 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 349 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 350 slots = PCI_SLOT_INFO_SLOTS(slots); 351 if (slots > 6 || bar > 5) { 352 device_printf(dev, "Incorrect slots information (%d, %d).\n", 353 slots, bar); 354 return (EINVAL); 355 } 356 /* Allocate IRQ. */ 357 i = 1; 358 rid = 0; 359 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 360 rid = 1; 361 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 362 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 363 if (sc->irq_res == NULL) { 364 device_printf(dev, "Can't allocate IRQ\n"); 365 pci_release_msi(dev); 366 return (ENOMEM); 367 } 368 /* Scan all slots. */ 369 for (i = 0; i < slots; i++) { 370 slot = &sc->slots[sc->num_slots]; 371 372 /* Allocate memory. */ 373 rid = PCIR_BAR(bar + i); 374 sc->mem_res[i] = bus_alloc_resource_any(dev, SYS_RES_MEMORY, 375 &rid, RF_ACTIVE); 376 if (sc->mem_res[i] == NULL) { 377 device_printf(dev, 378 "Can't allocate memory for slot %d\n", i); 379 continue; 380 } 381 382 slot->quirks = sc->quirks; 383 384 if (sdhci_init_slot(dev, slot, i) != 0) 385 continue; 386 387 sc->num_slots++; 388 } 389 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 390 /* Activate the interrupt */ 391 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 392 NULL, sdhci_pci_intr, sc, &sc->intrhand); 393 if (err) 394 device_printf(dev, "Can't setup IRQ\n"); 395 pci_enable_busmaster(dev); 396 /* Process cards detection. */ 397 for (i = 0; i < sc->num_slots; i++) 398 sdhci_start_slot(&sc->slots[i]); 399 400 return (0); 401} 402 403static int 404sdhci_pci_detach(device_t dev) 405{ 406 struct sdhci_pci_softc *sc = device_get_softc(dev); 407 int i; 408 409 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 410 bus_release_resource(dev, SYS_RES_IRQ, 411 rman_get_rid(sc->irq_res), sc->irq_res); 412 pci_release_msi(dev); 413 414 for (i = 0; i < sc->num_slots; i++) { 415 sdhci_cleanup_slot(&sc->slots[i]); 416 bus_release_resource(dev, SYS_RES_MEMORY, 417 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 418 } 419 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 420 sdhci_restore_frequency(dev); 421 return (0); 422} 423 424static int 425sdhci_pci_shutdown(device_t dev) 426{ 427 struct sdhci_pci_softc *sc = device_get_softc(dev); 428 429 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 430 sdhci_restore_frequency(dev); 431 return (0); 432} 433 434static int 435sdhci_pci_suspend(device_t dev) 436{ 437 struct sdhci_pci_softc *sc = device_get_softc(dev); 438 int i, err; 439 440 err = bus_generic_suspend(dev); 441 if (err) 442 return (err); 443 for (i = 0; i < sc->num_slots; i++) 444 sdhci_generic_suspend(&sc->slots[i]); 445 return (0); 446} 447 448static int 449sdhci_pci_resume(device_t dev) 450{ 451 struct sdhci_pci_softc *sc = device_get_softc(dev); 452 int i, err; 453 454 for (i = 0; i < sc->num_slots; i++) 455 sdhci_generic_resume(&sc->slots[i]); 456 err = bus_generic_resume(dev); 457 if (err) 458 return (err); 459 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 460 sdhci_lower_frequency(dev); 461 return (0); 462} 463 464static void 465sdhci_pci_intr(void *arg) 466{ 467 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 468 int i; 469 470 for (i = 0; i < sc->num_slots; i++) 471 sdhci_generic_intr(&sc->slots[i]); 472} 473 474static device_method_t sdhci_methods[] = { 475 /* device_if */ 476 DEVMETHOD(device_probe, sdhci_pci_probe), 477 DEVMETHOD(device_attach, sdhci_pci_attach), 478 DEVMETHOD(device_detach, sdhci_pci_detach), 479 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 480 DEVMETHOD(device_suspend, sdhci_pci_suspend), 481 DEVMETHOD(device_resume, sdhci_pci_resume), 482 483 /* Bus interface */ 484 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 485 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 486 487 /* mmcbr_if */ 488 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 489 DEVMETHOD(mmcbr_switch_vccq, sdhci_generic_switch_vccq), 490 DEVMETHOD(mmcbr_request, sdhci_generic_request), 491 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 492 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 493 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 494 495 /* SDHCI accessors */ 496 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 497 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 498 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 499 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 500 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 501 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 502 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 503 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 504 DEVMETHOD(sdhci_set_uhs_timing, sdhci_generic_set_uhs_timing), 505 506 DEVMETHOD_END 507}; 508 509static driver_t sdhci_pci_driver = { 510 "sdhci_pci", 511 sdhci_methods, 512 sizeof(struct sdhci_pci_softc), 513}; 514static devclass_t sdhci_pci_devclass; 515 516DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 517 NULL); 518MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 519MMC_DECLARE_BRIDGE(sdhci_pci); 520