sdhci_pci.c revision 312245
1/*- 2 * Copyright (c) 2008 Alexander Motin <mav@FreeBSD.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 15 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 16 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 17 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 18 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 19 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 20 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 21 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 22 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 23 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 24 */ 25 26#include <sys/cdefs.h> 27__FBSDID("$FreeBSD: stable/10/sys/dev/sdhci/sdhci_pci.c 312245 2017-01-15 22:30:59Z ian $"); 28 29#include <sys/param.h> 30#include <sys/systm.h> 31#include <sys/bus.h> 32#include <sys/conf.h> 33#include <sys/kernel.h> 34#include <sys/lock.h> 35#include <sys/module.h> 36#include <sys/mutex.h> 37#include <sys/resource.h> 38#include <sys/rman.h> 39#include <sys/sysctl.h> 40#include <sys/taskqueue.h> 41 42#include <dev/pci/pcireg.h> 43#include <dev/pci/pcivar.h> 44 45#include <machine/bus.h> 46#include <machine/resource.h> 47#include <machine/stdarg.h> 48 49#include <dev/mmc/bridge.h> 50#include <dev/mmc/mmcreg.h> 51#include <dev/mmc/mmcbrvar.h> 52 53#include "sdhci.h" 54#include "mmcbr_if.h" 55#include "sdhci_if.h" 56 57/* 58 * PCI registers 59 */ 60 61#define PCI_SDHCI_IFPIO 0x00 62#define PCI_SDHCI_IFDMA 0x01 63#define PCI_SDHCI_IFVENDOR 0x02 64 65#define PCI_SLOT_INFO 0x40 /* 8 bits */ 66#define PCI_SLOT_INFO_SLOTS(x) (((x >> 4) & 7) + 1) 67#define PCI_SLOT_INFO_FIRST_BAR(x) ((x) & 7) 68 69/* 70 * RICOH specific PCI registers 71 */ 72#define SDHC_PCI_MODE_KEY 0xf9 73#define SDHC_PCI_MODE 0x150 74#define SDHC_PCI_MODE_SD20 0x10 75#define SDHC_PCI_BASE_FREQ_KEY 0xfc 76#define SDHC_PCI_BASE_FREQ 0xe1 77 78static const struct sdhci_device { 79 uint32_t model; 80 uint16_t subvendor; 81 const char *desc; 82 u_int quirks; 83} sdhci_devices[] = { 84 { 0x08221180, 0xffff, "RICOH R5C822 SD", 85 SDHCI_QUIRK_FORCE_DMA }, 86 { 0xe8221180, 0xffff, "RICOH R5CE822 SD", 87 SDHCI_QUIRK_FORCE_DMA | 88 SDHCI_QUIRK_LOWER_FREQUENCY }, 89 { 0xe8231180, 0xffff, "RICOH R5CE823 SD", 90 SDHCI_QUIRK_LOWER_FREQUENCY }, 91 { 0x8034104c, 0xffff, "TI XX21/XX11 SD", 92 SDHCI_QUIRK_FORCE_DMA }, 93 { 0x05501524, 0xffff, "ENE CB712 SD", 94 SDHCI_QUIRK_BROKEN_TIMINGS }, 95 { 0x05511524, 0xffff, "ENE CB712 SD 2", 96 SDHCI_QUIRK_BROKEN_TIMINGS }, 97 { 0x07501524, 0xffff, "ENE CB714 SD", 98 SDHCI_QUIRK_RESET_ON_IOS | 99 SDHCI_QUIRK_BROKEN_TIMINGS }, 100 { 0x07511524, 0xffff, "ENE CB714 SD 2", 101 SDHCI_QUIRK_RESET_ON_IOS | 102 SDHCI_QUIRK_BROKEN_TIMINGS }, 103 { 0x410111ab, 0xffff, "Marvell CaFe SD", 104 SDHCI_QUIRK_INCR_TIMEOUT_CONTROL }, 105 { 0x2381197B, 0xffff, "JMicron JMB38X SD", 106 SDHCI_QUIRK_32BIT_DMA_SIZE | 107 SDHCI_QUIRK_RESET_AFTER_REQUEST }, 108 { 0x16bc14e4, 0xffff, "Broadcom BCM577xx SDXC/MMC Card Reader", 109 SDHCI_QUIRK_BCM577XX_400KHZ_CLKSRC }, 110 { 0, 0xffff, NULL, 111 0 } 112}; 113 114struct sdhci_pci_softc { 115 u_int quirks; /* Chip specific quirks */ 116 struct resource *irq_res; /* IRQ resource */ 117 void *intrhand; /* Interrupt handle */ 118 119 int num_slots; /* Number of slots on this controller */ 120 struct sdhci_slot slots[6]; 121 struct resource *mem_res[6]; /* Memory resource */ 122 uint8_t cfg_freq; /* Saved mode */ 123 uint8_t cfg_mode; /* Saved frequency */ 124}; 125 126static int sdhci_enable_msi = 1; 127TUNABLE_INT("hw.sdhci.enable_msi", &sdhci_enable_msi); 128SYSCTL_INT(_hw_sdhci, OID_AUTO, enable_msi, CTLFLAG_RDTUN, &sdhci_enable_msi, 129 0, "Enable MSI interrupts"); 130 131static uint8_t 132sdhci_pci_read_1(device_t dev, struct sdhci_slot *slot, bus_size_t off) 133{ 134 struct sdhci_pci_softc *sc = device_get_softc(dev); 135 136 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 137 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 138 return bus_read_1(sc->mem_res[slot->num], off); 139} 140 141static void 142sdhci_pci_write_1(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint8_t val) 143{ 144 struct sdhci_pci_softc *sc = device_get_softc(dev); 145 146 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 147 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 148 bus_write_1(sc->mem_res[slot->num], off, val); 149} 150 151static uint16_t 152sdhci_pci_read_2(device_t dev, struct sdhci_slot *slot, bus_size_t off) 153{ 154 struct sdhci_pci_softc *sc = device_get_softc(dev); 155 156 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 157 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 158 return bus_read_2(sc->mem_res[slot->num], off); 159} 160 161static void 162sdhci_pci_write_2(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint16_t val) 163{ 164 struct sdhci_pci_softc *sc = device_get_softc(dev); 165 166 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 167 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 168 bus_write_2(sc->mem_res[slot->num], off, val); 169} 170 171static uint32_t 172sdhci_pci_read_4(device_t dev, struct sdhci_slot *slot, bus_size_t off) 173{ 174 struct sdhci_pci_softc *sc = device_get_softc(dev); 175 176 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 177 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 178 return bus_read_4(sc->mem_res[slot->num], off); 179} 180 181static void 182sdhci_pci_write_4(device_t dev, struct sdhci_slot *slot, bus_size_t off, uint32_t val) 183{ 184 struct sdhci_pci_softc *sc = device_get_softc(dev); 185 186 bus_barrier(sc->mem_res[slot->num], 0, 0xFF, 187 BUS_SPACE_BARRIER_READ | BUS_SPACE_BARRIER_WRITE); 188 bus_write_4(sc->mem_res[slot->num], off, val); 189} 190 191static void 192sdhci_pci_read_multi_4(device_t dev, struct sdhci_slot *slot, 193 bus_size_t off, uint32_t *data, bus_size_t count) 194{ 195 struct sdhci_pci_softc *sc = device_get_softc(dev); 196 197 bus_read_multi_stream_4(sc->mem_res[slot->num], off, data, count); 198} 199 200static void 201sdhci_pci_write_multi_4(device_t dev, struct sdhci_slot *slot, 202 bus_size_t off, uint32_t *data, bus_size_t count) 203{ 204 struct sdhci_pci_softc *sc = device_get_softc(dev); 205 206 bus_write_multi_stream_4(sc->mem_res[slot->num], off, data, count); 207} 208 209static void sdhci_pci_intr(void *arg); 210 211static void 212sdhci_lower_frequency(device_t dev) 213{ 214 struct sdhci_pci_softc *sc = device_get_softc(dev); 215 216 /* 217 * Enable SD2.0 mode. 218 * NB: for RICOH R5CE823, this changes the PCI device ID to 0xe822. 219 */ 220 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 221 sc->cfg_mode = pci_read_config(dev, SDHC_PCI_MODE, 1); 222 pci_write_config(dev, SDHC_PCI_MODE, SDHC_PCI_MODE_SD20, 1); 223 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 224 225 /* 226 * Some SD/MMC cards don't work with the default base 227 * clock frequency of 200 MHz. Lower it to 50 MHz. 228 */ 229 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 230 sc->cfg_freq = pci_read_config(dev, SDHC_PCI_BASE_FREQ, 1); 231 pci_write_config(dev, SDHC_PCI_BASE_FREQ, 50, 1); 232 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 233} 234 235static void 236sdhci_restore_frequency(device_t dev) 237{ 238 struct sdhci_pci_softc *sc = device_get_softc(dev); 239 240 /* Restore mode. */ 241 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0xfc, 1); 242 pci_write_config(dev, SDHC_PCI_MODE, sc->cfg_mode, 1); 243 pci_write_config(dev, SDHC_PCI_MODE_KEY, 0x00, 1); 244 245 /* Restore frequency. */ 246 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x01, 1); 247 pci_write_config(dev, SDHC_PCI_BASE_FREQ, sc->cfg_freq, 1); 248 pci_write_config(dev, SDHC_PCI_BASE_FREQ_KEY, 0x00, 1); 249} 250 251static int 252sdhci_pci_probe(device_t dev) 253{ 254 uint32_t model; 255 uint16_t subvendor; 256 uint8_t class, subclass; 257 int i, result; 258 259 model = (uint32_t)pci_get_device(dev) << 16; 260 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 261 subvendor = pci_get_subvendor(dev); 262 class = pci_get_class(dev); 263 subclass = pci_get_subclass(dev); 264 265 result = ENXIO; 266 for (i = 0; sdhci_devices[i].model != 0; i++) { 267 if (sdhci_devices[i].model == model && 268 (sdhci_devices[i].subvendor == 0xffff || 269 sdhci_devices[i].subvendor == subvendor)) { 270 device_set_desc(dev, sdhci_devices[i].desc); 271 result = BUS_PROBE_DEFAULT; 272 break; 273 } 274 } 275 if (result == ENXIO && class == PCIC_BASEPERIPH && 276 subclass == PCIS_BASEPERIPH_SDHC) { 277 device_set_desc(dev, "Generic SD HCI"); 278 result = BUS_PROBE_GENERIC; 279 } 280 281 return (result); 282} 283 284static int 285sdhci_pci_attach(device_t dev) 286{ 287 struct sdhci_pci_softc *sc = device_get_softc(dev); 288 uint32_t model; 289 uint16_t subvendor; 290 int bar, err, rid, slots, i; 291 292 model = (uint32_t)pci_get_device(dev) << 16; 293 model |= (uint32_t)pci_get_vendor(dev) & 0x0000ffff; 294 subvendor = pci_get_subvendor(dev); 295 /* Apply chip specific quirks. */ 296 for (i = 0; sdhci_devices[i].model != 0; i++) { 297 if (sdhci_devices[i].model == model && 298 (sdhci_devices[i].subvendor == 0xffff || 299 sdhci_devices[i].subvendor == subvendor)) { 300 sc->quirks = sdhci_devices[i].quirks; 301 break; 302 } 303 } 304 /* Some controllers need to be bumped into the right mode. */ 305 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 306 sdhci_lower_frequency(dev); 307 /* Read slots info from PCI registers. */ 308 slots = pci_read_config(dev, PCI_SLOT_INFO, 1); 309 bar = PCI_SLOT_INFO_FIRST_BAR(slots); 310 slots = PCI_SLOT_INFO_SLOTS(slots); 311 if (slots > 6 || bar > 5) { 312 device_printf(dev, "Incorrect slots information (%d, %d).\n", 313 slots, bar); 314 return (EINVAL); 315 } 316 /* Allocate IRQ. */ 317 i = 1; 318 rid = 0; 319 if (sdhci_enable_msi != 0 && pci_alloc_msi(dev, &i) == 0) 320 rid = 1; 321 sc->irq_res = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 322 RF_ACTIVE | (rid != 0 ? 0 : RF_SHAREABLE)); 323 if (sc->irq_res == NULL) { 324 device_printf(dev, "Can't allocate IRQ\n"); 325 pci_release_msi(dev); 326 return (ENOMEM); 327 } 328 /* Scan all slots. */ 329 for (i = 0; i < slots; i++) { 330 struct sdhci_slot *slot = &sc->slots[sc->num_slots]; 331 332 /* Allocate memory. */ 333 rid = PCIR_BAR(bar + i); 334 sc->mem_res[i] = bus_alloc_resource(dev, SYS_RES_MEMORY, 335 &rid, 0ul, ~0ul, 0x100, RF_ACTIVE); 336 if (sc->mem_res[i] == NULL) { 337 device_printf(dev, "Can't allocate memory for slot %d\n", i); 338 continue; 339 } 340 341 slot->quirks = sc->quirks; 342 343 if (sdhci_init_slot(dev, slot, i) != 0) 344 continue; 345 346 sc->num_slots++; 347 } 348 device_printf(dev, "%d slot(s) allocated\n", sc->num_slots); 349 /* Activate the interrupt */ 350 err = bus_setup_intr(dev, sc->irq_res, INTR_TYPE_MISC | INTR_MPSAFE, 351 NULL, sdhci_pci_intr, sc, &sc->intrhand); 352 if (err) 353 device_printf(dev, "Can't setup IRQ\n"); 354 pci_enable_busmaster(dev); 355 /* Process cards detection. */ 356 for (i = 0; i < sc->num_slots; i++) { 357 struct sdhci_slot *slot = &sc->slots[i]; 358 359 sdhci_start_slot(slot); 360 } 361 362 return (0); 363} 364 365static int 366sdhci_pci_detach(device_t dev) 367{ 368 struct sdhci_pci_softc *sc = device_get_softc(dev); 369 int i; 370 371 bus_teardown_intr(dev, sc->irq_res, sc->intrhand); 372 bus_release_resource(dev, SYS_RES_IRQ, 373 rman_get_rid(sc->irq_res), sc->irq_res); 374 pci_release_msi(dev); 375 376 for (i = 0; i < sc->num_slots; i++) { 377 struct sdhci_slot *slot = &sc->slots[i]; 378 379 sdhci_cleanup_slot(slot); 380 bus_release_resource(dev, SYS_RES_MEMORY, 381 rman_get_rid(sc->mem_res[i]), sc->mem_res[i]); 382 } 383 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 384 sdhci_restore_frequency(dev); 385 return (0); 386} 387 388static int 389sdhci_pci_shutdown(device_t dev) 390{ 391 struct sdhci_pci_softc *sc = device_get_softc(dev); 392 393 if (sc->quirks & SDHCI_QUIRK_LOWER_FREQUENCY) 394 sdhci_restore_frequency(dev); 395 return (0); 396} 397 398static int 399sdhci_pci_suspend(device_t dev) 400{ 401 struct sdhci_pci_softc *sc = device_get_softc(dev); 402 int i, err; 403 404 err = bus_generic_suspend(dev); 405 if (err) 406 return (err); 407 for (i = 0; i < sc->num_slots; i++) 408 sdhci_generic_suspend(&sc->slots[i]); 409 return (0); 410} 411 412static int 413sdhci_pci_resume(device_t dev) 414{ 415 struct sdhci_pci_softc *sc = device_get_softc(dev); 416 int i; 417 418 for (i = 0; i < sc->num_slots; i++) 419 sdhci_generic_resume(&sc->slots[i]); 420 return (bus_generic_resume(dev)); 421} 422 423static void 424sdhci_pci_intr(void *arg) 425{ 426 struct sdhci_pci_softc *sc = (struct sdhci_pci_softc *)arg; 427 int i; 428 429 for (i = 0; i < sc->num_slots; i++) { 430 struct sdhci_slot *slot = &sc->slots[i]; 431 sdhci_generic_intr(slot); 432 } 433} 434 435static device_method_t sdhci_methods[] = { 436 /* device_if */ 437 DEVMETHOD(device_probe, sdhci_pci_probe), 438 DEVMETHOD(device_attach, sdhci_pci_attach), 439 DEVMETHOD(device_detach, sdhci_pci_detach), 440 DEVMETHOD(device_shutdown, sdhci_pci_shutdown), 441 DEVMETHOD(device_suspend, sdhci_pci_suspend), 442 DEVMETHOD(device_resume, sdhci_pci_resume), 443 444 /* Bus interface */ 445 DEVMETHOD(bus_read_ivar, sdhci_generic_read_ivar), 446 DEVMETHOD(bus_write_ivar, sdhci_generic_write_ivar), 447 448 /* mmcbr_if */ 449 DEVMETHOD(mmcbr_update_ios, sdhci_generic_update_ios), 450 DEVMETHOD(mmcbr_request, sdhci_generic_request), 451 DEVMETHOD(mmcbr_get_ro, sdhci_generic_get_ro), 452 DEVMETHOD(mmcbr_acquire_host, sdhci_generic_acquire_host), 453 DEVMETHOD(mmcbr_release_host, sdhci_generic_release_host), 454 455 /* SDHCI registers accessors */ 456 DEVMETHOD(sdhci_read_1, sdhci_pci_read_1), 457 DEVMETHOD(sdhci_read_2, sdhci_pci_read_2), 458 DEVMETHOD(sdhci_read_4, sdhci_pci_read_4), 459 DEVMETHOD(sdhci_read_multi_4, sdhci_pci_read_multi_4), 460 DEVMETHOD(sdhci_write_1, sdhci_pci_write_1), 461 DEVMETHOD(sdhci_write_2, sdhci_pci_write_2), 462 DEVMETHOD(sdhci_write_4, sdhci_pci_write_4), 463 DEVMETHOD(sdhci_write_multi_4, sdhci_pci_write_multi_4), 464 465 DEVMETHOD_END 466}; 467 468static driver_t sdhci_pci_driver = { 469 "sdhci_pci", 470 sdhci_methods, 471 sizeof(struct sdhci_pci_softc), 472}; 473static devclass_t sdhci_pci_devclass; 474 475DRIVER_MODULE(sdhci_pci, pci, sdhci_pci_driver, sdhci_pci_devclass, NULL, 476 NULL); 477MODULE_DEPEND(sdhci_pci, sdhci, 1, 1, 1); 478