1117845Ssam/*- 2117845Ssam * Copyright (c) 2003 Sam Leffler, Errno Consulting 3117845Ssam * Copyright (c) 2003 Global Technology Associates, Inc. 4117845Ssam * All rights reserved. 5117845Ssam * 6117845Ssam * Redistribution and use in source and binary forms, with or without 7117845Ssam * modification, are permitted provided that the following conditions 8117845Ssam * are met: 9117845Ssam * 1. Redistributions of source code must retain the above copyright 10117845Ssam * notice, this list of conditions and the following disclaimer. 11117845Ssam * 2. Redistributions in binary form must reproduce the above copyright 12117845Ssam * notice, this list of conditions and the following disclaimer in the 13117845Ssam * documentation and/or other materials provided with the distribution. 14117845Ssam * 15117845Ssam * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16117845Ssam * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17117845Ssam * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18117845Ssam * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19117845Ssam * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20117845Ssam * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21117845Ssam * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22117845Ssam * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23117845Ssam * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24117845Ssam * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25117845Ssam * SUCH DAMAGE. 26117845Ssam * 27117845Ssam * $FreeBSD$ 28117845Ssam */ 29117845Ssam#ifndef _SAFE_SAFEVAR_H_ 30117845Ssam#define _SAFE_SAFEVAR_H_ 31117845Ssam 32117845Ssam/* Maximum queue length */ 33117845Ssam#ifndef SAFE_MAX_NQUEUE 34117845Ssam#define SAFE_MAX_NQUEUE 60 35117845Ssam#endif 36117845Ssam 37117845Ssam#define SAFE_MAX_PART 64 /* Maximum scatter/gather depth */ 38117845Ssam#define SAFE_DMA_BOUNDARY 0 /* No boundary for source DMA ops */ 39117845Ssam#define SAFE_MAX_DSIZE MCLBYTES /* Fixed scatter particle size */ 40117845Ssam#define SAFE_MAX_SSIZE 0x0ffff /* Maximum gather particle size */ 41117845Ssam#define SAFE_MAX_DMA 0xfffff /* Maximum PE operand size (20 bits) */ 42117845Ssam/* total src+dst particle descriptors */ 43117845Ssam#define SAFE_TOTAL_DPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) 44117845Ssam#define SAFE_TOTAL_SPART (SAFE_MAX_NQUEUE * SAFE_MAX_PART) 45117845Ssam 46117845Ssam#define SAFE_RNG_MAXBUFSIZ 128 /* 32-bit words */ 47117845Ssam 48117845Ssam#define SAFE_CARD(sid) (((sid) & 0xf0000000) >> 28) 49117845Ssam#define SAFE_SESSION(sid) ( (sid) & 0x0fffffff) 50117845Ssam#define SAFE_SID(crd, sesn) (((crd) << 28) | ((sesn) & 0x0fffffff)) 51117845Ssam 52117845Ssam#define SAFE_DEF_RTY 0xff /* PCI Retry Timeout */ 53117845Ssam#define SAFE_DEF_TOUT 0xff /* PCI TRDY Timeout */ 54117845Ssam#define SAFE_DEF_CACHELINE 0x01 /* Cache Line setting */ 55117845Ssam 56117845Ssam#ifdef _KERNEL 57117845Ssam/* 58117845Ssam * State associated with the allocation of each chunk 59117845Ssam * of memory setup for DMA. 60117845Ssam */ 61117845Ssamstruct safe_dma_alloc { 62117845Ssam u_int32_t dma_paddr; /* physical address */ 63117845Ssam caddr_t dma_vaddr; /* virtual address */ 64117845Ssam bus_dma_tag_t dma_tag; /* bus dma tag used */ 65117845Ssam bus_dmamap_t dma_map; /* associated map */ 66117845Ssam bus_dma_segment_t dma_seg; 67117845Ssam bus_size_t dma_size; /* mapped memory size (bytes) */ 68117845Ssam int dma_nseg; /* number of segments */ 69117845Ssam}; 70117845Ssam 71117845Ssam/* 72117845Ssam * Cryptographic operand state. One of these exists for each 73117845Ssam * source and destination operand passed in from the crypto 74117845Ssam * subsystem. When possible source and destination operands 75117845Ssam * refer to the same memory. More often they are distinct. 76117845Ssam * We track the virtual address of each operand as well as 77117845Ssam * where each is mapped for DMA. 78117845Ssam */ 79117845Ssamstruct safe_operand { 80117845Ssam union { 81117845Ssam struct mbuf *m; 82117845Ssam struct uio *io; 83117845Ssam } u; 84117845Ssam bus_dmamap_t map; 85117845Ssam bus_size_t mapsize; 86117845Ssam int nsegs; 87117845Ssam bus_dma_segment_t segs[SAFE_MAX_PART]; 88117845Ssam}; 89117845Ssam 90117845Ssam/* 91117845Ssam * Packet engine ring entry and cryptographic operation state. 92117845Ssam * The packet engine requires a ring of descriptors that contain 93117845Ssam * pointers to various cryptographic state. However the ring 94117845Ssam * configuration register allows you to specify an arbitrary size 95117845Ssam * for ring entries. We use this feature to collect most of the 96117845Ssam * state for each cryptographic request into one spot. Other than 97117845Ssam * ring entries only the ``particle descriptors'' (scatter/gather 98117845Ssam * lists) and the actual operand data are kept separate. The 99117845Ssam * particle descriptors must also be organized in rings. The 100117845Ssam * operand data can be located aribtrarily (modulo alignment constraints). 101117845Ssam * 102117845Ssam * Note that the descriptor ring is mapped onto the PCI bus so 103117845Ssam * the hardware can DMA data. This means the entire ring must be 104117845Ssam * contiguous. 105117845Ssam */ 106117845Ssamstruct safe_ringentry { 107117845Ssam struct safe_desc re_desc; /* command descriptor */ 108117845Ssam struct safe_sarec re_sa; /* SA record */ 109117845Ssam struct safe_sastate re_sastate; /* SA state record */ 110117845Ssam struct cryptop *re_crp; /* crypto operation */ 111117845Ssam 112117845Ssam struct safe_operand re_src; /* source operand */ 113117845Ssam struct safe_operand re_dst; /* destination operand */ 114117845Ssam 115117845Ssam int re_sesn; /* crypto session ID */ 116117845Ssam int re_flags; 117117845Ssam#define SAFE_QFLAGS_COPYOUTIV 0x1 /* copy back on completion */ 118117845Ssam#define SAFE_QFLAGS_COPYOUTICV 0x2 /* copy back on completion */ 119117845Ssam}; 120117845Ssam 121117845Ssam#define re_src_m re_src.u.m 122117845Ssam#define re_src_io re_src.u.io 123117845Ssam#define re_src_map re_src.map 124117845Ssam#define re_src_nsegs re_src.nsegs 125117845Ssam#define re_src_segs re_src.segs 126117845Ssam#define re_src_mapsize re_src.mapsize 127117845Ssam 128117845Ssam#define re_dst_m re_dst.u.m 129117845Ssam#define re_dst_io re_dst.u.io 130117845Ssam#define re_dst_map re_dst.map 131117845Ssam#define re_dst_nsegs re_dst.nsegs 132117845Ssam#define re_dst_segs re_dst.segs 133117845Ssam#define re_dst_mapsize re_dst.mapsize 134117845Ssam 135117845Ssamstruct rndstate_test; 136117845Ssam 137117845Ssamstruct safe_session { 138117845Ssam u_int32_t ses_used; 139117845Ssam u_int32_t ses_klen; /* key length in bits */ 140117845Ssam u_int32_t ses_key[8]; /* DES/3DES/AES key */ 141158705Spjd u_int32_t ses_mlen; /* hmac length in bytes */ 142117845Ssam u_int32_t ses_hminner[5]; /* hmac inner state */ 143117845Ssam u_int32_t ses_hmouter[5]; /* hmac outer state */ 144117845Ssam u_int32_t ses_iv[4]; /* DES/3DES/AES iv */ 145117845Ssam}; 146117845Ssam 147117845Ssamstruct safe_softc { 148117845Ssam device_t sc_dev; /* device backpointer */ 149117845Ssam struct resource *sc_irq; 150117845Ssam void *sc_ih; /* interrupt handler cookie */ 151117845Ssam bus_space_handle_t sc_sh; /* memory handle */ 152117845Ssam bus_space_tag_t sc_st; /* memory tag */ 153117845Ssam struct resource *sc_sr; /* memory resource */ 154117845Ssam bus_dma_tag_t sc_srcdmat; /* source dma tag */ 155117845Ssam bus_dma_tag_t sc_dstdmat; /* destination dma tag */ 156117845Ssam u_int sc_chiprev; /* major/minor chip revision */ 157117845Ssam int sc_flags; /* device specific flags */ 158117845Ssam#define SAFE_FLAGS_KEY 0x01 /* has key accelerator */ 159117845Ssam#define SAFE_FLAGS_RNG 0x02 /* hardware rng */ 160117845Ssam int sc_suspended; 161117845Ssam int sc_needwakeup; /* notify crypto layer */ 162117845Ssam int32_t sc_cid; /* crypto tag */ 163117845Ssam struct safe_dma_alloc sc_ringalloc; /* PE ring allocation state */ 164117845Ssam struct safe_ringentry *sc_ring; /* PE ring */ 165117845Ssam struct safe_ringentry *sc_ringtop; /* PE ring top */ 166117845Ssam struct safe_ringentry *sc_front; /* next free entry */ 167117845Ssam struct safe_ringentry *sc_back; /* next pending entry */ 168117845Ssam int sc_nqchip; /* # passed to chip */ 169117845Ssam struct mtx sc_ringmtx; /* PE ring lock */ 170117845Ssam struct safe_pdesc *sc_spring; /* src particle ring */ 171117845Ssam struct safe_pdesc *sc_springtop; /* src particle ring top */ 172117845Ssam struct safe_pdesc *sc_spfree; /* next free src particle */ 173117845Ssam struct safe_dma_alloc sc_spalloc; /* src particle ring state */ 174117845Ssam struct safe_pdesc *sc_dpring; /* dest particle ring */ 175117845Ssam struct safe_pdesc *sc_dpringtop; /* dest particle ring top */ 176117845Ssam struct safe_pdesc *sc_dpfree; /* next free dest particle */ 177117845Ssam struct safe_dma_alloc sc_dpalloc; /* dst particle ring state */ 178117845Ssam int sc_nsessions; /* # of sessions */ 179117845Ssam struct safe_session *sc_sessions; /* sessions */ 180117845Ssam 181117845Ssam struct callout sc_rngto; /* rng timeout */ 182117845Ssam struct rndtest_state *sc_rndtest; /* RNG test state */ 183117845Ssam void (*sc_harvest)(struct rndtest_state *, 184117845Ssam void *, u_int); 185117845Ssam}; 186117845Ssam#endif /* _KERNEL */ 187117845Ssam 188117845Ssamstruct safe_stats { 189117845Ssam u_int64_t st_ibytes; 190117845Ssam u_int64_t st_obytes; 191117845Ssam u_int32_t st_ipackets; 192117845Ssam u_int32_t st_opackets; 193117845Ssam u_int32_t st_invalid; /* invalid argument */ 194117845Ssam u_int32_t st_badsession; /* invalid session id */ 195117845Ssam u_int32_t st_badflags; /* flags indicate !(mbuf | uio) */ 196117845Ssam u_int32_t st_nodesc; /* op submitted w/o descriptors */ 197117845Ssam u_int32_t st_badalg; /* unsupported algorithm */ 198117845Ssam u_int32_t st_ringfull; /* PE descriptor ring full */ 199117845Ssam u_int32_t st_peoperr; /* PE marked error */ 200117845Ssam u_int32_t st_dmaerr; /* PE DMA error */ 201117845Ssam u_int32_t st_bypasstoobig; /* bypass > 96 bytes */ 202117845Ssam u_int32_t st_skipmismatch; /* enc part begins before auth part */ 203117845Ssam u_int32_t st_lenmismatch; /* enc length different auth length */ 204117845Ssam u_int32_t st_coffmisaligned; /* crypto offset not 32-bit aligned */ 205117845Ssam u_int32_t st_cofftoobig; /* crypto offset > 255 words */ 206117845Ssam u_int32_t st_iovmisaligned; /* iov op not aligned */ 207117845Ssam u_int32_t st_iovnotuniform; /* iov op not suitable */ 208117845Ssam u_int32_t st_unaligned; /* unaligned src caused copy */ 209117845Ssam u_int32_t st_notuniform; /* non-uniform src caused copy */ 210117845Ssam u_int32_t st_nomap; /* bus_dmamap_create failed */ 211117845Ssam u_int32_t st_noload; /* bus_dmamap_load_* failed */ 212117845Ssam u_int32_t st_nombuf; /* MGET* failed */ 213117845Ssam u_int32_t st_nomcl; /* MCLGET* failed */ 214117845Ssam u_int32_t st_maxqchip; /* max mcr1 ops out for processing */ 215117845Ssam u_int32_t st_rng; /* RNG requests */ 216117845Ssam u_int32_t st_rngalarm; /* RNG alarm requests */ 217117845Ssam u_int32_t st_noicvcopy; /* ICV data copies suppressed */ 218117845Ssam}; 219117845Ssam#endif /* _SAFE_SAFEVAR_H_ */ 220