1176772Sraj/*- 2176772Sraj * Copyright (c) 2006 Marcel Moolenaar 3176772Sraj * All rights reserved. 4176772Sraj * 5176772Sraj * Redistribution and use in source and binary forms, with or without 6176772Sraj * modification, are permitted provided that the following conditions 7176772Sraj * are met: 8176772Sraj * 9176772Sraj * 1. Redistributions of source code must retain the above copyright 10176772Sraj * notice, this list of conditions and the following disclaimer. 11176772Sraj * 2. Redistributions in binary form must reproduce the above copyright 12176772Sraj * notice, this list of conditions and the following disclaimer in the 13176772Sraj * documentation and/or other materials provided with the distribution. 14176772Sraj * 15176772Sraj * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16176772Sraj * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17176772Sraj * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18176772Sraj * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19176772Sraj * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20176772Sraj * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21176772Sraj * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22176772Sraj * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23176772Sraj * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24176772Sraj * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25176772Sraj * 26176772Sraj * $FreeBSD$ 27176772Sraj */ 28176772Sraj 29176772Sraj#ifndef _DEV_QUICC_BUS_H_ 30176772Sraj#define _DEV_QUICC_BUS_H_ 31176772Sraj 32176772Sraj#define QUICC_IVAR_CLOCK 1 /* The CPM clock. */ 33176772Sraj#define QUICC_IVAR_BRGCLK 2 /* The BRG clock affected by SCCR. */ 34176772Sraj#define QUICC_IVAR_DEVTYPE 3 35176772Sraj 36176772Sraj/* Device types. */ 37176772Sraj#define QUICC_DEVTYPE_SCC 1 38176772Sraj 39176772Sraj#endif /* _DEV_QUICC_BUS_H_ */ 40