1250661Sdavidcs/* 2284982Sdavidcs * Copyright (c) 2013-2016 Qlogic Corporation 3250661Sdavidcs * All rights reserved. 4250661Sdavidcs * 5250661Sdavidcs * Redistribution and use in source and binary forms, with or without 6250661Sdavidcs * modification, are permitted provided that the following conditions 7250661Sdavidcs * are met: 8250661Sdavidcs * 9250661Sdavidcs * 1. Redistributions of source code must retain the above copyright 10250661Sdavidcs * notice, this list of conditions and the following disclaimer. 11250661Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12250661Sdavidcs * notice, this list of conditions and the following disclaimer in the 13250661Sdavidcs * documentation and/or other materials provided with the distribution. 14250661Sdavidcs * 15250661Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16250661Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17250661Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18250661Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19250661Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20250661Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21250661Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22250661Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23250661Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24250661Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25250661Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26250661Sdavidcs * 27250661Sdavidcs * $FreeBSD: stable/10/sys/dev/qlxgbe/ql_hw.h 330556 2018-03-06 23:17:56Z davidcs $ 28250661Sdavidcs */ 29250661Sdavidcs/* 30250661Sdavidcs * File: ql_hw.h 31250661Sdavidcs * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656. 32250661Sdavidcs */ 33250661Sdavidcs#ifndef _QL_HW_H_ 34250661Sdavidcs#define _QL_HW_H_ 35250661Sdavidcs 36250661Sdavidcs/* 37250661Sdavidcs * PCIe Registers; Direct Mapped; Offsets from BAR0 38250661Sdavidcs */ 39250661Sdavidcs 40250661Sdavidcs/* 41250661Sdavidcs * Register offsets for QLE8030 42250661Sdavidcs */ 43250661Sdavidcs 44250661Sdavidcs/* 45250661Sdavidcs * Firmware Mailbox Registers 46250661Sdavidcs * 0 thru 511; offsets 0x800 thru 0xFFC; 32bits each 47250661Sdavidcs */ 48250661Sdavidcs#define Q8_FW_MBOX0 0x00000800 49250661Sdavidcs#define Q8_FW_MBOX511 0x00000FFC 50250661Sdavidcs 51250661Sdavidcs/* 52250661Sdavidcs * Host Mailbox Registers 53250661Sdavidcs * 0 thru 511; offsets 0x000 thru 0x7FC; 32bits each 54250661Sdavidcs */ 55250661Sdavidcs#define Q8_HOST_MBOX0 0x00000000 56250661Sdavidcs#define Q8_HOST_MBOX511 0x000007FC 57250661Sdavidcs 58250661Sdavidcs#define Q8_MBOX_INT_ENABLE 0x00001000 59250661Sdavidcs#define Q8_MBOX_INT_MASK_MSIX 0x00001200 60250661Sdavidcs#define Q8_MBOX_INT_LEGACY 0x00003010 61250661Sdavidcs 62250661Sdavidcs#define Q8_HOST_MBOX_CNTRL 0x00003038 63250661Sdavidcs#define Q8_FW_MBOX_CNTRL 0x0000303C 64250661Sdavidcs 65250661Sdavidcs#define Q8_PEG_HALT_STATUS1 0x000034A8 66250661Sdavidcs#define Q8_PEG_HALT_STATUS2 0x000034AC 67250661Sdavidcs#define Q8_FIRMWARE_HEARTBEAT 0x000034B0 68250661Sdavidcs 69250661Sdavidcs#define Q8_FLASH_LOCK_ID 0x00003500 70250661Sdavidcs#define Q8_DRIVER_LOCK_ID 0x00003504 71250661Sdavidcs#define Q8_FW_CAPABILITIES 0x00003528 72250661Sdavidcs 73250661Sdavidcs#define Q8_FW_VER_MAJOR 0x00003550 74250661Sdavidcs#define Q8_FW_VER_MINOR 0x00003554 75250661Sdavidcs#define Q8_FW_VER_SUB 0x00003558 76250661Sdavidcs 77250661Sdavidcs#define Q8_BOOTLD_ADDR 0x0000355C 78250661Sdavidcs#define Q8_BOOTLD_SIZE 0x00003560 79250661Sdavidcs 80250661Sdavidcs#define Q8_FW_IMAGE_ADDR 0x00003564 81250661Sdavidcs#define Q8_FW_BUILD_NUMBER 0x00003568 82250661Sdavidcs#define Q8_FW_IMAGE_VALID 0x000035FC 83250661Sdavidcs 84250661Sdavidcs#define Q8_CMDPEG_STATE 0x00003650 85250661Sdavidcs 86250661Sdavidcs#define Q8_LINK_STATE 0x00003698 87250661Sdavidcs#define Q8_LINK_STATE_2 0x0000369C 88250661Sdavidcs 89250661Sdavidcs#define Q8_LINK_SPEED_0 0x000036E0 90250661Sdavidcs#define Q8_LINK_SPEED_1 0x000036E4 91250661Sdavidcs#define Q8_LINK_SPEED_2 0x000036E8 92250661Sdavidcs#define Q8_LINK_SPEED_3 0x000036EC 93250661Sdavidcs 94250661Sdavidcs#define Q8_MAX_LINK_SPEED_0 0x000036F0 95250661Sdavidcs#define Q8_MAX_LINK_SPEED_1 0x000036F4 96250661Sdavidcs#define Q8_MAX_LINK_SPEED_2 0x000036F8 97250661Sdavidcs#define Q8_MAX_LINK_SPEED_3 0x000036FC 98250661Sdavidcs 99250661Sdavidcs#define Q8_ASIC_TEMPERATURE 0x000037B4 100250661Sdavidcs 101250661Sdavidcs/* 102250661Sdavidcs * CRB Window Registers 103250661Sdavidcs * 0 thru 15; offsets 0x3800 thru 0x383C; 32bits each 104250661Sdavidcs */ 105250661Sdavidcs#define Q8_CRB_WINDOW_PF0 0x00003800 106250661Sdavidcs#define Q8_CRB_WINDOW_PF15 0x0000383C 107250661Sdavidcs 108250661Sdavidcs#define Q8_FLASH_LOCK 0x00003850 109250661Sdavidcs#define Q8_FLASH_UNLOCK 0x00003854 110250661Sdavidcs 111250661Sdavidcs#define Q8_DRIVER_LOCK 0x00003868 112250661Sdavidcs#define Q8_DRIVER_UNLOCK 0x0000386C 113250661Sdavidcs 114250661Sdavidcs#define Q8_LEGACY_INT_PTR 0x000038C0 115250661Sdavidcs#define Q8_LEGACY_INT_TRIG 0x000038C4 116250661Sdavidcs#define Q8_LEGACY_INT_MASK 0x000038C8 117250661Sdavidcs 118250661Sdavidcs#define Q8_WILD_CARD 0x000038F0 119250661Sdavidcs#define Q8_INFORMANT 0x000038FC 120250661Sdavidcs 121250661Sdavidcs/* 122250661Sdavidcs * Ethernet Interface Specific Registers 123250661Sdavidcs */ 124250661Sdavidcs#define Q8_DRIVER_OP_MODE 0x00003570 125250661Sdavidcs#define Q8_API_VERSION 0x0000356C 126250661Sdavidcs#define Q8_NPAR_STATE 0x0000359C 127250661Sdavidcs 128250661Sdavidcs/* 129250661Sdavidcs * End of PCIe Registers; Direct Mapped; Offsets from BAR0 130250661Sdavidcs */ 131250661Sdavidcs 132250661Sdavidcs/* 133250661Sdavidcs * Indirect Registers 134250661Sdavidcs */ 135250661Sdavidcs#define Q8_LED_DUAL_0 0x28084C80 136250661Sdavidcs#define Q8_LED_SINGLE_0 0x28084C90 137250661Sdavidcs 138250661Sdavidcs#define Q8_LED_DUAL_1 0x28084CA0 139250661Sdavidcs#define Q8_LED_SINGLE_1 0x28084CB0 140250661Sdavidcs 141250661Sdavidcs#define Q8_LED_DUAL_2 0x28084CC0 142250661Sdavidcs#define Q8_LED_SINGLE_2 0x28084CD0 143250661Sdavidcs 144250661Sdavidcs#define Q8_LED_DUAL_3 0x28084CE0 145250661Sdavidcs#define Q8_LED_SINGLE_3 0x28084CF0 146250661Sdavidcs 147250661Sdavidcs#define Q8_GPIO_1 0x28084D00 148250661Sdavidcs#define Q8_GPIO_2 0x28084D10 149250661Sdavidcs#define Q8_GPIO_3 0x28084D20 150250661Sdavidcs#define Q8_GPIO_4 0x28084D40 151250661Sdavidcs#define Q8_GPIO_5 0x28084D50 152250661Sdavidcs#define Q8_GPIO_6 0x28084D60 153250661Sdavidcs#define Q8_GPIO_7 0x42100060 154250661Sdavidcs#define Q8_GPIO_8 0x42100064 155250661Sdavidcs 156250661Sdavidcs#define Q8_FLASH_SPI_STATUS 0x2808E010 157250661Sdavidcs#define Q8_FLASH_SPI_CONTROL 0x2808E014 158250661Sdavidcs 159250661Sdavidcs#define Q8_FLASH_STATUS 0x42100004 160250661Sdavidcs#define Q8_FLASH_CONTROL 0x42110004 161250661Sdavidcs#define Q8_FLASH_ADDRESS 0x42110008 162250661Sdavidcs#define Q8_FLASH_WR_DATA 0x4211000C 163250661Sdavidcs#define Q8_FLASH_RD_DATA 0x42110018 164250661Sdavidcs 165250661Sdavidcs#define Q8_FLASH_DIRECT_WINDOW 0x42110030 166250661Sdavidcs#define Q8_FLASH_DIRECT_DATA 0x42150000 167250661Sdavidcs 168250661Sdavidcs#define Q8_MS_CNTRL 0x41000090 169250661Sdavidcs 170250661Sdavidcs#define Q8_MS_ADDR_LO 0x41000094 171250661Sdavidcs#define Q8_MS_ADDR_HI 0x41000098 172250661Sdavidcs 173250661Sdavidcs#define Q8_MS_WR_DATA_0_31 0x410000A0 174250661Sdavidcs#define Q8_MS_WR_DATA_32_63 0x410000A4 175250661Sdavidcs#define Q8_MS_WR_DATA_64_95 0x410000B0 176250661Sdavidcs#define Q8_MS_WR_DATA_96_127 0x410000B4 177250661Sdavidcs 178250661Sdavidcs#define Q8_MS_RD_DATA_0_31 0x410000A8 179250661Sdavidcs#define Q8_MS_RD_DATA_32_63 0x410000AC 180250661Sdavidcs#define Q8_MS_RD_DATA_64_95 0x410000B8 181250661Sdavidcs#define Q8_MS_RD_DATA_96_127 0x410000BC 182250661Sdavidcs 183250661Sdavidcs#define Q8_CRB_PEG_0 0x3400003c 184250661Sdavidcs#define Q8_CRB_PEG_1 0x3410003c 185250661Sdavidcs#define Q8_CRB_PEG_2 0x3420003c 186250661Sdavidcs#define Q8_CRB_PEG_3 0x3430003c 187250661Sdavidcs#define Q8_CRB_PEG_4 0x34B0003c 188250661Sdavidcs 189250661Sdavidcs/* 190250661Sdavidcs * Macros for reading and writing registers 191250661Sdavidcs */ 192250661Sdavidcs 193250661Sdavidcs#if defined(__i386__) || defined(__amd64__) 194250661Sdavidcs#define Q8_MB() __asm volatile("mfence" ::: "memory") 195250661Sdavidcs#define Q8_WMB() __asm volatile("sfence" ::: "memory") 196250661Sdavidcs#define Q8_RMB() __asm volatile("lfence" ::: "memory") 197250661Sdavidcs#else 198250661Sdavidcs#define Q8_MB() 199250661Sdavidcs#define Q8_WMB() 200250661Sdavidcs#define Q8_RMB() 201250661Sdavidcs#endif 202250661Sdavidcs 203250661Sdavidcs#define READ_REG32(ha, reg) bus_read_4((ha->pci_reg), reg) 204250661Sdavidcs 205250661Sdavidcs#define WRITE_REG32(ha, reg, val) \ 206250661Sdavidcs {\ 207250661Sdavidcs bus_write_4((ha->pci_reg), reg, val);\ 208250661Sdavidcs bus_read_4((ha->pci_reg), reg);\ 209250661Sdavidcs } 210250661Sdavidcs 211250661Sdavidcs#define Q8_NUM_MBOX 512 212250661Sdavidcs 213307525Sdavidcs#define Q8_MAX_NUM_MULTICAST_ADDRS 1022 214250661Sdavidcs#define Q8_MAC_ADDR_LEN 6 215250661Sdavidcs 216250661Sdavidcs/* 217250661Sdavidcs * Firmware Interface 218250661Sdavidcs */ 219250661Sdavidcs 220250661Sdavidcs/* 221250661Sdavidcs * Command Response Interface - Commands 222250661Sdavidcs */ 223250661Sdavidcs 224250661Sdavidcs#define Q8_MBX_CONFIG_IP_ADDRESS 0x0001 225250661Sdavidcs#define Q8_MBX_CONFIG_INTR 0x0002 226250661Sdavidcs#define Q8_MBX_MAP_INTR_SRC 0x0003 227250661Sdavidcs#define Q8_MBX_MAP_SDS_TO_RDS 0x0006 228250661Sdavidcs#define Q8_MBX_CREATE_RX_CNTXT 0x0007 229250661Sdavidcs#define Q8_MBX_DESTROY_RX_CNTXT 0x0008 230250661Sdavidcs#define Q8_MBX_CREATE_TX_CNTXT 0x0009 231250661Sdavidcs#define Q8_MBX_DESTROY_TX_CNTXT 0x000A 232250661Sdavidcs#define Q8_MBX_ADD_RX_RINGS 0x000B 233250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW 0x000C 234250661Sdavidcs#define Q8_MBX_CONFIG_MAC_LEARNING 0x000D 235250661Sdavidcs#define Q8_MBX_GET_STATS 0x000F 236250661Sdavidcs#define Q8_MBX_GENERATE_INTR 0x0011 237250661Sdavidcs#define Q8_MBX_SET_MAX_MTU 0x0012 238250661Sdavidcs#define Q8_MBX_MAC_ADDR_CNTRL 0x001F 239250661Sdavidcs#define Q8_MBX_GET_PCI_CONFIG 0x0020 240250661Sdavidcs#define Q8_MBX_GET_NIC_PARTITION 0x0021 241250661Sdavidcs#define Q8_MBX_SET_NIC_PARTITION 0x0022 242250661Sdavidcs#define Q8_MBX_QUERY_WOL_CAP 0x002C 243250661Sdavidcs#define Q8_MBX_SET_WOL_CONFIG 0x002D 244250661Sdavidcs#define Q8_MBX_GET_MINIDUMP_TMPLT_SIZE 0x002F 245250661Sdavidcs#define Q8_MBX_GET_MINIDUMP_TMPLT 0x0030 246250661Sdavidcs#define Q8_MBX_GET_FW_DCBX_CAPS 0x0034 247250661Sdavidcs#define Q8_MBX_QUERY_DCBX_SETTINGS 0x0035 248250661Sdavidcs#define Q8_MBX_CONFIG_RSS 0x0041 249250661Sdavidcs#define Q8_MBX_CONFIG_RSS_TABLE 0x0042 250250661Sdavidcs#define Q8_MBX_CONFIG_INTR_COALESCE 0x0043 251250661Sdavidcs#define Q8_MBX_CONFIG_LED 0x0044 252250661Sdavidcs#define Q8_MBX_CONFIG_MAC_ADDR 0x0045 253250661Sdavidcs#define Q8_MBX_CONFIG_STATISTICS 0x0046 254250661Sdavidcs#define Q8_MBX_CONFIG_LOOPBACK 0x0047 255250661Sdavidcs#define Q8_MBX_LINK_EVENT_REQ 0x0048 256250661Sdavidcs#define Q8_MBX_CONFIG_MAC_RX_MODE 0x0049 257250661Sdavidcs#define Q8_MBX_CONFIG_FW_LRO 0x004A 258305491Sdavidcs#define Q8_MBX_HW_CONFIG 0x004C 259250661Sdavidcs#define Q8_MBX_INIT_NIC_FUNC 0x0060 260250661Sdavidcs#define Q8_MBX_STOP_NIC_FUNC 0x0061 261284982Sdavidcs#define Q8_MBX_IDC_REQ 0x0062 262284982Sdavidcs#define Q8_MBX_IDC_ACK 0x0063 263250661Sdavidcs#define Q8_MBX_SET_PORT_CONFIG 0x0066 264250661Sdavidcs#define Q8_MBX_GET_PORT_CONFIG 0x0067 265250661Sdavidcs#define Q8_MBX_GET_LINK_STATUS 0x0068 266250661Sdavidcs 267250661Sdavidcs 268250661Sdavidcs 269250661Sdavidcs/* 270250661Sdavidcs * Mailbox Command Response 271250661Sdavidcs */ 272250661Sdavidcs#define Q8_MBX_RSP_SUCCESS 0x0001 273250661Sdavidcs#define Q8_MBX_RSP_RESPONSE_FAILURE 0x0002 274250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_CRB 0x0003 275250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_MEM 0x0004 276250661Sdavidcs#define Q8_MBX_RSP_NO_CARD_RSRC 0x0005 277250661Sdavidcs#define Q8_MBX_RSP_INVALID_ARGS 0x0006 278250661Sdavidcs#define Q8_MBX_RSP_INVALID_ACTION 0x0007 279250661Sdavidcs#define Q8_MBX_RSP_INVALID_STATE 0x0008 280250661Sdavidcs#define Q8_MBX_RSP_NOT_SUPPORTED 0x0009 281250661Sdavidcs#define Q8_MBX_RSP_NOT_PERMITTED 0x000A 282250661Sdavidcs#define Q8_MBX_RSP_NOT_READY 0x000B 283250661Sdavidcs#define Q8_MBX_RSP_DOES_NOT_EXIST 0x000C 284250661Sdavidcs#define Q8_MBX_RSP_ALREADY_EXISTS 0x000D 285250661Sdavidcs#define Q8_MBX_RSP_BAD_SIGNATURE 0x000E 286250661Sdavidcs#define Q8_MBX_RSP_CMD_NOT_IMPLEMENTED 0x000F 287250661Sdavidcs#define Q8_MBX_RSP_CMD_INVALID 0x0010 288250661Sdavidcs#define Q8_MBX_RSP_TIMEOUT 0x0011 289250661Sdavidcs#define Q8_MBX_RSP_CMD_FAILED 0x0012 290250661Sdavidcs#define Q8_MBX_RSP_FATAL_TEMP 0x0013 291250661Sdavidcs#define Q8_MBX_RSP_MAX_EXCEEDED 0x0014 292250661Sdavidcs#define Q8_MBX_RSP_UNSPECIFIED 0x0015 293250661Sdavidcs#define Q8_MBX_RSP_INTR_CREATE_FAILED 0x0017 294250661Sdavidcs#define Q8_MBX_RSP_INTR_DELETE_FAILED 0x0018 295250661Sdavidcs#define Q8_MBX_RSP_INTR_INVALID_OP 0x0019 296250661Sdavidcs#define Q8_MBX_RSP_IDC_INTRMD_RSP 0x001A 297250661Sdavidcs 298250661Sdavidcs#define Q8_MBX_CMD_VERSION (0x2 << 13) 299250661Sdavidcs#define Q8_MBX_RSP_STATUS(x) (((!(x >> 9)) || ((x >> 9) == 1)) ? 0: (x >> 9)) 300250661Sdavidcs/* 301250661Sdavidcs * Configure IP Address 302250661Sdavidcs */ 303250661Sdavidcstypedef struct _q80_config_ip_addr { 304250661Sdavidcs uint16_t opcode; 305250661Sdavidcs uint16_t count_version; 306250661Sdavidcs 307250661Sdavidcs uint8_t cmd; 308250661Sdavidcs#define Q8_MBX_CONFIG_IP_ADD_IP 0x1 309250661Sdavidcs#define Q8_MBX_CONFIG_IP_DEL_IP 0x2 310250661Sdavidcs 311250661Sdavidcs uint8_t ip_type; 312250661Sdavidcs#define Q8_MBX_CONFIG_IP_V4 0x0 313250661Sdavidcs#define Q8_MBX_CONFIG_IP_V6 0x1 314250661Sdavidcs 315250661Sdavidcs uint16_t rsrvd; 316250661Sdavidcs union { 317250661Sdavidcs struct { 318250661Sdavidcs uint32_t addr; 319250661Sdavidcs uint32_t rsrvd[3]; 320250661Sdavidcs } ipv4; 321250661Sdavidcs uint8_t ipv6_addr[16]; 322250661Sdavidcs } u; 323250661Sdavidcs} __packed q80_config_ip_addr_t; 324250661Sdavidcs 325250661Sdavidcstypedef struct _q80_config_ip_addr_rsp { 326250661Sdavidcs uint16_t opcode; 327250661Sdavidcs uint16_t regcnt_status; 328250661Sdavidcs} __packed q80_config_ip_addr_rsp_t; 329250661Sdavidcs 330250661Sdavidcs/* 331250661Sdavidcs * Configure Interrupt Command 332250661Sdavidcs */ 333250661Sdavidcstypedef struct _q80_intr { 334250661Sdavidcs uint8_t cmd_type; 335250661Sdavidcs#define Q8_MBX_CONFIG_INTR_CREATE 0x1 336250661Sdavidcs#define Q8_MBX_CONFIG_INTR_DELETE 0x2 337250661Sdavidcs#define Q8_MBX_CONFIG_INTR_TYPE_LINE (0x1 << 4) 338250661Sdavidcs#define Q8_MBX_CONFIG_INTR_TYPE_MSI_X (0x3 << 4) 339250661Sdavidcs 340250661Sdavidcs uint8_t rsrvd; 341250661Sdavidcs uint16_t msix_index; 342250661Sdavidcs} __packed q80_intr_t; 343250661Sdavidcs 344250661Sdavidcs#define Q8_MAX_INTR_VECTORS 16 345250661Sdavidcstypedef struct _q80_config_intr { 346250661Sdavidcs uint16_t opcode; 347250661Sdavidcs uint16_t count_version; 348250661Sdavidcs uint8_t nentries; 349250661Sdavidcs uint8_t rsrvd[3]; 350250661Sdavidcs q80_intr_t intr[Q8_MAX_INTR_VECTORS]; 351250661Sdavidcs} __packed q80_config_intr_t; 352250661Sdavidcs 353250661Sdavidcstypedef struct _q80_intr_rsp { 354250661Sdavidcs uint8_t status; 355250661Sdavidcs uint8_t cmd; 356250661Sdavidcs uint16_t intr_id; 357250661Sdavidcs uint32_t intr_src; 358250661Sdavidcs} q80_intr_rsp_t; 359250661Sdavidcs 360250661Sdavidcstypedef struct _q80_config_intr_rsp { 361250661Sdavidcs uint16_t opcode; 362250661Sdavidcs uint16_t regcnt_status; 363250661Sdavidcs uint8_t nentries; 364250661Sdavidcs uint8_t rsrvd[3]; 365250661Sdavidcs q80_intr_rsp_t intr[Q8_MAX_INTR_VECTORS]; 366250661Sdavidcs} __packed q80_config_intr_rsp_t; 367250661Sdavidcs 368250661Sdavidcs/* 369250661Sdavidcs * Configure LRO Flow Command 370250661Sdavidcs */ 371250661Sdavidcstypedef struct _q80_config_lro_flow { 372250661Sdavidcs uint16_t opcode; 373250661Sdavidcs uint16_t count_version; 374250661Sdavidcs 375250661Sdavidcs uint8_t cmd; 376250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_ADD 0x01 377250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_DELETE 0x02 378250661Sdavidcs 379250661Sdavidcs uint8_t type_ts; 380250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_IPV4 0x00 381250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_IPV6 0x01 382250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_TS_ABSENT 0x00 383250661Sdavidcs#define Q8_MBX_CONFIG_LRO_FLOW_TS_PRESENT 0x02 384250661Sdavidcs 385250661Sdavidcs uint16_t rsrvd; 386250661Sdavidcs union { 387250661Sdavidcs struct { 388250661Sdavidcs uint32_t addr; 389250661Sdavidcs uint32_t rsrvd[3]; 390250661Sdavidcs } ipv4; 391250661Sdavidcs uint8_t ipv6_addr[16]; 392250661Sdavidcs } dst; 393250661Sdavidcs union { 394250661Sdavidcs struct { 395250661Sdavidcs uint32_t addr; 396250661Sdavidcs uint32_t rsrvd[3]; 397250661Sdavidcs } ipv4; 398250661Sdavidcs uint8_t ipv6_addr[16]; 399250661Sdavidcs } src; 400250661Sdavidcs uint16_t dst_port; 401250661Sdavidcs uint16_t src_port; 402250661Sdavidcs} __packed q80_config_lro_flow_t; 403250661Sdavidcs 404250661Sdavidcstypedef struct _q80_config_lro_flow_rsp { 405250661Sdavidcs uint16_t opcode; 406250661Sdavidcs uint16_t regcnt_status; 407250661Sdavidcs} __packed q80_config_lro_flow_rsp_t; 408250661Sdavidcs 409250661Sdavidcstypedef struct _q80_set_max_mtu { 410250661Sdavidcs uint16_t opcode; 411250661Sdavidcs uint16_t count_version; 412250661Sdavidcs uint32_t cntxt_id; 413250661Sdavidcs uint32_t mtu; 414250661Sdavidcs} __packed q80_set_max_mtu_t; 415250661Sdavidcs 416250661Sdavidcstypedef struct _q80_set_max_mtu_rsp { 417250661Sdavidcs uint16_t opcode; 418250661Sdavidcs uint16_t regcnt_status; 419250661Sdavidcs} __packed q80_set_max_mtu_rsp_t; 420250661Sdavidcs 421250661Sdavidcs/* 422250661Sdavidcs * Configure RSS 423250661Sdavidcs */ 424250661Sdavidcstypedef struct _q80_config_rss { 425250661Sdavidcs uint16_t opcode; 426250661Sdavidcs uint16_t count_version; 427250661Sdavidcs 428250661Sdavidcs uint16_t cntxt_id; 429250661Sdavidcs uint16_t rsrvd; 430250661Sdavidcs 431250661Sdavidcs uint8_t hash_type; 432284982Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV4_IP (0x1 << 4) 433284982Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP (0x2 << 4) 434250661Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV4_TCP_IP (0x3 << 4) 435284982Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV6_IP (0x1 << 6) 436284982Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP (0x2 << 6) 437250661Sdavidcs#define Q8_MBX_RSS_HASH_TYPE_IPV6_TCP_IP (0x3 << 6) 438250661Sdavidcs 439250661Sdavidcs uint8_t flags; 440250661Sdavidcs#define Q8_MBX_RSS_FLAGS_ENABLE_RSS (0x1) 441250661Sdavidcs#define Q8_MBX_RSS_FLAGS_USE_IND_TABLE (0x2) 442250661Sdavidcs#define Q8_MBX_RSS_FLAGS_TYPE_CRSS (0x4) 443250661Sdavidcs 444250661Sdavidcs uint16_t indtbl_mask; 445250661Sdavidcs#define Q8_MBX_RSS_INDTBL_MASK 0x7F 446250661Sdavidcs#define Q8_MBX_RSS_FLAGS_MULTI_RSS_VALID 0x8000 447250661Sdavidcs 448250661Sdavidcs uint32_t multi_rss; 449250661Sdavidcs#define Q8_MBX_RSS_MULTI_RSS_ENGINE_ASSIGN BIT_30 450250661Sdavidcs#define Q8_MBX_RSS_USE_MULTI_RSS_ENGINES BIT_31 451250661Sdavidcs 452250661Sdavidcs uint64_t rss_key[5]; 453250661Sdavidcs} __packed q80_config_rss_t; 454250661Sdavidcs 455250661Sdavidcstypedef struct _q80_config_rss_rsp { 456250661Sdavidcs uint16_t opcode; 457250661Sdavidcs uint16_t regcnt_status; 458250661Sdavidcs} __packed q80_config_rss_rsp_t; 459250661Sdavidcs 460250661Sdavidcs/* 461250661Sdavidcs * Configure RSS Indirection Table 462250661Sdavidcs */ 463250661Sdavidcs#define Q8_RSS_IND_TBL_SIZE 40 464250661Sdavidcs#define Q8_RSS_IND_TBL_MIN_IDX 0 465250661Sdavidcs#define Q8_RSS_IND_TBL_MAX_IDX 127 466250661Sdavidcs 467250661Sdavidcstypedef struct _q80_config_rss_ind_table { 468250661Sdavidcs uint16_t opcode; 469250661Sdavidcs uint16_t count_version; 470250661Sdavidcs uint8_t start_idx; 471250661Sdavidcs uint8_t end_idx; 472250661Sdavidcs uint16_t cntxt_id; 473284982Sdavidcs uint8_t ind_table[Q8_RSS_IND_TBL_SIZE]; 474250661Sdavidcs} __packed q80_config_rss_ind_table_t; 475250661Sdavidcs 476250661Sdavidcstypedef struct _q80_config_rss_ind_table_rsp { 477250661Sdavidcs uint16_t opcode; 478250661Sdavidcs uint16_t regcnt_status; 479250661Sdavidcs} __packed q80_config_rss_ind_table_rsp_t; 480250661Sdavidcs 481250661Sdavidcs/* 482250661Sdavidcs * Configure Interrupt Coalescing and Generation 483250661Sdavidcs */ 484250661Sdavidcstypedef struct _q80_config_intr_coalesc { 485250661Sdavidcs uint16_t opcode; 486250661Sdavidcs uint16_t count_version; 487250661Sdavidcs uint16_t flags; 488250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_RCV 1 489250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_XMT 2 490250661Sdavidcs#define Q8_MBX_INTRC_FLAGS_PERIODIC (1 << 3) 491250661Sdavidcs 492250661Sdavidcs uint16_t cntxt_id; 493250661Sdavidcs uint16_t max_pkts; 494250661Sdavidcs uint16_t max_mswait; 495250661Sdavidcs uint8_t timer_type; 496250661Sdavidcs#define Q8_MBX_INTRC_TIMER_NONE 0 497250661Sdavidcs#define Q8_MBX_INTRC_TIMER_SINGLE 1 498250661Sdavidcs#define Q8_MBX_INTRC_TIMER_PERIODIC 2 499250661Sdavidcs 500250661Sdavidcs uint16_t sds_ring_mask; 501250661Sdavidcs 502250661Sdavidcs uint8_t rsrvd; 503250661Sdavidcs uint32_t ms_timeout; 504250661Sdavidcs} __packed q80_config_intr_coalesc_t; 505250661Sdavidcs 506250661Sdavidcstypedef struct _q80_config_intr_coalesc_rsp { 507250661Sdavidcs uint16_t opcode; 508250661Sdavidcs uint16_t regcnt_status; 509250661Sdavidcs} __packed q80_config_intr_coalesc_rsp_t; 510250661Sdavidcs 511250661Sdavidcs/* 512250661Sdavidcs * Configure MAC Address 513250661Sdavidcs */ 514307525Sdavidcs#define Q8_ETHER_ADDR_LEN 6 515250661Sdavidcstypedef struct _q80_mac_addr { 516307525Sdavidcs uint8_t addr[Q8_ETHER_ADDR_LEN]; 517250661Sdavidcs uint16_t vlan_tci; 518250661Sdavidcs} __packed q80_mac_addr_t; 519250661Sdavidcs 520250661Sdavidcs#define Q8_MAX_MAC_ADDRS 64 521250661Sdavidcs 522250661Sdavidcstypedef struct _q80_config_mac_addr { 523250661Sdavidcs uint16_t opcode; 524250661Sdavidcs uint16_t count_version; 525250661Sdavidcs uint8_t cmd; 526250661Sdavidcs#define Q8_MBX_CMAC_CMD_ADD_MAC_ADDR 1 527250661Sdavidcs#define Q8_MBX_CMAC_CMD_DEL_MAC_ADDR 2 528250661Sdavidcs 529250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_BOTH (0x0 << 6) 530250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_INGRESS (0x1 << 6) 531250661Sdavidcs#define Q8_MBX_CMAC_CMD_CAM_EGRESS (0x2 << 6) 532250661Sdavidcs 533250661Sdavidcs uint8_t nmac_entries; 534250661Sdavidcs uint16_t cntxt_id; 535250661Sdavidcs q80_mac_addr_t mac_addr[Q8_MAX_MAC_ADDRS]; 536250661Sdavidcs} __packed q80_config_mac_addr_t; 537250661Sdavidcs 538250661Sdavidcstypedef struct _q80_config_mac_addr_rsp { 539250661Sdavidcs uint16_t opcode; 540250661Sdavidcs uint16_t regcnt_status; 541250661Sdavidcs uint8_t cmd; 542250661Sdavidcs uint8_t nmac_entries; 543250661Sdavidcs uint16_t cntxt_id; 544250661Sdavidcs uint32_t status[Q8_MAX_MAC_ADDRS]; 545250661Sdavidcs} __packed q80_config_mac_addr_rsp_t; 546250661Sdavidcs 547250661Sdavidcs/* 548250661Sdavidcs * Configure MAC Receive Mode 549250661Sdavidcs */ 550250661Sdavidcstypedef struct _q80_config_mac_rcv_mode { 551250661Sdavidcs uint16_t opcode; 552250661Sdavidcs uint16_t count_version; 553250661Sdavidcs 554250661Sdavidcs uint8_t mode; 555250661Sdavidcs#define Q8_MBX_MAC_RCV_PROMISC_ENABLE 0x1 556250661Sdavidcs#define Q8_MBX_MAC_ALL_MULTI_ENABLE 0x2 557250661Sdavidcs 558250661Sdavidcs uint8_t rsrvd; 559250661Sdavidcs uint16_t cntxt_id; 560250661Sdavidcs} __packed q80_config_mac_rcv_mode_t; 561250661Sdavidcs 562250661Sdavidcstypedef struct _q80_config_mac_rcv_mode_rsp { 563250661Sdavidcs uint16_t opcode; 564250661Sdavidcs uint16_t regcnt_status; 565250661Sdavidcs} __packed q80_config_mac_rcv_mode_rsp_t; 566250661Sdavidcs 567250661Sdavidcs/* 568250661Sdavidcs * Configure Firmware Controlled LRO 569250661Sdavidcs */ 570250661Sdavidcstypedef struct _q80_config_fw_lro { 571250661Sdavidcs uint16_t opcode; 572250661Sdavidcs uint16_t count_version; 573250661Sdavidcs 574250661Sdavidcs uint8_t flags; 575250661Sdavidcs#define Q8_MBX_FW_LRO_IPV4 0x1 576250661Sdavidcs#define Q8_MBX_FW_LRO_IPV6 0x2 577250661Sdavidcs#define Q8_MBX_FW_LRO_IPV4_WO_DST_IP_CHK 0x4 578250661Sdavidcs#define Q8_MBX_FW_LRO_IPV6_WO_DST_IP_CHK 0x8 579258457Sdavidcs#define Q8_MBX_FW_LRO_LOW_THRESHOLD 0x10 580250661Sdavidcs 581250661Sdavidcs uint8_t rsrvd; 582250661Sdavidcs uint16_t cntxt_id; 583258457Sdavidcs 584258457Sdavidcs uint16_t low_threshold; 585258457Sdavidcs uint16_t rsrvd0; 586250661Sdavidcs} __packed q80_config_fw_lro_t; 587250661Sdavidcs 588250661Sdavidcstypedef struct _q80_config_fw_lro_rsp { 589250661Sdavidcs uint16_t opcode; 590250661Sdavidcs uint16_t regcnt_status; 591250661Sdavidcs} __packed q80_config_fw_lro_rsp_t; 592250661Sdavidcs 593250661Sdavidcs/* 594250661Sdavidcs * Minidump mailbox commands 595250661Sdavidcs */ 596250661Sdavidcstypedef struct _q80_config_md_templ_size { 597250661Sdavidcs uint16_t opcode; 598250661Sdavidcs uint16_t count_version; 599250661Sdavidcs} __packed q80_config_md_templ_size_t; 600250661Sdavidcs 601250661Sdavidcstypedef struct _q80_config_md_templ_size_rsp { 602250661Sdavidcs uint16_t opcode; 603250661Sdavidcs uint16_t regcnt_status; 604250661Sdavidcs uint32_t rsrvd; 605250661Sdavidcs uint32_t templ_size; 606250661Sdavidcs uint32_t templ_version; 607250661Sdavidcs} __packed q80_config_md_templ_size_rsp_t; 608250661Sdavidcs 609250661Sdavidcstypedef struct _q80_config_md_templ_cmd { 610250661Sdavidcs uint16_t opcode; 611250661Sdavidcs uint16_t count_version; 612250661Sdavidcs uint64_t buf_addr; /* physical address of buffer */ 613250661Sdavidcs uint32_t buff_size; 614250661Sdavidcs uint32_t offset; 615250661Sdavidcs} __packed q80_config_md_templ_cmd_t; 616250661Sdavidcs 617250661Sdavidcstypedef struct _q80_config_md_templ_cmd_rsp { 618250661Sdavidcs uint16_t opcode; 619250661Sdavidcs uint16_t regcnt_status; 620250661Sdavidcs uint32_t rsrvd; 621250661Sdavidcs uint32_t templ_size; 622250661Sdavidcs uint32_t buff_size; 623250661Sdavidcs uint32_t offset; 624250661Sdavidcs} __packed q80_config_md_templ_cmd_rsp_t; 625250661Sdavidcs 626250661Sdavidcs/* 627305491Sdavidcs * Hardware Configuration Commands 628305491Sdavidcs */ 629305491Sdavidcs 630305491Sdavidcstypedef struct _q80_hw_config { 631305491Sdavidcs uint16_t opcode; 632305491Sdavidcs uint16_t count_version; 633305491Sdavidcs#define Q8_HW_CONFIG_SET_MDIO_REG_COUNT 0x06 634305491Sdavidcs#define Q8_HW_CONFIG_GET_MDIO_REG_COUNT 0x05 635305491Sdavidcs#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE_COUNT 0x03 636305491Sdavidcs#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE_COUNT 0x02 637305491Sdavidcs#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD_COUNT 0x03 638305491Sdavidcs#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD_COUNT 0x02 639305491Sdavidcs#define Q8_HW_CONFIG_GET_ECC_COUNTS_COUNT 0x02 640305491Sdavidcs 641305491Sdavidcs uint32_t cmd; 642305491Sdavidcs#define Q8_HW_CONFIG_SET_MDIO_REG 0x01 643305491Sdavidcs#define Q8_HW_CONFIG_GET_MDIO_REG 0x02 644305491Sdavidcs#define Q8_HW_CONFIG_SET_CAM_SEARCH_MODE 0x03 645305491Sdavidcs#define Q8_HW_CONFIG_GET_CAM_SEARCH_MODE 0x04 646305491Sdavidcs#define Q8_HW_CONFIG_SET_TEMP_THRESHOLD 0x07 647305491Sdavidcs#define Q8_HW_CONFIG_GET_TEMP_THRESHOLD 0x08 648305491Sdavidcs#define Q8_HW_CONFIG_GET_ECC_COUNTS 0x0A 649305491Sdavidcs 650305491Sdavidcs union { 651305491Sdavidcs struct { 652305491Sdavidcs uint32_t phys_port_number; 653305491Sdavidcs uint32_t phy_dev_addr; 654305491Sdavidcs uint32_t reg_addr; 655305491Sdavidcs uint32_t data; 656305491Sdavidcs } set_mdio; 657305491Sdavidcs 658305491Sdavidcs struct { 659305491Sdavidcs uint32_t phys_port_number; 660305491Sdavidcs uint32_t phy_dev_addr; 661305491Sdavidcs uint32_t reg_addr; 662305491Sdavidcs } get_mdio; 663305491Sdavidcs 664305491Sdavidcs struct { 665305491Sdavidcs uint32_t mode; 666305491Sdavidcs#define Q8_HW_CONFIG_CAM_SEARCH_MODE_INTERNAL 0x1 667305491Sdavidcs#define Q8_HW_CONFIG_CAM_SEARCH_MODE_AUTO 0x2 668305491Sdavidcs 669305491Sdavidcs } set_cam_search_mode; 670305491Sdavidcs 671305491Sdavidcs struct { 672305491Sdavidcs uint32_t value; 673305491Sdavidcs } set_temp_threshold; 674305491Sdavidcs } u; 675305491Sdavidcs} __packed q80_hw_config_t; 676305491Sdavidcs 677305491Sdavidcstypedef struct _q80_hw_config_rsp { 678305491Sdavidcs uint16_t opcode; 679305491Sdavidcs uint16_t regcnt_status; 680305491Sdavidcs 681305491Sdavidcs union { 682305491Sdavidcs struct { 683305491Sdavidcs uint32_t value; 684305491Sdavidcs } get_mdio; 685305491Sdavidcs 686305491Sdavidcs struct { 687305491Sdavidcs uint32_t mode; 688305491Sdavidcs } get_cam_search_mode; 689305491Sdavidcs 690305491Sdavidcs struct { 691305491Sdavidcs uint32_t temp_warn; 692305491Sdavidcs uint32_t curr_temp; 693305491Sdavidcs uint32_t osc_ring_rate; 694305491Sdavidcs uint32_t core_voltage; 695305491Sdavidcs } get_temp_threshold; 696305491Sdavidcs 697305491Sdavidcs struct { 698305491Sdavidcs uint32_t ddr_ecc_error_count; 699305491Sdavidcs uint32_t ocm_ecc_error_count; 700305491Sdavidcs uint32_t l2_dcache_ecc_error_count; 701305491Sdavidcs uint32_t l2_icache_ecc_error_count; 702305491Sdavidcs uint32_t eport_ecc_error_count; 703305491Sdavidcs } get_ecc_counts; 704305491Sdavidcs } u; 705305491Sdavidcs} __packed q80_hw_config_rsp_t; 706305491Sdavidcs 707305491Sdavidcs/* 708250661Sdavidcs * Link Event Request Command 709250661Sdavidcs */ 710250661Sdavidcstypedef struct _q80_link_event { 711250661Sdavidcs uint16_t opcode; 712250661Sdavidcs uint16_t count_version; 713250661Sdavidcs uint8_t cmd; 714250661Sdavidcs#define Q8_LINK_EVENT_CMD_STOP_PERIODIC 0 715250661Sdavidcs#define Q8_LINK_EVENT_CMD_ENABLE_ASYNC 1 716250661Sdavidcs 717250661Sdavidcs uint8_t flags; 718250661Sdavidcs#define Q8_LINK_EVENT_FLAGS_SEND_RSP 1 719250661Sdavidcs 720250661Sdavidcs uint16_t cntxt_id; 721250661Sdavidcs} __packed q80_link_event_t; 722250661Sdavidcs 723250661Sdavidcstypedef struct _q80_link_event_rsp { 724250661Sdavidcs uint16_t opcode; 725250661Sdavidcs uint16_t regcnt_status; 726250661Sdavidcs} __packed q80_link_event_rsp_t; 727250661Sdavidcs 728250661Sdavidcs/* 729250661Sdavidcs * Get Statistics Command 730250661Sdavidcs */ 731250661Sdavidcstypedef struct _q80_rcv_stats { 732250661Sdavidcs uint64_t total_bytes; 733250661Sdavidcs uint64_t total_pkts; 734250661Sdavidcs uint64_t lro_pkt_count; 735250661Sdavidcs uint64_t sw_pkt_count; 736250661Sdavidcs uint64_t ip_chksum_err; 737250661Sdavidcs uint64_t pkts_wo_acntxts; 738250661Sdavidcs uint64_t pkts_dropped_no_sds_card; 739250661Sdavidcs uint64_t pkts_dropped_no_sds_host; 740250661Sdavidcs uint64_t oversized_pkts; 741250661Sdavidcs uint64_t pkts_dropped_no_rds; 742250661Sdavidcs uint64_t unxpctd_mcast_pkts; 743250661Sdavidcs uint64_t re1_fbq_error; 744250661Sdavidcs uint64_t invalid_mac_addr; 745250661Sdavidcs uint64_t rds_prime_trys; 746250661Sdavidcs uint64_t rds_prime_success; 747250661Sdavidcs uint64_t lro_flows_added; 748250661Sdavidcs uint64_t lro_flows_deleted; 749250661Sdavidcs uint64_t lro_flows_active; 750250661Sdavidcs uint64_t pkts_droped_unknown; 751320368Sdavidcs uint64_t pkts_cnt_oversized; 752250661Sdavidcs} __packed q80_rcv_stats_t; 753250661Sdavidcs 754250661Sdavidcstypedef struct _q80_xmt_stats { 755250661Sdavidcs uint64_t total_bytes; 756250661Sdavidcs uint64_t total_pkts; 757250661Sdavidcs uint64_t errors; 758250661Sdavidcs uint64_t pkts_dropped; 759250661Sdavidcs uint64_t switch_pkts; 760250661Sdavidcs uint64_t num_buffers; 761250661Sdavidcs} __packed q80_xmt_stats_t; 762250661Sdavidcs 763250661Sdavidcstypedef struct _q80_mac_stats { 764250661Sdavidcs uint64_t xmt_frames; 765250661Sdavidcs uint64_t xmt_bytes; 766250661Sdavidcs uint64_t xmt_mcast_pkts; 767250661Sdavidcs uint64_t xmt_bcast_pkts; 768250661Sdavidcs uint64_t xmt_pause_frames; 769250661Sdavidcs uint64_t xmt_cntrl_pkts; 770250661Sdavidcs uint64_t xmt_pkt_lt_64bytes; 771250661Sdavidcs uint64_t xmt_pkt_lt_127bytes; 772250661Sdavidcs uint64_t xmt_pkt_lt_255bytes; 773250661Sdavidcs uint64_t xmt_pkt_lt_511bytes; 774250661Sdavidcs uint64_t xmt_pkt_lt_1023bytes; 775250661Sdavidcs uint64_t xmt_pkt_lt_1518bytes; 776250661Sdavidcs uint64_t xmt_pkt_gt_1518bytes; 777250661Sdavidcs uint64_t rsrvd0[3]; 778250661Sdavidcs uint64_t rcv_frames; 779250661Sdavidcs uint64_t rcv_bytes; 780250661Sdavidcs uint64_t rcv_mcast_pkts; 781250661Sdavidcs uint64_t rcv_bcast_pkts; 782250661Sdavidcs uint64_t rcv_pause_frames; 783250661Sdavidcs uint64_t rcv_cntrl_pkts; 784250661Sdavidcs uint64_t rcv_pkt_lt_64bytes; 785250661Sdavidcs uint64_t rcv_pkt_lt_127bytes; 786250661Sdavidcs uint64_t rcv_pkt_lt_255bytes; 787250661Sdavidcs uint64_t rcv_pkt_lt_511bytes; 788250661Sdavidcs uint64_t rcv_pkt_lt_1023bytes; 789250661Sdavidcs uint64_t rcv_pkt_lt_1518bytes; 790250661Sdavidcs uint64_t rcv_pkt_gt_1518bytes; 791250661Sdavidcs uint64_t rsrvd1[3]; 792250661Sdavidcs uint64_t rcv_len_error; 793250661Sdavidcs uint64_t rcv_len_small; 794250661Sdavidcs uint64_t rcv_len_large; 795250661Sdavidcs uint64_t rcv_jabber; 796250661Sdavidcs uint64_t rcv_dropped; 797250661Sdavidcs uint64_t fcs_error; 798250661Sdavidcs uint64_t align_error; 799284982Sdavidcs uint64_t eswitched_frames; 800284982Sdavidcs uint64_t eswitched_bytes; 801284982Sdavidcs uint64_t eswitched_mcast_frames; 802284982Sdavidcs uint64_t eswitched_bcast_frames; 803284982Sdavidcs uint64_t eswitched_ucast_frames; 804284982Sdavidcs uint64_t eswitched_err_free_frames; 805284982Sdavidcs uint64_t eswitched_err_free_bytes; 806250661Sdavidcs} __packed q80_mac_stats_t; 807250661Sdavidcs 808250661Sdavidcstypedef struct _q80_get_stats { 809250661Sdavidcs uint16_t opcode; 810250661Sdavidcs uint16_t count_version; 811250661Sdavidcs 812250661Sdavidcs uint32_t cmd; 813250661Sdavidcs#define Q8_GET_STATS_CMD_CLEAR 0x01 814250661Sdavidcs#define Q8_GET_STATS_CMD_RCV 0x00 815250661Sdavidcs#define Q8_GET_STATS_CMD_XMT 0x02 816250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_CNTXT 0x00 817250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_MAC 0x04 818250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_FUNC 0x08 819250661Sdavidcs#define Q8_GET_STATS_CMD_TYPE_VPORT 0x0C 820284982Sdavidcs#define Q8_GET_STATS_CMD_TYPE_ALL (0x7 << 2) 821250661Sdavidcs 822250661Sdavidcs} __packed q80_get_stats_t; 823250661Sdavidcs 824250661Sdavidcstypedef struct _q80_get_stats_rsp { 825250661Sdavidcs uint16_t opcode; 826250661Sdavidcs uint16_t regcnt_status; 827250661Sdavidcs uint32_t cmd; 828250661Sdavidcs union { 829250661Sdavidcs q80_rcv_stats_t rcv; 830250661Sdavidcs q80_xmt_stats_t xmt; 831250661Sdavidcs q80_mac_stats_t mac; 832250661Sdavidcs } u; 833250661Sdavidcs} __packed q80_get_stats_rsp_t; 834250661Sdavidcs 835284982Sdavidcstypedef struct _q80_get_mac_rcv_xmt_stats_rsp { 836284982Sdavidcs uint16_t opcode; 837284982Sdavidcs uint16_t regcnt_status; 838284982Sdavidcs uint32_t cmd; 839284982Sdavidcs q80_mac_stats_t mac; 840284982Sdavidcs q80_rcv_stats_t rcv; 841284982Sdavidcs q80_xmt_stats_t xmt; 842284982Sdavidcs} __packed q80_get_mac_rcv_xmt_stats_rsp_t; 843284982Sdavidcs 844250661Sdavidcs/* 845250661Sdavidcs * Init NIC Function 846250661Sdavidcs * Used to Register DCBX Configuration Change AEN 847250661Sdavidcs */ 848250661Sdavidcstypedef struct _q80_init_nic_func { 849250661Sdavidcs uint16_t opcode; 850250661Sdavidcs uint16_t count_version; 851250661Sdavidcs 852250661Sdavidcs uint32_t options; 853284982Sdavidcs#define Q8_INIT_NIC_REG_IDC_AEN 0x01 854250661Sdavidcs#define Q8_INIT_NIC_REG_DCBX_CHNG_AEN 0x02 855250661Sdavidcs#define Q8_INIT_NIC_REG_SFP_CHNG_AEN 0x04 856250661Sdavidcs 857250661Sdavidcs} __packed q80_init_nic_func_t; 858250661Sdavidcs 859250661Sdavidcstypedef struct _q80_init_nic_func_rsp { 860250661Sdavidcs uint16_t opcode; 861250661Sdavidcs uint16_t regcnt_status; 862250661Sdavidcs} __packed q80_init_nic_func_rsp_t; 863250661Sdavidcs 864250661Sdavidcs/* 865250661Sdavidcs * Stop NIC Function 866250661Sdavidcs * Used to DeRegister DCBX Configuration Change AEN 867250661Sdavidcs */ 868250661Sdavidcstypedef struct _q80_stop_nic_func { 869250661Sdavidcs uint16_t opcode; 870250661Sdavidcs uint16_t count_version; 871250661Sdavidcs 872250661Sdavidcs uint32_t options; 873250661Sdavidcs#define Q8_STOP_NIC_DEREG_DCBX_CHNG_AEN 0x02 874250661Sdavidcs#define Q8_STOP_NIC_DEREG_SFP_CHNG_AEN 0x04 875250661Sdavidcs 876250661Sdavidcs} __packed q80_stop_nic_func_t; 877250661Sdavidcs 878250661Sdavidcstypedef struct _q80_stop_nic_func_rsp { 879250661Sdavidcs uint16_t opcode; 880250661Sdavidcs uint16_t regcnt_status; 881250661Sdavidcs} __packed q80_stop_nic_func_rsp_t; 882250661Sdavidcs 883250661Sdavidcs/* 884250661Sdavidcs * Query Firmware DCBX Capabilities 885250661Sdavidcs */ 886250661Sdavidcstypedef struct _q80_query_fw_dcbx_caps { 887250661Sdavidcs uint16_t opcode; 888250661Sdavidcs uint16_t count_version; 889250661Sdavidcs} __packed q80_query_fw_dcbx_caps_t; 890250661Sdavidcs 891250661Sdavidcstypedef struct _q80_query_fw_dcbx_caps_rsp { 892250661Sdavidcs uint16_t opcode; 893250661Sdavidcs uint16_t regcnt_status; 894250661Sdavidcs 895250661Sdavidcs uint32_t dcbx_caps; 896250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_TSA 0x00000001 897250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_ETS 0x00000002 898250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_DCBX_CEE_1_01 0x00000004 899250661Sdavidcs#define Q8_QUERY_FW_DCBX_CAPS_DCBX_IEEE_1_0 0x00000008 900250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_TC_MASK 0x00F00000 901250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_ETS_TC_MASK 0x0F000000 902250661Sdavidcs#define Q8_QUERY_FW_DCBX_MAX_PFC_TC_MASK 0xF0000000 903250661Sdavidcs 904250661Sdavidcs} __packed q80_query_fw_dcbx_caps_rsp_t; 905250661Sdavidcs 906250661Sdavidcs/* 907284982Sdavidcs * IDC Ack Cmd 908284982Sdavidcs */ 909284982Sdavidcs 910284982Sdavidcstypedef struct _q80_idc_ack { 911284982Sdavidcs uint16_t opcode; 912284982Sdavidcs uint16_t count_version; 913284982Sdavidcs 914284982Sdavidcs uint32_t aen_mb1; 915284982Sdavidcs uint32_t aen_mb2; 916284982Sdavidcs uint32_t aen_mb3; 917284982Sdavidcs uint32_t aen_mb4; 918284982Sdavidcs 919284982Sdavidcs} __packed q80_idc_ack_t; 920284982Sdavidcs 921284982Sdavidcstypedef struct _q80_idc_ack_rsp { 922284982Sdavidcs uint16_t opcode; 923284982Sdavidcs uint16_t regcnt_status; 924284982Sdavidcs} __packed q80_idc_ack_rsp_t; 925284982Sdavidcs 926284982Sdavidcs 927284982Sdavidcs/* 928250661Sdavidcs * Set Port Configuration command 929250661Sdavidcs * Used to set Ethernet Standard Pause values 930250661Sdavidcs */ 931250661Sdavidcs 932250661Sdavidcstypedef struct _q80_set_port_cfg { 933250661Sdavidcs uint16_t opcode; 934250661Sdavidcs uint16_t count_version; 935250661Sdavidcs 936250661Sdavidcs uint32_t cfg_bits; 937250661Sdavidcs 938250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_MASK (0x7 << 1) 939250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE (0x0 << 1) 940250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS (0x2 << 1) 941250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_PHY (0x3 << 1) 942250661Sdavidcs#define Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT (0x4 << 1) 943250661Sdavidcs 944250661Sdavidcs#define Q8_VALID_LOOPBACK_MODE(mode) \ 945250661Sdavidcs (((mode) == Q8_PORT_CFG_BITS_LOOPBACK_MODE_NONE) || \ 946250661Sdavidcs (((mode) >= Q8_PORT_CFG_BITS_LOOPBACK_MODE_HSS) && \ 947250661Sdavidcs ((mode) <= Q8_PORT_CFG_BITS_LOOPBACK_MODE_EXT))) 948250661Sdavidcs 949250661Sdavidcs#define Q8_PORT_CFG_BITS_DCBX_ENABLE BIT_4 950250661Sdavidcs 951250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 5) 952250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_DISABLED (0x0 << 5) 953250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_STD (0x1 << 5) 954250661Sdavidcs#define Q8_PORT_CFG_BITS_PAUSE_PPM (0x2 << 5) 955250661Sdavidcs 956250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_10MB BIT_8 957250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_100MB BIT_9 958250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_1GB BIT_10 959250661Sdavidcs#define Q8_PORT_CFG_BITS_LNKCAP_10GB BIT_11 960250661Sdavidcs 961250661Sdavidcs#define Q8_PORT_CFG_BITS_AUTONEG BIT_15 962250661Sdavidcs#define Q8_PORT_CFG_BITS_XMT_DISABLE BIT_17 963250661Sdavidcs#define Q8_PORT_CFG_BITS_FEC_RQSTD BIT_18 964250661Sdavidcs#define Q8_PORT_CFG_BITS_EEE_RQSTD BIT_19 965250661Sdavidcs 966250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 967250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_XMT_RCV (0x0 << 20) 968250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 969250661Sdavidcs#define Q8_PORT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 970250661Sdavidcs 971250661Sdavidcs} __packed q80_set_port_cfg_t; 972250661Sdavidcs 973250661Sdavidcstypedef struct _q80_set_port_cfg_rsp { 974250661Sdavidcs uint16_t opcode; 975250661Sdavidcs uint16_t regcnt_status; 976250661Sdavidcs} __packed q80_set_port_cfg_rsp_t; 977250661Sdavidcs 978250661Sdavidcs/* 979250661Sdavidcs * Get Port Configuration Command 980250661Sdavidcs */ 981250661Sdavidcs 982250661Sdavidcstypedef struct _q80_get_port_cfg { 983250661Sdavidcs uint16_t opcode; 984250661Sdavidcs uint16_t count_version; 985250661Sdavidcs} __packed q80_get_port_cfg_t; 986250661Sdavidcs 987250661Sdavidcstypedef struct _q80_get_port_cfg_rsp { 988250661Sdavidcs uint16_t opcode; 989250661Sdavidcs uint16_t regcnt_status; 990250661Sdavidcs 991250661Sdavidcs uint32_t cfg_bits; /* same as in q80_set_port_cfg_t */ 992250661Sdavidcs 993250661Sdavidcs uint8_t phys_port_type; 994250661Sdavidcs uint8_t rsvd[3]; 995250661Sdavidcs} __packed q80_get_port_cfg_rsp_t; 996250661Sdavidcs 997250661Sdavidcs/* 998250661Sdavidcs * Get Link Status Command 999250661Sdavidcs * Used to get current PAUSE values for the port 1000250661Sdavidcs */ 1001250661Sdavidcs 1002250661Sdavidcstypedef struct _q80_get_link_status { 1003250661Sdavidcs uint16_t opcode; 1004250661Sdavidcs uint16_t count_version; 1005250661Sdavidcs} __packed q80_get_link_status_t; 1006250661Sdavidcs 1007250661Sdavidcstypedef struct _q80_get_link_status_rsp { 1008250661Sdavidcs uint16_t opcode; 1009250661Sdavidcs uint16_t regcnt_status; 1010250661Sdavidcs 1011250661Sdavidcs uint32_t cfg_bits; 1012250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_UP BIT_0 1013250661Sdavidcs 1014250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_MASK (0x7 << 3) 1015250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_UNKNOWN (0x0 << 3) 1016250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10MB (0x1 << 3) 1017250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_100MB (0x2 << 3) 1018250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_1GB (0x3 << 3) 1019250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LINK_SPEED_10GB (0x4 << 3) 1020250661Sdavidcs 1021250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_MASK (0x3 << 6) 1022250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_DISABLE (0x0 << 6) 1023250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_STD (0x1 << 6) 1024250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_PAUSE_CFG_PPM (0x2 << 6) 1025250661Sdavidcs 1026250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_MASK (0x7 << 8) 1027250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_NONE (0x0 << 6) 1028250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_HSS (0x2 << 6) 1029250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_LOOPBACK_PHY (0x3 << 6) 1030250661Sdavidcs 1031250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_FEC_ENABLED BIT_12 1032250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_EEE_ENABLED BIT_13 1033250661Sdavidcs 1034250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_DIR_MASK (0x3 << 20) 1035250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_NONE (0x0 << 20) 1036250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT (0x1 << 20) 1037250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_RCV (0x2 << 20) 1038250661Sdavidcs#define Q8_GET_LINK_STAT_CFG_BITS_STDPAUSE_XMT_RCV (0x3 << 20) 1039250661Sdavidcs 1040250661Sdavidcs uint32_t link_state; 1041250661Sdavidcs#define Q8_GET_LINK_STAT_LOSS_OF_SIGNAL BIT_0 1042250661Sdavidcs#define Q8_GET_LINK_STAT_PORT_RST_DONE BIT_3 1043250661Sdavidcs#define Q8_GET_LINK_STAT_PHY_LINK_DOWN BIT_4 1044250661Sdavidcs#define Q8_GET_LINK_STAT_PCS_LINK_DOWN BIT_5 1045250661Sdavidcs#define Q8_GET_LINK_STAT_MAC_LOCAL_FAULT BIT_6 1046250661Sdavidcs#define Q8_GET_LINK_STAT_MAC_REMOTE_FAULT BIT_7 1047250661Sdavidcs#define Q8_GET_LINK_STAT_XMT_DISABLED BIT_9 1048250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 1049250661Sdavidcs 1050250661Sdavidcs uint32_t sfp_info; 1051250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_MASK 0x3 1052250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_NOT_EXPECTED 0x0 1053250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_NONE 0x1 1054250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_INVALID 0x2 1055250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_TRNCVR_VALID 0x3 1056250661Sdavidcs 1057250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_MASK (0x3 << 2) 1058250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_UNREC_TRSVR (0x0 << 2) 1059250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_NOT_QLOGIC (0x1 << 2) 1060250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_SPEED_FAILED (0x2 << 2) 1061250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_ADDTL_INFO_ACCESS_ERROR (0x3 << 2) 1062250661Sdavidcs 1063250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_TYPE_MASK (0x1F << 4) 1064250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_NONE (0x00 << 4) 1065250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBLRM (0x01 << 4) 1066250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBLR (0x02 << 4) 1067250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBSR (0x03 << 4) 1068250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_P (0x04 << 4) 1069250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_AL (0x05 << 4) 1070250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_10GBC_PL (0x06 << 4) 1071250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBSX (0x07 << 4) 1072250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBLX (0x08 << 4) 1073250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBCX (0x09 << 4) 1074250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBT (0x0A << 4) 1075250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_1GBC_PL (0x0B << 4) 1076250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MOD_UNKNOWN (0x0F << 4) 1077250661Sdavidcs 1078250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_MULTI_RATE_MOD BIT_9 1079250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_XMT_FAULT BIT_10 1080250661Sdavidcs#define Q8_GET_LINK_STAT_SFP_COPPER_CBL_LENGTH_MASK (0xFF << 16) 1081250661Sdavidcs 1082250661Sdavidcs} __packed q80_get_link_status_rsp_t; 1083250661Sdavidcs 1084250661Sdavidcs 1085250661Sdavidcs/* 1086250661Sdavidcs * Transmit Related Definitions 1087250661Sdavidcs */ 1088250661Sdavidcs/* Max# of TX Rings per Tx Create Cntxt Mbx Cmd*/ 1089250661Sdavidcs#define MAX_TCNTXT_RINGS 8 1090250661Sdavidcs 1091250661Sdavidcs/* 1092250661Sdavidcs * Transmit Context - Q8_CMD_CREATE_TX_CNTXT Command Configuration Data 1093250661Sdavidcs */ 1094250661Sdavidcs 1095250661Sdavidcstypedef struct _q80_rq_tx_ring { 1096250661Sdavidcs uint64_t paddr; 1097250661Sdavidcs uint64_t tx_consumer; 1098250661Sdavidcs uint16_t nentries; 1099250661Sdavidcs uint16_t intr_id; 1100250661Sdavidcs uint8_t intr_src_bit; 1101250661Sdavidcs uint8_t rsrvd[3]; 1102250661Sdavidcs} __packed q80_rq_tx_ring_t; 1103250661Sdavidcs 1104250661Sdavidcstypedef struct _q80_rq_tx_cntxt { 1105250661Sdavidcs uint16_t opcode; 1106250661Sdavidcs uint16_t count_version; 1107250661Sdavidcs 1108250661Sdavidcs uint32_t cap0; 1109250661Sdavidcs#define Q8_TX_CNTXT_CAP0_BASEFW (1 << 0) 1110250661Sdavidcs#define Q8_TX_CNTXT_CAP0_LSO (1 << 6) 1111250661Sdavidcs#define Q8_TX_CNTXT_CAP0_TC (1 << 25) 1112250661Sdavidcs 1113250661Sdavidcs uint32_t cap1; 1114250661Sdavidcs uint32_t cap2; 1115250661Sdavidcs uint32_t cap3; 1116250661Sdavidcs uint8_t ntx_rings; 1117250661Sdavidcs uint8_t traffic_class; /* bits 8-10; others reserved */ 1118250661Sdavidcs uint16_t tx_vpid; 1119250661Sdavidcs q80_rq_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1120250661Sdavidcs} __packed q80_rq_tx_cntxt_t; 1121250661Sdavidcs 1122250661Sdavidcstypedef struct _q80_rsp_tx_ring { 1123250661Sdavidcs uint32_t prod_index; 1124250661Sdavidcs uint16_t cntxt_id; 1125250661Sdavidcs uint8_t state; 1126250661Sdavidcs uint8_t rsrvd; 1127250661Sdavidcs} q80_rsp_tx_ring_t; 1128250661Sdavidcs 1129250661Sdavidcstypedef struct _q80_rsp_tx_cntxt { 1130250661Sdavidcs uint16_t opcode; 1131250661Sdavidcs uint16_t regcnt_status; 1132250661Sdavidcs uint8_t ntx_rings; 1133250661Sdavidcs uint8_t phy_port; 1134250661Sdavidcs uint8_t virt_port; 1135250661Sdavidcs uint8_t rsrvd; 1136250661Sdavidcs q80_rsp_tx_ring_t tx_ring[MAX_TCNTXT_RINGS]; 1137250661Sdavidcs} __packed q80_rsp_tx_cntxt_t; 1138250661Sdavidcs 1139250661Sdavidcstypedef struct _q80_tx_cntxt_destroy { 1140250661Sdavidcs uint16_t opcode; 1141250661Sdavidcs uint16_t count_version; 1142250661Sdavidcs uint32_t cntxt_id; 1143250661Sdavidcs} __packed q80_tx_cntxt_destroy_t; 1144250661Sdavidcs 1145250661Sdavidcstypedef struct _q80_tx_cntxt_destroy_rsp { 1146250661Sdavidcs uint16_t opcode; 1147250661Sdavidcs uint16_t regcnt_status; 1148250661Sdavidcs} __packed q80_tx_cntxt_destroy_rsp_t; 1149250661Sdavidcs 1150250661Sdavidcs/* 1151250661Sdavidcs * Transmit Command Descriptor 1152250661Sdavidcs * These commands are issued on the Transmit Ring associated with a Transmit 1153250661Sdavidcs * context 1154250661Sdavidcs */ 1155250661Sdavidcstypedef struct _q80_tx_cmd { 1156250661Sdavidcs uint8_t tcp_hdr_off; /* TCP Header Offset */ 1157250661Sdavidcs uint8_t ip_hdr_off; /* IP Header Offset */ 1158250661Sdavidcs uint16_t flags_opcode; /* Bits 0-6: flags; 7-12: opcode */ 1159250661Sdavidcs 1160250661Sdavidcs /* flags field */ 1161250661Sdavidcs#define Q8_TX_CMD_FLAGS_MULTICAST 0x01 1162250661Sdavidcs#define Q8_TX_CMD_FLAGS_LSO_TSO 0x02 1163250661Sdavidcs#define Q8_TX_CMD_FLAGS_VLAN_TAGGED 0x10 1164250661Sdavidcs#define Q8_TX_CMD_FLAGS_HW_VLAN_ID 0x40 1165250661Sdavidcs 1166250661Sdavidcs /* opcode field */ 1167250661Sdavidcs#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM_IPV6 (0xC << 7) 1168250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM_IPV6 (0xB << 7) 1169250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_LSO_IPV6 (0x6 << 7) 1170250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_LSO (0x5 << 7) 1171250661Sdavidcs#define Q8_TX_CMD_OP_XMT_UDP_CHKSUM (0x3 << 7) 1172250661Sdavidcs#define Q8_TX_CMD_OP_XMT_TCP_CHKSUM (0x2 << 7) 1173250661Sdavidcs#define Q8_TX_CMD_OP_XMT_ETHER (0x1 << 7) 1174250661Sdavidcs 1175250661Sdavidcs uint8_t n_bufs; /* # of data segs in data buffer */ 1176250661Sdavidcs uint8_t data_len_lo; /* data length lower 8 bits */ 1177250661Sdavidcs uint16_t data_len_hi; /* data length upper 16 bits */ 1178250661Sdavidcs 1179250661Sdavidcs uint64_t buf2_addr; /* buffer 2 address */ 1180250661Sdavidcs 1181250661Sdavidcs uint16_t rsrvd0; 1182250661Sdavidcs uint16_t mss; /* MSS for this packet */ 1183250661Sdavidcs uint8_t cntxtid; /* Bits 7-4: ContextId; 3-0: reserved */ 1184250661Sdavidcs 1185250661Sdavidcs#define Q8_TX_CMD_PORT_CNXTID(c_id) ((c_id & 0xF) << 4) 1186250661Sdavidcs 1187250661Sdavidcs uint8_t total_hdr_len; /* MAC+IP+TCP Header Length for LSO */ 1188250661Sdavidcs uint16_t rsrvd1; 1189250661Sdavidcs 1190250661Sdavidcs uint64_t buf3_addr; /* buffer 3 address */ 1191250661Sdavidcs uint64_t buf1_addr; /* buffer 1 address */ 1192250661Sdavidcs 1193250661Sdavidcs uint16_t buf1_len; /* length of buffer 1 */ 1194250661Sdavidcs uint16_t buf2_len; /* length of buffer 2 */ 1195250661Sdavidcs uint16_t buf3_len; /* length of buffer 3 */ 1196250661Sdavidcs uint16_t buf4_len; /* length of buffer 4 */ 1197250661Sdavidcs 1198250661Sdavidcs uint64_t buf4_addr; /* buffer 4 address */ 1199250661Sdavidcs 1200250661Sdavidcs uint32_t rsrvd2; 1201250661Sdavidcs uint16_t rsrvd3; 1202250661Sdavidcs uint16_t vlan_tci; /* VLAN TCI when hw tagging is enabled*/ 1203250661Sdavidcs 1204250661Sdavidcs} __packed q80_tx_cmd_t; /* 64 bytes */ 1205250661Sdavidcs 1206250661Sdavidcs#define Q8_TX_CMD_MAX_SEGMENTS 4 1207250661Sdavidcs#define Q8_TX_CMD_TSO_ALIGN 2 1208250661Sdavidcs#define Q8_TX_MAX_NON_TSO_SEGS 62 1209250661Sdavidcs 1210250661Sdavidcs 1211250661Sdavidcs/* 1212250661Sdavidcs * Receive Related Definitions 1213250661Sdavidcs */ 1214250661Sdavidcs#define MAX_RDS_RING_SETS 8 /* Max# of Receive Descriptor Rings */ 1215284982Sdavidcs 1216284982Sdavidcs#ifdef QL_ENABLE_ISCSI_TLV 1217284982Sdavidcs#define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ 1218284982Sdavidcs#define NUM_TX_RINGS (MAX_SDS_RINGS * 2) 1219284982Sdavidcs#else 1220322975Sdavidcs#define MAX_SDS_RINGS 32 /* Max# of Status Descriptor Rings */ 1221284982Sdavidcs#define NUM_TX_RINGS MAX_SDS_RINGS 1222284982Sdavidcs#endif /* #ifdef QL_ENABLE_ISCSI_TLV */ 1223284982Sdavidcs#define MAX_RDS_RINGS MAX_SDS_RINGS /* Max# of Rcv Descriptor Rings */ 1224250661Sdavidcs 1225284982Sdavidcs 1226250661Sdavidcstypedef struct _q80_rq_sds_ring { 1227250661Sdavidcs uint64_t paddr; /* physical addr of status ring in system memory */ 1228250661Sdavidcs uint64_t hdr_split1; 1229250661Sdavidcs uint64_t hdr_split2; 1230250661Sdavidcs uint16_t size; /* number of entries in status ring */ 1231250661Sdavidcs uint16_t hdr_split1_size; 1232250661Sdavidcs uint16_t hdr_split2_size; 1233250661Sdavidcs uint16_t hdr_split_count; 1234250661Sdavidcs uint16_t intr_id; 1235250661Sdavidcs uint8_t intr_src_bit; 1236250661Sdavidcs uint8_t rsrvd[5]; 1237250661Sdavidcs} __packed q80_rq_sds_ring_t; /* 10 32bit words */ 1238250661Sdavidcs 1239250661Sdavidcstypedef struct _q80_rq_rds_ring { 1240250661Sdavidcs uint64_t paddr_std; /* physical addr of rcv ring in system memory */ 1241250661Sdavidcs uint64_t paddr_jumbo; /* physical addr of rcv ring in system memory */ 1242250661Sdavidcs uint16_t std_bsize; 1243250661Sdavidcs uint16_t std_nentries; 1244250661Sdavidcs uint16_t jumbo_bsize; 1245250661Sdavidcs uint16_t jumbo_nentries; 1246250661Sdavidcs} __packed q80_rq_rds_ring_t; /* 6 32bit words */ 1247250661Sdavidcs 1248250661Sdavidcs#define MAX_RCNTXT_SDS_RINGS 8 1249250661Sdavidcs 1250250661Sdavidcstypedef struct _q80_rq_rcv_cntxt { 1251250661Sdavidcs uint16_t opcode; 1252250661Sdavidcs uint16_t count_version; 1253250661Sdavidcs uint32_t cap0; 1254250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_BASEFW (1 << 0) 1255250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_MULTI_RDS (1 << 1) 1256250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_LRO (1 << 5) 1257250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_HW_LRO (1 << 10) 1258250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_VLAN_ALIGN (1 << 14) 1259250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_RSS (1 << 15) 1260250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_MSFT_RSS (1 << 16) 1261250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_SGL_JUMBO (1 << 18) 1262250661Sdavidcs#define Q8_RCV_CNTXT_CAP0_SGL_LRO (1 << 19) 1263284982Sdavidcs#define Q8_RCV_CNTXT_CAP0_SINGLE_JUMBO (1 << 26) 1264250661Sdavidcs 1265250661Sdavidcs uint32_t cap1; 1266250661Sdavidcs uint32_t cap2; 1267250661Sdavidcs uint32_t cap3; 1268250661Sdavidcs uint8_t nrds_sets_rings; 1269250661Sdavidcs uint8_t nsds_rings; 1270250661Sdavidcs uint16_t rds_producer_mode; 1271250661Sdavidcs#define Q8_RCV_CNTXT_RDS_PROD_MODE_UNIQUE 0 1272250661Sdavidcs#define Q8_RCV_CNTXT_RDS_PROD_MODE_SHARED 1 1273250661Sdavidcs 1274250661Sdavidcs uint16_t rcv_vpid; 1275250661Sdavidcs uint16_t rsrvd0; 1276250661Sdavidcs uint32_t rsrvd1; 1277250661Sdavidcs q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1278250661Sdavidcs q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1279250661Sdavidcs} __packed q80_rq_rcv_cntxt_t; 1280250661Sdavidcs 1281250661Sdavidcstypedef struct _q80_rsp_rds_ring { 1282250661Sdavidcs uint32_t prod_std; 1283250661Sdavidcs uint32_t prod_jumbo; 1284250661Sdavidcs} __packed q80_rsp_rds_ring_t; /* 8 bytes */ 1285250661Sdavidcs 1286250661Sdavidcstypedef struct _q80_rsp_rcv_cntxt { 1287250661Sdavidcs uint16_t opcode; 1288250661Sdavidcs uint16_t regcnt_status; 1289250661Sdavidcs uint8_t nrds_sets_rings; 1290250661Sdavidcs uint8_t nsds_rings; 1291250661Sdavidcs uint16_t cntxt_id; 1292250661Sdavidcs uint8_t state; 1293250661Sdavidcs uint8_t num_funcs; 1294250661Sdavidcs uint8_t phy_port; 1295250661Sdavidcs uint8_t virt_port; 1296250661Sdavidcs uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1297250661Sdavidcs q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1298250661Sdavidcs} __packed q80_rsp_rcv_cntxt_t; 1299250661Sdavidcs 1300250661Sdavidcstypedef struct _q80_rcv_cntxt_destroy { 1301250661Sdavidcs uint16_t opcode; 1302250661Sdavidcs uint16_t count_version; 1303250661Sdavidcs uint32_t cntxt_id; 1304250661Sdavidcs} __packed q80_rcv_cntxt_destroy_t; 1305250661Sdavidcs 1306250661Sdavidcstypedef struct _q80_rcv_cntxt_destroy_rsp { 1307250661Sdavidcs uint16_t opcode; 1308250661Sdavidcs uint16_t regcnt_status; 1309250661Sdavidcs} __packed q80_rcv_cntxt_destroy_rsp_t; 1310250661Sdavidcs 1311250661Sdavidcs 1312250661Sdavidcs/* 1313250661Sdavidcs * Add Receive Rings 1314250661Sdavidcs */ 1315250661Sdavidcstypedef struct _q80_rq_add_rcv_rings { 1316250661Sdavidcs uint16_t opcode; 1317250661Sdavidcs uint16_t count_version; 1318250661Sdavidcs uint8_t nrds_sets_rings; 1319250661Sdavidcs uint8_t nsds_rings; 1320250661Sdavidcs uint16_t cntxt_id; 1321250661Sdavidcs q80_rq_sds_ring_t sds[MAX_RCNTXT_SDS_RINGS]; 1322250661Sdavidcs q80_rq_rds_ring_t rds[MAX_RDS_RING_SETS]; 1323250661Sdavidcs} __packed q80_rq_add_rcv_rings_t; 1324250661Sdavidcs 1325250661Sdavidcstypedef struct _q80_rsp_add_rcv_rings { 1326250661Sdavidcs uint16_t opcode; 1327250661Sdavidcs uint16_t regcnt_status; 1328250661Sdavidcs uint8_t nrds_sets_rings; 1329250661Sdavidcs uint8_t nsds_rings; 1330250661Sdavidcs uint16_t cntxt_id; 1331250661Sdavidcs uint32_t sds_cons[MAX_RCNTXT_SDS_RINGS]; 1332250661Sdavidcs q80_rsp_rds_ring_t rds[MAX_RDS_RING_SETS]; 1333250661Sdavidcs} __packed q80_rsp_add_rcv_rings_t; 1334250661Sdavidcs 1335250661Sdavidcs/* 1336250661Sdavidcs * Map Status Ring to Receive Descriptor Set 1337250661Sdavidcs */ 1338250661Sdavidcs 1339250661Sdavidcs#define MAX_SDS_TO_RDS_MAP 16 1340250661Sdavidcs 1341250661Sdavidcstypedef struct _q80_sds_rds_map_e { 1342250661Sdavidcs uint8_t sds_ring; 1343250661Sdavidcs uint8_t rsrvd0; 1344250661Sdavidcs uint8_t rds_ring; 1345250661Sdavidcs uint8_t rsrvd1; 1346250661Sdavidcs} __packed q80_sds_rds_map_e_t; 1347250661Sdavidcs 1348250661Sdavidcstypedef struct _q80_rq_map_sds_to_rds { 1349250661Sdavidcs uint16_t opcode; 1350250661Sdavidcs uint16_t count_version; 1351250661Sdavidcs uint16_t cntxt_id; 1352250661Sdavidcs uint16_t num_rings; 1353250661Sdavidcs q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1354250661Sdavidcs} __packed q80_rq_map_sds_to_rds_t; 1355250661Sdavidcs 1356250661Sdavidcs 1357250661Sdavidcstypedef struct _q80_rsp_map_sds_to_rds { 1358250661Sdavidcs uint16_t opcode; 1359250661Sdavidcs uint16_t regcnt_status; 1360250661Sdavidcs uint16_t cntxt_id; 1361250661Sdavidcs uint16_t num_rings; 1362250661Sdavidcs q80_sds_rds_map_e_t sds_rds[MAX_SDS_TO_RDS_MAP]; 1363250661Sdavidcs} __packed q80_rsp_map_sds_to_rds_t; 1364250661Sdavidcs 1365250661Sdavidcs 1366250661Sdavidcs/* 1367250661Sdavidcs * Receive Descriptor corresponding to each entry in the receive ring 1368250661Sdavidcs */ 1369250661Sdavidcstypedef struct _q80_rcv_desc { 1370250661Sdavidcs uint16_t handle; 1371250661Sdavidcs uint16_t rsrvd; 1372250661Sdavidcs uint32_t buf_size; /* buffer size in bytes */ 1373250661Sdavidcs uint64_t buf_addr; /* physical address of buffer */ 1374250661Sdavidcs} __packed q80_recv_desc_t; 1375250661Sdavidcs 1376250661Sdavidcs/* 1377250661Sdavidcs * Status Descriptor corresponding to each entry in the Status ring 1378250661Sdavidcs */ 1379250661Sdavidcstypedef struct _q80_stat_desc { 1380250661Sdavidcs uint64_t data[2]; 1381250661Sdavidcs} __packed q80_stat_desc_t; 1382250661Sdavidcs 1383250661Sdavidcs/* 1384250661Sdavidcs * definitions for data[0] field of Status Descriptor 1385250661Sdavidcs */ 1386250661Sdavidcs#define Q8_STAT_DESC_RSS_HASH(data) (data & 0xFFFFFFFF) 1387250661Sdavidcs#define Q8_STAT_DESC_TOTAL_LENGTH(data) ((data >> 32) & 0x3FFF) 1388250661Sdavidcs#define Q8_STAT_DESC_TOTAL_LENGTH_SGL_RCV(data) ((data >> 32) & 0xFFFF) 1389250661Sdavidcs#define Q8_STAT_DESC_HANDLE(data) ((data >> 48) & 0xFFFF) 1390250661Sdavidcs/* 1391250661Sdavidcs * definitions for data[1] field of Status Descriptor 1392250661Sdavidcs */ 1393250661Sdavidcs 1394250661Sdavidcs#define Q8_STAT_DESC_OPCODE(data) ((data >> 42) & 0xF) 1395250661Sdavidcs#define Q8_STAT_DESC_OPCODE_RCV_PKT 0x01 1396250661Sdavidcs#define Q8_STAT_DESC_OPCODE_LRO_PKT 0x02 1397250661Sdavidcs#define Q8_STAT_DESC_OPCODE_SGL_LRO 0x04 1398250661Sdavidcs#define Q8_STAT_DESC_OPCODE_SGL_RCV 0x05 1399250661Sdavidcs#define Q8_STAT_DESC_OPCODE_CONT 0x06 1400250661Sdavidcs 1401250661Sdavidcs/* 1402250661Sdavidcs * definitions for data[1] field of Status Descriptor for standard frames 1403250661Sdavidcs * status descriptor opcode equals 0x04 1404250661Sdavidcs */ 1405250661Sdavidcs#define Q8_STAT_DESC_STATUS(data) ((data >> 39) & 0x0007) 1406250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_NOT_DONE 0x00 1407250661Sdavidcs#define Q8_STAT_DESC_STATUS_NO_CHKSUM 0x01 1408250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_OK 0x02 1409250661Sdavidcs#define Q8_STAT_DESC_STATUS_CHKSUM_ERR 0x03 1410250661Sdavidcs 1411250661Sdavidcs#define Q8_STAT_DESC_VLAN(data) ((data >> 47) & 1) 1412250661Sdavidcs#define Q8_STAT_DESC_VLAN_ID(data) ((data >> 48) & 0xFFFF) 1413250661Sdavidcs 1414250661Sdavidcs#define Q8_STAT_DESC_PROTOCOL(data) ((data >> 44) & 0x000F) 1415250661Sdavidcs#define Q8_STAT_DESC_L2_OFFSET(data) ((data >> 48) & 0x001F) 1416250661Sdavidcs#define Q8_STAT_DESC_COUNT(data) ((data >> 37) & 0x0007) 1417250661Sdavidcs 1418250661Sdavidcs/* 1419250661Sdavidcs * definitions for data[0-1] fields of Status Descriptor for LRO 1420250661Sdavidcs * status descriptor opcode equals 0x04 1421250661Sdavidcs */ 1422250661Sdavidcs 1423250661Sdavidcs/* definitions for data[1] field */ 1424250661Sdavidcs#define Q8_LRO_STAT_DESC_SEQ_NUM(data) (uint32_t)(data) 1425250661Sdavidcs 1426250661Sdavidcs/* 1427250661Sdavidcs * definitions specific to opcode 0x04 data[1] 1428250661Sdavidcs */ 1429250661Sdavidcs#define Q8_STAT_DESC_COUNT_SGL_LRO(data) ((data >> 13) & 0x0007) 1430250661Sdavidcs#define Q8_SGL_LRO_STAT_L2_OFFSET(data) ((data >> 16) & 0xFF) 1431250661Sdavidcs#define Q8_SGL_LRO_STAT_L4_OFFSET(data) ((data >> 24) & 0xFF) 1432250661Sdavidcs#define Q8_SGL_LRO_STAT_TS(data) ((data >> 40) & 0x1) 1433250661Sdavidcs#define Q8_SGL_LRO_STAT_PUSH_BIT(data) ((data >> 41) & 0x1) 1434250661Sdavidcs 1435250661Sdavidcs 1436250661Sdavidcs/* 1437250661Sdavidcs * definitions specific to opcode 0x05 data[1] 1438250661Sdavidcs */ 1439250661Sdavidcs#define Q8_STAT_DESC_COUNT_SGL_RCV(data) ((data >> 37) & 0x0003) 1440250661Sdavidcs 1441250661Sdavidcs/* 1442250661Sdavidcs * definitions for opcode 0x06 1443250661Sdavidcs */ 1444250661Sdavidcs/* definitions for data[0] field */ 1445250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE1(data) (data & 0xFFFF) 1446250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE2(data) ((data >> 16) & 0xFFFF) 1447250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE3(data) ((data >> 32) & 0xFFFF) 1448250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE4(data) ((data >> 48) & 0xFFFF) 1449250661Sdavidcs 1450250661Sdavidcs/* definitions for data[1] field */ 1451250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE5(data) (data & 0xFFFF) 1452250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE6(data) ((data >> 16) & 0xFFFF) 1453250661Sdavidcs#define Q8_SGL_STAT_DESC_NUM_HANDLES(data) ((data >> 32) & 0x7) 1454250661Sdavidcs#define Q8_SGL_STAT_DESC_HANDLE7(data) ((data >> 48) & 0xFFFF) 1455250661Sdavidcs 1456250661Sdavidcs/** Driver Related Definitions Begin **/ 1457250661Sdavidcs 1458250661Sdavidcs#define TX_SMALL_PKT_SIZE 128 /* size in bytes of small packets */ 1459250661Sdavidcs 1460250661Sdavidcs/* The number of descriptors should be a power of 2 */ 1461250661Sdavidcs#define NUM_TX_DESCRIPTORS 1024 1462250661Sdavidcs#define NUM_STATUS_DESCRIPTORS 1024 1463250661Sdavidcs 1464250661Sdavidcs 1465250661Sdavidcs#define NUM_RX_DESCRIPTORS 2048 1466250661Sdavidcs 1467250661Sdavidcs/* 1468250661Sdavidcs * structure describing various dma buffers 1469250661Sdavidcs */ 1470250661Sdavidcs 1471250661Sdavidcstypedef struct qla_dmabuf { 1472250661Sdavidcs volatile struct { 1473250661Sdavidcs uint32_t tx_ring :1, 1474250661Sdavidcs rds_ring :1, 1475250661Sdavidcs sds_ring :1, 1476250661Sdavidcs minidump :1; 1477250661Sdavidcs } flags; 1478250661Sdavidcs 1479250661Sdavidcs qla_dma_t tx_ring; 1480250661Sdavidcs qla_dma_t rds_ring[MAX_RDS_RINGS]; 1481250661Sdavidcs qla_dma_t sds_ring[MAX_SDS_RINGS]; 1482250661Sdavidcs qla_dma_t minidump; 1483250661Sdavidcs} qla_dmabuf_t; 1484250661Sdavidcs 1485250661Sdavidcstypedef struct _qla_sds { 1486250661Sdavidcs q80_stat_desc_t *sds_ring_base; /* start of sds ring */ 1487250661Sdavidcs uint32_t sdsr_next; /* next entry in SDS ring to process */ 1488250661Sdavidcs struct lro_ctrl lro; 1489250661Sdavidcs void *rxb_free; 1490250661Sdavidcs uint32_t rx_free; 1491250661Sdavidcs volatile uint32_t rcv_active; 1492250661Sdavidcs uint32_t sds_consumer; 1493250661Sdavidcs uint64_t intr_count; 1494305491Sdavidcs uint64_t spurious_intr_count; 1495250661Sdavidcs} qla_sds_t; 1496250661Sdavidcs 1497250661Sdavidcs#define Q8_MAX_LRO_CONT_DESC 7 1498250661Sdavidcs#define Q8_MAX_HANDLES_LRO (1 + (Q8_MAX_LRO_CONT_DESC * 7)) 1499250661Sdavidcs#define Q8_MAX_HANDLES_NON_LRO 8 1500250661Sdavidcs 1501250661Sdavidcstypedef struct _qla_sgl_rcv { 1502250661Sdavidcs uint16_t pkt_length; 1503250661Sdavidcs uint16_t num_handles; 1504250661Sdavidcs uint16_t chksum_status; 1505250661Sdavidcs uint32_t rss_hash; 1506250661Sdavidcs uint16_t rss_hash_flags; 1507250661Sdavidcs uint16_t vlan_tag; 1508250661Sdavidcs uint16_t handle[Q8_MAX_HANDLES_NON_LRO]; 1509250661Sdavidcs} qla_sgl_rcv_t; 1510250661Sdavidcs 1511250661Sdavidcstypedef struct _qla_sgl_lro { 1512250661Sdavidcs uint16_t flags; 1513250661Sdavidcs#define Q8_LRO_COMP_TS 0x1 1514250661Sdavidcs#define Q8_LRO_COMP_PUSH_BIT 0x2 1515250661Sdavidcs uint16_t l2_offset; 1516250661Sdavidcs uint16_t l4_offset; 1517250661Sdavidcs 1518250661Sdavidcs uint16_t payload_length; 1519250661Sdavidcs uint16_t num_handles; 1520250661Sdavidcs uint32_t rss_hash; 1521250661Sdavidcs uint16_t rss_hash_flags; 1522250661Sdavidcs uint16_t vlan_tag; 1523250661Sdavidcs uint16_t handle[Q8_MAX_HANDLES_LRO]; 1524250661Sdavidcs} qla_sgl_lro_t; 1525250661Sdavidcs 1526250661Sdavidcstypedef union { 1527250661Sdavidcs qla_sgl_rcv_t rcv; 1528250661Sdavidcs qla_sgl_lro_t lro; 1529250661Sdavidcs} qla_sgl_comp_t; 1530250661Sdavidcs 1531250661Sdavidcs#define QL_FRAME_HDR_SIZE (ETHER_HDR_LEN + ETHER_VLAN_ENCAP_LEN +\ 1532250661Sdavidcs sizeof (struct ip6_hdr) + sizeof (struct tcphdr) + 16) 1533250661Sdavidcs 1534250661Sdavidcstypedef struct _qla_hw_tx_cntxt { 1535250661Sdavidcs q80_tx_cmd_t *tx_ring_base; 1536250661Sdavidcs bus_addr_t tx_ring_paddr; 1537250661Sdavidcs 1538250661Sdavidcs volatile uint32_t *tx_cons; /* tx consumer shadow reg */ 1539250661Sdavidcs bus_addr_t tx_cons_paddr; 1540250661Sdavidcs 1541250661Sdavidcs volatile uint32_t txr_free; /* # of free entries in tx ring */ 1542250661Sdavidcs volatile uint32_t txr_next; /* # next available tx ring entry */ 1543250661Sdavidcs volatile uint32_t txr_comp; /* index of last tx entry completed */ 1544250661Sdavidcs 1545250661Sdavidcs uint32_t tx_prod_reg; 1546250661Sdavidcs uint16_t tx_cntxt_id; 1547250661Sdavidcs 1548250661Sdavidcs} qla_hw_tx_cntxt_t; 1549250661Sdavidcs 1550250661Sdavidcstypedef struct _qla_mcast { 1551250661Sdavidcs uint16_t rsrvd; 1552307525Sdavidcs uint8_t addr[ETHER_ADDR_LEN]; 1553250661Sdavidcs} __packed qla_mcast_t; 1554250661Sdavidcs 1555250661Sdavidcstypedef struct _qla_rdesc { 1556250661Sdavidcs volatile uint32_t prod_std; 1557250661Sdavidcs volatile uint32_t prod_jumbo; 1558250661Sdavidcs volatile uint32_t rx_next; /* next standard rcv ring to arm fw */ 1559250661Sdavidcs volatile int32_t rx_in; /* next standard rcv ring to add mbufs */ 1560322975Sdavidcs uint64_t count; 1561322975Sdavidcs uint64_t lro_pkt_count; 1562322975Sdavidcs uint64_t lro_bytes; 1563250661Sdavidcs} qla_rdesc_t; 1564250661Sdavidcs 1565250661Sdavidcstypedef struct _qla_flash_desc_table { 1566250661Sdavidcs uint32_t flash_valid; 1567250661Sdavidcs uint16_t flash_ver; 1568250661Sdavidcs uint16_t flash_len; 1569250661Sdavidcs uint16_t flash_cksum; 1570250661Sdavidcs uint16_t flash_unused; 1571250661Sdavidcs uint8_t flash_model[16]; 1572250661Sdavidcs uint16_t flash_manuf; 1573250661Sdavidcs uint16_t flash_id; 1574250661Sdavidcs uint8_t flash_flag; 1575250661Sdavidcs uint8_t erase_cmd; 1576250661Sdavidcs uint8_t alt_erase_cmd; 1577250661Sdavidcs uint8_t write_enable_cmd; 1578250661Sdavidcs uint8_t write_enable_bits; 1579250661Sdavidcs uint8_t write_statusreg_cmd; 1580250661Sdavidcs uint8_t unprotected_sec_cmd; 1581250661Sdavidcs uint8_t read_manuf_cmd; 1582250661Sdavidcs uint32_t block_size; 1583250661Sdavidcs uint32_t alt_block_size; 1584250661Sdavidcs uint32_t flash_size; 1585250661Sdavidcs uint32_t write_enable_data; 1586250661Sdavidcs uint8_t readid_addr_len; 1587250661Sdavidcs uint8_t write_disable_bits; 1588250661Sdavidcs uint8_t read_dev_id_len; 1589250661Sdavidcs uint8_t chip_erase_cmd; 1590250661Sdavidcs uint16_t read_timeo; 1591250661Sdavidcs uint8_t protected_sec_cmd; 1592250661Sdavidcs uint8_t resvd[65]; 1593250661Sdavidcs} __packed qla_flash_desc_table_t; 1594250661Sdavidcs 1595250661Sdavidcs/* 1596250661Sdavidcs * struct for storing hardware specific information for a given interface 1597250661Sdavidcs */ 1598250661Sdavidcstypedef struct _qla_hw { 1599250661Sdavidcs struct { 1600250661Sdavidcs uint32_t 1601250661Sdavidcs unicast_mac :1, 1602250661Sdavidcs bcast_mac :1, 1603250661Sdavidcs init_tx_cnxt :1, 1604250661Sdavidcs init_rx_cnxt :1, 1605250661Sdavidcs init_intr_cnxt :1, 1606250661Sdavidcs fdt_valid :1; 1607250661Sdavidcs } flags; 1608250661Sdavidcs 1609250661Sdavidcs 1610330556Sdavidcs volatile uint16_t link_speed; 1611330556Sdavidcs volatile uint16_t cable_length; 1612330556Sdavidcs volatile uint32_t cable_oui; 1613330556Sdavidcs volatile uint8_t link_up; 1614330556Sdavidcs volatile uint8_t module_type; 1615330556Sdavidcs volatile uint8_t link_faults; 1616330556Sdavidcs volatile uint8_t loopback_mode; 1617330556Sdavidcs volatile uint8_t fduplex; 1618330556Sdavidcs volatile uint8_t autoneg; 1619250661Sdavidcs 1620330556Sdavidcs volatile uint8_t mac_rcv_mode; 1621250661Sdavidcs 1622330556Sdavidcs volatile uint32_t max_mtu; 1623250661Sdavidcs 1624250661Sdavidcs uint8_t mac_addr[ETHER_ADDR_LEN]; 1625250661Sdavidcs 1626250661Sdavidcs uint32_t num_sds_rings; 1627250661Sdavidcs uint32_t num_rds_rings; 1628250661Sdavidcs uint32_t num_tx_rings; 1629250661Sdavidcs 1630250661Sdavidcs qla_dmabuf_t dma_buf; 1631250661Sdavidcs 1632250661Sdavidcs /* Transmit Side */ 1633250661Sdavidcs 1634250661Sdavidcs qla_hw_tx_cntxt_t tx_cntxt[NUM_TX_RINGS]; 1635250661Sdavidcs 1636250661Sdavidcs /* Receive Side */ 1637250661Sdavidcs 1638250661Sdavidcs uint16_t rcv_cntxt_id; 1639250661Sdavidcs 1640250661Sdavidcs uint32_t mbx_intr_mask_offset; 1641250661Sdavidcs 1642250661Sdavidcs uint16_t intr_id[MAX_SDS_RINGS]; 1643250661Sdavidcs uint32_t intr_src[MAX_SDS_RINGS]; 1644250661Sdavidcs 1645250661Sdavidcs qla_sds_t sds[MAX_SDS_RINGS]; 1646250661Sdavidcs uint32_t mbox[Q8_NUM_MBOX]; 1647250661Sdavidcs qla_rdesc_t rds[MAX_RDS_RINGS]; 1648250661Sdavidcs 1649250661Sdavidcs uint32_t rds_pidx_thres; 1650250661Sdavidcs uint32_t sds_cidx_thres; 1651250661Sdavidcs 1652284982Sdavidcs uint32_t rcv_intr_coalesce; 1653284982Sdavidcs uint32_t xmt_intr_coalesce; 1654284982Sdavidcs 1655284982Sdavidcs /* Immediate Completion */ 1656284982Sdavidcs volatile uint32_t imd_compl; 1657284982Sdavidcs volatile uint32_t aen_mb0; 1658284982Sdavidcs volatile uint32_t aen_mb1; 1659284982Sdavidcs volatile uint32_t aen_mb2; 1660284982Sdavidcs volatile uint32_t aen_mb3; 1661284982Sdavidcs volatile uint32_t aen_mb4; 1662284982Sdavidcs 1663250661Sdavidcs /* multicast address list */ 1664250661Sdavidcs uint32_t nmcast; 1665250661Sdavidcs qla_mcast_t mcast[Q8_MAX_NUM_MULTICAST_ADDRS]; 1666307525Sdavidcs uint8_t mac_addr_arr[(Q8_MAX_MAC_ADDRS * ETHER_ADDR_LEN)]; 1667250661Sdavidcs 1668250661Sdavidcs /* reset sequence */ 1669250661Sdavidcs#define Q8_MAX_RESET_SEQ_IDX 16 1670250661Sdavidcs uint32_t rst_seq[Q8_MAX_RESET_SEQ_IDX]; 1671250661Sdavidcs uint32_t rst_seq_idx; 1672250661Sdavidcs 1673250661Sdavidcs /* heart beat register value */ 1674250661Sdavidcs uint32_t hbeat_value; 1675250661Sdavidcs uint32_t health_count; 1676321499Sdavidcs uint32_t hbeat_failure; 1677250661Sdavidcs 1678250661Sdavidcs uint32_t max_tx_segs; 1679258457Sdavidcs uint32_t min_lro_pkt_size; 1680250661Sdavidcs 1681317111Sdavidcs uint32_t enable_hw_lro; 1682317111Sdavidcs uint32_t enable_soft_lro; 1683284982Sdavidcs uint32_t enable_9kb; 1684284982Sdavidcs 1685284982Sdavidcs uint32_t user_pri_nic; 1686284982Sdavidcs uint32_t user_pri_iscsi; 1687284982Sdavidcs 1688250661Sdavidcs /* Flash Descriptor Table */ 1689250661Sdavidcs qla_flash_desc_table_t fdt; 1690250661Sdavidcs 1691322975Sdavidcs /* stats */ 1692322975Sdavidcs q80_mac_stats_t mac; 1693322975Sdavidcs q80_rcv_stats_t rcv; 1694322975Sdavidcs q80_xmt_stats_t xmt[NUM_TX_RINGS]; 1695322975Sdavidcs 1696250661Sdavidcs /* Minidump Related */ 1697250661Sdavidcs uint32_t mdump_init; 1698305490Sdavidcs uint32_t mdump_done; 1699250661Sdavidcs uint32_t mdump_active; 1700305490Sdavidcs uint32_t mdump_capture_mask; 1701250661Sdavidcs uint32_t mdump_start_seq_index; 1702305490Sdavidcs void *mdump_buffer; 1703305490Sdavidcs uint32_t mdump_buffer_size; 1704305490Sdavidcs void *mdump_template; 1705305490Sdavidcs uint32_t mdump_template_size; 1706330556Sdavidcs uint64_t mdump_usec_ts; 1707324764Sdavidcs 1708330556Sdavidcs#define Q8_MBX_COMP_MSECS (19) 1709330556Sdavidcs uint64_t mbx_comp_msecs[Q8_MBX_COMP_MSECS]; 1710324764Sdavidcs /* driver state related */ 1711324764Sdavidcs void *drvr_state; 1712330556Sdavidcs 1713330556Sdavidcs /* slow path trace */ 1714330556Sdavidcs uint32_t sp_log_stop_events; 1715330556Sdavidcs#define Q8_SP_LOG_STOP_HBEAT_FAILURE 0x001 1716330556Sdavidcs#define Q8_SP_LOG_STOP_TEMP_FAILURE 0x002 1717330556Sdavidcs#define Q8_SP_LOG_STOP_HW_INIT_FAILURE 0x004 1718330556Sdavidcs#define Q8_SP_LOG_STOP_IF_START_FAILURE 0x008 1719330556Sdavidcs#define Q8_SP_LOG_STOP_ERR_RECOVERY_FAILURE 0x010 1720330556Sdavidcs 1721330556Sdavidcs uint32_t sp_log_stop; 1722330556Sdavidcs uint32_t sp_log_index; 1723330556Sdavidcs uint32_t sp_log_num_entries; 1724330556Sdavidcs void *sp_log; 1725250661Sdavidcs} qla_hw_t; 1726250661Sdavidcs 1727250661Sdavidcs#define QL_UPDATE_RDS_PRODUCER_INDEX(ha, prod_reg, val) \ 1728251076Sdavidcs bus_write_4((ha->pci_reg), prod_reg, val); 1729250661Sdavidcs 1730250661Sdavidcs#define QL_UPDATE_TX_PRODUCER_INDEX(ha, val, i) \ 1731251076Sdavidcs WRITE_REG32(ha, ha->hw.tx_cntxt[i].tx_prod_reg, val) 1732250661Sdavidcs 1733250661Sdavidcs#define QL_UPDATE_SDS_CONSUMER_INDEX(ha, i, val) \ 1734251076Sdavidcs bus_write_4((ha->pci_reg), (ha->hw.sds[i].sds_consumer), val); 1735250661Sdavidcs 1736251076Sdavidcs#define QL_ENABLE_INTERRUPTS(ha, i) \ 1737251076Sdavidcs bus_write_4((ha->pci_reg), (ha->hw.intr_src[i]), 0); 1738250661Sdavidcs 1739250661Sdavidcs#define QL_BUFFER_ALIGN 16 1740250661Sdavidcs 1741250661Sdavidcs 1742250661Sdavidcs/* 1743250661Sdavidcs * Flash Configuration 1744250661Sdavidcs */ 1745250661Sdavidcs#define Q8_BOARD_CONFIG_OFFSET 0x370000 1746250661Sdavidcs#define Q8_BOARD_CONFIG_LENGTH 0x2000 1747250661Sdavidcs 1748250661Sdavidcs#define Q8_BOARD_CONFIG_MAC0_LO 0x400 1749250661Sdavidcs 1750250661Sdavidcs#define Q8_FDT_LOCK_MAGIC_ID 0x00FD00FD 1751250661Sdavidcs#define Q8_FDT_FLASH_ADDR_VAL 0xFD009F 1752250661Sdavidcs#define Q8_FDT_FLASH_CTRL_VAL 0x3F 1753250661Sdavidcs#define Q8_FDT_MASK_VAL 0xFF 1754250661Sdavidcs 1755250661Sdavidcs#define Q8_WR_ENABLE_FL_ADDR 0xFD0100 1756250661Sdavidcs#define Q8_WR_ENABLE_FL_CTRL 0x5 1757250661Sdavidcs 1758250661Sdavidcs#define Q8_ERASE_LOCK_MAGIC_ID 0x00EF00EF 1759250661Sdavidcs#define Q8_ERASE_FL_ADDR_MASK 0xFD0300 1760250661Sdavidcs#define Q8_ERASE_FL_CTRL_MASK 0x3D 1761250661Sdavidcs 1762250661Sdavidcs#define Q8_WR_FL_LOCK_MAGIC_ID 0xABCDABCD 1763250661Sdavidcs#define Q8_WR_FL_ADDR_MASK 0x800000 1764250661Sdavidcs#define Q8_WR_FL_CTRL_MASK 0x3D 1765250661Sdavidcs 1766250661Sdavidcs#define QL_FDT_OFFSET 0x3F0000 1767250661Sdavidcs#define Q8_FLASH_SECTOR_SIZE 0x10000 1768250661Sdavidcs 1769250661Sdavidcs/* 1770250661Sdavidcs * Off Chip Memory Access 1771250661Sdavidcs */ 1772250661Sdavidcs 1773250661Sdavidcstypedef struct _q80_offchip_mem_val { 1774250661Sdavidcs uint32_t data_lo; 1775250661Sdavidcs uint32_t data_hi; 1776250661Sdavidcs uint32_t data_ulo; 1777250661Sdavidcs uint32_t data_uhi; 1778250661Sdavidcs} q80_offchip_mem_val_t; 1779250661Sdavidcs 1780250661Sdavidcs#endif /* #ifndef _QL_HW_H_ */ 1781