ql_def.h revision 313072 
1/*
2 * Copyright (c) 2013-2016 Qlogic Corporation
3 * All rights reserved.
4 *
5 *  Redistribution and use in source and binary forms, with or without
6 *  modification, are permitted provided that the following conditions
7 *  are met:
8 *
9 *  1. Redistributions of source code must retain the above copyright
10 *     notice, this list of conditions and the following disclaimer.
11 *  2. Redistributions in binary form must reproduce the above copyright
12 *     notice, this list of conditions and the following disclaimer in the
13 *     documentation and/or other materials provided with the distribution.
14 *
15 *  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
16 *  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 *  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 *  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
19 *  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
20 *  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
21 *  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
22 *  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
23 *  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
24 *  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
25 *  POSSIBILITY OF SUCH DAMAGE.
26 *
27 * $FreeBSD: stable/10/sys/dev/qlxgbe/ql_def.h 313072 2017-02-02 00:20:53Z davidcs $
28 */
29
30/*
31 * File: ql_def.h
32 * Author : David C Somayajulu, Qlogic Corporation, Aliso Viejo, CA 92656.
33 */
34
35#ifndef _QL_DEF_H_
36#define _QL_DEF_H_
37
38#define BIT_0                   (0x1 << 0)
39#define BIT_1                   (0x1 << 1)
40#define BIT_2                   (0x1 << 2)
41#define BIT_3                   (0x1 << 3)
42#define BIT_4                   (0x1 << 4)
43#define BIT_5                   (0x1 << 5)
44#define BIT_6                   (0x1 << 6)
45#define BIT_7                   (0x1 << 7)
46#define BIT_8                   (0x1 << 8)
47#define BIT_9                   (0x1 << 9)
48#define BIT_10                  (0x1 << 10)
49#define BIT_11                  (0x1 << 11)
50#define BIT_12                  (0x1 << 12)
51#define BIT_13                  (0x1 << 13)
52#define BIT_14                  (0x1 << 14)
53#define BIT_15                  (0x1 << 15)
54#define BIT_16                  (0x1 << 16)
55#define BIT_17                  (0x1 << 17)
56#define BIT_18                  (0x1 << 18)
57#define BIT_19                  (0x1 << 19)
58#define BIT_20                  (0x1 << 20)
59#define BIT_21                  (0x1 << 21)
60#define BIT_22                  (0x1 << 22)
61#define BIT_23                  (0x1 << 23)
62#define BIT_24                  (0x1 << 24)
63#define BIT_25                  (0x1 << 25)
64#define BIT_26                  (0x1 << 26)
65#define BIT_27                  (0x1 << 27)
66#define BIT_28                  (0x1 << 28)
67#define BIT_29                  (0x1 << 29)
68#define BIT_30                  (0x1 << 30)
69#define BIT_31                  (0x1 << 31)
70
71struct qla_rx_buf {
72	struct mbuf	*m_head;
73	bus_dmamap_t	map;
74	bus_addr_t      paddr;
75	uint32_t	handle;
76	void		*next;
77};
78typedef struct qla_rx_buf qla_rx_buf_t;
79
80struct qla_rx_ring {
81	qla_rx_buf_t	rx_buf[NUM_RX_DESCRIPTORS];
82};
83typedef struct qla_rx_ring qla_rx_ring_t;
84
85struct qla_tx_buf {
86	struct mbuf	*m_head;
87	bus_dmamap_t	map;
88};
89typedef struct qla_tx_buf qla_tx_buf_t;
90
91#define QLA_MAX_SEGMENTS	62	/* maximum # of segs in a sg list */
92#define QLA_MAX_MTU		9000
93#define QLA_STD_FRAME_SIZE	1514
94#define QLA_MAX_TSO_FRAME_SIZE	((64 * 1024 - 1) + 22)
95
96/* Number of MSIX/MSI Vectors required */
97
98struct qla_ivec {
99	uint32_t		sds_idx;
100	void			*ha;
101	struct resource		*irq;
102	void			*handle;
103	int			irq_rid;
104};
105
106typedef struct qla_ivec qla_ivec_t;
107
108#define QLA_WATCHDOG_CALLOUT_TICKS	1
109
110typedef struct _qla_tx_ring {
111	qla_tx_buf_t	tx_buf[NUM_TX_DESCRIPTORS];
112	uint64_t	count;
113} qla_tx_ring_t;
114
115typedef struct _qla_tx_fp {
116	struct mtx		tx_mtx;
117	char			tx_mtx_name[32];
118	struct buf_ring		*tx_br;
119	struct task		fp_task;
120	struct taskqueue	*fp_taskqueue;
121	void			*ha;
122	uint32_t		txr_idx;
123} qla_tx_fp_t;
124
125/*
126 * Adapter structure contains the hardware independant information of the
127 * pci function.
128 */
129struct qla_host {
130        volatile struct {
131                volatile uint32_t
132			qla_interface_up        :1,
133			qla_callout_init	:1,
134			qla_watchdog_active	:1,
135			qla_watchdog_exit	:1,
136			qla_watchdog_pause	:1,
137			stop_rcv		:1,
138			parent_tag		:1,
139			lock_init		:1;
140        } flags;
141
142	volatile uint32_t	qla_watchdog_exited;
143	volatile uint32_t	qla_watchdog_paused;
144	volatile uint32_t	qla_initiate_recovery;
145
146	device_t		pci_dev;
147
148	uint16_t		watchdog_ticks;
149	uint8_t			pci_func;
150	uint8_t			resvd;
151
152        /* ioctl related */
153        struct cdev             *ioctl_dev;
154
155	/* register mapping */
156	struct resource		*pci_reg;
157	int			reg_rid;
158	struct resource		*pci_reg1;
159	int			reg_rid1;
160
161	/* interrupts */
162	struct resource         *mbx_irq;
163	void			*mbx_handle;
164	int			mbx_irq_rid;
165
166	int			msix_count;
167
168	qla_ivec_t		irq_vec[MAX_SDS_RINGS];
169
170	/* parent dma tag */
171	bus_dma_tag_t           parent_tag;
172
173	/* interface to o.s */
174	struct ifnet		*ifp;
175
176	struct ifmedia		media;
177	uint16_t		max_frame_size;
178	uint16_t		rsrvd0;
179	int			if_flags;
180
181	/* hardware access lock */
182
183	struct mtx		hw_lock;
184	volatile uint32_t	hw_lock_held;
185
186	/* transmit and receive buffers */
187	uint32_t		txr_idx; /* index of the current tx ring */
188	qla_tx_ring_t		tx_ring[NUM_TX_RINGS];
189
190	bus_dma_tag_t		tx_tag;
191	struct callout		tx_callout;
192
193	qla_tx_fp_t		tx_fp[MAX_SDS_RINGS];
194
195	qla_rx_ring_t		rx_ring[MAX_RDS_RINGS];
196	bus_dma_tag_t		rx_tag;
197	uint32_t		std_replenish;
198
199	qla_rx_buf_t		*rxb_free;
200	uint32_t		rxb_free_count;
201	volatile uint32_t	posting;
202
203	/* stats */
204	uint32_t		err_m_getcl;
205	uint32_t		err_m_getjcl;
206	uint32_t		err_tx_dmamap_create;
207	uint32_t		err_tx_dmamap_load;
208	uint32_t		err_tx_defrag;
209
210	uint64_t		rx_frames;
211	uint64_t		rx_bytes;
212
213	uint64_t		lro_pkt_count;
214	uint64_t		lro_bytes;
215
216	uint64_t		ipv4_lro;
217	uint64_t		ipv6_lro;
218
219	uint64_t		tx_frames;
220	uint64_t		tx_bytes;
221	uint64_t		tx_tso_frames;
222	uint64_t		hw_vlan_tx_frames;
223
224        uint32_t                fw_ver_major;
225        uint32_t                fw_ver_minor;
226        uint32_t                fw_ver_sub;
227        uint32_t                fw_ver_build;
228
229	/* hardware specific */
230	qla_hw_t		hw;
231
232	/* debug stuff */
233	volatile const char 	*qla_lock;
234	volatile const char	*qla_unlock;
235	uint32_t		dbg_level;
236
237	uint8_t			fw_ver_str[32];
238
239	/* Error Injection Related */
240	uint32_t		err_inject;
241	struct task		err_task;
242	struct taskqueue	*err_tq;
243
244	/* Async Event Related */
245	uint32_t                async_event;
246	struct task             async_event_task;
247	struct taskqueue        *async_event_tq;
248
249	/* Peer Device */
250	device_t		peer_dev;
251
252	volatile uint32_t	msg_from_peer;
253#define QL_PEER_MSG_RESET	0x01
254#define QL_PEER_MSG_ACK		0x02
255
256};
257typedef struct qla_host qla_host_t;
258
259/* note that align has to be a power of 2 */
260#define QL_ALIGN(size, align) (size + (align - 1)) & ~(align - 1);
261#define QL_MIN(x, y) ((x < y) ? x : y)
262
263#define QL_RUNNING(ifp) \
264		((ifp->if_drv_flags & (IFF_DRV_RUNNING | IFF_DRV_OACTIVE)) == \
265			IFF_DRV_RUNNING)
266
267/* Return 0, if identical, else 1 */
268#define QL_MAC_CMP(mac1, mac2)    \
269	((((*(uint32_t *) mac1) == (*(uint32_t *) mac2) && \
270	(*(uint16_t *)(mac1 + 4)) == (*(uint16_t *)(mac2 + 4)))) ? 0 : 1)
271
272#endif /* #ifndef _QL_DEF_H_ */
273