12038SN/A/* 212209Skshefov * Copyright (c) 2017-2018 Cavium, Inc. 32038SN/A * All rights reserved. 42038SN/A * 52038SN/A * Redistribution and use in source and binary forms, with or without 62038SN/A * modification, are permitted provided that the following conditions 78729Sserb * are met: 82038SN/A * 92038SN/A * 1. Redistributions of source code must retain the above copyright 102038SN/A * notice, this list of conditions and the following disclaimer. 112038SN/A * 2. Redistributions in binary form must reproduce the above copyright 122038SN/A * notice, this list of conditions and the following disclaimer in the 132038SN/A * documentation and/or other materials provided with the distribution. 142038SN/A * 152038SN/A * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 162038SN/A * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 172038SN/A * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 182038SN/A * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 192362SN/A * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 202362SN/A * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 212362SN/A * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 222038SN/A * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 232038SN/A * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 242038SN/A * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 253793Sjrose * POSSIBILITY OF SUCH DAMAGE. 2612209Skshefov * 275688Stwisti * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/qlnx_ioctl.h 337519 2018-08-09 01:39:47Z davidcs $ 286085Sjiangli * 292038SN/A */ 302038SN/A 313793Sjrose#ifndef _QLNX_IOCTL_H_ 322038SN/A#define _QLNX_IOCTL_H_ 335688Stwisti 343793Sjrose#include <sys/ioccom.h> 3513111Smhaupt 363793Sjrose#define QLNX_MAX_HW_FUNCS 2 372038SN/A 382038SN/A/* 392038SN/A * Read grcdump and grcdump size 402038SN/A */ 4112209Skshefov 422038SN/Astruct qlnx_grcdump { 432038SN/A uint16_t pci_func; 442038SN/A uint32_t grcdump_size[QLNX_MAX_HW_FUNCS]; 452038SN/A void *grcdump[QLNX_MAX_HW_FUNCS]; 462038SN/A uint32_t grcdump_dwords[QLNX_MAX_HW_FUNCS]; 472038SN/A}; 482038SN/Atypedef struct qlnx_grcdump qlnx_grcdump_t; 494383Sjrose 502038SN/A/* 512431SN/A * Read idle_chk and idle_chk size 522435SN/A */ 534383Sjrosestruct qlnx_idle_chk { 544383Sjrose uint16_t pci_func; 554383Sjrose uint32_t idle_chk_size[QLNX_MAX_HW_FUNCS]; 562435SN/A void *idle_chk[QLNX_MAX_HW_FUNCS]; 572435SN/A uint32_t idle_chk_dwords[QLNX_MAX_HW_FUNCS]; 582038SN/A}; 592038SN/Atypedef struct qlnx_idle_chk qlnx_idle_chk_t; 602038SN/A 612038SN/A/* 625688Stwisti * Retrive traces 635688Stwisti */ 645688Stwististruct qlnx_trace { 655688Stwisti uint16_t pci_func; 665688Stwisti 675688Stwisti uint16_t cmd; 685688Stwisti#define QLNX_MCP_TRACE 0x01 692038SN/A#define QLNX_REG_FIFO 0x02 704383Sjrose#define QLNX_IGU_FIFO 0x03 714383Sjrose#define QLNX_PROTECTION_OVERRIDE 0x04 724383Sjrose#define QLNX_FW_ASSERTS 0x05 732038SN/A 742038SN/A uint32_t size[QLNX_MAX_HW_FUNCS]; 752038SN/A void *buffer[QLNX_MAX_HW_FUNCS]; 762038SN/A uint32_t dwords[QLNX_MAX_HW_FUNCS]; 772038SN/A}; 782431SN/Atypedef struct qlnx_trace qlnx_trace_t; 792038SN/A 802038SN/A 812038SN/A/* 822038SN/A * Read driver info 832038SN/A */ 842038SN/A#define QLNX_DRV_INFO_NAME_LENGTH 32 852038SN/A#define QLNX_DRV_INFO_VERSION_LENGTH 32 862038SN/A#define QLNX_DRV_INFO_MFW_VERSION_LENGTH 32 872435SN/A#define QLNX_DRV_INFO_STORMFW_VERSION_LENGTH 32 882038SN/A#define QLNX_DRV_INFO_BUS_INFO_LENGTH 32 892038SN/A 902038SN/Astruct qlnx_drvinfo { 912431SN/A char drv_name[QLNX_DRV_INFO_NAME_LENGTH]; 922038SN/A char drv_version[QLNX_DRV_INFO_VERSION_LENGTH]; 932038SN/A char mfw_version[QLNX_DRV_INFO_MFW_VERSION_LENGTH]; 942038SN/A char stormfw_version[QLNX_DRV_INFO_STORMFW_VERSION_LENGTH]; 952435SN/A uint32_t eeprom_dump_len; /* in bytes */ 962435SN/A uint32_t reg_dump_len; /* in bytes */ 972431SN/A char bus_info[QLNX_DRV_INFO_BUS_INFO_LENGTH]; 982038SN/A}; 992038SN/Atypedef struct qlnx_drvinfo qlnx_drvinfo_t; 1002038SN/A 1012038SN/A/* 1022038SN/A * Read Device Setting 1032038SN/A */ 1042038SN/Astruct qlnx_dev_setting { 1052038SN/A uint32_t supported; /* Features this interface supports */ 1062038SN/A uint32_t advertising; /* Features this interface advertises */ 1072431SN/A uint32_t speed; /* The forced speed, 10Mb, 100Mb, gigabit */ 1082038SN/A uint32_t duplex; /* Duplex, half or full */ 1092038SN/A uint32_t port; /* Which connector port */ 1102038SN/A uint32_t phy_address; /* port number*/ 1112038SN/A uint32_t autoneg; /* Enable or disable autonegotiation */ 1122038SN/A}; 1132038SN/Atypedef struct qlnx_dev_setting qlnx_dev_setting_t; 1142038SN/A 1152038SN/A/* 1162038SN/A * Get Registers 1172431SN/A */ 1182038SN/Astruct qlnx_get_regs { 1192038SN/A void *reg_buf; 1202038SN/A uint32_t reg_buf_len; 1212038SN/A}; 1222435SN/Atypedef struct qlnx_get_regs qlnx_get_regs_t; 1234383Sjrose 1242435SN/A/* 1252435SN/A * Get/Set NVRAM 1262435SN/A */ 1272435SN/Astruct qlnx_nvram { 1282038SN/A uint32_t cmd; 1292038SN/A#define QLNX_NVRAM_CMD_WRITE_NVRAM 0x01 1304935Sjrose#define QLNX_NVRAM_CMD_READ_NVRAM 0x02 1312038SN/A#define QLNX_NVRAM_CMD_SET_SECURE_MODE 0x03 1322038SN/A#define QLNX_NVRAM_CMD_DEL_FILE 0x04 1332038SN/A#define QLNX_NVRAM_CMD_PUT_FILE_BEGIN 0x05 1345688Stwisti#define QLNX_NVRAM_CMD_GET_NVRAM_RESP 0x06 1352038SN/A#define QLNX_NVRAM_CMD_PUT_FILE_DATA 0x07 1362038SN/A 1372038SN/A void *data; 1382038SN/A uint32_t offset; 1392038SN/A uint32_t data_len; 1402038SN/A uint32_t magic; 1412038SN/A}; 1422431SN/Atypedef struct qlnx_nvram qlnx_nvram_t; 1432038SN/A 1448311Sjrose/* 1452038SN/A * Get/Set Device registers 1462038SN/A */ 1472038SN/Astruct qlnx_reg_rd_wr { 1482038SN/A uint32_t cmd; 1492038SN/A#define QLNX_REG_READ_CMD 0x01 1502038SN/A#define QLNX_REG_WRITE_CMD 0x02 1512431SN/A 1528311Sjrose uint32_t addr; 1538311Sjrose uint32_t val; 1548311Sjrose 1558311Sjrose uint32_t access_type; 1568311Sjrose#define QLNX_REG_ACCESS_DIRECT 0x01 1578311Sjrose#define QLNX_REG_ACCESS_INDIRECT 0x02 1588311Sjrose 1598311Sjrose uint32_t hwfn_index; 1608311Sjrose}; 1618311Sjrosetypedef struct qlnx_reg_rd_wr qlnx_reg_rd_wr_t; 1628311Sjrose 1638311Sjrose/* 1648311Sjrose * Read/Write PCI Configuration 1658311Sjrose */ 1668311Sjrosestruct qlnx_pcicfg_rd_wr { 1678311Sjrose uint32_t cmd; 1688311Sjrose#define QLNX_PCICFG_READ 0x01 1698311Sjrose#define QLNX_PCICFG_WRITE 0x02 1708311Sjrose uint32_t reg; 1712038SN/A uint32_t val; 1722038SN/A uint32_t width; 1732038SN/A}; 1742038SN/Atypedef struct qlnx_pcicfg_rd_wr qlnx_pcicfg_rd_wr_t; 1752038SN/A 1762038SN/A/* 1772038SN/A * Read MAC address 1782038SN/A */ 1792038SN/Astruct qlnx_perm_mac_addr { 1802038SN/A char addr[32]; 1812038SN/A}; 1822038SN/Atypedef struct qlnx_perm_mac_addr qlnx_perm_mac_addr_t; 1834935Sjrose 1842038SN/A 1852038SN/A/* 1862038SN/A * Read STORM statistics registers 1872038SN/A */ 1882038SN/Astruct qlnx_storm_stats { 1892038SN/A 1902038SN/A /* xstorm */ 1912038SN/A uint32_t xstorm_active_cycles; 1922038SN/A uint32_t xstorm_stall_cycles; 1932038SN/A uint32_t xstorm_sleeping_cycles; 1942038SN/A uint32_t xstorm_inactive_cycles; 1952038SN/A 1962038SN/A /* ystorm */ 1972040SN/A uint32_t ystorm_active_cycles; 1982040SN/A uint32_t ystorm_stall_cycles; 1992040SN/A uint32_t ystorm_sleeping_cycles; 2002040SN/A uint32_t ystorm_inactive_cycles; 2012038SN/A 2022038SN/A /* pstorm */ 2032038SN/A uint32_t pstorm_active_cycles; 2042431SN/A uint32_t pstorm_stall_cycles; 2052431SN/A uint32_t pstorm_sleeping_cycles; 2062431SN/A uint32_t pstorm_inactive_cycles; 2072431SN/A 2082431SN/A /* tstorm */ 2092431SN/A uint32_t tstorm_active_cycles; 2102431SN/A uint32_t tstorm_stall_cycles; 2112431SN/A uint32_t tstorm_sleeping_cycles; 2122431SN/A uint32_t tstorm_inactive_cycles; 2132431SN/A 2142431SN/A /* mstorm */ 2152431SN/A uint32_t mstorm_active_cycles; 2162431SN/A uint32_t mstorm_stall_cycles; 2172431SN/A uint32_t mstorm_sleeping_cycles; 2182431SN/A uint32_t mstorm_inactive_cycles; 2192431SN/A 2202431SN/A /* ustorm */ 2212431SN/A uint32_t ustorm_active_cycles; 2222431SN/A uint32_t ustorm_stall_cycles; 2232431SN/A uint32_t ustorm_sleeping_cycles; 2242431SN/A uint32_t ustorm_inactive_cycles; 2252431SN/A}; 2262431SN/A 2272431SN/Atypedef struct qlnx_storm_stats qlnx_storm_stats_t; 2282431SN/A 2292431SN/A#define QLNX_STORM_STATS_SAMPLES_PER_HWFN (10000) 2302431SN/A 2312431SN/A#define QLNX_STORM_STATS_BYTES_PER_HWFN (sizeof(qlnx_storm_stats_t) * \ 2322431SN/A QLNX_STORM_STATS_SAMPLES_PER_HWFN) 2332431SN/A 2342431SN/Astruct qlnx_storm_stats_dump { 2352038SN/A int num_hwfns; 2362431SN/A int num_samples; 2372038SN/A void *buffer[QLNX_MAX_HW_FUNCS]; 2382038SN/A}; 2392038SN/A 2403793Sjrosetypedef struct qlnx_storm_stats_dump qlnx_storm_stats_dump_t; 2412038SN/A 2422038SN/A#define QLNX_LLDP_TYPE_END_OF_LLDPDU 0 2432038SN/A#define QLNX_LLDP_TYPE_CHASSIS_ID 1 2442038SN/A#define QLNX_LLDP_TYPE_PORT_ID 2 2452038SN/A#define QLNX_LLDP_TYPE_TTL 3 2463012SN/A#define QLNX_LLDP_TYPE_PORT_DESC 4 2473012SN/A#define QLNX_LLDP_TYPE_SYS_NAME 5 2483012SN/A#define QLNX_LLDP_TYPE_SYS_DESC 6 2493012SN/A#define QLNX_LLDP_TYPE_SYS_CAPS 7 2503012SN/A#define QLNX_LLDP_TYPE_MGMT_ADDR 8 2513012SN/A#define QLNX_LLDP_TYPE_ORG_SPECIFIC 127 2528311Sjrose 2538311Sjrose#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 2548311Sjrose#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_MAC 0x04 //Mac Address 2558311Sjrose#define QLNX_LLDP_CHASSIS_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 2568311Sjrose#define QLNX_LLDP_CHASSIS_ID_SUBTYPE_IF_NAME 0x06 //Interface Name 2578311Sjrose 2585685Sjrose#define QLNX_LLDP_PORT_ID_SUBTYPE_OCTETS 1 //Subtype is 1 byte 2595685Sjrose#define QLNX_LLDP_PORT_ID_SUBTYPE_MAC 0x03 //Mac Address 2602038SN/A#define QLNX_LLDP_PORT_ID_MAC_ADDR_LEN 6 // Mac address is 6 bytes 2612431SN/A#define QLNX_LLDP_PORT_ID_SUBTYPE_IF_NAME 0x05 //Interface Name 2622038SN/A 2632038SN/A#define QLNX_LLDP_SYS_TLV_SIZE 256 2642038SN/Astruct qlnx_lldp_sys_tlvs { 2654935Sjrose int discard_mandatory_tlv; 2662038SN/A uint8_t buf[QLNX_LLDP_SYS_TLV_SIZE]; 2672038SN/A uint16_t buf_size; 2682038SN/A}; 2692038SN/Atypedef struct qlnx_lldp_sys_tlvs qlnx_lldp_sys_tlvs_t; 2702038SN/A 2712038SN/A 2722038SN/A/* 2732038SN/A * Read grcdump size 2742038SN/A */ 2752038SN/A#define QLNX_GRC_DUMP_SIZE _IOWR('q', 1, qlnx_grcdump_t) 2762038SN/A 2772038SN/A/* 2782038SN/A * Read grcdump 2792038SN/A */ 2802038SN/A#define QLNX_GRC_DUMP _IOWR('q', 2, qlnx_grcdump_t) 2818316Sjrose 2828316Sjrose/* 2838316Sjrose * Read idle_chk size 2842038SN/A */ 2854935Sjrose#define QLNX_IDLE_CHK_SIZE _IOWR('q', 3, qlnx_idle_chk_t) 2862038SN/A 2872038SN/A/* 2882038SN/A * Read idle_chk 2894935Sjrose */ 2902038SN/A#define QLNX_IDLE_CHK _IOWR('q', 4, qlnx_idle_chk_t) 2912038SN/A 2922038SN/A/* 2932038SN/A * Read driver info 2942038SN/A */ 2952038SN/A#define QLNX_DRV_INFO _IOWR('q', 5, qlnx_drvinfo_t) 2962038SN/A 2972038SN/A/* 2982038SN/A * Read Device Setting 2992038SN/A */ 3002038SN/A#define QLNX_DEV_SETTING _IOR('q', 6, qlnx_dev_setting_t) 3012038SN/A 3022038SN/A/* 3032038SN/A * Get Registers 3042038SN/A */ 3052038SN/A#define QLNX_GET_REGS _IOR('q', 7, qlnx_get_regs_t) 3062038SN/A 3072038SN/A/* 3082038SN/A * Get/Set NVRAM 3092038SN/A */ 3102038SN/A#define QLNX_NVRAM _IOWR('q', 8, qlnx_nvram_t) 3112038SN/A 3122038SN/A/* 3132038SN/A * Get/Set Device registers 3142038SN/A */ 3152038SN/A#define QLNX_RD_WR_REG _IOWR('q', 9, qlnx_reg_rd_wr_t) 3162038SN/A 3173529SN/A/* 3183529SN/A * Read/Write PCI Configuration 3193529SN/A */ 3203529SN/A#define QLNX_RD_WR_PCICFG _IOWR('q', 10, qlnx_pcicfg_rd_wr_t) 3213529SN/A 3223529SN/A/* 3233529SN/A * Read MAC address 3243529SN/A */ 3254183Sjrose#define QLNX_MAC_ADDR _IOWR('q', 11, qlnx_perm_mac_addr_t) 3264183Sjrose 3274183Sjrose/* 3283529SN/A * Read STORM statistics 3293529SN/A */ 3303529SN/A#define QLNX_STORM_STATS _IOWR('q', 12, qlnx_storm_stats_dump_t) 3313529SN/A 3323529SN/A/* 3333529SN/A * Read trace size 3343529SN/A */ 3353529SN/A#define QLNX_TRACE_SIZE _IOWR('q', 13, qlnx_trace_t) 3363529SN/A 3373529SN/A/* 3383529SN/A * Read trace 3394935Sjrose */ 3403529SN/A#define QLNX_TRACE _IOWR('q', 14, qlnx_trace_t) 3413529SN/A 3423529SN/A/* 3433529SN/A * Set LLDP TLVS 3443529SN/A */ 3453529SN/A#define QLNX_SET_LLDP_TLVS _IOWR('q', 15, qlnx_lldp_sys_tlvs_t) 3464935Sjrose 3473529SN/A#endif /* #ifndef _QLNX_IOCTL_H_ */ 3483529SN/A