nvm_map.h revision 320162
1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/nvm_map.h 320162 2017-06-20 18:52:35Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31320162Sdavidcs 32316485Sdavidcs/**************************************************************************** 33316485Sdavidcs * Name: nvm_map.h 34316485Sdavidcs * 35316485Sdavidcs * Description: Everest NVRAM map 36316485Sdavidcs * 37316485Sdavidcs ****************************************************************************/ 38316485Sdavidcs 39316485Sdavidcs#ifndef NVM_MAP_H 40316485Sdavidcs#define NVM_MAP_H 41316485Sdavidcs 42316485Sdavidcs#define CRC_MAGIC_VALUE 0xDEBB20E3 43316485Sdavidcs#define CRC32_POLYNOMIAL 0xEDB88320 44316485Sdavidcs#define NVM_CRC_SIZE (sizeof(u32)) 45316485Sdavidcsenum nvm_sw_arbitrator { 46316485Sdavidcs NVM_SW_ARB_HOST, 47316485Sdavidcs NVM_SW_ARB_MCP, 48316485Sdavidcs NVM_SW_ARB_UART, 49316485Sdavidcs NVM_SW_ARB_RESERVED 50316485Sdavidcs}; 51316485Sdavidcs 52316485Sdavidcs/**************************************************************************** 53316485Sdavidcs * Boot Strap Region * 54316485Sdavidcs ****************************************************************************/ 55316485Sdavidcsstruct legacy_bootstrap_region { 56316485Sdavidcs u32 magic_value; /* a pattern not likely to occur randomly */ 57316485Sdavidcs#define NVM_MAGIC_VALUE 0x669955aa 58316485Sdavidcs u32 sram_start_addr; /* where to locate LIM code (byte addr) */ 59316485Sdavidcs u32 code_len; /* boot code length (in dwords) */ 60316485Sdavidcs u32 code_start_addr; /* location of code on media (media byte addr) */ 61316485Sdavidcs u32 crc; /* 32-bit CRC */ 62316485Sdavidcs}; 63316485Sdavidcs 64316485Sdavidcs/**************************************************************************** 65316485Sdavidcs * Directories Region * 66316485Sdavidcs ****************************************************************************/ 67316485Sdavidcsstruct nvm_code_entry { 68316485Sdavidcs u32 image_type; /* Image type */ 69316485Sdavidcs u32 nvm_start_addr; /* NVM address of the image */ 70316485Sdavidcs u32 len; /* Include CRC */ 71316485Sdavidcs u32 sram_start_addr; /* Where to load the image on the scratchpad */ 72316485Sdavidcs u32 sram_run_addr; /* Relevant in case of MIM only */ 73316485Sdavidcs}; 74316485Sdavidcs 75316485Sdavidcsenum nvm_image_type { 76316485Sdavidcs NVM_TYPE_TIM1 = 0x01, 77316485Sdavidcs NVM_TYPE_TIM2 = 0x02, 78316485Sdavidcs NVM_TYPE_MIM1 = 0x03, 79316485Sdavidcs NVM_TYPE_MIM2 = 0x04, 80316485Sdavidcs NVM_TYPE_MBA = 0x05, 81316485Sdavidcs NVM_TYPE_MODULES_PN = 0x06, 82316485Sdavidcs NVM_TYPE_VPD = 0x07, 83316485Sdavidcs NVM_TYPE_MFW_TRACE1 = 0x08, 84316485Sdavidcs NVM_TYPE_MFW_TRACE2 = 0x09, 85316485Sdavidcs NVM_TYPE_NVM_CFG1 = 0x0a, 86316485Sdavidcs NVM_TYPE_L2B = 0x0b, 87316485Sdavidcs NVM_TYPE_DIR1 = 0x0c, 88316485Sdavidcs NVM_TYPE_EAGLE_FW1 = 0x0d, 89316485Sdavidcs NVM_TYPE_FALCON_FW1 = 0x0e, 90316485Sdavidcs NVM_TYPE_PCIE_FW1 = 0x0f, 91316485Sdavidcs NVM_TYPE_HW_SET = 0x10, 92316485Sdavidcs NVM_TYPE_LIM = 0x11, 93316485Sdavidcs NVM_TYPE_AVS_FW1 = 0x12, 94316485Sdavidcs NVM_TYPE_DIR2 = 0x13, 95316485Sdavidcs NVM_TYPE_CCM = 0x14, 96316485Sdavidcs NVM_TYPE_EAGLE_FW2 = 0x15, 97316485Sdavidcs NVM_TYPE_FALCON_FW2 = 0x16, 98316485Sdavidcs NVM_TYPE_PCIE_FW2 = 0x17, 99316485Sdavidcs NVM_TYPE_AVS_FW2 = 0x18, 100316485Sdavidcs NVM_TYPE_INIT_HW = 0x19, 101316485Sdavidcs NVM_TYPE_DEFAULT_CFG= 0x1a, 102316485Sdavidcs NVM_TYPE_MDUMP = 0x1b, 103316485Sdavidcs NVM_TYPE_NVM_META = 0x1c, 104316485Sdavidcs NVM_TYPE_ISCSI_CFG = 0x1d, 105316485Sdavidcs NVM_TYPE_FCOE_CFG = 0x1f, 106316485Sdavidcs NVM_TYPE_ETH_PHY_FW1 = 0x20, 107316485Sdavidcs NVM_TYPE_ETH_PHY_FW2 = 0x21, 108316485Sdavidcs NVM_TYPE_BDN = 0x22, 109316485Sdavidcs NVM_TYPE_8485X_PHY_FW = 0x23, 110316485Sdavidcs NVM_TYPE_PUB_KEY = 0x24, 111316485Sdavidcs NVM_TYPE_RECOVERY = 0x25, 112316485Sdavidcs NVM_TYPE_MAX, 113316485Sdavidcs}; 114316485Sdavidcs 115316485Sdavidcs#ifdef DEFINE_IMAGE_TABLE 116316485Sdavidcsstruct image_map { 117316485Sdavidcs char name[32]; 118316485Sdavidcs char option[32]; 119316485Sdavidcs u32 image_type; 120316485Sdavidcs}; 121316485Sdavidcs 122316485Sdavidcsstruct image_map g_image_table[] = { 123316485Sdavidcs {"TIM1", "-tim1", NVM_TYPE_TIM1}, 124316485Sdavidcs {"TIM2", "-tim2", NVM_TYPE_TIM2}, 125316485Sdavidcs {"MIM1", "-mim1", NVM_TYPE_MIM1}, 126316485Sdavidcs {"MIM2", "-mim2", NVM_TYPE_MIM2}, 127316485Sdavidcs {"MBA", "-mba", NVM_TYPE_MBA}, 128316485Sdavidcs {"OPT_MODULES", "-optm", NVM_TYPE_MODULES_PN}, 129316485Sdavidcs {"VPD", "-vpd", NVM_TYPE_VPD}, 130316485Sdavidcs {"MFW_TRACE1", "-mfwt1", NVM_TYPE_MFW_TRACE1}, 131316485Sdavidcs {"MFW_TRACE2", "-mfwt2", NVM_TYPE_MFW_TRACE2}, 132316485Sdavidcs {"NVM_CFG1", "-cfg", NVM_TYPE_NVM_CFG1}, 133316485Sdavidcs {"L2B", "-l2b", NVM_TYPE_L2B}, 134316485Sdavidcs {"DIR1", "-dir1", NVM_TYPE_DIR1}, 135316485Sdavidcs {"EAGLE_FW1", "-eagle1", NVM_TYPE_EAGLE_FW1}, 136316485Sdavidcs {"FALCON_FW1", "-falcon1", NVM_TYPE_FALCON_FW1}, 137316485Sdavidcs {"PCIE_FW1", "-pcie1", NVM_TYPE_PCIE_FW1}, 138316485Sdavidcs {"HW_SET", "-hw_set", NVM_TYPE_HW_SET}, 139316485Sdavidcs {"LIM", "-lim", NVM_TYPE_LIM}, 140316485Sdavidcs {"AVS_FW1", "-avs1", NVM_TYPE_AVS_FW1}, 141316485Sdavidcs {"DIR2", "-dir2", NVM_TYPE_DIR2}, 142316485Sdavidcs {"CCM", "-ccm", NVM_TYPE_CCM}, 143316485Sdavidcs {"EAGLE_FW2", "-eagle2", NVM_TYPE_EAGLE_FW2}, 144316485Sdavidcs {"FALCON_FW2", "-falcon2", NVM_TYPE_FALCON_FW2}, 145316485Sdavidcs {"PCIE_FW2", "-pcie2", NVM_TYPE_PCIE_FW2}, 146316485Sdavidcs {"AVS_FW2", "-avs2", NVM_TYPE_AVS_FW2}, 147316485Sdavidcs {"INIT_HW", "-init_hw", NVM_TYPE_INIT_HW}, 148316485Sdavidcs {"DEFAULT_CFG", "-def_cfg", NVM_TYPE_DEFAULT_CFG}, 149316485Sdavidcs {"CRASH_DUMP", "-mdump", NVM_TYPE_MDUMP}, 150316485Sdavidcs {"META", "-meta", NVM_TYPE_NVM_META}, 151316485Sdavidcs {"ISCSI_CFG", "-iscsi_cfg", NVM_TYPE_ISCSI_CFG}, 152316485Sdavidcs {"FCOE_CFG", "-fcoe_cfg",NVM_TYPE_FCOE_CFG}, 153316485Sdavidcs {"ETH_PHY_FW1", "-ethphy1", NVM_TYPE_ETH_PHY_FW1}, 154316485Sdavidcs {"ETH_PHY_FW2", "-ethphy2", NVM_TYPE_ETH_PHY_FW2}, 155316485Sdavidcs {"BDN", "-bdn", NVM_TYPE_BDN}, 156316485Sdavidcs {"PK", "-pk", NVM_TYPE_PUB_KEY}, 157316485Sdavidcs {"RECOVERY", "-recovery",NVM_TYPE_RECOVERY} 158316485Sdavidcs}; 159316485Sdavidcs 160316485Sdavidcs#define IMAGE_TABLE_SIZE (sizeof(g_image_table) / sizeof(struct image_map)) 161316485Sdavidcs 162316485Sdavidcs#endif /* #ifdef DEFINE_IMAGE_TABLE */ 163316485Sdavidcs#define MAX_NVM_DIR_ENTRIES 150 164316485Sdavidcs/* Note: The has given 150 possible entries since anyway each file captures at least one page. */ 165316485Sdavidcs 166316485Sdavidcsstruct nvm_dir { 167316485Sdavidcs s32 seq; /* This dword is used to indicate whether this dir is valid, and whether it is more updated than the other dir */ 168316485Sdavidcs#define NVM_DIR_NEXT_MFW_MASK 0x00000001 169316485Sdavidcs#define NVM_DIR_SEQ_MASK 0xfffffffe 170316485Sdavidcs#define NVM_DIR_NEXT_MFW(seq) ((seq) & NVM_DIR_NEXT_MFW_MASK) 171316485Sdavidcs#define NVM_DIR_UPDATE_SEQ(_seq, swap_mfw) \ 172316485Sdavidcs do { \ 173316485Sdavidcs _seq = (((_seq + 2) & NVM_DIR_SEQ_MASK) | (NVM_DIR_NEXT_MFW(_seq ^ swap_mfw))); \ 174316485Sdavidcs } while (0) 175316485Sdavidcs#define IS_DIR_SEQ_VALID(seq) ((seq & NVM_DIR_SEQ_MASK) != NVM_DIR_SEQ_MASK) 176316485Sdavidcs 177316485Sdavidcs u32 num_images; 178316485Sdavidcs u32 rsrv; 179316485Sdavidcs struct nvm_code_entry code[1]; /* Up to MAX_NVM_DIR_ENTRIES */ 180316485Sdavidcs}; 181316485Sdavidcs#define NVM_DIR_SIZE(_num_images) (sizeof(struct nvm_dir) + (_num_images - 1) * sizeof(struct nvm_code_entry) + NVM_CRC_SIZE) 182316485Sdavidcs 183316485Sdavidcsstruct nvm_vpd_image { 184316485Sdavidcs u32 format_revision; 185316485Sdavidcs#define VPD_IMAGE_VERSION 1 186316485Sdavidcs 187316485Sdavidcs /* This array length depends on the number of VPD fields */ 188316485Sdavidcs u8 vpd_data[1]; 189316485Sdavidcs}; 190316485Sdavidcs 191316485Sdavidcs/**************************************************************************** 192316485Sdavidcs * NVRAM FULL MAP * 193316485Sdavidcs ****************************************************************************/ 194316485Sdavidcs#define DIR_ID_1 (0) 195316485Sdavidcs#define DIR_ID_2 (1) 196316485Sdavidcs#define MAX_DIR_IDS (2) 197316485Sdavidcs 198316485Sdavidcs#define MFW_BUNDLE_1 (0) 199316485Sdavidcs#define MFW_BUNDLE_2 (1) 200316485Sdavidcs#define MAX_MFW_BUNDLES (2) 201316485Sdavidcs 202316485Sdavidcs#define FLASH_PAGE_SIZE 0x1000 203316485Sdavidcs#define NVM_DIR_MAX_SIZE (FLASH_PAGE_SIZE) /* 4Kb */ 204316485Sdavidcs#define ASIC_MIM_MAX_SIZE (300*FLASH_PAGE_SIZE) /* 1.2Mb */ 205316485Sdavidcs#define FPGA_MIM_MAX_SIZE (62*FLASH_PAGE_SIZE) /* 250Kb */ 206316485Sdavidcs 207316485Sdavidcs/* Each image must start on its own page. Bootstrap and LIM are bound together, so they can share the same page. 208316485Sdavidcs * The LIM itself should be very small, so limit it to 8Kb, but in order to open a new page, we decrement the bootstrap size out of it. 209316485Sdavidcs */ 210316485Sdavidcs#define LIM_MAX_SIZE ((2*FLASH_PAGE_SIZE) - sizeof(struct legacy_bootstrap_region) - NVM_RSV_SIZE) 211316485Sdavidcs#define LIM_OFFSET (NVM_OFFSET(lim_image)) 212316485Sdavidcs#define NVM_RSV_SIZE (44) 213316485Sdavidcs#define MIM_MAX_SIZE(is_asic) ((is_asic) ? ASIC_MIM_MAX_SIZE : FPGA_MIM_MAX_SIZE ) 214316485Sdavidcs#define MIM_OFFSET(idx, is_asic) (NVM_OFFSET(dir[MAX_MFW_BUNDLES]) + ((idx == NVM_TYPE_MIM2) ? MIM_MAX_SIZE(is_asic) : 0)) 215316485Sdavidcs#define NVM_FIXED_AREA_SIZE(is_asic) (sizeof(struct nvm_image) + MIM_MAX_SIZE(is_asic)*2) 216316485Sdavidcs 217316485Sdavidcsunion nvm_dir_union { 218316485Sdavidcs struct nvm_dir dir; 219316485Sdavidcs u8 page[FLASH_PAGE_SIZE]; 220316485Sdavidcs}; 221316485Sdavidcs 222316485Sdavidcs/* Address 223316485Sdavidcs * +-------------------+ 0x000000 224316485Sdavidcs * | Bootstrap: | 225316485Sdavidcs * | magic_number | 226316485Sdavidcs * | sram_start_addr | 227316485Sdavidcs * | code_len | 228316485Sdavidcs * | code_start_addr | 229316485Sdavidcs * | crc | 230316485Sdavidcs * +-------------------+ 0x000014 231316485Sdavidcs * | rsrv | 232316485Sdavidcs * +-------------------+ 0x000040 233316485Sdavidcs * | LIM | 234316485Sdavidcs * +-------------------+ 0x002000 235316485Sdavidcs * | Dir1 | 236316485Sdavidcs * +-------------------+ 0x003000 237316485Sdavidcs * | Dir2 | 238316485Sdavidcs * +-------------------+ 0x004000 239316485Sdavidcs * | MIM1 | 240316485Sdavidcs * +-------------------+ 0x130000 241316485Sdavidcs * | MIM2 | 242316485Sdavidcs * +-------------------+ 0x25C000 243316485Sdavidcs * | Rest Images: | 244316485Sdavidcs * | TIM1/2 | 245316485Sdavidcs * | MFW_TRACE1/2 | 246316485Sdavidcs * | Eagle/Falcon FW | 247316485Sdavidcs * | PCIE/AVS FW | 248316485Sdavidcs * | MBA/CCM/L2B | 249316485Sdavidcs * | VPD | 250316485Sdavidcs * | optic_modules | 251316485Sdavidcs * | ... | 252316485Sdavidcs * +-------------------+ 0x400000 253316485Sdavidcs*/ 254316485Sdavidcsstruct nvm_image { 255316485Sdavidcs/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 256316485Sdavidcs /* NVM Offset (size) */ 257316485Sdavidcs struct legacy_bootstrap_region bootstrap; /* 0x000000 (0x000014) */ 258316485Sdavidcs u8 rsrv[NVM_RSV_SIZE]; /* 0x000014 (0x00002c) */ 259316485Sdavidcs u8 lim_image[LIM_MAX_SIZE]; /* 0x000040 (0x001fc0) */ 260316485Sdavidcs union nvm_dir_union dir[MAX_MFW_BUNDLES]; /* 0x002000 (0x001000)x2 */ 261316485Sdavidcs /* MIM1_IMAGE 0x004000 (0x12c000) */ 262316485Sdavidcs /* MIM2_IMAGE 0x130000 (0x12c000) */ 263316485Sdavidcs/*********** !!! FIXED SECTIONS !!! DO NOT MODIFY !!! **********************/ 264316485Sdavidcs}; /* 0x134 */ 265316485Sdavidcs 266316485Sdavidcs#define NVM_OFFSET(f) ((u32_t)((int_ptr_t)(&(((struct nvm_image*)0)->f)))) 267316485Sdavidcs 268316485Sdavidcsstruct hw_set_info { 269316485Sdavidcs u32 reg_type; 270316485Sdavidcs#define GRC_REG_TYPE 1 271316485Sdavidcs#define PHY_REG_TYPE 2 272316485Sdavidcs#define PCI_REG_TYPE 4 273316485Sdavidcs 274316485Sdavidcs u32 bank_num; 275316485Sdavidcs u32 pf_num; 276316485Sdavidcs u32 operation; 277316485Sdavidcs#define READ_OP 1 278316485Sdavidcs#define WRITE_OP 2 279316485Sdavidcs#define RMW_SET_OP 3 280316485Sdavidcs#define RMW_CLR_OP 4 281316485Sdavidcs 282316485Sdavidcs u32 reg_addr; 283316485Sdavidcs u32 reg_data; 284316485Sdavidcs 285316485Sdavidcs u32 reset_type; 286316485Sdavidcs#define POR_RESET_TYPE (1 << 0) 287316485Sdavidcs#define HARD_RESET_TYPE (1 << 1) 288316485Sdavidcs#define CORE_RESET_TYPE (1 << 2) 289316485Sdavidcs#define MCP_RESET_TYPE (1 << 3) 290316485Sdavidcs#define PERSET_ASSERT (1 << 4) 291316485Sdavidcs#define PERSET_DEASSERT (1 << 5) 292316485Sdavidcs 293316485Sdavidcs}; 294316485Sdavidcs 295316485Sdavidcsstruct hw_set_image { 296316485Sdavidcs u32 format_version; 297316485Sdavidcs#define HW_SET_IMAGE_VERSION 1 298316485Sdavidcs u32 no_hw_sets; 299316485Sdavidcs /* This array length depends on the no_hw_sets */ 300316485Sdavidcs struct hw_set_info hw_sets[1]; 301316485Sdavidcs}; 302316485Sdavidcs 303316485Sdavidcs#endif //NVM_MAP_H 304