1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/mcp_private.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs/**************************************************************************** 32316485Sdavidcs * 33316485Sdavidcs * Name: mcp_private.h 34316485Sdavidcs * 35316485Sdavidcs * Description: MCP private data. Located in HSI only to provide debug access 36316485Sdavidcs * for diag. 37316485Sdavidcs * 38316485Sdavidcs ****************************************************************************/ 39316485Sdavidcs 40316485Sdavidcs#ifndef MCP_PRIVATE_H 41316485Sdavidcs#define MCP_PRIVATE_H 42316485Sdavidcs 43316485Sdavidcs#if (!defined MFW_SIM) && (!defined RECOVERY) 44316485Sdavidcs#include "eth.h" 45316485Sdavidcs#include "pmm.h" 46316485Sdavidcs#include "ah_eth.h" 47337519Sdavidcs#include "e5_eth.h" 48316485Sdavidcs#endif 49337519Sdavidcs#include "global.h" 50316485Sdavidcs#include "mcp_public.h" 51316485Sdavidcs 52316485Sdavidcstypedef enum active_mf_mode { 53316485Sdavidcs MF_MODE_SF = 0, 54316485Sdavidcs MF_MODE_MF_ALLOWED, 55316485Sdavidcs MF_MODE_MF_SWITCH_INDEPENDENT, 56316485Sdavidcs MF_MODE_NIV 57316485Sdavidcs} active_mf_mode_t; 58316485Sdavidcs 59316485Sdavidcsenum ov_current_cfg { 60316485Sdavidcs CURR_CFG_NONE = 0, 61316485Sdavidcs CURR_CFG_OS, 62316485Sdavidcs CURR_CFG_VENDOR_SPEC, 63316485Sdavidcs CURR_CFG_OTHER, 64316485Sdavidcs CURR_CFG_VC_CLP, 65316485Sdavidcs CURR_CFG_CNU, 66316485Sdavidcs CURR_CFG_DCI, 67316485Sdavidcs CURR_CFG_HII, 68316485Sdavidcs}; 69316485Sdavidcs 70316485Sdavidcsstruct dci_info_global { 71337519Sdavidcs u16 mba_ver; 72337519Sdavidcs u8 current_cfg; 73337519Sdavidcs u8 extern_dci_mgmt; 74316485Sdavidcs u8 pci_bus_num; 75316485Sdavidcs u8 boot_progress; 76316485Sdavidcs}; 77316485Sdavidcs 78316485Sdavidcs/* Resource allocation information of one resource */ 79316485Sdavidcsstruct resource_info_private { 80316485Sdavidcs u16 size; /* number of allocated resources */ 81316485Sdavidcs u16 offset; /* Offset of the 1st resource */ 82316485Sdavidcs u8 flags; 83316485Sdavidcs}; 84316485Sdavidcs 85316485Sdavidcs/* Cache for resource allocation of one PF */ 86316485Sdavidcsstruct res_alloc_cache { 87316485Sdavidcs u8 pf_num; 88316485Sdavidcs struct resource_info_private res[RESOURCE_MAX_NUM]; 89316485Sdavidcs}; 90316485Sdavidcs 91316485Sdavidcsstruct pf_sb_t { 92316485Sdavidcs u8 sb_for_pf_size; 93316485Sdavidcs u8 sb_for_pf_offset; 94316485Sdavidcs u8 sb_for_vf_size; 95316485Sdavidcs u8 sb_for_vf_offset; 96316485Sdavidcs}; 97316485Sdavidcs 98316485Sdavidcs/**************************************/ 99316485Sdavidcs/* */ 100316485Sdavidcs/* P R I V A T E G L O B A L */ 101316485Sdavidcs/* */ 102316485Sdavidcs/**************************************/ 103316485Sdavidcsstruct private_global { 104316485Sdavidcs active_mf_mode_t mf_mode; /* TBD - require initialization */ 105316485Sdavidcs u32 exp_rom_nvm_addr; 106316485Sdavidcs 107316485Sdavidcs /* The pmm_config structure holds all active phy/link configuration */ 108337519Sdavidcs#if (!defined MFW_SIM) && (!defined RECOVERY) 109316485Sdavidcs#ifdef b900 110316485Sdavidcs struct pmm_config eth_cfg; 111337519Sdavidcs#elif b940 112337519Sdavidcs struct ah_eth eth_cfg; 113337519Sdavidcs#elif b510 114337519Sdavidcs struct e5_eth eth_cfg; 115316485Sdavidcs#else 116316485Sdavidcs#endif 117316485Sdavidcs#endif 118316485Sdavidcs u32 lldp_counter; 119316485Sdavidcs 120316485Sdavidcs u32 avs_init_timestamp; 121316485Sdavidcs 122316485Sdavidcs u32 seconds_since_mcp_reset; 123316485Sdavidcs 124316485Sdavidcs u32 last_malloc_dir_used_timestamp; 125316485Sdavidcs#define MAX_USED_DIR_ALLOWED_TIME (3) /* Seconds */ 126316485Sdavidcs 127316485Sdavidcs u32 drv_nvm_state; 128316485Sdavidcs /* Per PF bitmask */ 129337519Sdavidcs#define DRV_NVM_STATE_IN_PROGRESS_MASK (0x0001ffff) 130316485Sdavidcs#define DRV_NVM_STATE_IN_PROGRESS_OFFSET (0) 131337519Sdavidcs#define DRV_NVM_STATE_IN_PROGRESS_VAL_MFW (0x00010000) 132316485Sdavidcs 133316485Sdavidcs u32 storm_fw_ver; 134316485Sdavidcs 135316485Sdavidcs /* OneView data*/ 136316485Sdavidcs struct dci_info_global dci_global; 137316485Sdavidcs 138316485Sdavidcs /* Resource allocation cached data */ 139316485Sdavidcs struct res_alloc_cache res_alloc; 140316485Sdavidcs#define G_RES_ALLOC_P (&g_spad.private_data.global.res_alloc) 141316485Sdavidcs u32 resource_max_values[RESOURCE_MAX_NUM]; 142337519Sdavidcs u32 glb_counter_100ms; 143337519Sdavidcs /*collection of global bits and controls*/ 144337519Sdavidcs u32 flags_and_ctrl; 145337519Sdavidcs#define PRV_GLOBAL_FIO_BMB_INITIATED_MASK 0x00000001 146337519Sdavidcs#define PRV_GLOBAL_FIO_BMB_INITIATED_OFFSET 0 147337519Sdavidcs#define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_MASK 0x00000002 148337519Sdavidcs#define PRV_GLOBAL_ENABLE_NET_THREAD_LONG_RUN_OFFSET 1 149337519Sdavidcs 150337519Sdavidcs#ifdef b900 151337519Sdavidcs u32 es_fir_engines : 8, es_fir_valid_bitmap : 8, es_l2_engines : 8, es_l2_valid_bitmap : 8; 152337519Sdavidcs#endif 153337519Sdavidcs u64 ecc_events; 154316485Sdavidcs}; 155316485Sdavidcs 156316485Sdavidcs/**************************************/ 157316485Sdavidcs/* */ 158316485Sdavidcs/* P R I V A T E P A T H */ 159316485Sdavidcs/* */ 160316485Sdavidcs/**************************************/ 161316485Sdavidcsstruct private_path { 162316485Sdavidcs u32 recovery_countdown; /* Counting down 2 seconds, using TMR3 */ 163316485Sdavidcs#define RECOVERY_MAX_COUNTDOWN_SECONDS 2 164316485Sdavidcs 165316485Sdavidcs u32 drv_load_vars; /* When the seconds_since_mcp_reset gets here */ 166337519Sdavidcs#define DRV_LOAD_DEF_TIMEOUT 10 167316485Sdavidcs#define DRV_LOAD_TIMEOUT_MASK 0x0000ffff 168320162Sdavidcs#define DRV_LOAD_TIMEOUT_OFFSET 0 169316485Sdavidcs#define DRV_LOAD_NEED_FORCE_MASK 0xffff0000 170320162Sdavidcs#define DRV_LOAD_NEED_FORCE_OFFSET 16 171316485Sdavidcs struct load_rsp_stc drv_load_params; 172337519Sdavidcs u64 ecc_events; 173316485Sdavidcs}; 174316485Sdavidcs 175316485Sdavidcs 176316485Sdavidcs/**************************************/ 177316485Sdavidcs/* */ 178316485Sdavidcs/* P R I V A T E P O R T */ 179316485Sdavidcs/* */ 180316485Sdavidcs/**************************************/ 181316485Sdavidcsstruct drv_port_info_t { 182316485Sdavidcs u32_t port_state; 183316485Sdavidcs#define DRV_STATE_LINK_LOCK_FLAG 0x00000001 184316485Sdavidcs#define DRV_WAIT_DBG_PRN 0x00000002 185316485Sdavidcs 186316485Sdavidcs /* There are maximum 8 PFs per port */ 187316485Sdavidcs#define DRV_STATE_LOADED_MASK 0x0000ff00 188320162Sdavidcs#define DRV_STATE_LOADED_OFFSET 8 189316485Sdavidcs 190316485Sdavidcs#define DRV_STATE_PF_TRANSITION_MASK 0x00ff0000 191320162Sdavidcs#define DRV_STATE_PF_TRANSITION_OFFSET 16 192316485Sdavidcs 193316485Sdavidcs#define DRV_STATE_PF_PHY_INIT_MASK 0xff000000 194320162Sdavidcs#define DRV_STATE_PF_PHY_INIT_OFFSET 24 195316485Sdavidcs}; 196316485Sdavidcs 197316485Sdavidcstypedef enum _lldp_subscriber_e { 198316485Sdavidcs LLDP_SUBSCRIBER_MANDATORY = 0, 199337519Sdavidcs LLDP_SUBSCRIBER_SYSTEM, 200316485Sdavidcs LLDP_SUBSCRIBER_DCBX_IEEE, 201316485Sdavidcs LLDP_SUBSCRIBER_DCBX_CEE, 202316485Sdavidcs LLDP_SUBSCRIBER_EEE, 203337519Sdavidcs LLDP_SUBSCRIBER_CDCP, 204316485Sdavidcs LLDP_SUBSCRIBER_DCI, 205337519Sdavidcs LLDP_SUBSCRIBER_UFP, 206337519Sdavidcs LLDP_SUBSCRIBER_NCSI, 207316485Sdavidcs MAX_SUBSCRIBERS 208316485Sdavidcs} lldp_subscriber_e; 209316485Sdavidcs 210316485Sdavidcstypedef struct { 211316485Sdavidcs u16 valid; 212316485Sdavidcs u16 type_len; 213316485Sdavidcs#define LLDP_LEN_MASK (0x01ff) 214320162Sdavidcs#define LLDP_LEN_OFFSET (0) 215316485Sdavidcs#define LLDP_TYPE_MASK (0xfe00) 216320162Sdavidcs#define LLDP_TYPE_OFFSET (9) 217316485Sdavidcs u8 *value_p; 218316485Sdavidcs} tlv_s; 219316485Sdavidcs 220316485Sdavidcstypedef u16(*lldp_prepare_tlv_func)(u8 port, lldp_agent_e lldp_agent, u8 *buffer); 221316485Sdavidcs 222316485Sdavidcstypedef struct { 223316485Sdavidcs u16 valid; 224316485Sdavidcs lldp_prepare_tlv_func func; 225316485Sdavidcs} subscriber_callback_send_s; 226316485Sdavidcs 227316485Sdavidcstypedef u8(*lldp_process_func)(u8 port, u8 num, u8 **tlvs); 228316485Sdavidcs 229316485Sdavidcs#define MAX_NUM_SUBTYPES 4 230316485Sdavidcstypedef struct { 231316485Sdavidcs u8 valid; 232316485Sdavidcs u8 oui[3]; 233316485Sdavidcs u8 subtype_list[MAX_NUM_SUBTYPES]; 234316485Sdavidcs u8 num_subtypes; 235316485Sdavidcs lldp_process_func func; 236316485Sdavidcs} subscriber_callback_receive_s; 237316485Sdavidcs 238316485Sdavidcs#define MAX_ETH_HEADER 14 /* TODO: to be extended per requirements */ 239320162Sdavidcs#define MAX_PACKET_SIZE (1516) /* So it can be devided by 4 */ 240316485Sdavidcs#define LLDP_CHASSIS_ID_TLV_LEN 7 241316485Sdavidcs#define LLDP_PORT_ID_TLV_LEN 7 242316485Sdavidcstypedef struct { 243316485Sdavidcs u16 len; 244316485Sdavidcs u8 header[MAX_ETH_HEADER]; 245316485Sdavidcs} lldp_eth_header_s; 246316485Sdavidcs 247316485Sdavidcstypedef struct { 248316485Sdavidcs struct lldp_config_params_s lldp_config_params; 249316485Sdavidcs u16 lldp_ttl; 250316485Sdavidcs u8 lldp_cur_credit; 251316485Sdavidcs subscriber_callback_send_s subscriber_callback_send[MAX_SUBSCRIBERS]; 252316485Sdavidcs lldp_eth_header_s lldp_eth_header; 253316485Sdavidcs u32 lldp_time_to_send; 254316485Sdavidcs u32 lldp_ttl_expired; 255316485Sdavidcs u32 lldp_sent; 256316485Sdavidcs u8 first_lldp; 257316485Sdavidcs subscriber_callback_receive_s subscriber_callback_receive[MAX_SUBSCRIBERS]; 258316485Sdavidcs} lldp_params_s; 259316485Sdavidcs 260316485Sdavidcs#define MAX_TLVS 20 261316485Sdavidcstypedef struct { 262316485Sdavidcs u8 current_received_tlv_index; 263316485Sdavidcs u8 *received_tlvs[MAX_TLVS]; 264316485Sdavidcs} lldp_receive_data_s; 265316485Sdavidcs 266337519Sdavidcs#define MAX_REGISTERED_TLVS 12 267316485Sdavidcs 268316485Sdavidcstypedef struct { 269316485Sdavidcs u32 config; /* Uses same defines as local config plus some more below*/ 270316485Sdavidcs#define DCBX_MODE_MASK 0x00000010 271320162Sdavidcs#define DCBX_MODE_OFFSET 4 272316485Sdavidcs#define DCBX_MODE_DRIVER 0 273316485Sdavidcs#define DCBX_MODE_DEFAULT 1 274316485Sdavidcs#define DCBX_CHANGED_MASK 0x00000f00 275320162Sdavidcs#define DCBX_CHANGED_OFFSET 8 276316485Sdavidcs#define DCBX_CONTROL_CHANGED_MASK 0x00000100 277320162Sdavidcs#define DCBX_CONTROL_CHANGED_OFFSET 8 278316485Sdavidcs#define DCBX_PFC_CHANGED_MASK 0x00000200 279320162Sdavidcs#define DCBX_PFC_CHANGED_OFFSET 9 280316485Sdavidcs#define DCBX_ETS_CHANGED_MASK 0x00000400 281320162Sdavidcs#define DCBX_ETS_CHANGED_OFFSET 10 282316485Sdavidcs#define DCBX_APP_CHANGED_MASK 0x00000800 283320162Sdavidcs#define DCBX_APP_CHANGED_OFFSET 11 284316485Sdavidcs 285316485Sdavidcs u32 seq_no; 286316485Sdavidcs u32 ack_no; 287316485Sdavidcs u32 received_seq_no; 288316485Sdavidcs u8 tc_map[8]; 289316485Sdavidcs u8 num_used_tcs; 290316485Sdavidcs} dcbx_state_s; 291316485Sdavidcs 292316485Sdavidcs#ifdef CONFIG_HP_DCI_SUPPORT 293316485Sdavidcsstruct dci_info_port { 294316485Sdavidcs u32 config; 295320162Sdavidcs#define DCI_PORT_CFG_ENABLE_OFFSET (0) 296320162Sdavidcs#define DCI_PORT_CFG_ENABLE_MASK (1 << DCI_PORT_CFG_ENABLE_OFFSET) 297320162Sdavidcs#define DCI_PORT_CFG_ENABLE_DIAG_OFFSET (1) 298320162Sdavidcs#define DCI_PORT_CFG_ENABLE_DIAG_MASK (1 << DCI_PORT_CFG_ENABLE_DIAG_OFFSET) 299320162Sdavidcs#define DCI_PORT_CFG_DIAG_L_LOOP_OFFSET (2) 300320162Sdavidcs#define DCI_PORT_CFG_DIAG_L_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_L_LOOP_OFFSET) 301320162Sdavidcs#define DCI_PORT_CFG_DIAG_R_LOOP_OFFSET (3) 302320162Sdavidcs#define DCI_PORT_CFG_DIAG_R_LOOP_MASK (1 << DCI_PORT_CFG_DIAG_R_LOOP_OFFSET) 303316485Sdavidcs 304316485Sdavidcs}; 305316485Sdavidcs#endif 306316485Sdavidcs 307337519Sdavidcsstruct lldp_cdcp { 308337519Sdavidcs u32 flags; 309337519Sdavidcs#define NTPMR_TTL_EXPIRED 0x00000001 310337519Sdavidcs#define CDCP_TLV_RCVD 0x00000002 311337519Sdavidcs#define CDCP_TLV_SENT 0x00000004 312337519Sdavidcs 313337519Sdavidcs u32 remote_mib; 314337519Sdavidcs#define CDCP_ROLE_MASK 0x00000001 315337519Sdavidcs#define CDCP_ROLE_OFFSET 0 316337519Sdavidcs#define CDCP_ROLE_BRIDGE 0x0 317337519Sdavidcs#define CDCP_ROLE_STATION 0x1 318337519Sdavidcs 319337519Sdavidcs#define CDCP_SCOMP_MASK 0x00000002 320337519Sdavidcs#define CDCP_SCOMP_OFFSET 1 321337519Sdavidcs 322337519Sdavidcs#define CDCP_CHAN_CAP_MASK 0x0000fff0 323337519Sdavidcs#define CDCP_CHAN_CAP_OFFSET 4 324337519Sdavidcs 325337519Sdavidcs u32 num_of_chan; 326337519Sdavidcs}; 327337519Sdavidcs 328337519Sdavidcs/* Accommodates link-tlv size for max-pf scids (27) + end-of-tlv size (2) */ 329337519Sdavidcs#define UFP_REQ_MAX_PAYLOAD_SIZE (32) 330337519Sdavidcs 331337519Sdavidcs/* Accommodates max-NIC props-tlv-size (117:5 +(16*7)), link-tlv (27), 332337519Sdavidcs * end-tlv (2). 333337519Sdavidcs */ 334337519Sdavidcs#define UFP_RSP_MAX_PAYLOAD_SIZE (160) 335337519Sdavidcsstruct ufp_info_port { 336337519Sdavidcs u8 req_payload[UFP_REQ_MAX_PAYLOAD_SIZE]; 337337519Sdavidcs u8 rsp_payload[UFP_RSP_MAX_PAYLOAD_SIZE]; 338337519Sdavidcs u16 req_len; 339337519Sdavidcs u16 rsp_len; 340337519Sdavidcs u8 switch_version; 341337519Sdavidcs u8 switch_status; 342337519Sdavidcs u8 flags; 343337519Sdavidcs#define UFP_CAP_ENABLED (1 << 0) 344337519Sdavidcs#define UFP_REQ_SENT (1 << 1) 345337519Sdavidcs#define UFP_RSP_SENT (1 << 2) 346337519Sdavidcs#define UFP_CAP_SENT (1 << 3) 347337519Sdavidcs u8 pending_flags; 348337519Sdavidcs#define UFP_REQ_PENDING (1 << 0) 349337519Sdavidcs#define UFP_RSP_PENDING (1 << 1) 350337519Sdavidcs}; 351337519Sdavidcs 352337519Sdavidcs#define UFP_ENABLED(_port_) \ 353337519Sdavidcs (g_spad.private_data.port[_port_].ufp_port.flags & UFP_CAP_ENABLED) 354337519Sdavidcs 355337519Sdavidcs/* Max 200-byte packet, accommodates UFP_RSP_MAX_PAYLOAD_SIZE */ 356337519Sdavidcs#define ECP_MAX_PKT_SIZE (200) 357337519Sdavidcs 358337519Sdavidcs/* Tx-state machine, Qbg variable names specified in comments on the right */ 359337519Sdavidcsstruct ecp_tx_state { 360337519Sdavidcs u8 tx_pkt[ECP_MAX_PKT_SIZE]; 361337519Sdavidcs BOOL ulp_req_rcvd; /* requestReceived */ 362337519Sdavidcs BOOL ack_rcvd; /* ackReceived */ 363337519Sdavidcs u16 req_seq_num; /* sequence */ 364337519Sdavidcs 365337519Sdavidcs /* State used for timer-based retries */ 366337519Sdavidcs u16 ack_timer_counter; 367337519Sdavidcs#define ECP_TIMEOUT_COUNT 1 /* 1 second to detect ACK timeout */ 368337519Sdavidcs u16 num_retries; /* retries */ 369337519Sdavidcs#define ECP_MAX_RETRIES 3 370337519Sdavidcs u32 tx_errors; /* txErrors */ 371337519Sdavidcs u32 ulp_pkt_len; 372337519Sdavidcs}; 373337519Sdavidcs 374337519Sdavidcstypedef void (*ulp_rx_indication_t)(u8 port, u16 subtype, u32 pkt_len, u8 *pkt); 375337519Sdavidcs/* Rx state machine, Qbg variable names specified in comments on the right */ 376337519Sdavidcsstruct ecp_rx_state { 377337519Sdavidcs BOOL ecpdu_rcvd; /* ecpduReceived */ 378337519Sdavidcs u16 last_req_seq; /* lastSeq */ 379337519Sdavidcs u8 first_req_rcvd; 380337519Sdavidcs u8 rsvd; 381337519Sdavidcs ulp_rx_indication_t rx_cb_func; 382337519Sdavidcs}; 383337519Sdavidcs 384337519Sdavidcsstruct ecp_state_s { 385337519Sdavidcs struct ecp_tx_state tx_state; 386337519Sdavidcs struct ecp_rx_state rx_state; 387337519Sdavidcs u16 subtype; 388337519Sdavidcs}; 389337519Sdavidcs 390316485Sdavidcsstruct private_port { 391316485Sdavidcs struct drv_port_info_t port_info; 392316485Sdavidcs active_mf_mode_t mf_mode; 393316485Sdavidcs u32 prev_link_change_count; 394316485Sdavidcs /* LLDP structures */ 395316485Sdavidcs lldp_params_s lldp_params[LLDP_MAX_LLDP_AGENTS]; 396316485Sdavidcs lldp_receive_data_s lldp_receive_data[MAX_SUBSCRIBERS]; 397316485Sdavidcs 398316485Sdavidcs /* DCBX */ 399316485Sdavidcs dcbx_state_s dcbx_state; 400316485Sdavidcs 401316485Sdavidcs u32 net_buffer[MAX_PACKET_SIZE / 4]; /* Buffer to send any packet to network */ 402316485Sdavidcs 403316485Sdavidcs /* time stamp of the end of NIG drain time for the TX drain */ 404316485Sdavidcs u32 nig_drain_end_ts; 405316485Sdavidcs /* time stamp of the end of NIG drain time for the TC pause drain, this timer is used togther for all TC */ 406316485Sdavidcs u32 nig_drain_tc_end_ts; 407337519Sdavidcs u32 tc_drain_en_bitmap; 408316485Sdavidcs tlv_s lldp_core_tlv_desc[LLDP_MAX_LLDP_AGENTS][MAX_REGISTERED_TLVS]; 409316485Sdavidcs u8 current_core_tlv_num[LLDP_MAX_LLDP_AGENTS]; 410316485Sdavidcs struct mcp_mac lldp_mac; 411316485Sdavidcs#ifdef CONFIG_HP_DCI_SUPPORT 412316485Sdavidcs struct dci_info_port dci_port; 413316485Sdavidcs#endif 414337519Sdavidcs struct lldp_cdcp cdcp_info; 415337519Sdavidcs struct ufp_info_port ufp_port; 416337519Sdavidcs struct ecp_state_s ecp_info; 417337519Sdavidcs struct lldp_stats_stc lldp_stats[LLDP_MAX_LLDP_AGENTS]; 418316485Sdavidcs u32 temperature; 419337519Sdavidcs u8 prev_ext_lasi_status; 420337519Sdavidcs u8 rsvd1; 421337519Sdavidcs u16 rsvd2; 422316485Sdavidcs 423316485Sdavidcs}; 424316485Sdavidcs 425316485Sdavidcs/**************************************/ 426316485Sdavidcs/* */ 427316485Sdavidcs/* P R I V A T E F U N C */ 428316485Sdavidcs/* */ 429316485Sdavidcs/**************************************/ 430316485Sdavidcsstruct drv_func_info_t { 431316485Sdavidcs u32_t func_state; 432316485Sdavidcs#define DRV_STATE_UNKNOWN 0x00000000 433316485Sdavidcs#define DRV_STATE_UNLOADED 0x00000001 434316485Sdavidcs#define DRV_STATE_D3 0x00000004 435316485Sdavidcs 436316485Sdavidcs#define DRV_STATE_PRESENT_FLAG 0x00000100 437316485Sdavidcs#define DRV_STATE_RUNNING (0x00000002 | DRV_STATE_PRESENT_FLAG) 438316485Sdavidcs 439316485Sdavidcs#define DRV_STATE_NOT_RESPONDING 0x00000003 /* Will result with non-zero value when compared with DRV_STATE_RUNNING or with DRV_STATE_UNLOADED */ 440316485Sdavidcs#define DRV_STATE_BACK_AFTER_TO (DRV_STATE_NOT_RESPONDING | DRV_STATE_PRESENT_FLAG) 441316485Sdavidcs 442316485Sdavidcs#define DRV_STATE_DIAG (0x00000010 | DRV_STATE_PRESENT_FLAG) 443316485Sdavidcs 444316485Sdavidcs#define DRV_STATE_TRANSITION_FLAG 0x00001000 445316485Sdavidcs#define DRV_STATE_LOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG) 446316485Sdavidcs#define DRV_STATE_UNLOADING_TRANSITION (DRV_STATE_TRANSITION_FLAG | DRV_STATE_PRESENT_FLAG | DRV_STATE_UNLOADED) 447316485Sdavidcs 448316485Sdavidcs u32_t driver_last_activity; 449316485Sdavidcs 450316485Sdavidcs u32_t wol_mac_addr[2]; 451316485Sdavidcs u32_t drv_feature_support; /* See DRV_MB_PARAM_FEATURE_SUPPORT_FUNC_* */ 452316485Sdavidcs 453316485Sdavidcs u8_t unload_wol_param; /* See drv_mb_param */ 454316485Sdavidcs u8_t eswitch_mode; 455337519Sdavidcs u8_t ppfid_bmp; 456316485Sdavidcs}; 457316485Sdavidcs 458316485Sdavidcsstruct dci_info_func { 459316485Sdavidcs u8 config; 460320162Sdavidcs#define DCI_FUNC_CFG_FNIC_ENABLE_OFFSET (0) 461320162Sdavidcs#define DCI_FUNC_CFG_FNIC_ENABLE_MASK (1 << DCI_FUNC_CFG_FNIC_ENABLE_OFFSET) 462320162Sdavidcs#define DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET (1) 463320162Sdavidcs#define DCI_FUNC_CFG_OS_MTU_OVERRIDE_MASK (1 << DCI_FUNC_CFG_OS_MTU_OVERRIDE_OFFSET) 464320162Sdavidcs#define DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET (2) 465320162Sdavidcs#define DCI_FUNC_CFG_DIAG_WOL_ENABLE_MASK (1 << DCI_FUNC_CFG_DIAG_WOL_ENABLE_OFFSET) 466316485Sdavidcs 467316485Sdavidcs u8 drv_state; 468316485Sdavidcs u16 fcoe_cvid; 469316485Sdavidcs u8 fcoe_fabric_name[8]; 470337519Sdavidcs#define CONNECTION_ID_LENGTH 16 471337519Sdavidcs u8 local_conn_id[CONNECTION_ID_LENGTH]; 472316485Sdavidcs}; 473316485Sdavidcs 474316485Sdavidcsstruct private_func { 475316485Sdavidcs struct drv_func_info_t func_info; 476316485Sdavidcs u32 init_hw_page; 477316485Sdavidcs struct pf_sb_t sb; 478316485Sdavidcs struct dci_info_func dci_func; 479316485Sdavidcs}; 480316485Sdavidcs 481316485Sdavidcs 482316485Sdavidcs/**************************************/ 483316485Sdavidcs/* */ 484316485Sdavidcs/* P R I V A T E D A T A */ 485316485Sdavidcs/* */ 486316485Sdavidcs/**************************************/ 487316485Sdavidcsstruct mcp_private_data { 488316485Sdavidcs /* Basically no need for section offsets here, since this is private data. 489316485Sdavidcs * TBD - should consider adding section offsets if we want diag to parse this correctly !! 490316485Sdavidcs */ 491316485Sdavidcs struct private_global global; 492316485Sdavidcs struct private_path path[MCP_GLOB_PATH_MAX]; 493316485Sdavidcs struct private_port port[MCP_GLOB_PORT_MAX]; 494316485Sdavidcs struct private_func func[MCP_GLOB_FUNC_MAX]; 495316485Sdavidcs 496316485Sdavidcs}; 497316485Sdavidcs#endif /* MCP_PRIVATE_H */ 498