1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/fcoe_common.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31320162Sdavidcs 32316485Sdavidcs#ifndef __FCOE_COMMON__ 33316485Sdavidcs#define __FCOE_COMMON__ 34316485Sdavidcs/*********************/ 35316485Sdavidcs/* FCOE FW CONSTANTS */ 36316485Sdavidcs/*********************/ 37316485Sdavidcs 38316485Sdavidcs#define FC_ABTS_REPLY_MAX_PAYLOAD_LEN 12 39316485Sdavidcs 40316485Sdavidcs 41316485Sdavidcs 42316485Sdavidcs 43316485Sdavidcs 44316485Sdavidcs/* 45316485Sdavidcs * The fcoe storm task context protection-information of Ystorm 46316485Sdavidcs */ 47316485Sdavidcsstruct protection_info_ctx 48316485Sdavidcs{ 49316485Sdavidcs __le16 flags; 50316485Sdavidcs#define PROTECTION_INFO_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 51316485Sdavidcs#define PROTECTION_INFO_CTX_HOST_INTERFACE_SHIFT 0 52316485Sdavidcs#define PROTECTION_INFO_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 53316485Sdavidcs#define PROTECTION_INFO_CTX_DIF_TO_PEER_SHIFT 2 54316485Sdavidcs#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_MASK 0x1 /* 0=no, 1=yes */ 55316485Sdavidcs#define PROTECTION_INFO_CTX_VALIDATE_DIX_APP_TAG_SHIFT 3 56316485Sdavidcs#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 57316485Sdavidcs#define PROTECTION_INFO_CTX_INTERVAL_SIZE_LOG_SHIFT 4 58316485Sdavidcs#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 59316485Sdavidcs#define PROTECTION_INFO_CTX_VALIDATE_DIX_REF_TAG_SHIFT 8 60316485Sdavidcs#define PROTECTION_INFO_CTX_RESERVED0_MASK 0x7F 61316485Sdavidcs#define PROTECTION_INFO_CTX_RESERVED0_SHIFT 9 62316485Sdavidcs u8 dix_block_size /* Source protection data size */; 63316485Sdavidcs u8 dst_size /* Destination protection data size */; 64316485Sdavidcs}; 65316485Sdavidcs 66316485Sdavidcs/* 67316485Sdavidcs * The fcoe storm task context protection-information of Ystorm 68316485Sdavidcs */ 69316485Sdavidcsunion protection_info_union_ctx 70316485Sdavidcs{ 71316485Sdavidcs struct protection_info_ctx info; 72316485Sdavidcs __le32 value /* If and only if this field is not 0 then protection is set */; 73316485Sdavidcs}; 74316485Sdavidcs 75316485Sdavidcs/* 76320162Sdavidcs * FCP CMD payload 77320162Sdavidcs */ 78320162Sdavidcsstruct fcoe_fcp_cmd_payload 79320162Sdavidcs{ 80320162Sdavidcs __le32 opaque[8] /* The FCP_CMD payload */; 81320162Sdavidcs}; 82320162Sdavidcs 83320162Sdavidcs/* 84316485Sdavidcs * FCP RSP payload 85316485Sdavidcs */ 86320162Sdavidcsstruct fcoe_fcp_rsp_payload 87320162Sdavidcs{ 88320162Sdavidcs __le32 opaque[6] /* The FCP_RSP payload */; 89320162Sdavidcs}; 90320162Sdavidcs 91320162Sdavidcs/* 92320162Sdavidcs * FCP RSP payload 93320162Sdavidcs */ 94316485Sdavidcsstruct fcp_rsp_payload_padded 95316485Sdavidcs{ 96316485Sdavidcs struct fcoe_fcp_rsp_payload rsp_payload /* The FCP_RSP payload */; 97316485Sdavidcs __le32 reserved[2]; 98316485Sdavidcs}; 99316485Sdavidcs 100316485Sdavidcs/* 101316485Sdavidcs * FCP RSP payload 102316485Sdavidcs */ 103320162Sdavidcsstruct fcoe_fcp_xfer_payload 104320162Sdavidcs{ 105320162Sdavidcs __le32 opaque[3] /* The FCP_XFER payload */; 106320162Sdavidcs}; 107320162Sdavidcs 108320162Sdavidcs/* 109320162Sdavidcs * FCP RSP payload 110320162Sdavidcs */ 111316485Sdavidcsstruct fcp_xfer_payload_padded 112316485Sdavidcs{ 113316485Sdavidcs struct fcoe_fcp_xfer_payload xfer_payload /* The FCP_XFER payload */; 114316485Sdavidcs __le32 reserved[5]; 115316485Sdavidcs}; 116316485Sdavidcs 117316485Sdavidcs/* 118316485Sdavidcs * Task params 119316485Sdavidcs */ 120316485Sdavidcsstruct fcoe_tx_data_params 121316485Sdavidcs{ 122316485Sdavidcs __le32 data_offset /* Data offset */; 123316485Sdavidcs __le32 offset_in_io /* For sequence cleanup */; 124316485Sdavidcs u8 flags; 125316485Sdavidcs#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_MASK 0x1 /* Should we send offset in IO */ 126316485Sdavidcs#define FCOE_TX_DATA_PARAMS_OFFSET_IN_IO_VALID_SHIFT 0 127316485Sdavidcs#define FCOE_TX_DATA_PARAMS_DROP_DATA_MASK 0x1 /* Should the PBF drop this data */ 128316485Sdavidcs#define FCOE_TX_DATA_PARAMS_DROP_DATA_SHIFT 1 129316485Sdavidcs#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_MASK 0x1 /* Indication if the task after seqqence recovery flow */ 130316485Sdavidcs#define FCOE_TX_DATA_PARAMS_AFTER_SEQ_REC_SHIFT 2 131316485Sdavidcs#define FCOE_TX_DATA_PARAMS_RESERVED0_MASK 0x1F 132316485Sdavidcs#define FCOE_TX_DATA_PARAMS_RESERVED0_SHIFT 3 133316485Sdavidcs u8 dif_residual /* Residual from protection interval */; 134316485Sdavidcs __le16 seq_cnt /* Sequence counter */; 135316485Sdavidcs __le16 single_sge_saved_offset /* Saved SGE length for single SGE case */; 136316485Sdavidcs __le16 next_dif_offset /* Tracking next DIF offset in FC payload */; 137316485Sdavidcs __le16 seq_id /* Sequence ID (Set [saved] upon seq_cnt==0 (start of sequence) and used throughout sequence) */; 138316485Sdavidcs __le16 reserved3; 139316485Sdavidcs}; 140316485Sdavidcs 141316485Sdavidcs/* 142316485Sdavidcs * Middle path parameters: FC header fields provided by the driver 143316485Sdavidcs */ 144316485Sdavidcsstruct fcoe_tx_mid_path_params 145316485Sdavidcs{ 146316485Sdavidcs __le32 parameter; 147316485Sdavidcs u8 r_ctl; 148316485Sdavidcs u8 type; 149316485Sdavidcs u8 cs_ctl; 150316485Sdavidcs u8 df_ctl; 151316485Sdavidcs __le16 rx_id; 152316485Sdavidcs __le16 ox_id; 153316485Sdavidcs}; 154316485Sdavidcs 155316485Sdavidcs/* 156316485Sdavidcs * Task params 157316485Sdavidcs */ 158316485Sdavidcsstruct fcoe_tx_params 159316485Sdavidcs{ 160316485Sdavidcs struct fcoe_tx_data_params data /* Data offset */; 161316485Sdavidcs struct fcoe_tx_mid_path_params mid_path; 162316485Sdavidcs}; 163316485Sdavidcs 164316485Sdavidcs/* 165316485Sdavidcs * Union of FCP CMD payload \ TX params \ ABTS \ Cleanup 166316485Sdavidcs */ 167316485Sdavidcsunion fcoe_tx_info_union_ctx 168316485Sdavidcs{ 169316485Sdavidcs struct fcoe_fcp_cmd_payload fcp_cmd_payload /* FCP CMD payload */; 170316485Sdavidcs struct fcp_rsp_payload_padded fcp_rsp_payload /* FCP RSP payload */; 171316485Sdavidcs struct fcp_xfer_payload_padded fcp_xfer_payload /* FCP XFER payload */; 172316485Sdavidcs struct fcoe_tx_params tx_params /* Task TX params */; 173316485Sdavidcs}; 174316485Sdavidcs 175316485Sdavidcs/* 176320162Sdavidcs * Data sgl 177320162Sdavidcs */ 178320162Sdavidcsstruct fcoe_slow_sgl_ctx 179320162Sdavidcs{ 180320162Sdavidcs struct regpair base_sgl_addr /* Address of first SGE in SGL */; 181320162Sdavidcs __le16 curr_sge_off /* Offset in current BD (in bytes) */; 182320162Sdavidcs __le16 remainder_num_sges /* Number of BDs */; 183320162Sdavidcs __le16 curr_sgl_index /* Index of current SGE */; 184320162Sdavidcs __le16 reserved; 185320162Sdavidcs}; 186320162Sdavidcs 187320162Sdavidcs/* 188320162Sdavidcs * Union of DIX SGL \ cached DIX sges 189320162Sdavidcs */ 190320162Sdavidcsunion fcoe_dix_desc_ctx 191320162Sdavidcs{ 192320162Sdavidcs struct fcoe_slow_sgl_ctx dix_sgl /* DIX slow-SGL data base */; 193320162Sdavidcs struct scsi_sge cached_dix_sge /* Cached DIX sge */; 194320162Sdavidcs}; 195320162Sdavidcs 196320162Sdavidcs/* 197316485Sdavidcs * The fcoe storm task context of Ystorm 198316485Sdavidcs */ 199316485Sdavidcsstruct ystorm_fcoe_task_st_ctx 200316485Sdavidcs{ 201337519Sdavidcs u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 202316485Sdavidcs u8 sgl_mode; 203316485Sdavidcs#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 204316485Sdavidcs#define YSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 0 205316485Sdavidcs#define YSTORM_FCOE_TASK_ST_CTX_RSRV_MASK 0x7F 206316485Sdavidcs#define YSTORM_FCOE_TASK_ST_CTX_RSRV_SHIFT 1 207316485Sdavidcs u8 cached_dix_sge /* Dix sge is cached on task context */; 208316485Sdavidcs u8 expect_first_xfer /* Will let Ystorm know when it should initialize fcp_cmd_payload_params_union.params */; 209316485Sdavidcs __le32 num_pbf_zero_write /* The amount of bytes that PBF should dummy write - Relevant for protection only. */; 210316485Sdavidcs union protection_info_union_ctx protection_info_union /* Protection information */; 211316485Sdavidcs __le32 data_2_trns_rem /* Entire SGL-buffer remainder */; 212316485Sdavidcs struct scsi_sgl_params sgl_params; 213316485Sdavidcs u8 reserved1[12]; 214316485Sdavidcs union fcoe_tx_info_union_ctx tx_info_union /* Union of FCP CMD payload / TX params / ABTS / Cleanup */; 215316485Sdavidcs union fcoe_dix_desc_ctx dix_desc /* Union of DIX SGL / cached DIX sges */; 216316485Sdavidcs struct scsi_cached_sges data_desc /* Data cached SGEs */; 217316485Sdavidcs __le16 ox_id /* OX-ID. Used in Target mode only */; 218316485Sdavidcs __le16 rx_id /* RX-ID. Used in Target mode only */; 219316485Sdavidcs __le32 task_rety_identifier /* Parameter field of the FCP CMDs FC header */; 220316485Sdavidcs u8 reserved2[8]; 221316485Sdavidcs}; 222316485Sdavidcs 223316485Sdavidcsstruct e4_ystorm_fcoe_task_ag_ctx 224316485Sdavidcs{ 225316485Sdavidcs u8 byte0 /* cdu_validation */; 226316485Sdavidcs u8 byte1 /* state */; 227316485Sdavidcs __le16 word0 /* icid */; 228316485Sdavidcs u8 flags0; 229316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 230316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 231316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 232316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 233316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 234316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 235316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 236316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 237316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 238316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 239316485Sdavidcs u8 flags1; 240316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 241316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 242316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 243316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 244316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 245316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 246316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 247316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 248316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 249316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 250316485Sdavidcs u8 flags2; 251316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 252316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 253316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 254316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 255316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 256316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 257316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 258316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 259316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 260316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 261316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 262316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 263316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 264316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 265316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 266316485Sdavidcs#define E4_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 267316485Sdavidcs u8 byte2 /* byte2 */; 268316485Sdavidcs __le32 reg0 /* reg0 */; 269316485Sdavidcs u8 byte3 /* byte3 */; 270316485Sdavidcs u8 byte4 /* byte4 */; 271316485Sdavidcs __le16 rx_id /* word1 */; 272316485Sdavidcs __le16 word2 /* word2 */; 273316485Sdavidcs __le16 word3 /* word3 */; 274316485Sdavidcs __le16 word4 /* word4 */; 275316485Sdavidcs __le16 word5 /* word5 */; 276316485Sdavidcs __le32 reg1 /* reg1 */; 277316485Sdavidcs __le32 reg2 /* reg2 */; 278316485Sdavidcs}; 279316485Sdavidcs 280316485Sdavidcsstruct e4_tstorm_fcoe_task_ag_ctx 281316485Sdavidcs{ 282316485Sdavidcs u8 reserved /* cdu_validation */; 283316485Sdavidcs u8 byte1 /* state */; 284316485Sdavidcs __le16 icid /* icid */; 285316485Sdavidcs u8 flags0; 286316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 287316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 288316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 289316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 290316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 291316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 292316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 293316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 294316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 295316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 296316485Sdavidcs u8 flags1; 297316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 298316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 299316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 300316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 301316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 302316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 303316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 304316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 305316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 306316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 307316485Sdavidcs u8 flags2; 308316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 309316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 310316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 311316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 312316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 313316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 314316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 315316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 316316485Sdavidcs u8 flags3; 317316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 318316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 319316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 320316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 321316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 322316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 323316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 324316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 325316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 326316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 327316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 328316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 329316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 330316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 331316485Sdavidcs u8 flags4; 332316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 333316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 334316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 335316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 336316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 337316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 338316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 339316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 340316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 341316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 342316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 343316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 344316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 345316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 346316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 347316485Sdavidcs#define E4_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 348316485Sdavidcs u8 cleanup_state /* byte2 */; 349316485Sdavidcs __le16 last_sent_tid /* word1 */; 350316485Sdavidcs __le32 rec_rr_tov_exp_timeout /* reg0 */; 351316485Sdavidcs u8 byte3 /* byte3 */; 352316485Sdavidcs u8 byte4 /* byte4 */; 353316485Sdavidcs __le16 word2 /* word2 */; 354316485Sdavidcs __le16 word3 /* word3 */; 355316485Sdavidcs __le16 word4 /* word4 */; 356316485Sdavidcs __le32 data_offset_end_of_seq /* reg1 */; 357316485Sdavidcs __le32 data_offset_next /* reg2 */; 358316485Sdavidcs}; 359316485Sdavidcs 360316485Sdavidcs/* 361320162Sdavidcs * Cached data sges 362320162Sdavidcs */ 363320162Sdavidcsstruct fcoe_exp_ro 364320162Sdavidcs{ 365320162Sdavidcs __le32 data_offset /* data-offset */; 366320162Sdavidcs __le32 reserved /* High data-offset */; 367320162Sdavidcs}; 368320162Sdavidcs 369320162Sdavidcs/* 370320162Sdavidcs * Union of Cleanup address \ expected relative offsets 371320162Sdavidcs */ 372320162Sdavidcsunion fcoe_cleanup_addr_exp_ro_union 373320162Sdavidcs{ 374320162Sdavidcs struct regpair abts_rsp_fc_payload_hi /* Abts flow: first 64 bits of fcPayload, out of 96 */; 375320162Sdavidcs struct fcoe_exp_ro exp_ro /* Expected relative offsets */; 376320162Sdavidcs}; 377320162Sdavidcs 378320162Sdavidcs/* 379320162Sdavidcs * fields coppied from ABTSrsp pckt 380320162Sdavidcs */ 381320162Sdavidcsstruct fcoe_abts_pkt 382320162Sdavidcs{ 383320162Sdavidcs __le32 abts_rsp_fc_payload_lo /* Abts flow: last 32 bits of fcPayload, out of 96 */; 384320162Sdavidcs __le16 abts_rsp_rx_id /* Abts flow: rxId parameter of the abts packet */; 385320162Sdavidcs u8 abts_rsp_rctl /* Abts flow: rctl parameter of the abts packet */; 386320162Sdavidcs u8 reserved2; 387320162Sdavidcs}; 388320162Sdavidcs 389320162Sdavidcs/* 390316485Sdavidcs * FW read- write (modifyable) part The fcoe task storm context of Tstorm 391316485Sdavidcs */ 392316485Sdavidcsstruct fcoe_tstorm_fcoe_task_st_ctx_read_write 393316485Sdavidcs{ 394316485Sdavidcs union fcoe_cleanup_addr_exp_ro_union cleanup_addr_exp_ro_union /* Union of Cleanup address / expected relative offsets */; 395316485Sdavidcs __le16 flags; 396316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_MASK 0x1 /* Rx SGL type. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 397316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RX_SGL_MODE_SHIFT 0 398316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_MASK 0x1 /* Expected first frame flag */ 399316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_EXP_FIRST_FRAME_SHIFT 1 400316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_MASK 0x1 /* Sequence active */ 401316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_ACTIVE_SHIFT 2 402316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_MASK 0x1 /* Sequence timeout for an active Sequence */ 403316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SEQ_TIMEOUT_SHIFT 3 404316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_MASK 0x1 /* Set by Data-in flow. Indicate that this exchange contains a single FCP DATA packet */ 405316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_SINGLE_PKT_IN_EX_SHIFT 4 406316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_MASK 0x1 /* The status of the current out of order received Sequence */ 407316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_OOO_RX_SEQ_STAT_SHIFT 5 408316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_MASK 0x3 /* number of additional CQE that will be produced for this task completion */ 409316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_CQ_ADD_ADV_SHIFT 6 410316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_MASK 0xFF 411316485Sdavidcs#define FCOE_TSTORM_FCOE_TASK_ST_CTX_READ_WRITE_RSRV1_SHIFT 8 412316485Sdavidcs __le16 seq_cnt /* Sequence counter */; 413316485Sdavidcs u8 seq_id /* Sequence id */; 414316485Sdavidcs u8 ooo_rx_seq_id /* The last out of order received SEQ_ID */; 415316485Sdavidcs __le16 rx_id /* RX_ID of the exchange - should match each packet expect for the first */; 416316485Sdavidcs struct fcoe_abts_pkt abts_data /* The last out of order received SEQ_CNT */; 417316485Sdavidcs __le32 e_d_tov_exp_timeout_val /* E_D_TOV timer val (in msec) */; 418316485Sdavidcs __le16 ooo_rx_seq_cnt /* The last out of order received SEQ_CNT */; 419316485Sdavidcs __le16 reserved1; 420316485Sdavidcs}; 421316485Sdavidcs 422316485Sdavidcs/* 423316485Sdavidcs * FW read only part The fcoe task storm context of Tstorm 424316485Sdavidcs */ 425316485Sdavidcsstruct fcoe_tstorm_fcoe_task_st_ctx_read_only 426316485Sdavidcs{ 427337519Sdavidcs u8 task_type /* Task type. use enum fcoe_task_type (use enum fcoe_task_type) */; 428337519Sdavidcs u8 dev_type /* Device type (disk or tape). use enum fcoe_device_type (use enum fcoe_device_type) */; 429316485Sdavidcs u8 conf_supported /* Confirmation supported indication */; 430316485Sdavidcs u8 glbl_q_num /* Global RQ/CQ num to be used for sense data placement/completion */; 431316485Sdavidcs __le32 cid /* CID which that tasks associated to */; 432316485Sdavidcs __le32 fcp_cmd_trns_size /* IO size as reflected in FCP CMD */; 433316485Sdavidcs __le32 rsrv; 434316485Sdavidcs}; 435316485Sdavidcs 436316485Sdavidcs/* 437316485Sdavidcs * The fcoe task storm context of Tstorm 438316485Sdavidcs */ 439316485Sdavidcsstruct tstorm_fcoe_task_st_ctx 440316485Sdavidcs{ 441316485Sdavidcs struct fcoe_tstorm_fcoe_task_st_ctx_read_write read_write /* FW read- write (modifyable) part The fcoe task storm context of Tstorm */; 442316485Sdavidcs struct fcoe_tstorm_fcoe_task_st_ctx_read_only read_only /* FW read only part The fcoe task storm context of Tstorm */; 443316485Sdavidcs}; 444316485Sdavidcs 445316485Sdavidcsstruct e4_mstorm_fcoe_task_ag_ctx 446316485Sdavidcs{ 447316485Sdavidcs u8 byte0 /* cdu_validation */; 448316485Sdavidcs u8 byte1 /* state */; 449316485Sdavidcs __le16 icid /* icid */; 450316485Sdavidcs u8 flags0; 451316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 452316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 453316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 454316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 455316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 456316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 457316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 458316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 459316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 460316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 461316485Sdavidcs u8 flags1; 462316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 463316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 464316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 465316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 466316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 467316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 468316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 469316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 470316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 471316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 472316485Sdavidcs u8 flags2; 473316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 474316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 475316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 476316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 477316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 478316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 479316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 480316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 481316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 482316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 483316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 484316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 485316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 486316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 487316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 488316485Sdavidcs#define E4_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 489316485Sdavidcs u8 cleanup_state /* byte2 */; 490316485Sdavidcs __le32 received_bytes /* reg0 */; 491316485Sdavidcs u8 byte3 /* byte3 */; 492316485Sdavidcs u8 glbl_q_num /* byte4 */; 493316485Sdavidcs __le16 word1 /* word1 */; 494316485Sdavidcs __le16 tid_to_xfer /* word2 */; 495316485Sdavidcs __le16 word3 /* word3 */; 496316485Sdavidcs __le16 word4 /* word4 */; 497316485Sdavidcs __le16 word5 /* word5 */; 498316485Sdavidcs __le32 expected_bytes /* reg1 */; 499316485Sdavidcs __le32 reg2 /* reg2 */; 500316485Sdavidcs}; 501316485Sdavidcs 502316485Sdavidcs/* 503316485Sdavidcs * The fcoe task storm context of Mstorm 504316485Sdavidcs */ 505316485Sdavidcsstruct mstorm_fcoe_task_st_ctx 506316485Sdavidcs{ 507316485Sdavidcs struct regpair rsp_buf_addr /* Buffer to place the sense/response data attached to FCP_RSP frame */; 508316485Sdavidcs __le32 rsrv[2]; 509316485Sdavidcs struct scsi_sgl_params sgl_params; 510316485Sdavidcs __le32 data_2_trns_rem /* Entire SGL buffer size remainder */; 511316485Sdavidcs __le32 data_buffer_offset /* Buffer offset */; 512316485Sdavidcs __le16 parent_id /* Used for multiple continuation in Target mode */; 513316485Sdavidcs __le16 flags; 514316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 515316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_INTERVAL_SIZE_LOG_SHIFT 0 516316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_MASK 0x3 /* 0=none, 1=DIF, 2=DIX */ 517316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_HOST_INTERFACE_SHIFT 4 518316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_MASK 0x1 /* 0=no, 1=yes */ 519316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIF_TO_PEER_SHIFT 6 520316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_MASK 0x1 /* 0 = 24 Bytes FC Header not included in Middle-Path placement, 1 = 24 Bytes FC Header included in MP placement */ 521316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_MP_INCLUDE_FC_HEADER_SHIFT 7 522316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_MASK 0x3 /* DIX block size: can be 0:2B, 1:4B, 2:8B */ 523316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIX_BLOCK_SIZE_SHIFT 8 524316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_MASK 0x1 /* 0=no, 1=yes */ 525316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_VALIDATE_DIX_REF_TAG_SHIFT 10 526316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_MASK 0x1 /* Indication to a single cached DIX SGE instead of SGL */ 527316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIX_CACHED_SGE_FLG_SHIFT 11 528316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_MASK 0x1 529316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_DIF_SUPPORTED_SHIFT 12 530316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_MASK 0x1 /* use_enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 531316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_TX_SGL_MODE_SHIFT 13 532316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_MASK 0x3 533316485Sdavidcs#define MSTORM_FCOE_TASK_ST_CTX_RESERVED_SHIFT 14 534316485Sdavidcs struct scsi_cached_sges data_desc /* Union of Data SGL / cached sge */; 535316485Sdavidcs}; 536316485Sdavidcs 537316485Sdavidcsstruct e4_ustorm_fcoe_task_ag_ctx 538316485Sdavidcs{ 539316485Sdavidcs u8 reserved /* cdu_validation */; 540316485Sdavidcs u8 byte1 /* state */; 541316485Sdavidcs __le16 icid /* icid */; 542316485Sdavidcs u8 flags0; 543316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 544316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 545316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 546316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 547316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 548316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 549316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 550316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 551316485Sdavidcs u8 flags1; 552316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 553316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 554316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 555316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 556316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 557316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 558316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 559316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 560316485Sdavidcs u8 flags2; 561316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 562316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 563316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 564316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 565316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 566316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 567316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 568316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 569316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 570316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 571316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 572316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 573316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 574316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 575316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 576316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 577316485Sdavidcs u8 flags3; 578316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 579316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 580316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 581316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 582316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 583316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 584316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 585316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 586316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 587316485Sdavidcs#define E4_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 588316485Sdavidcs __le32 dif_err_intervals /* reg0 */; 589316485Sdavidcs __le32 dif_error_1st_interval /* reg1 */; 590316485Sdavidcs __le32 global_cq_num /* reg2 */; 591316485Sdavidcs __le32 reg3 /* reg3 */; 592316485Sdavidcs __le32 reg4 /* reg4 */; 593316485Sdavidcs __le32 reg5 /* reg5 */; 594316485Sdavidcs}; 595316485Sdavidcs 596316485Sdavidcs/* 597316485Sdavidcs * fcoe task context 598316485Sdavidcs */ 599320162Sdavidcsstruct e4_fcoe_task_context 600316485Sdavidcs{ 601316485Sdavidcs struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 602316485Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 603316485Sdavidcs struct tdif_task_context tdif_context /* tdif context */; 604316485Sdavidcs struct e4_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 605316485Sdavidcs struct e4_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 606316485Sdavidcs struct timers_context timer_context /* timer context */; 607316485Sdavidcs struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 608316485Sdavidcs struct regpair tstorm_st_padding[2] /* padding */; 609316485Sdavidcs struct e4_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 610316485Sdavidcs struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 611316485Sdavidcs struct e4_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 612316485Sdavidcs struct rdif_task_context rdif_context /* rdif context */; 613316485Sdavidcs}; 614316485Sdavidcs 615316485Sdavidcs 616320162Sdavidcsstruct e5_ystorm_fcoe_task_ag_ctx 617316485Sdavidcs{ 618316485Sdavidcs u8 byte0 /* cdu_validation */; 619316485Sdavidcs u8 byte1 /* state_and_core_id */; 620320162Sdavidcs __le16 word0 /* icid */; 621316485Sdavidcs u8 flags0; 622320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 623320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_NIBBLE0_SHIFT 0 624320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 625320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT0_SHIFT 4 626320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 627320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 628320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 629320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 630320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 631320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 632316485Sdavidcs u8 flags1; 633320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 634320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 0 635320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 636320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 637320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 638320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 639320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 640320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 6 641320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 642320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 643316485Sdavidcs u8 flags2; 644320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 645320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_BIT4_SHIFT 0 646320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 647320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 648320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 649320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 650320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 651320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 652320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 653320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 654320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 655320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 656320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 657320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 6 658320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 659320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 660316485Sdavidcs u8 flags3; 661320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 662320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 663320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 664320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 665320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 666320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 667320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 668320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 669320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 670320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 671320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 672320162Sdavidcs#define E5_YSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 673320162Sdavidcs __le32 reg0 /* reg0 */; 674320162Sdavidcs u8 byte2 /* byte2 */; 675316485Sdavidcs u8 byte3 /* byte3 */; 676320162Sdavidcs u8 byte4 /* byte4 */; 677316485Sdavidcs u8 e4_reserved7 /* byte5 */; 678320162Sdavidcs __le16 rx_id /* word1 */; 679320162Sdavidcs __le16 word2 /* word2 */; 680316485Sdavidcs __le16 word3 /* word3 */; 681316485Sdavidcs __le16 word4 /* word4 */; 682320162Sdavidcs __le16 word5 /* word5 */; 683316485Sdavidcs __le16 e4_reserved8 /* word6 */; 684320162Sdavidcs __le32 reg1 /* reg1 */; 685316485Sdavidcs}; 686316485Sdavidcs 687316485Sdavidcsstruct e5_tstorm_fcoe_task_ag_ctx 688316485Sdavidcs{ 689316485Sdavidcs u8 reserved /* cdu_validation */; 690316485Sdavidcs u8 byte1 /* state_and_core_id */; 691316485Sdavidcs __le16 icid /* icid */; 692316485Sdavidcs u8 flags0; 693316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 694316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 695316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 696316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 697316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 698316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 699316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_MASK 0x1 /* bit2 */ 700316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_WAIT_ABTS_RSP_F_SHIFT 6 701316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_MASK 0x1 /* bit3 */ 702316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_VALID_SHIFT 7 703316485Sdavidcs u8 flags1; 704316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_MASK 0x1 /* bit4 */ 705316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_FALSE_RR_TOV_SHIFT 0 706316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 707316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_BIT5_SHIFT 1 708316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_MASK 0x3 /* timer0cf */ 709316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_SHIFT 2 710316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_MASK 0x3 /* timer1cf */ 711316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_SHIFT 4 712316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 713316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 6 714316485Sdavidcs u8 flags2; 715316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_MASK 0x3 /* timer_stop_all */ 716316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_SHIFT 0 717316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf4 */ 718316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 2 719316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_MASK 0x3 /* cf5 */ 720316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_SHIFT 4 721316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_MASK 0x3 /* cf6 */ 722316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_SHIFT 6 723316485Sdavidcs u8 flags3; 724316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_MASK 0x3 /* cf7 */ 725316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_SHIFT 0 726316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_MASK 0x1 /* cf0en */ 727316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_REC_RR_TOV_CF_EN_SHIFT 2 728316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_MASK 0x1 /* cf1en */ 729316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_ED_TOV_CF_EN_SHIFT 3 730316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 731316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 4 732316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_MASK 0x1 /* cf3en */ 733316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_TIMER_STOP_ALL_EN_SHIFT 5 734316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf4en */ 735316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 736316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_MASK 0x1 /* cf5en */ 737316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_INIT_CF_EN_SHIFT 7 738316485Sdavidcs u8 flags4; 739316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_MASK 0x1 /* cf6en */ 740316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_SEQ_RECOVERY_CF_EN_SHIFT 0 741316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_MASK 0x1 /* cf7en */ 742316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_UNSOL_COMP_CF_EN_SHIFT 1 743316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 744316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 2 745316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 746316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 3 747316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 748316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 4 749316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 750316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 5 751316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 752316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 6 753316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 754316485Sdavidcs#define E5_TSTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 7 755316485Sdavidcs u8 cleanup_state /* byte2 */; 756316485Sdavidcs __le16 last_sent_tid /* word1 */; 757316485Sdavidcs __le32 rec_rr_tov_exp_timeout /* reg0 */; 758316485Sdavidcs u8 byte3 /* regpair0 */; 759316485Sdavidcs u8 byte4 /* byte4 */; 760316485Sdavidcs __le16 word2 /* word2 */; 761316485Sdavidcs __le16 word3 /* word3 */; 762316485Sdavidcs __le16 word4 /* word4 */; 763316485Sdavidcs __le32 data_offset_end_of_seq /* regpair1 */; 764316485Sdavidcs __le32 data_offset_next /* reg2 */; 765316485Sdavidcs}; 766316485Sdavidcs 767320162Sdavidcsstruct e5_mstorm_fcoe_task_ag_ctx 768320162Sdavidcs{ 769320162Sdavidcs u8 byte0 /* cdu_validation */; 770320162Sdavidcs u8 byte1 /* state_and_core_id */; 771320162Sdavidcs __le16 icid /* icid */; 772320162Sdavidcs u8 flags0; 773320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 774320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 775320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 776320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 777320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_MASK 0x1 /* exist_in_qm1 */ 778320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CQE_PLACED_SHIFT 5 779320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 780320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_BIT2_SHIFT 6 781320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 782320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_BIT3_SHIFT 7 783320162Sdavidcs u8 flags1; 784320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_MASK 0x3 /* cf0 */ 785320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_SHIFT 0 786320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 787320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 2 788320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 789320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 4 790320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_MASK 0x1 /* cf0en */ 791320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_EX_CLEANUP_CF_EN_SHIFT 6 792320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 793320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 7 794320162Sdavidcs u8 flags2; 795320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 796320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 0 797320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 798320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 1 799320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 800320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 2 801320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 802320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 3 803320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 804320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 4 805320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 806320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 5 807320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_MASK 0x1 /* rule5en */ 808320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_XFER_PLACEMENT_EN_SHIFT 6 809320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 810320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 7 811320162Sdavidcs u8 flags3; 812320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 813320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 814320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 815320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 816320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 817320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 818320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 819320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 820320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 821320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 822320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 823320162Sdavidcs#define E5_MSTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 824320162Sdavidcs __le32 received_bytes /* reg0 */; 825320162Sdavidcs u8 cleanup_state /* byte2 */; 826320162Sdavidcs u8 byte3 /* byte3 */; 827320162Sdavidcs u8 glbl_q_num /* byte4 */; 828320162Sdavidcs u8 e4_reserved7 /* byte5 */; 829320162Sdavidcs __le16 word1 /* regpair0 */; 830320162Sdavidcs __le16 tid_to_xfer /* word2 */; 831320162Sdavidcs __le16 word3 /* word3 */; 832320162Sdavidcs __le16 word4 /* word4 */; 833320162Sdavidcs __le16 word5 /* regpair1 */; 834320162Sdavidcs __le16 e4_reserved8 /* word6 */; 835320162Sdavidcs __le32 expected_bytes /* reg1 */; 836320162Sdavidcs}; 837316485Sdavidcs 838316485Sdavidcsstruct e5_ustorm_fcoe_task_ag_ctx 839316485Sdavidcs{ 840316485Sdavidcs u8 reserved /* cdu_validation */; 841316485Sdavidcs u8 byte1 /* state_and_core_id */; 842316485Sdavidcs __le16 icid /* icid */; 843316485Sdavidcs u8 flags0; 844316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 845316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 846316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 847316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 848316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 849316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_BIT1_SHIFT 5 850316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 851316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF0_SHIFT 6 852316485Sdavidcs u8 flags1; 853316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 854316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF1_SHIFT 0 855316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 856316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF2_SHIFT 2 857316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 858316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF3_SHIFT 4 859316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 860316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 861316485Sdavidcs u8 flags2; 862316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 863316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF0EN_SHIFT 0 864316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 865316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF1EN_SHIFT 1 866316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 867316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF2EN_SHIFT 2 868316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 869316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_CF3EN_SHIFT 3 870316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 871316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 872316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 873316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE0EN_SHIFT 5 874316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 875316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE1EN_SHIFT 6 876316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 877316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE2EN_SHIFT 7 878316485Sdavidcs u8 flags3; 879316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 880316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE3EN_SHIFT 0 881316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 882316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE4EN_SHIFT 1 883316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 884316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE5EN_SHIFT 2 885316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 886316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_RULE6EN_SHIFT 3 887316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 888316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 889316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 890316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 891316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 892316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 893316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 894316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 895316485Sdavidcs u8 flags4; 896316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 897316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 898316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 899316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 900316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 901316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 902316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 903316485Sdavidcs#define E5_USTORM_FCOE_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 904316485Sdavidcs u8 byte2 /* byte2 */; 905316485Sdavidcs u8 byte3 /* byte3 */; 906316485Sdavidcs u8 e4_reserved8 /* byte4 */; 907316485Sdavidcs __le32 dif_err_intervals /* dif_err_intervals */; 908316485Sdavidcs __le32 dif_error_1st_interval /* dif_error_1st_interval */; 909316485Sdavidcs __le32 global_cq_num /* reg2 */; 910316485Sdavidcs __le32 reg3 /* reg3 */; 911316485Sdavidcs __le32 reg4 /* reg4 */; 912316485Sdavidcs}; 913316485Sdavidcs 914320162Sdavidcs/* 915320162Sdavidcs * fcoe task context 916320162Sdavidcs */ 917320162Sdavidcsstruct e5_fcoe_task_context 918320162Sdavidcs{ 919320162Sdavidcs struct ystorm_fcoe_task_st_ctx ystorm_st_context /* ystorm storm context */; 920320162Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 921320162Sdavidcs struct tdif_task_context tdif_context /* tdif context */; 922320162Sdavidcs struct e5_ystorm_fcoe_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 923320162Sdavidcs struct e5_tstorm_fcoe_task_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 924320162Sdavidcs struct timers_context timer_context /* timer context */; 925320162Sdavidcs struct tstorm_fcoe_task_st_ctx tstorm_st_context /* tstorm storm context */; 926320162Sdavidcs struct regpair tstorm_st_padding[2] /* padding */; 927320162Sdavidcs struct e5_mstorm_fcoe_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 928320162Sdavidcs struct mstorm_fcoe_task_st_ctx mstorm_st_context /* mstorm storm context */; 929320162Sdavidcs struct e5_ustorm_fcoe_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 930320162Sdavidcs struct rdif_task_context rdif_context /* rdif context */; 931320162Sdavidcs}; 932316485Sdavidcs 933320162Sdavidcs 934320162Sdavidcs 935320162Sdavidcs/* 936320162Sdavidcs * FCoE additional WQE (Sq/ XferQ) information 937320162Sdavidcs */ 938320162Sdavidcsunion fcoe_additional_info_union 939316485Sdavidcs{ 940320162Sdavidcs __le32 previous_tid /* Previous tid. Used for Send XFER WQEs in Multiple continuation mode - Target only. */; 941320162Sdavidcs __le32 parent_tid /* Parent tid. Used for write tasks in a continuation mode - Target only */; 942320162Sdavidcs __le32 burst_length /* The desired burst length. */; 943320162Sdavidcs __le32 seq_rec_updated_offset /* The updated offset in SGL - Used in sequence recovery */; 944316485Sdavidcs}; 945316485Sdavidcs 946316485Sdavidcs 947320162Sdavidcs 948316485Sdavidcs/* 949320162Sdavidcs * FCoE Ramrod Command IDs 950320162Sdavidcs */ 951320162Sdavidcsenum fcoe_completion_status 952320162Sdavidcs{ 953320162Sdavidcs FCOE_COMPLETION_STATUS_SUCCESS /* FCoE ramrod completed successfully */, 954320162Sdavidcs FCOE_COMPLETION_STATUS_FCOE_VER_ERR /* Wrong FCoE version */, 955320162Sdavidcs FCOE_COMPLETION_STATUS_SRC_MAC_ADD_ARR_ERR /* src_mac_arr for the current physical port is full- allocation failed */, 956320162Sdavidcs MAX_FCOE_COMPLETION_STATUS 957320162Sdavidcs}; 958320162Sdavidcs 959320162Sdavidcs 960320162Sdavidcs/* 961320162Sdavidcs * FC address (SID/DID) network presentation 962320162Sdavidcs */ 963320162Sdavidcsstruct fc_addr_nw 964320162Sdavidcs{ 965320162Sdavidcs u8 addr_lo /* First byte of the SID/DID address that comes/goes from/to the NW (for example if SID is 11:22:33 - this is 0x11) */; 966320162Sdavidcs u8 addr_mid; 967320162Sdavidcs u8 addr_hi; 968320162Sdavidcs}; 969320162Sdavidcs 970320162Sdavidcs/* 971320162Sdavidcs * FCoE connection offload 972320162Sdavidcs */ 973320162Sdavidcsstruct fcoe_conn_offload_ramrod_data 974320162Sdavidcs{ 975320162Sdavidcs struct regpair sq_pbl_addr /* SQ Pbl base address */; 976320162Sdavidcs struct regpair sq_curr_page_addr /* SQ current page address */; 977320162Sdavidcs struct regpair sq_next_page_addr /* SQ next page address */; 978320162Sdavidcs struct regpair xferq_pbl_addr /* XFERQ Pbl base address */; 979320162Sdavidcs struct regpair xferq_curr_page_addr /* XFERQ current page address */; 980320162Sdavidcs struct regpair xferq_next_page_addr /* XFERQ next page address */; 981320162Sdavidcs struct regpair respq_pbl_addr /* RESPQ Pbl base address */; 982320162Sdavidcs struct regpair respq_curr_page_addr /* RESPQ current page address */; 983320162Sdavidcs struct regpair respq_next_page_addr /* RESPQ next page address */; 984320162Sdavidcs __le16 dst_mac_addr_lo /* First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 985320162Sdavidcs __le16 dst_mac_addr_mid; 986320162Sdavidcs __le16 dst_mac_addr_hi; 987320162Sdavidcs __le16 src_mac_addr_lo /* Source MAC address in NW order - First word of the MAC address that comes/goes from/to the NW (for example if MAC is 11:22:33:44:55:66 - this is 0x2211) */; 988320162Sdavidcs __le16 src_mac_addr_mid; 989320162Sdavidcs __le16 src_mac_addr_hi; 990320162Sdavidcs __le16 tx_max_fc_pay_len /* The maximum acceptable FC payload size (Buffer-to-buffer Receive Data_Field size) supported by target, received during both FLOGI and PLOGI, minimum value should be taken */; 991320162Sdavidcs __le16 e_d_tov_timer_val /* E_D_TOV timeout value in resolution of 1 msec */; 992320162Sdavidcs __le16 rx_max_fc_pay_len /* Maximum acceptable FC payload size supported by us */; 993320162Sdavidcs __le16 vlan_tag; 994320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_MASK 0xFFF /* Vlan id */ 995320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_VLAN_ID_SHIFT 0 996320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_MASK 0x1 /* Canonical format indicator */ 997320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_CFI_SHIFT 12 998320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_MASK 0x7 /* Vlan priority */ 999320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_PRIORITY_SHIFT 13 1000320162Sdavidcs __le16 physical_q0 /* Physical QM queue to be linked to logical queue 0 (fastPath queue) */; 1001320162Sdavidcs __le16 rec_rr_tov_timer_val /* REC_TOV timeout value in resolution of 1 msec */; 1002320162Sdavidcs struct fc_addr_nw s_id /* Source ID in NW order, received during FLOGI */; 1003320162Sdavidcs u8 max_conc_seqs_c3 /* Maximum concurrent Sequences for Class 3 supported by target, received during PLOGI */; 1004320162Sdavidcs struct fc_addr_nw d_id /* Destination ID in NW order, received after inquiry of the fabric network */; 1005320162Sdavidcs u8 flags; 1006320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_MASK 0x1 /* Continuously increasing SEQ_CNT indication, received during PLOGI */ 1007320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONT_INCR_SEQ_CNT_SHIFT 0 1008320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_MASK 0x1 /* Confirmation request supported */ 1009320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_CONF_REQ_SHIFT 1 1010320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_MASK 0x1 /* REC allowed */ 1011320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_REC_VALID_SHIFT 2 1012320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_MASK 0x1 /* Does inner vlan exist */ 1013320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_VLAN_FLAG_SHIFT 3 1014337519Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_MASK 0x1 /* Does a single vlan (inner/outer) should be used. - UFP mode */ 1015337519Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_B_SINGLE_VLAN_SHIFT 4 1016320162Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_MASK 0x3 /* indication for conn mode: 0=Initiator, 1=Target, 2=Both Initiator and Traget */ 1017337519Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_MODE_SHIFT 5 1018337519Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_MASK 0x1 1019337519Sdavidcs#define FCOE_CONN_OFFLOAD_RAMROD_DATA_RESERVED0_SHIFT 7 1020320162Sdavidcs __le16 conn_id /* Drivers connection ID. Should be sent in EQs to speed-up drivers access to connection data. */; 1021320162Sdavidcs u8 def_q_idx /* Default queue number to be used for unsolicited traffic */; 1022320162Sdavidcs u8 reserved[5]; 1023320162Sdavidcs}; 1024320162Sdavidcs 1025320162Sdavidcs 1026320162Sdavidcs/* 1027320162Sdavidcs * FCoE terminate connection request 1028320162Sdavidcs */ 1029320162Sdavidcsstruct fcoe_conn_terminate_ramrod_data 1030320162Sdavidcs{ 1031320162Sdavidcs struct regpair terminate_params_addr /* Terminate params ptr */; 1032320162Sdavidcs}; 1033320162Sdavidcs 1034320162Sdavidcs 1035337519Sdavidcs/* 1036337519Sdavidcs * FCoE device type 1037337519Sdavidcs */ 1038337519Sdavidcsenum fcoe_device_type 1039337519Sdavidcs{ 1040337519Sdavidcs FCOE_TASK_DEV_TYPE_DISK, 1041337519Sdavidcs FCOE_TASK_DEV_TYPE_TAPE, 1042337519Sdavidcs MAX_FCOE_DEVICE_TYPE 1043337519Sdavidcs}; 1044320162Sdavidcs 1045320162Sdavidcs 1046337519Sdavidcs 1047337519Sdavidcs 1048320162Sdavidcs/* 1049320162Sdavidcs * Data sgl 1050320162Sdavidcs */ 1051320162Sdavidcsstruct fcoe_fast_sgl_ctx 1052320162Sdavidcs{ 1053320162Sdavidcs struct regpair sgl_start_addr /* Current sge address */; 1054320162Sdavidcs __le32 sgl_byte_offset /* Byte offset from the beginning of the first page in the SGL. In case SGL starts in the middle of page then driver should init this value with the start offset */; 1055320162Sdavidcs __le16 task_reuse_cnt /* The reuse count for that task. Wrap ion 4K value. */; 1056320162Sdavidcs __le16 init_offset_in_first_sge /* offset from the beginning of the first page in the SGL, never changed by FW */; 1057320162Sdavidcs}; 1058320162Sdavidcs 1059320162Sdavidcs 1060320162Sdavidcs 1061320162Sdavidcs 1062320162Sdavidcs 1063320162Sdavidcs/* 1064320162Sdavidcs * FCoE firmware function init 1065320162Sdavidcs */ 1066320162Sdavidcsstruct fcoe_init_func_ramrod_data 1067320162Sdavidcs{ 1068320162Sdavidcs struct scsi_init_func_params func_params /* Common SCSI init params passed by driver to FW in function init ramrod */; 1069320162Sdavidcs struct scsi_init_func_queues q_params /* SCSI RQ/CQ/CMDQ firmware function init parameters */; 1070320162Sdavidcs __le16 mtu /* Max transmission unit */; 1071320162Sdavidcs __le16 sq_num_pages_in_pbl /* Number of pages at Send Queue */; 1072320162Sdavidcs __le32 reserved[3]; 1073320162Sdavidcs}; 1074320162Sdavidcs 1075320162Sdavidcs 1076320162Sdavidcs/* 1077320162Sdavidcs * FCoE: Mode of the connection: Target or Initiator or both 1078320162Sdavidcs */ 1079320162Sdavidcsenum fcoe_mode_type 1080320162Sdavidcs{ 1081320162Sdavidcs FCOE_INITIATOR_MODE=0x0, 1082320162Sdavidcs FCOE_TARGET_MODE=0x1, 1083320162Sdavidcs FCOE_BOTH_OR_NOT_CHOSEN=0x3, 1084320162Sdavidcs MAX_FCOE_MODE_TYPE 1085320162Sdavidcs}; 1086320162Sdavidcs 1087320162Sdavidcs 1088320162Sdavidcs/* 1089320162Sdavidcs * Per PF FCoE receive path statistics - tStorm RAM structure 1090320162Sdavidcs */ 1091320162Sdavidcsstruct fcoe_rx_stat 1092320162Sdavidcs{ 1093320162Sdavidcs struct regpair fcoe_rx_byte_cnt /* Number of FCoE bytes that were received */; 1094320162Sdavidcs struct regpair fcoe_rx_data_pkt_cnt /* Number of FCoE FCP DATA packets that were received */; 1095320162Sdavidcs struct regpair fcoe_rx_xfer_pkt_cnt /* Number of FCoE FCP XFER RDY packets that were received */; 1096320162Sdavidcs struct regpair fcoe_rx_other_pkt_cnt /* Number of FCoE packets which are not DATA/XFER_RDY that were received */; 1097320162Sdavidcs __le32 fcoe_silent_drop_pkt_cmdq_full_cnt /* Number of packets that were silently dropped since CMDQ was full */; 1098320162Sdavidcs __le32 fcoe_silent_drop_pkt_rq_full_cnt /* Number of packets that were silently dropped since RQ (BDQ) was full */; 1099320162Sdavidcs __le32 fcoe_silent_drop_pkt_crc_error_cnt /* Number of packets that were silently dropped due to FC CRC error */; 1100320162Sdavidcs __le32 fcoe_silent_drop_pkt_task_invalid_cnt /* Number of packets that were silently dropped since task was not valid */; 1101320162Sdavidcs __le32 fcoe_silent_drop_total_pkt_cnt /* Number of FCoE packets that were silently dropped */; 1102320162Sdavidcs __le32 rsrv; 1103320162Sdavidcs}; 1104320162Sdavidcs 1105320162Sdavidcs 1106320162Sdavidcs 1107320162Sdavidcs/* 1108337519Sdavidcs * FCoE SQE request type 1109337519Sdavidcs */ 1110337519Sdavidcsenum fcoe_sqe_request_type 1111337519Sdavidcs{ 1112337519Sdavidcs SEND_FCOE_CMD, 1113337519Sdavidcs SEND_FCOE_MIDPATH, 1114337519Sdavidcs SEND_FCOE_ABTS_REQUEST, 1115337519Sdavidcs FCOE_EXCHANGE_CLEANUP, 1116337519Sdavidcs FCOE_SEQUENCE_RECOVERY, 1117337519Sdavidcs SEND_FCOE_XFER_RDY, 1118337519Sdavidcs SEND_FCOE_RSP, 1119337519Sdavidcs SEND_FCOE_RSP_WITH_SENSE_DATA, 1120337519Sdavidcs SEND_FCOE_TARGET_DATA, 1121337519Sdavidcs SEND_FCOE_INITIATOR_DATA, 1122337519Sdavidcs SEND_FCOE_XFER_CONTINUATION_RDY /* Xfer Continuation (==1) ready to be sent. Previous XFERs data received successfully. */, 1123337519Sdavidcs SEND_FCOE_TARGET_ABTS_RSP, 1124337519Sdavidcs MAX_FCOE_SQE_REQUEST_TYPE 1125337519Sdavidcs}; 1126337519Sdavidcs 1127337519Sdavidcs 1128337519Sdavidcs/* 1129320162Sdavidcs * FCoe statistics request 1130320162Sdavidcs */ 1131320162Sdavidcsstruct fcoe_stat_ramrod_data 1132320162Sdavidcs{ 1133320162Sdavidcs struct regpair stat_params_addr /* Statistics host address */; 1134320162Sdavidcs}; 1135320162Sdavidcs 1136320162Sdavidcs 1137337519Sdavidcs/* 1138337519Sdavidcs * FCoE task type 1139337519Sdavidcs */ 1140337519Sdavidcsenum fcoe_task_type 1141337519Sdavidcs{ 1142337519Sdavidcs FCOE_TASK_TYPE_WRITE_INITIATOR, 1143337519Sdavidcs FCOE_TASK_TYPE_READ_INITIATOR, 1144337519Sdavidcs FCOE_TASK_TYPE_MIDPATH, 1145337519Sdavidcs FCOE_TASK_TYPE_UNSOLICITED, 1146337519Sdavidcs FCOE_TASK_TYPE_ABTS, 1147337519Sdavidcs FCOE_TASK_TYPE_EXCHANGE_CLEANUP, 1148337519Sdavidcs FCOE_TASK_TYPE_SEQUENCE_CLEANUP, 1149337519Sdavidcs FCOE_TASK_TYPE_WRITE_TARGET, 1150337519Sdavidcs FCOE_TASK_TYPE_READ_TARGET, 1151337519Sdavidcs FCOE_TASK_TYPE_RSP, 1152337519Sdavidcs FCOE_TASK_TYPE_RSP_SENSE_DATA, 1153337519Sdavidcs FCOE_TASK_TYPE_ABTS_TARGET, 1154337519Sdavidcs FCOE_TASK_TYPE_ENUM_SIZE, 1155337519Sdavidcs MAX_FCOE_TASK_TYPE 1156337519Sdavidcs}; 1157320162Sdavidcs 1158320162Sdavidcs 1159320162Sdavidcs 1160320162Sdavidcs 1161320162Sdavidcs 1162320162Sdavidcs 1163337519Sdavidcs 1164337519Sdavidcs 1165320162Sdavidcs/* 1166320162Sdavidcs * Per PF FCoE transmit path statistics - pStorm RAM structure 1167320162Sdavidcs */ 1168320162Sdavidcsstruct fcoe_tx_stat 1169320162Sdavidcs{ 1170320162Sdavidcs struct regpair fcoe_tx_byte_cnt /* Transmitted FCoE bytes count */; 1171320162Sdavidcs struct regpair fcoe_tx_data_pkt_cnt /* Transmitted FCoE FCP DATA packets count */; 1172320162Sdavidcs struct regpair fcoe_tx_xfer_pkt_cnt /* Transmitted FCoE XFER_RDY packets count */; 1173320162Sdavidcs struct regpair fcoe_tx_other_pkt_cnt /* Transmitted FCoE packets which are not DATA/XFER_RDY count */; 1174320162Sdavidcs}; 1175320162Sdavidcs 1176320162Sdavidcs 1177320162Sdavidcs/* 1178320162Sdavidcs * FCoE SQ/XferQ element 1179320162Sdavidcs */ 1180320162Sdavidcsstruct fcoe_wqe 1181320162Sdavidcs{ 1182320162Sdavidcs __le16 task_id /* Initiator - The task identifier (OX_ID). Target - Continuation tid or RX_ID in non-continuation mode */; 1183320162Sdavidcs __le16 flags; 1184320162Sdavidcs#define FCOE_WQE_REQ_TYPE_MASK 0xF /* Type of the wqe request. use enum fcoe_sqe_request_type (use enum fcoe_sqe_request_type) */ 1185320162Sdavidcs#define FCOE_WQE_REQ_TYPE_SHIFT 0 1186320162Sdavidcs#define FCOE_WQE_SGL_MODE_MASK 0x1 /* The driver will give a hint about sizes of SGEs for better credits evaluation at Xstorm. use enum scsi_sgl_mode (use enum scsi_sgl_mode) */ 1187320162Sdavidcs#define FCOE_WQE_SGL_MODE_SHIFT 4 1188320162Sdavidcs#define FCOE_WQE_CONTINUATION_MASK 0x1 /* Indication if this wqe is a continuation to an existing task (Target only) */ 1189320162Sdavidcs#define FCOE_WQE_CONTINUATION_SHIFT 5 1190320162Sdavidcs#define FCOE_WQE_SEND_AUTO_RSP_MASK 0x1 /* Indication to FW to send FCP_RSP after all data was sent - Target only */ 1191320162Sdavidcs#define FCOE_WQE_SEND_AUTO_RSP_SHIFT 6 1192320162Sdavidcs#define FCOE_WQE_RESERVED_MASK 0x1 1193320162Sdavidcs#define FCOE_WQE_RESERVED_SHIFT 7 1194320162Sdavidcs#define FCOE_WQE_NUM_SGES_MASK 0xF /* Number of SGEs. 8 = at least 8 sges */ 1195320162Sdavidcs#define FCOE_WQE_NUM_SGES_SHIFT 8 1196320162Sdavidcs#define FCOE_WQE_RESERVED1_MASK 0xF 1197320162Sdavidcs#define FCOE_WQE_RESERVED1_SHIFT 12 1198320162Sdavidcs union fcoe_additional_info_union additional_info_union /* Additional wqe information (if needed) */; 1199320162Sdavidcs}; 1200320162Sdavidcs 1201320162Sdavidcs 1202320162Sdavidcs 1203320162Sdavidcs 1204320162Sdavidcs 1205320162Sdavidcs 1206320162Sdavidcs 1207320162Sdavidcs 1208320162Sdavidcs 1209320162Sdavidcs/* 1210320162Sdavidcs * FCoE XFRQ element 1211320162Sdavidcs */ 1212320162Sdavidcsstruct xfrqe_prot_flags 1213320162Sdavidcs{ 1214320162Sdavidcs u8 flags; 1215320162Sdavidcs#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_MASK 0xF /* Protection log interval (9=512 10=1024 11=2048 12=4096 13=8192) */ 1216320162Sdavidcs#define XFRQE_PROT_FLAGS_PROT_INTERVAL_SIZE_LOG_SHIFT 0 1217320162Sdavidcs#define XFRQE_PROT_FLAGS_DIF_TO_PEER_MASK 0x1 /* If DIF protection is configured against target (0=no, 1=yes) */ 1218320162Sdavidcs#define XFRQE_PROT_FLAGS_DIF_TO_PEER_SHIFT 4 1219320162Sdavidcs#define XFRQE_PROT_FLAGS_HOST_INTERFACE_MASK 0x3 /* If DIF/DIX protection is configured against the host (0=none, 1=DIF, 2=DIX) */ 1220320162Sdavidcs#define XFRQE_PROT_FLAGS_HOST_INTERFACE_SHIFT 5 1221320162Sdavidcs#define XFRQE_PROT_FLAGS_RESERVED_MASK 0x1 /* Must set to 0 */ 1222320162Sdavidcs#define XFRQE_PROT_FLAGS_RESERVED_SHIFT 7 1223320162Sdavidcs}; 1224320162Sdavidcs 1225320162Sdavidcs 1226320162Sdavidcs 1227320162Sdavidcs 1228320162Sdavidcs 1229320162Sdavidcs 1230320162Sdavidcs 1231320162Sdavidcs 1232320162Sdavidcs 1233320162Sdavidcs 1234320162Sdavidcs 1235320162Sdavidcs/* 1236316485Sdavidcs * FCoE doorbell data 1237316485Sdavidcs */ 1238316485Sdavidcsstruct fcoe_db_data 1239316485Sdavidcs{ 1240316485Sdavidcs u8 params; 1241316485Sdavidcs#define FCOE_DB_DATA_DEST_MASK 0x3 /* destination of doorbell (use enum db_dest) */ 1242316485Sdavidcs#define FCOE_DB_DATA_DEST_SHIFT 0 1243316485Sdavidcs#define FCOE_DB_DATA_AGG_CMD_MASK 0x3 /* aggregative command to CM (use enum db_agg_cmd_sel) */ 1244316485Sdavidcs#define FCOE_DB_DATA_AGG_CMD_SHIFT 2 1245316485Sdavidcs#define FCOE_DB_DATA_BYPASS_EN_MASK 0x1 /* enable QM bypass */ 1246316485Sdavidcs#define FCOE_DB_DATA_BYPASS_EN_SHIFT 4 1247316485Sdavidcs#define FCOE_DB_DATA_RESERVED_MASK 0x1 1248316485Sdavidcs#define FCOE_DB_DATA_RESERVED_SHIFT 5 1249316485Sdavidcs#define FCOE_DB_DATA_AGG_VAL_SEL_MASK 0x3 /* aggregative value selection */ 1250316485Sdavidcs#define FCOE_DB_DATA_AGG_VAL_SEL_SHIFT 6 1251316485Sdavidcs u8 agg_flags /* bit for every DQ counter flags in CM context that DQ can increment */; 1252316485Sdavidcs __le16 sq_prod; 1253316485Sdavidcs}; 1254316485Sdavidcs 1255316485Sdavidcs#endif /* __FCOE_COMMON__ */ 1256