1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hw_defs.h 316485 2017-04-04 06:16:59Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs#ifndef _ECORE_IGU_DEF_H_ 32316485Sdavidcs#define _ECORE_IGU_DEF_H_ 33316485Sdavidcs 34316485Sdavidcs/* Fields of IGU PF CONFIGRATION REGISTER */ 35316485Sdavidcs#define IGU_PF_CONF_FUNC_EN (0x1<<0) /* function enable */ 36316485Sdavidcs#define IGU_PF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 37316485Sdavidcs#define IGU_PF_CONF_INT_LINE_EN (0x1<<2) /* INT enable */ 38316485Sdavidcs#define IGU_PF_CONF_ATTN_BIT_EN (0x1<<3) /* attention enable */ 39316485Sdavidcs#define IGU_PF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 40316485Sdavidcs#define IGU_PF_CONF_SIMD_MODE (0x1<<5) /* simd all ones mode */ 41316485Sdavidcs 42316485Sdavidcs/* Fields of IGU VF CONFIGRATION REGISTER */ 43316485Sdavidcs#define IGU_VF_CONF_FUNC_EN (0x1<<0) /* function enable */ 44316485Sdavidcs#define IGU_VF_CONF_MSI_MSIX_EN (0x1<<1) /* MSI/MSIX enable */ 45316485Sdavidcs#define IGU_VF_CONF_SINGLE_ISR_EN (0x1<<4) /* single ISR mode enable */ 46316485Sdavidcs#define IGU_VF_CONF_PARENT_MASK (0xF) /* Parent PF */ 47316485Sdavidcs#define IGU_VF_CONF_PARENT_SHIFT 5 /* Parent PF */ 48316485Sdavidcs 49316485Sdavidcs/* Igu control commands 50316485Sdavidcs */ 51316485Sdavidcsenum igu_ctrl_cmd 52316485Sdavidcs{ 53316485Sdavidcs IGU_CTRL_CMD_TYPE_RD, 54316485Sdavidcs IGU_CTRL_CMD_TYPE_WR, 55316485Sdavidcs MAX_IGU_CTRL_CMD 56316485Sdavidcs}; 57316485Sdavidcs 58316485Sdavidcs/* Control register for the IGU command register 59316485Sdavidcs */ 60316485Sdavidcsstruct igu_ctrl_reg 61316485Sdavidcs{ 62316485Sdavidcs u32 ctrl_data; 63316485Sdavidcs#define IGU_CTRL_REG_FID_MASK 0xFFFF /* Opaque_FID */ 64316485Sdavidcs#define IGU_CTRL_REG_FID_SHIFT 0 65316485Sdavidcs#define IGU_CTRL_REG_PXP_ADDR_MASK 0xFFF /* Command address */ 66316485Sdavidcs#define IGU_CTRL_REG_PXP_ADDR_SHIFT 16 67316485Sdavidcs#define IGU_CTRL_REG_RESERVED_MASK 0x1 68316485Sdavidcs#define IGU_CTRL_REG_RESERVED_SHIFT 28 69316485Sdavidcs#define IGU_CTRL_REG_TYPE_MASK 0x1 /* use enum igu_ctrl_cmd */ 70316485Sdavidcs#define IGU_CTRL_REG_TYPE_SHIFT 31 71316485Sdavidcs}; 72316485Sdavidcs 73316485Sdavidcs#endif 74