1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hsi_rdma.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs#ifndef __ECORE_HSI_RDMA__ 32316485Sdavidcs#define __ECORE_HSI_RDMA__ 33316485Sdavidcs/************************************************************************/ 34316485Sdavidcs/* Add include to common rdma target for both eCore and protocol rdma driver */ 35316485Sdavidcs/************************************************************************/ 36316485Sdavidcs#include "rdma_common.h" 37316485Sdavidcs 38316485Sdavidcs/* 39320162Sdavidcs * The rdma task context of Mstorm 40320162Sdavidcs */ 41320162Sdavidcsstruct ystorm_rdma_task_st_ctx 42320162Sdavidcs{ 43320162Sdavidcs struct regpair temp[4]; 44320162Sdavidcs}; 45320162Sdavidcs 46320162Sdavidcsstruct e4_ystorm_rdma_task_ag_ctx 47320162Sdavidcs{ 48320162Sdavidcs u8 reserved /* cdu_validation */; 49320162Sdavidcs u8 byte1 /* state */; 50320162Sdavidcs __le16 msem_ctx_upd_seq /* icid */; 51320162Sdavidcs u8 flags0; 52320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 53320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 54320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 55320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 56320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 57320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 58320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 59320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 60337519Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */ 61337519Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 62320162Sdavidcs u8 flags1; 63320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 64320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 65320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 66320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 67320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 68320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 69320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 70320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 71320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 72320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 73320162Sdavidcs u8 flags2; 74320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 75320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 76320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 77320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 78320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 79320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 80320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 81320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 82320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 83320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 84320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 85320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 86320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 87320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 88320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 89320162Sdavidcs#define E4_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 90320162Sdavidcs u8 key /* byte2 */; 91320162Sdavidcs __le32 mw_cnt /* reg0 */; 92320162Sdavidcs u8 ref_cnt_seq /* byte3 */; 93320162Sdavidcs u8 ctx_upd_seq /* byte4 */; 94320162Sdavidcs __le16 dif_flags /* word1 */; 95320162Sdavidcs __le16 tx_ref_count /* word2 */; 96320162Sdavidcs __le16 last_used_ltid /* word3 */; 97320162Sdavidcs __le16 parent_mr_lo /* word4 */; 98320162Sdavidcs __le16 parent_mr_hi /* word5 */; 99320162Sdavidcs __le32 fbo_lo /* reg1 */; 100320162Sdavidcs __le32 fbo_hi /* reg2 */; 101320162Sdavidcs}; 102320162Sdavidcs 103320162Sdavidcsstruct e4_mstorm_rdma_task_ag_ctx 104320162Sdavidcs{ 105320162Sdavidcs u8 reserved /* cdu_validation */; 106320162Sdavidcs u8 byte1 /* state */; 107320162Sdavidcs __le16 icid /* icid */; 108320162Sdavidcs u8 flags0; 109320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 110320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 111320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 112320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 113320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 114320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 115320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 116320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 117337519Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_MASK 0x1 /* bit3 */ 118337519Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_DIF_FIRST_IO_SHIFT 7 119320162Sdavidcs u8 flags1; 120320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 121320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 122320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 123320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 124320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 125320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 126320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 127320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 128320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 129320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 130320162Sdavidcs u8 flags2; 131320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 132320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 133320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 134320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 135320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 136320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 137320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 138320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 139320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 140320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 141320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 142320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 143320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 144320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 145320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 146320162Sdavidcs#define E4_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 147320162Sdavidcs u8 key /* byte2 */; 148320162Sdavidcs __le32 mw_cnt /* reg0 */; 149320162Sdavidcs u8 ref_cnt_seq /* byte3 */; 150320162Sdavidcs u8 ctx_upd_seq /* byte4 */; 151320162Sdavidcs __le16 dif_flags /* word1 */; 152320162Sdavidcs __le16 tx_ref_count /* word2 */; 153320162Sdavidcs __le16 last_used_ltid /* word3 */; 154320162Sdavidcs __le16 parent_mr_lo /* word4 */; 155320162Sdavidcs __le16 parent_mr_hi /* word5 */; 156320162Sdavidcs __le32 fbo_lo /* reg1 */; 157320162Sdavidcs __le32 fbo_hi /* reg2 */; 158320162Sdavidcs}; 159320162Sdavidcs 160320162Sdavidcs/* 161316485Sdavidcs * The roce task context of Mstorm 162316485Sdavidcs */ 163316485Sdavidcsstruct mstorm_rdma_task_st_ctx 164316485Sdavidcs{ 165316485Sdavidcs struct regpair temp[4]; 166316485Sdavidcs}; 167316485Sdavidcs 168320162Sdavidcs/* 169320162Sdavidcs * The roce task context of Ustorm 170320162Sdavidcs */ 171320162Sdavidcsstruct ustorm_rdma_task_st_ctx 172320162Sdavidcs{ 173320162Sdavidcs struct regpair temp[2]; 174320162Sdavidcs}; 175316485Sdavidcs 176320162Sdavidcsstruct e4_ustorm_rdma_task_ag_ctx 177320162Sdavidcs{ 178320162Sdavidcs u8 reserved /* cdu_validation */; 179320162Sdavidcs u8 byte1 /* state */; 180320162Sdavidcs __le16 icid /* icid */; 181320162Sdavidcs u8 flags0; 182320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 183320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 184320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 185320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 186320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 187320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 188320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 189320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 190320162Sdavidcs u8 flags1; 191320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 192320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 193320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 194320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 195320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 196320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 197320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* cf4 */ 198320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 199320162Sdavidcs u8 flags2; 200320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 201320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 202320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 203320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 204320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 205320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 206320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 207320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 208320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 209320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 210320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 211320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 212320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 213320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 214320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 215320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 216320162Sdavidcs u8 flags3; 217320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 218320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 219320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 220320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 221320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 222320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 223320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 224320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 225320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* nibble1 */ 226320162Sdavidcs#define E4_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 227320162Sdavidcs __le32 dif_err_intervals /* reg0 */; 228320162Sdavidcs __le32 dif_error_1st_interval /* reg1 */; 229320162Sdavidcs __le32 reg2 /* reg2 */; 230320162Sdavidcs __le32 dif_runt_value /* reg3 */; 231320162Sdavidcs __le32 reg4 /* reg4 */; 232320162Sdavidcs __le32 reg5 /* reg5 */; 233320162Sdavidcs}; 234320162Sdavidcs 235316485Sdavidcs/* 236320162Sdavidcs * RDMA task context 237320162Sdavidcs */ 238320162Sdavidcsstruct e4_rdma_task_context 239320162Sdavidcs{ 240320162Sdavidcs struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 241320162Sdavidcs struct e4_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 242320162Sdavidcs struct tdif_task_context tdif_context /* tdif context */; 243320162Sdavidcs struct e4_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 244320162Sdavidcs struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 245320162Sdavidcs struct rdif_task_context rdif_context /* rdif context */; 246320162Sdavidcs struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 247320162Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 248320162Sdavidcs struct e4_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 249320162Sdavidcs}; 250320162Sdavidcs 251320162Sdavidcs 252320162Sdavidcsstruct e5_ystorm_rdma_task_ag_ctx 253320162Sdavidcs{ 254320162Sdavidcs u8 reserved /* cdu_validation */; 255320162Sdavidcs u8 byte1 /* state_and_core_id */; 256320162Sdavidcs __le16 msem_ctx_upd_seq /* icid */; 257320162Sdavidcs u8 flags0; 258320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 259320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 260320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 261320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 262320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 263320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 264320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_MASK 0x1 /* bit2 */ 265320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_VALID_SHIFT 6 266320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 267320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 268320162Sdavidcs u8 flags1; 269320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 270320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 271320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 272320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 273320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_MASK 0x3 /* cf2special */ 274320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF2SPECIAL_SHIFT 4 275320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 276320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 277320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 278320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 279320162Sdavidcs u8 flags2; 280320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 281320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 282320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 283320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 284320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 285320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 286320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 287320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 288320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 289320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 290320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 291320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 292320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 293320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 294320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 295320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 296320162Sdavidcs u8 flags3; 297320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit5 */ 298320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 299320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 300320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 301320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 302320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 303320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 304320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 305320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 306320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 307320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 308320162Sdavidcs#define E5_YSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 309320162Sdavidcs __le32 mw_cnt /* reg0 */; 310320162Sdavidcs u8 key /* byte2 */; 311320162Sdavidcs u8 ref_cnt_seq /* byte3 */; 312320162Sdavidcs u8 ctx_upd_seq /* byte4 */; 313320162Sdavidcs u8 e4_reserved7 /* byte5 */; 314320162Sdavidcs __le16 dif_flags /* word1 */; 315320162Sdavidcs __le16 tx_ref_count /* word2 */; 316320162Sdavidcs __le16 last_used_ltid /* word3 */; 317320162Sdavidcs __le16 parent_mr_lo /* word4 */; 318320162Sdavidcs __le16 parent_mr_hi /* word5 */; 319320162Sdavidcs __le16 e4_reserved8 /* word6 */; 320320162Sdavidcs __le32 fbo_lo /* reg1 */; 321320162Sdavidcs}; 322320162Sdavidcs 323320162Sdavidcsstruct e5_mstorm_rdma_task_ag_ctx 324320162Sdavidcs{ 325320162Sdavidcs u8 reserved /* cdu_validation */; 326320162Sdavidcs u8 byte1 /* state_and_core_id */; 327320162Sdavidcs __le16 icid /* icid */; 328320162Sdavidcs u8 flags0; 329320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 330320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 331320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 332320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 333320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 334320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 335320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 336320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 337320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 338320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 339320162Sdavidcs u8 flags1; 340320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* cf0 */ 341320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 0 342320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* cf1 */ 343320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 2 344320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* cf2 */ 345320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 4 346320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 347320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 6 348320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 349320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 7 350320162Sdavidcs u8 flags2; 351320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 352320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 0 353320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 354320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 1 355320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 356320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 2 357320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 358320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 3 359320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 360320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 4 361320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 362320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 5 363320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 364320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 6 365320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 366320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 7 367320162Sdavidcs u8 flags3; 368320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit4 */ 369320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 0 370320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x3 /* cf3 */ 371320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 1 372320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf4 */ 373320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 3 374320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* cf3en */ 375320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 5 376320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf4en */ 377320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 6 378320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule7en */ 379320162Sdavidcs#define E5_MSTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 7 380320162Sdavidcs __le32 mw_cnt /* reg0 */; 381320162Sdavidcs u8 key /* byte2 */; 382320162Sdavidcs u8 ref_cnt_seq /* byte3 */; 383320162Sdavidcs u8 ctx_upd_seq /* byte4 */; 384320162Sdavidcs u8 e4_reserved7 /* byte5 */; 385320162Sdavidcs __le16 dif_flags /* regpair0 */; 386320162Sdavidcs __le16 tx_ref_count /* word2 */; 387320162Sdavidcs __le16 last_used_ltid /* word3 */; 388320162Sdavidcs __le16 parent_mr_lo /* word4 */; 389320162Sdavidcs __le16 parent_mr_hi /* regpair1 */; 390320162Sdavidcs __le16 e4_reserved8 /* word6 */; 391320162Sdavidcs __le32 fbo_lo /* reg1 */; 392320162Sdavidcs}; 393320162Sdavidcs 394320162Sdavidcsstruct e5_ustorm_rdma_task_ag_ctx 395320162Sdavidcs{ 396320162Sdavidcs u8 reserved /* cdu_validation */; 397320162Sdavidcs u8 byte1 /* state_and_core_id */; 398320162Sdavidcs __le16 icid /* icid */; 399320162Sdavidcs u8 flags0; 400320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_MASK 0xF /* connection_type */ 401320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CONNECTION_TYPE_SHIFT 0 402320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 403320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_EXIST_IN_QM0_SHIFT 4 404320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_MASK 0x1 /* exist_in_qm1 */ 405320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RUNT_VALID_SHIFT 5 406320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_MASK 0x3 /* timer0cf */ 407320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_SHIFT 6 408320162Sdavidcs u8 flags1; 409320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_MASK 0x3 /* timer1cf */ 410320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_RESULT_TOGGLE_BIT_SHIFT 0 411320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_MASK 0x3 /* timer2cf */ 412320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_TX_IO_FLG_SHIFT 2 413320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 414320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 4 415320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_MASK 0x3 /* dif_error_cf */ 416320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_SHIFT 6 417320162Sdavidcs u8 flags2; 418320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_MASK 0x1 /* cf0en */ 419320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_WRITE_RESULT_CF_EN_SHIFT 0 420320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_MASK 0x1 /* cf1en */ 421320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED2_SHIFT 1 422320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_MASK 0x1 /* cf2en */ 423320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RESERVED3_SHIFT 2 424320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 425320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 3 426320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_MASK 0x1 /* cf4en */ 427320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_CF_EN_SHIFT 4 428320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 429320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 5 430320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 431320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 6 432320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 433320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 7 434320162Sdavidcs u8 flags3; 435320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 436320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 0 437320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 438320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 1 439320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 440320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 2 441320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 442320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_RULE6EN_SHIFT 3 443320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 444320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED1_SHIFT 4 445320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 446320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED2_SHIFT 5 447320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit4 */ 448320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED3_SHIFT 6 449320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_MASK 0x1 /* rule7en */ 450320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED4_SHIFT 7 451320162Sdavidcs u8 flags4; 452320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_MASK 0x3 /* cf5 */ 453320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED5_SHIFT 0 454320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf5en */ 455320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED6_SHIFT 2 456320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule8en */ 457320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_E4_RESERVED7_SHIFT 3 458320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_MASK 0xF /* dif_error_type */ 459320162Sdavidcs#define E5_USTORM_RDMA_TASK_AG_CTX_DIF_ERROR_TYPE_SHIFT 4 460320162Sdavidcs u8 byte2 /* byte2 */; 461320162Sdavidcs u8 byte3 /* byte3 */; 462320162Sdavidcs u8 e4_reserved8 /* byte4 */; 463320162Sdavidcs __le32 dif_err_intervals /* dif_err_intervals */; 464320162Sdavidcs __le32 dif_error_1st_interval /* dif_error_1st_interval */; 465320162Sdavidcs __le32 reg2 /* reg2 */; 466320162Sdavidcs __le32 dif_runt_value /* reg3 */; 467320162Sdavidcs __le32 reg4 /* reg4 */; 468320162Sdavidcs}; 469320162Sdavidcs 470320162Sdavidcs/* 471320162Sdavidcs * RDMA task context 472320162Sdavidcs */ 473320162Sdavidcsstruct e5_rdma_task_context 474320162Sdavidcs{ 475320162Sdavidcs struct ystorm_rdma_task_st_ctx ystorm_st_context /* ystorm storm context */; 476320162Sdavidcs struct e5_ystorm_rdma_task_ag_ctx ystorm_ag_context /* ystorm aggregative context */; 477320162Sdavidcs struct tdif_task_context tdif_context /* tdif context */; 478320162Sdavidcs struct e5_mstorm_rdma_task_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 479320162Sdavidcs struct mstorm_rdma_task_st_ctx mstorm_st_context /* mstorm storm context */; 480320162Sdavidcs struct rdif_task_context rdif_context /* rdif context */; 481320162Sdavidcs struct ustorm_rdma_task_st_ctx ustorm_st_context /* ustorm storm context */; 482320162Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 483320162Sdavidcs struct e5_ustorm_rdma_task_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 484320162Sdavidcs}; 485320162Sdavidcs 486320162Sdavidcs 487320162Sdavidcs 488320162Sdavidcs/* 489316485Sdavidcs * rdma function init ramrod data 490316485Sdavidcs */ 491316485Sdavidcsstruct rdma_close_func_ramrod_data 492316485Sdavidcs{ 493316485Sdavidcs u8 cnq_start_offset; 494316485Sdavidcs u8 num_cnqs; 495316485Sdavidcs u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 496316485Sdavidcs u8 vf_valid; 497316485Sdavidcs u8 reserved[4]; 498316485Sdavidcs}; 499316485Sdavidcs 500316485Sdavidcs 501316485Sdavidcs/* 502316485Sdavidcs * rdma function init CNQ parameters 503316485Sdavidcs */ 504316485Sdavidcsstruct rdma_cnq_params 505316485Sdavidcs{ 506316485Sdavidcs __le16 sb_num /* Status block number used by the queue */; 507316485Sdavidcs u8 sb_index /* Status block index used by the queue */; 508316485Sdavidcs u8 num_pbl_pages /* Number of pages in the PBL allocated for this queue */; 509316485Sdavidcs __le32 reserved; 510316485Sdavidcs struct regpair pbl_base_addr /* Address to the first entry of the queue PBL */; 511316485Sdavidcs __le16 queue_zone_num /* Queue Zone ID used for CNQ consumer update */; 512316485Sdavidcs u8 reserved1[6]; 513316485Sdavidcs}; 514316485Sdavidcs 515316485Sdavidcs 516316485Sdavidcs/* 517316485Sdavidcs * rdma create cq ramrod data 518316485Sdavidcs */ 519316485Sdavidcsstruct rdma_create_cq_ramrod_data 520316485Sdavidcs{ 521316485Sdavidcs struct regpair cq_handle; 522316485Sdavidcs struct regpair pbl_addr; 523316485Sdavidcs __le32 max_cqes; 524316485Sdavidcs __le16 pbl_num_pages; 525316485Sdavidcs __le16 dpi; 526316485Sdavidcs u8 is_two_level_pbl; 527316485Sdavidcs u8 cnq_id; 528316485Sdavidcs u8 pbl_log_page_size; 529316485Sdavidcs u8 toggle_bit; 530316485Sdavidcs __le16 int_timeout /* Timeout used for interrupt moderation */; 531316485Sdavidcs __le16 reserved1; 532316485Sdavidcs}; 533316485Sdavidcs 534316485Sdavidcs 535316485Sdavidcs/* 536316485Sdavidcs * rdma deregister tid ramrod data 537316485Sdavidcs */ 538316485Sdavidcsstruct rdma_deregister_tid_ramrod_data 539316485Sdavidcs{ 540316485Sdavidcs __le32 itid; 541316485Sdavidcs __le32 reserved; 542316485Sdavidcs}; 543316485Sdavidcs 544316485Sdavidcs 545316485Sdavidcs/* 546316485Sdavidcs * rdma destroy cq output params 547316485Sdavidcs */ 548316485Sdavidcsstruct rdma_destroy_cq_output_params 549316485Sdavidcs{ 550316485Sdavidcs __le16 cnq_num /* Sequence number of completion notification sent for the cq on the associated CNQ */; 551316485Sdavidcs __le16 reserved0; 552316485Sdavidcs __le32 reserved1; 553316485Sdavidcs}; 554316485Sdavidcs 555316485Sdavidcs 556316485Sdavidcs/* 557316485Sdavidcs * rdma destroy cq ramrod data 558316485Sdavidcs */ 559316485Sdavidcsstruct rdma_destroy_cq_ramrod_data 560316485Sdavidcs{ 561316485Sdavidcs struct regpair output_params_addr; 562316485Sdavidcs}; 563316485Sdavidcs 564316485Sdavidcs 565316485Sdavidcs/* 566316485Sdavidcs * RDMA slow path EQ cmd IDs 567316485Sdavidcs */ 568316485Sdavidcsenum rdma_event_opcode 569316485Sdavidcs{ 570316485Sdavidcs RDMA_EVENT_UNUSED, 571316485Sdavidcs RDMA_EVENT_FUNC_INIT, 572316485Sdavidcs RDMA_EVENT_FUNC_CLOSE, 573316485Sdavidcs RDMA_EVENT_REGISTER_MR, 574316485Sdavidcs RDMA_EVENT_DEREGISTER_MR, 575316485Sdavidcs RDMA_EVENT_CREATE_CQ, 576316485Sdavidcs RDMA_EVENT_RESIZE_CQ, 577316485Sdavidcs RDMA_EVENT_DESTROY_CQ, 578316485Sdavidcs RDMA_EVENT_CREATE_SRQ, 579316485Sdavidcs RDMA_EVENT_MODIFY_SRQ, 580316485Sdavidcs RDMA_EVENT_DESTROY_SRQ, 581316485Sdavidcs MAX_RDMA_EVENT_OPCODE 582316485Sdavidcs}; 583316485Sdavidcs 584316485Sdavidcs 585316485Sdavidcs/* 586316485Sdavidcs * RDMA FW return code for slow path ramrods 587316485Sdavidcs */ 588316485Sdavidcsenum rdma_fw_return_code 589316485Sdavidcs{ 590316485Sdavidcs RDMA_RETURN_OK=0, 591316485Sdavidcs RDMA_RETURN_REGISTER_MR_BAD_STATE_ERR, 592316485Sdavidcs RDMA_RETURN_DEREGISTER_MR_BAD_STATE_ERR, 593316485Sdavidcs RDMA_RETURN_RESIZE_CQ_ERR, 594316485Sdavidcs RDMA_RETURN_NIG_DRAIN_REQ, 595316485Sdavidcs MAX_RDMA_FW_RETURN_CODE 596316485Sdavidcs}; 597316485Sdavidcs 598316485Sdavidcs 599316485Sdavidcs/* 600316485Sdavidcs * rdma function init header 601316485Sdavidcs */ 602316485Sdavidcsstruct rdma_init_func_hdr 603316485Sdavidcs{ 604316485Sdavidcs u8 cnq_start_offset /* First RDMA CNQ */; 605316485Sdavidcs u8 num_cnqs /* Number of CNQs */; 606316485Sdavidcs u8 cq_ring_mode /* 0 for 32 bit cq producer and consumer counters and 1 for 16 bit */; 607316485Sdavidcs u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 608316485Sdavidcs u8 vf_valid; 609337519Sdavidcs u8 relaxed_ordering /* 1 for using relaxed ordering PCI writes */; 610337519Sdavidcs __le16 first_reg_srq_id /* The SRQ ID of thr first regular (non XRC) SRQ */; 611337519Sdavidcs __le32 reg_srq_base_addr /* Logical base address of first regular (non XRC) SRQ */; 612337519Sdavidcs __le32 reserved; 613316485Sdavidcs}; 614316485Sdavidcs 615316485Sdavidcs 616316485Sdavidcs/* 617316485Sdavidcs * rdma function init ramrod data 618316485Sdavidcs */ 619316485Sdavidcsstruct rdma_init_func_ramrod_data 620316485Sdavidcs{ 621316485Sdavidcs struct rdma_init_func_hdr params_header; 622316485Sdavidcs struct rdma_cnq_params cnq_params[NUM_OF_GLOBAL_QUEUES]; 623316485Sdavidcs}; 624316485Sdavidcs 625316485Sdavidcs 626316485Sdavidcs/* 627316485Sdavidcs * RDMA ramrod command IDs 628316485Sdavidcs */ 629316485Sdavidcsenum rdma_ramrod_cmd_id 630316485Sdavidcs{ 631316485Sdavidcs RDMA_RAMROD_UNUSED, 632316485Sdavidcs RDMA_RAMROD_FUNC_INIT, 633316485Sdavidcs RDMA_RAMROD_FUNC_CLOSE, 634316485Sdavidcs RDMA_RAMROD_REGISTER_MR, 635316485Sdavidcs RDMA_RAMROD_DEREGISTER_MR, 636316485Sdavidcs RDMA_RAMROD_CREATE_CQ, 637316485Sdavidcs RDMA_RAMROD_RESIZE_CQ, 638316485Sdavidcs RDMA_RAMROD_DESTROY_CQ, 639316485Sdavidcs RDMA_RAMROD_CREATE_SRQ, 640316485Sdavidcs RDMA_RAMROD_MODIFY_SRQ, 641316485Sdavidcs RDMA_RAMROD_DESTROY_SRQ, 642316485Sdavidcs MAX_RDMA_RAMROD_CMD_ID 643316485Sdavidcs}; 644316485Sdavidcs 645316485Sdavidcs 646316485Sdavidcs/* 647316485Sdavidcs * rdma register tid ramrod data 648316485Sdavidcs */ 649316485Sdavidcsstruct rdma_register_tid_ramrod_data 650316485Sdavidcs{ 651337519Sdavidcs __le16 flags; 652316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_MASK 0x1F 653337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PAGE_SIZE_LOG_SHIFT 0 654316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_MASK 0x1 655337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_TWO_LEVEL_PBL_SHIFT 5 656316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_MASK 0x1 657337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_ZERO_BASED_SHIFT 6 658316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_MASK 0x1 659337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PHY_MR_SHIFT 7 660316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_MASK 0x1 661337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_READ_SHIFT 8 662316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_MASK 0x1 663337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_WRITE_SHIFT 9 664316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_MASK 0x1 665337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_REMOTE_ATOMIC_SHIFT 10 666316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_MASK 0x1 667337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_WRITE_SHIFT 11 668316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_MASK 0x1 669337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_LOCAL_READ_SHIFT 12 670316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_MASK 0x1 671337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_ENABLE_MW_BIND_SHIFT 13 672337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_MASK 0x3 673337519Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED_SHIFT 14 674316485Sdavidcs u8 flags1; 675316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_MASK 0x1F 676316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_PBL_PAGE_SIZE_LOG_SHIFT 0 677316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_MASK 0x7 678316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_TID_TYPE_SHIFT 5 679316485Sdavidcs u8 flags2; 680316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_MASK 0x1 /* Bit indicating that this MR is DMA_MR meaning SGEs that use it have the physical address on them */ 681316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_DMA_MR_SHIFT 0 682316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_MASK 0x1 /* Bit indicating that this MR has DIF protection enabled. */ 683316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_DIF_ON_HOST_FLG_SHIFT 1 684316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_MASK 0x3F 685316485Sdavidcs#define RDMA_REGISTER_TID_RAMROD_DATA_RESERVED1_SHIFT 2 686316485Sdavidcs u8 key; 687316485Sdavidcs u8 length_hi; 688316485Sdavidcs u8 vf_id /* This field should be assigned to Virtual Function ID if vf_valid == 1. Otherwise its dont care */; 689316485Sdavidcs u8 vf_valid; 690316485Sdavidcs __le16 pd; 691337519Sdavidcs __le16 reserved2; 692316485Sdavidcs __le32 length_lo /* lower 32 bits of the registered MR length. */; 693316485Sdavidcs __le32 itid; 694337519Sdavidcs __le32 reserved3; 695316485Sdavidcs struct regpair va; 696316485Sdavidcs struct regpair pbl_base; 697316485Sdavidcs struct regpair dif_error_addr /* DIF TX IO writes error information to this location when memory region is invalidated. */; 698316485Sdavidcs struct regpair dif_runt_addr /* DIF RX IO writes runt value to this location when last RDMA Read of the IO has completed. */; 699337519Sdavidcs __le32 reserved4[2]; 700316485Sdavidcs}; 701316485Sdavidcs 702316485Sdavidcs 703316485Sdavidcs/* 704316485Sdavidcs * rdma resize cq output params 705316485Sdavidcs */ 706316485Sdavidcsstruct rdma_resize_cq_output_params 707316485Sdavidcs{ 708316485Sdavidcs __le32 old_cq_cons /* cq consumer value on old PBL */; 709316485Sdavidcs __le32 old_cq_prod /* cq producer value on old PBL */; 710316485Sdavidcs}; 711316485Sdavidcs 712316485Sdavidcs 713316485Sdavidcs/* 714316485Sdavidcs * rdma resize cq ramrod data 715316485Sdavidcs */ 716316485Sdavidcsstruct rdma_resize_cq_ramrod_data 717316485Sdavidcs{ 718316485Sdavidcs u8 flags; 719316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_MASK 0x1 720316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_TOGGLE_BIT_SHIFT 0 721316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_MASK 0x1 722316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_IS_TWO_LEVEL_PBL_SHIFT 1 723316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_MASK 0x3F 724316485Sdavidcs#define RDMA_RESIZE_CQ_RAMROD_DATA_RESERVED_SHIFT 2 725316485Sdavidcs u8 pbl_log_page_size; 726316485Sdavidcs __le16 pbl_num_pages; 727316485Sdavidcs __le32 max_cqes; 728316485Sdavidcs struct regpair pbl_addr; 729316485Sdavidcs struct regpair output_params_addr; 730316485Sdavidcs}; 731316485Sdavidcs 732316485Sdavidcs 733316485Sdavidcs/* 734337519Sdavidcs * The rdma SRQ context 735316485Sdavidcs */ 736316485Sdavidcsstruct rdma_srq_context 737316485Sdavidcs{ 738316485Sdavidcs struct regpair temp[8]; 739316485Sdavidcs}; 740316485Sdavidcs 741316485Sdavidcs 742316485Sdavidcs/* 743316485Sdavidcs * rdma create qp requester ramrod data 744316485Sdavidcs */ 745316485Sdavidcsstruct rdma_srq_create_ramrod_data 746316485Sdavidcs{ 747337519Sdavidcs u8 flags; 748337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_MASK 0x1 749337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_XRC_FLAG_SHIFT 0 750337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_MASK 0x1 /* Only applicable when xrc_flag is set */ 751337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED_KEY_EN_SHIFT 1 752337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_MASK 0x3F 753337519Sdavidcs#define RDMA_SRQ_CREATE_RAMROD_DATA_RESERVED1_SHIFT 2 754337519Sdavidcs u8 reserved2; 755337519Sdavidcs __le16 xrc_domain /* Only applicable when xrc_flag is set */; 756337519Sdavidcs __le32 xrc_srq_cq_cid /* Only applicable when xrc_flag is set */; 757316485Sdavidcs struct regpair pbl_base_addr /* SRQ PBL base address */; 758316485Sdavidcs __le16 pages_in_srq_pbl /* Number of pages in PBL */; 759316485Sdavidcs __le16 pd_id; 760316485Sdavidcs struct rdma_srq_id srq_id /* SRQ Index */; 761316485Sdavidcs __le16 page_size /* Page size in SGEs(16 bytes) elements. Supports up to 2M bytes page size */; 762337519Sdavidcs __le16 reserved3; 763337519Sdavidcs __le32 reserved4; 764316485Sdavidcs struct regpair producers_addr /* SRQ PBL base address */; 765316485Sdavidcs}; 766316485Sdavidcs 767316485Sdavidcs 768316485Sdavidcs/* 769316485Sdavidcs * rdma create qp requester ramrod data 770316485Sdavidcs */ 771316485Sdavidcsstruct rdma_srq_destroy_ramrod_data 772316485Sdavidcs{ 773316485Sdavidcs struct rdma_srq_id srq_id /* SRQ Index */; 774316485Sdavidcs __le32 reserved; 775316485Sdavidcs}; 776316485Sdavidcs 777316485Sdavidcs 778316485Sdavidcs/* 779316485Sdavidcs * rdma create qp requester ramrod data 780316485Sdavidcs */ 781316485Sdavidcsstruct rdma_srq_modify_ramrod_data 782316485Sdavidcs{ 783316485Sdavidcs struct rdma_srq_id srq_id /* SRQ Index */; 784316485Sdavidcs __le32 wqe_limit; 785316485Sdavidcs}; 786316485Sdavidcs 787316485Sdavidcs 788316485Sdavidcs/* 789316485Sdavidcs * RDMA Tid type enumeration (for register_tid ramrod) 790316485Sdavidcs */ 791316485Sdavidcsenum rdma_tid_type 792316485Sdavidcs{ 793316485Sdavidcs RDMA_TID_REGISTERED_MR, 794316485Sdavidcs RDMA_TID_FMR, 795316485Sdavidcs RDMA_TID_MW_TYPE1, 796316485Sdavidcs RDMA_TID_MW_TYPE2A, 797316485Sdavidcs MAX_RDMA_TID_TYPE 798316485Sdavidcs}; 799316485Sdavidcs 800316485Sdavidcs 801337519Sdavidcs/* 802337519Sdavidcs * The rdma XRC SRQ context 803337519Sdavidcs */ 804337519Sdavidcsstruct rdma_xrc_srq_context 805337519Sdavidcs{ 806337519Sdavidcs struct regpair temp[9]; 807337519Sdavidcs}; 808316485Sdavidcs 809316485Sdavidcs 810337519Sdavidcs 811337519Sdavidcs 812316485Sdavidcsstruct E4XstormRoceConnAgCtxDqExtLdPart 813316485Sdavidcs{ 814316485Sdavidcs u8 reserved0 /* cdu_validation */; 815316485Sdavidcs u8 state /* state */; 816316485Sdavidcs u8 flags0; 817316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 818316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM0_SHIFT 0 819316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_MASK 0x1 /* exist_in_qm1 */ 820316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT1_SHIFT 1 821316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_MASK 0x1 /* exist_in_qm2 */ 822316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT2_SHIFT 2 823316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 824316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_EXIST_IN_QM3_SHIFT 3 825316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_MASK 0x1 /* bit4 */ 826316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT4_SHIFT 4 827316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_MASK 0x1 /* cf_array_active */ 828316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT5_SHIFT 5 829316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_MASK 0x1 /* bit6 */ 830316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT6_SHIFT 6 831316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_MASK 0x1 /* bit7 */ 832316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT7_SHIFT 7 833316485Sdavidcs u8 flags1; 834316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_MASK 0x1 /* bit8 */ 835316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT8_SHIFT 0 836316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_MASK 0x1 /* bit9 */ 837316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT9_SHIFT 1 838316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_MASK 0x1 /* bit10 */ 839316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT10_SHIFT 2 840316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_MASK 0x1 /* bit11 */ 841316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT11_SHIFT 3 842316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_MASK 0x1 /* bit12 */ 843316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT12_SHIFT 4 844316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 845316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MSTORM_FLUSH_SHIFT 5 846316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_MASK 0x1 /* bit14 */ 847316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT14_SHIFT 6 848316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 849316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_YSTORM_FLUSH_SHIFT 7 850316485Sdavidcs u8 flags2; 851316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_MASK 0x3 /* timer0cf */ 852316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0_SHIFT 0 853316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_MASK 0x3 /* timer1cf */ 854316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1_SHIFT 2 855316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_MASK 0x3 /* timer2cf */ 856316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2_SHIFT 4 857316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_MASK 0x3 /* timer_stop_all */ 858316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3_SHIFT 6 859316485Sdavidcs u8 flags3; 860316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_MASK 0x3 /* cf4 */ 861316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4_SHIFT 0 862316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_MASK 0x3 /* cf5 */ 863316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5_SHIFT 2 864316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_MASK 0x3 /* cf6 */ 865316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6_SHIFT 4 866316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 867316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_SHIFT 6 868316485Sdavidcs u8 flags4; 869316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_MASK 0x3 /* cf8 */ 870316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8_SHIFT 0 871316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_MASK 0x3 /* cf9 */ 872316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9_SHIFT 2 873316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_MASK 0x3 /* cf10 */ 874316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10_SHIFT 4 875316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_MASK 0x3 /* cf11 */ 876316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11_SHIFT 6 877316485Sdavidcs u8 flags5; 878316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_MASK 0x3 /* cf12 */ 879316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12_SHIFT 0 880316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_MASK 0x3 /* cf13 */ 881316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13_SHIFT 2 882316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_MASK 0x3 /* cf14 */ 883316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14_SHIFT 4 884316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_MASK 0x3 /* cf15 */ 885316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15_SHIFT 6 886316485Sdavidcs u8 flags6; 887316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_MASK 0x3 /* cf16 */ 888316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16_SHIFT 0 889316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_MASK 0x3 /* cf_array_cf */ 890316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17_SHIFT 2 891316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_MASK 0x3 /* cf18 */ 892316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18_SHIFT 4 893316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_MASK 0x3 /* cf19 */ 894316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19_SHIFT 6 895316485Sdavidcs u8 flags7; 896316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_MASK 0x3 /* cf20 */ 897316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20_SHIFT 0 898316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_MASK 0x3 /* cf21 */ 899316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21_SHIFT 2 900316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_MASK 0x3 /* cf22 */ 901316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_SHIFT 4 902316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_MASK 0x1 /* cf0en */ 903316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF0EN_SHIFT 6 904316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_MASK 0x1 /* cf1en */ 905316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF1EN_SHIFT 7 906316485Sdavidcs u8 flags8; 907316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_MASK 0x1 /* cf2en */ 908316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF2EN_SHIFT 0 909316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_MASK 0x1 /* cf3en */ 910316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF3EN_SHIFT 1 911316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_MASK 0x1 /* cf4en */ 912316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF4EN_SHIFT 2 913316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_MASK 0x1 /* cf5en */ 914316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF5EN_SHIFT 3 915316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_MASK 0x1 /* cf6en */ 916316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF6EN_SHIFT 4 917316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 918316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_FLUSH_Q0_CF_EN_SHIFT 5 919316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_MASK 0x1 /* cf8en */ 920316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF8EN_SHIFT 6 921316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_MASK 0x1 /* cf9en */ 922316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF9EN_SHIFT 7 923316485Sdavidcs u8 flags9; 924316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_MASK 0x1 /* cf10en */ 925316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF10EN_SHIFT 0 926316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_MASK 0x1 /* cf11en */ 927316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF11EN_SHIFT 1 928316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_MASK 0x1 /* cf12en */ 929316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF12EN_SHIFT 2 930316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_MASK 0x1 /* cf13en */ 931316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF13EN_SHIFT 3 932316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_MASK 0x1 /* cf14en */ 933316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF14EN_SHIFT 4 934316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_MASK 0x1 /* cf15en */ 935316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF15EN_SHIFT 5 936316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_MASK 0x1 /* cf16en */ 937316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF16EN_SHIFT 6 938316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_MASK 0x1 /* cf_array_cf_en */ 939316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF17EN_SHIFT 7 940316485Sdavidcs u8 flags10; 941316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_MASK 0x1 /* cf18en */ 942316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF18EN_SHIFT 0 943316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_MASK 0x1 /* cf19en */ 944316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF19EN_SHIFT 1 945316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_MASK 0x1 /* cf20en */ 946316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF20EN_SHIFT 2 947316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_MASK 0x1 /* cf21en */ 948316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF21EN_SHIFT 3 949316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 950316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_SLOW_PATH_EN_SHIFT 4 951316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_MASK 0x1 /* cf23en */ 952316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23EN_SHIFT 5 953316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_MASK 0x1 /* rule0en */ 954316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE0EN_SHIFT 6 955316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_MASK 0x1 /* rule1en */ 956316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE1EN_SHIFT 7 957316485Sdavidcs u8 flags11; 958316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_MASK 0x1 /* rule2en */ 959316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE2EN_SHIFT 0 960316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_MASK 0x1 /* rule3en */ 961316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE3EN_SHIFT 1 962316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_MASK 0x1 /* rule4en */ 963316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE4EN_SHIFT 2 964316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_MASK 0x1 /* rule5en */ 965316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE5EN_SHIFT 3 966316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_MASK 0x1 /* rule6en */ 967316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE6EN_SHIFT 4 968316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_MASK 0x1 /* rule7en */ 969316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE7EN_SHIFT 5 970316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_MASK 0x1 /* rule8en */ 971316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED1_SHIFT 6 972316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_MASK 0x1 /* rule9en */ 973316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE9EN_SHIFT 7 974316485Sdavidcs u8 flags12; 975316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_MASK 0x1 /* rule10en */ 976316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE10EN_SHIFT 0 977316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_MASK 0x1 /* rule11en */ 978316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE11EN_SHIFT 1 979316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_MASK 0x1 /* rule12en */ 980316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED2_SHIFT 2 981316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_MASK 0x1 /* rule13en */ 982316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED3_SHIFT 3 983316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_MASK 0x1 /* rule14en */ 984316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE14EN_SHIFT 4 985316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_MASK 0x1 /* rule15en */ 986316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE15EN_SHIFT 5 987316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_MASK 0x1 /* rule16en */ 988316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE16EN_SHIFT 6 989316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_MASK 0x1 /* rule17en */ 990316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE17EN_SHIFT 7 991316485Sdavidcs u8 flags13; 992316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_MASK 0x1 /* rule18en */ 993316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE18EN_SHIFT 0 994316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_MASK 0x1 /* rule19en */ 995316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RULE19EN_SHIFT 1 996316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_MASK 0x1 /* rule20en */ 997316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED4_SHIFT 2 998316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_MASK 0x1 /* rule21en */ 999316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED5_SHIFT 3 1000316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_MASK 0x1 /* rule22en */ 1001316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED6_SHIFT 4 1002316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_MASK 0x1 /* rule23en */ 1003316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED7_SHIFT 5 1004316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_MASK 0x1 /* rule24en */ 1005316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED8_SHIFT 6 1006316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_MASK 0x1 /* rule25en */ 1007316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_A0_RESERVED9_SHIFT 7 1008316485Sdavidcs u8 flags14; 1009316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_MASK 0x1 /* bit16 */ 1010316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_MIGRATION_SHIFT 0 1011316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_MASK 0x1 /* bit17 */ 1012316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_BIT17_SHIFT 1 1013316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1014316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_DPM_PORT_NUM_SHIFT 2 1015316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_MASK 0x1 /* bit20 */ 1016316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_RESERVED_SHIFT 4 1017316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1018316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_ROCE_EDPM_ENABLE_SHIFT 5 1019316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_MASK 0x3 /* cf23 */ 1020316485Sdavidcs#define E4XSTORMROCECONNAGCTXDQEXTLDPART_CF23_SHIFT 6 1021316485Sdavidcs u8 byte2 /* byte2 */; 1022316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 1023316485Sdavidcs __le16 word1 /* physical_q1 */; 1024316485Sdavidcs __le16 word2 /* physical_q2 */; 1025316485Sdavidcs __le16 word3 /* word3 */; 1026316485Sdavidcs __le16 word4 /* word4 */; 1027316485Sdavidcs __le16 word5 /* word5 */; 1028316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1029316485Sdavidcs u8 byte3 /* byte3 */; 1030316485Sdavidcs u8 byte4 /* byte4 */; 1031316485Sdavidcs u8 byte5 /* byte5 */; 1032316485Sdavidcs u8 byte6 /* byte6 */; 1033316485Sdavidcs __le32 reg0 /* reg0 */; 1034316485Sdavidcs __le32 reg1 /* reg1 */; 1035316485Sdavidcs __le32 reg2 /* reg2 */; 1036316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 1037316485Sdavidcs __le32 reg4 /* reg4 */; 1038316485Sdavidcs}; 1039316485Sdavidcs 1040316485Sdavidcs 1041316485Sdavidcsstruct e4_mstorm_rdma_conn_ag_ctx 1042316485Sdavidcs{ 1043316485Sdavidcs u8 byte0 /* cdu_validation */; 1044316485Sdavidcs u8 byte1 /* state */; 1045316485Sdavidcs u8 flags0; 1046316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1047316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1048316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1049316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1050316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1051316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1052316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1053316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1054316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1055316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1056316485Sdavidcs u8 flags1; 1057316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1058316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1059316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1060316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1061316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1062316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1063316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1064316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1065316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1066316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1067316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1068316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1069316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1070316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1071316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1072316485Sdavidcs#define E4_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1073316485Sdavidcs __le16 word0 /* word0 */; 1074316485Sdavidcs __le16 word1 /* word1 */; 1075316485Sdavidcs __le32 reg0 /* reg0 */; 1076316485Sdavidcs __le32 reg1 /* reg1 */; 1077316485Sdavidcs}; 1078316485Sdavidcs 1079316485Sdavidcs 1080316485Sdavidcs 1081316485Sdavidcsstruct e4_tstorm_rdma_conn_ag_ctx 1082316485Sdavidcs{ 1083316485Sdavidcs u8 reserved0 /* cdu_validation */; 1084316485Sdavidcs u8 byte1 /* state */; 1085316485Sdavidcs u8 flags0; 1086316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1087316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1088316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1089316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1090316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1091316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1092316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1093316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1094316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1095316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1096316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1097316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1098316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1099316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1100316485Sdavidcs u8 flags1; 1101316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1102316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1103316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1104316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1105316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1106316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1107316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1108316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1109316485Sdavidcs u8 flags2; 1110316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1111316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1112316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1113316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1114316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1115316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1116316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1117316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1118316485Sdavidcs u8 flags3; 1119316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1120316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1121316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1122316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1123316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1124316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1125316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1126316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1127316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1128316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1129316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1130316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1131316485Sdavidcs u8 flags4; 1132316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1133316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1134316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1135316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1136316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1137316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1138316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1139316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1140316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1141316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1142316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1143316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1144316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1145316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1146316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1147316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1148316485Sdavidcs u8 flags5; 1149316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1150316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1151316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1152316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1153316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1154316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1155316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1156316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1157316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1158316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1159316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1160316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1161316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1162316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1163316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1164316485Sdavidcs#define E4_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1165316485Sdavidcs __le32 reg0 /* reg0 */; 1166316485Sdavidcs __le32 reg1 /* reg1 */; 1167316485Sdavidcs __le32 reg2 /* reg2 */; 1168316485Sdavidcs __le32 reg3 /* reg3 */; 1169316485Sdavidcs __le32 reg4 /* reg4 */; 1170316485Sdavidcs __le32 reg5 /* reg5 */; 1171316485Sdavidcs __le32 reg6 /* reg6 */; 1172316485Sdavidcs __le32 reg7 /* reg7 */; 1173316485Sdavidcs __le32 reg8 /* reg8 */; 1174316485Sdavidcs u8 byte2 /* byte2 */; 1175316485Sdavidcs u8 byte3 /* byte3 */; 1176316485Sdavidcs __le16 word0 /* word0 */; 1177316485Sdavidcs u8 byte4 /* byte4 */; 1178316485Sdavidcs u8 byte5 /* byte5 */; 1179316485Sdavidcs __le16 word1 /* word1 */; 1180316485Sdavidcs __le16 word2 /* conn_dpi */; 1181316485Sdavidcs __le16 word3 /* word3 */; 1182316485Sdavidcs __le32 reg9 /* reg9 */; 1183316485Sdavidcs __le32 reg10 /* reg10 */; 1184316485Sdavidcs}; 1185316485Sdavidcs 1186316485Sdavidcs 1187316485Sdavidcsstruct e4_tstorm_rdma_task_ag_ctx 1188316485Sdavidcs{ 1189316485Sdavidcs u8 byte0 /* cdu_validation */; 1190316485Sdavidcs u8 byte1 /* state */; 1191316485Sdavidcs __le16 word0 /* icid */; 1192316485Sdavidcs u8 flags0; 1193316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1194316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1195316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1196316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1197316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1198316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1199316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1200316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1201316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1202316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1203316485Sdavidcs u8 flags1; 1204316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1205316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1206316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1207316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1208316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1209316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1210316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1211316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1212316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1213316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1214316485Sdavidcs u8 flags2; 1215316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1216316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1217316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1218316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1219316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1220316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1221316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1222316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1223316485Sdavidcs u8 flags3; 1224316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1225316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1226316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1227316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1228316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1229316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1230316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1231316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1232316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1233316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1234316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1235316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1236316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1237316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1238316485Sdavidcs u8 flags4; 1239316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1240316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1241316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1242316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1243316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1244316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1245316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1246316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1247316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1248316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1249316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1250316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1251316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1252316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1253316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1254316485Sdavidcs#define E4_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1255316485Sdavidcs u8 byte2 /* byte2 */; 1256316485Sdavidcs __le16 word1 /* word1 */; 1257316485Sdavidcs __le32 reg0 /* reg0 */; 1258316485Sdavidcs u8 byte3 /* byte3 */; 1259316485Sdavidcs u8 byte4 /* byte4 */; 1260316485Sdavidcs __le16 word2 /* word2 */; 1261316485Sdavidcs __le16 word3 /* word3 */; 1262316485Sdavidcs __le16 word4 /* word4 */; 1263316485Sdavidcs __le32 reg1 /* reg1 */; 1264316485Sdavidcs __le32 reg2 /* reg2 */; 1265316485Sdavidcs}; 1266316485Sdavidcs 1267316485Sdavidcs 1268316485Sdavidcsstruct e4_ustorm_rdma_conn_ag_ctx 1269316485Sdavidcs{ 1270316485Sdavidcs u8 reserved /* cdu_validation */; 1271316485Sdavidcs u8 byte1 /* state */; 1272316485Sdavidcs u8 flags0; 1273316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1274316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1275316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1276316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1277316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1278316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1279316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1280316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1281316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1282316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1283316485Sdavidcs u8 flags1; 1284316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1285316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1286316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1287316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1288316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1289316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1290316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1291316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1292316485Sdavidcs u8 flags2; 1293316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1294316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1295316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1296316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1297316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1298316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1299316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1300316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1301316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1302316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1303316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1304316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1305316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1306316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1307316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1308316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1309316485Sdavidcs u8 flags3; 1310316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1311316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1312316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1313316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1314316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1315316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1316316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1317316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1318316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1319316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1320316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1321316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1322316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1323316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1324316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1325316485Sdavidcs#define E4_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1326316485Sdavidcs u8 byte2 /* byte2 */; 1327316485Sdavidcs u8 byte3 /* byte3 */; 1328316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1329316485Sdavidcs __le16 word1 /* word1 */; 1330316485Sdavidcs __le32 cq_cons /* reg0 */; 1331316485Sdavidcs __le32 cq_se_prod /* reg1 */; 1332316485Sdavidcs __le32 cq_prod /* reg2 */; 1333316485Sdavidcs __le32 reg3 /* reg3 */; 1334316485Sdavidcs __le16 int_timeout /* word2 */; 1335316485Sdavidcs __le16 word3 /* word3 */; 1336316485Sdavidcs}; 1337316485Sdavidcs 1338316485Sdavidcs 1339316485Sdavidcs 1340316485Sdavidcsstruct e4_xstorm_rdma_conn_ag_ctx 1341316485Sdavidcs{ 1342316485Sdavidcs u8 reserved0 /* cdu_validation */; 1343316485Sdavidcs u8 state /* state */; 1344316485Sdavidcs u8 flags0; 1345316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1346316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1347316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1348316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1349316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1350316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1351316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1352316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1353316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1354316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1355316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1356316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1357316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1358316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1359316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1360316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1361316485Sdavidcs u8 flags1; 1362316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1363316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1364316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1365316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1366316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1367316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1368316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1369316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1370316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1371316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1372316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1373316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1374316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1375316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1376316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1377316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1378316485Sdavidcs u8 flags2; 1379316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1380316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1381316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1382316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1383316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1384316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1385316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1386316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1387316485Sdavidcs u8 flags3; 1388316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1389316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1390316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1391316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1392316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1393316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1394316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 1395316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1396316485Sdavidcs u8 flags4; 1397316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1398316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 1399316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1400316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 1401316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1402316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 1403316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1404316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 1405316485Sdavidcs u8 flags5; 1406316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1407316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 1408316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1409316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 1410316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1411316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 1412316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1413316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 1414316485Sdavidcs u8 flags6; 1415316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 1416316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 1417316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1418316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 1419316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 1420316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 1421316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 1422316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 1423316485Sdavidcs u8 flags7; 1424316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 1425316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 1426316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 1427316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 1428316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1429316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1430316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1431316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 1432316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1433316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 1434316485Sdavidcs u8 flags8; 1435316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1436316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 1437316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1438316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 1439316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1440316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 1441316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1442316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 1443316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1444316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 1445316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 1446316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1447316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1448316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 1449316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1450316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 1451316485Sdavidcs u8 flags9; 1452316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1453316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 1454316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1455316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 1456316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1457316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 1458316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1459316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 1460316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1461316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 1462316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1463316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 1464316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 1465316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 1466316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1467316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 1468316485Sdavidcs u8 flags10; 1469316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 1470316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 1471316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 1472316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 1473316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 1474316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 1475316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 1476316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 1477316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1478316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1479316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1480316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 1481316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1482316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 1483316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1484316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 1485316485Sdavidcs u8 flags11; 1486316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1487316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 1488316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1489316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 1490316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1491316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 1492316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1493316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 1494316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1495316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 1496316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1497316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 1498316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1499316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1500316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1501316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 1502316485Sdavidcs u8 flags12; 1503316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1504316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 1505316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1506316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 1507316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1508316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1509316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1510316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1511316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1512316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 1513316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1514316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 1515316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1516316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 1517316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1518316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 1519316485Sdavidcs u8 flags13; 1520316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1521316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 1522316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1523316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 1524316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1525316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1526316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1527316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1528316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1529316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1530316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1531316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1532316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1533316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1534316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1535316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1536316485Sdavidcs u8 flags14; 1537316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 1538316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 1539316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1540316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 1541316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 1542316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 1543316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 1544316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 1545316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 1546316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 1547316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1548316485Sdavidcs#define E4_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 1549316485Sdavidcs u8 byte2 /* byte2 */; 1550316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 1551316485Sdavidcs __le16 word1 /* physical_q1 */; 1552316485Sdavidcs __le16 word2 /* physical_q2 */; 1553316485Sdavidcs __le16 word3 /* word3 */; 1554316485Sdavidcs __le16 word4 /* word4 */; 1555316485Sdavidcs __le16 word5 /* word5 */; 1556316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1557316485Sdavidcs u8 byte3 /* byte3 */; 1558316485Sdavidcs u8 byte4 /* byte4 */; 1559316485Sdavidcs u8 byte5 /* byte5 */; 1560316485Sdavidcs u8 byte6 /* byte6 */; 1561316485Sdavidcs __le32 reg0 /* reg0 */; 1562316485Sdavidcs __le32 reg1 /* reg1 */; 1563316485Sdavidcs __le32 reg2 /* reg2 */; 1564316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 1565316485Sdavidcs __le32 reg4 /* reg4 */; 1566316485Sdavidcs __le32 reg5 /* cf_array0 */; 1567316485Sdavidcs __le32 reg6 /* cf_array1 */; 1568316485Sdavidcs}; 1569316485Sdavidcs 1570316485Sdavidcs 1571316485Sdavidcsstruct e4_ystorm_rdma_conn_ag_ctx 1572316485Sdavidcs{ 1573316485Sdavidcs u8 byte0 /* cdu_validation */; 1574316485Sdavidcs u8 byte1 /* state */; 1575316485Sdavidcs u8 flags0; 1576316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1577316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1578316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1579316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1580316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1581316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1582316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1583316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1584316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1585316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1586316485Sdavidcs u8 flags1; 1587316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1588316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1589316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1590316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1591316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1592316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1593316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1594316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1595316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1596316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1597316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1598316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1599316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1600316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1601316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1602316485Sdavidcs#define E4_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1603316485Sdavidcs u8 byte2 /* byte2 */; 1604316485Sdavidcs u8 byte3 /* byte3 */; 1605316485Sdavidcs __le16 word0 /* word0 */; 1606316485Sdavidcs __le32 reg0 /* reg0 */; 1607316485Sdavidcs __le32 reg1 /* reg1 */; 1608316485Sdavidcs __le16 word1 /* word1 */; 1609316485Sdavidcs __le16 word2 /* word2 */; 1610316485Sdavidcs __le16 word3 /* word3 */; 1611316485Sdavidcs __le16 word4 /* word4 */; 1612316485Sdavidcs __le32 reg2 /* reg2 */; 1613316485Sdavidcs __le32 reg3 /* reg3 */; 1614316485Sdavidcs}; 1615316485Sdavidcs 1616316485Sdavidcs 1617316485Sdavidcs 1618316485Sdavidcsstruct e5_mstorm_rdma_conn_ag_ctx 1619316485Sdavidcs{ 1620316485Sdavidcs u8 byte0 /* cdu_validation */; 1621316485Sdavidcs u8 byte1 /* state_and_core_id */; 1622316485Sdavidcs u8 flags0; 1623316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1624316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 1625316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1626316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1627316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1628316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 1629316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1630316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1631316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1632316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1633316485Sdavidcs u8 flags1; 1634316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1635316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 1636316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1637316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1638316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1639316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1640316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1641316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 1642316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1643316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 1644316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1645316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 1646316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1647316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 1648316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1649316485Sdavidcs#define E5_MSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 1650316485Sdavidcs __le16 word0 /* word0 */; 1651316485Sdavidcs __le16 word1 /* word1 */; 1652316485Sdavidcs __le32 reg0 /* reg0 */; 1653316485Sdavidcs __le32 reg1 /* reg1 */; 1654316485Sdavidcs}; 1655316485Sdavidcs 1656316485Sdavidcs 1657316485Sdavidcs 1658316485Sdavidcsstruct e5_tstorm_rdma_conn_ag_ctx 1659316485Sdavidcs{ 1660316485Sdavidcs u8 reserved0 /* cdu_validation */; 1661316485Sdavidcs u8 byte1 /* state_and_core_id */; 1662316485Sdavidcs u8 flags0; 1663316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1664316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1665316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1666316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1667316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1668316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1669316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1670316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT3_SHIFT 3 1671316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1672316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1673316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1674316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1675316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1676316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 6 1677316485Sdavidcs u8 flags1; 1678316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1679316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 0 1680316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1681316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 2 1682316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1683316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1684316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf4 */ 1685316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 1686316485Sdavidcs u8 flags2; 1687316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_MASK 0x3 /* cf5 */ 1688316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_SHIFT 0 1689316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1690316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 2 1691316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1692316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7_SHIFT 4 1693316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1694316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 6 1695316485Sdavidcs u8 flags3; 1696316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1697316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 0 1698316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1699316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 2 1700316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1701316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 4 1702316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1703316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 5 1704316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1705316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 6 1706316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1707316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1708316485Sdavidcs u8 flags4; 1709316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf4en */ 1710316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1711316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_MASK 0x1 /* cf5en */ 1712316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_CF_EN_SHIFT 1 1713316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1714316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 2 1715316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1716316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF7EN_SHIFT 3 1717316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1718316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 4 1719316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1720316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 5 1721316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1722316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 6 1723316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1724316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 7 1725316485Sdavidcs u8 flags5; 1726316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1727316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 0 1728316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1729316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1730316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1731316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1732316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1733316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1734316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1735316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1736316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1737316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1738316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1739316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1740316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1741316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1742316485Sdavidcs u8 flags6; 1743316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1744316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1745316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1746316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1747316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1748316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1749316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1750316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1751316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1752316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1753316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1754316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1755316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1756316485Sdavidcs#define E5_TSTORM_RDMA_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1757316485Sdavidcs u8 byte2 /* byte2 */; 1758316485Sdavidcs __le16 word0 /* word0 */; 1759316485Sdavidcs __le32 reg0 /* reg0 */; 1760316485Sdavidcs __le32 reg1 /* reg1 */; 1761316485Sdavidcs __le32 reg2 /* reg2 */; 1762316485Sdavidcs __le32 reg3 /* reg3 */; 1763316485Sdavidcs __le32 reg4 /* reg4 */; 1764316485Sdavidcs __le32 reg5 /* reg5 */; 1765316485Sdavidcs __le32 reg6 /* reg6 */; 1766316485Sdavidcs __le32 reg7 /* reg7 */; 1767316485Sdavidcs __le32 reg8 /* reg8 */; 1768316485Sdavidcs u8 byte3 /* byte3 */; 1769316485Sdavidcs u8 byte4 /* byte4 */; 1770316485Sdavidcs u8 byte5 /* byte5 */; 1771316485Sdavidcs u8 e4_reserved8 /* byte6 */; 1772316485Sdavidcs __le16 word1 /* word1 */; 1773316485Sdavidcs __le16 word2 /* conn_dpi */; 1774316485Sdavidcs __le32 reg9 /* reg9 */; 1775316485Sdavidcs __le16 word3 /* word3 */; 1776316485Sdavidcs __le16 e4_reserved9 /* word4 */; 1777316485Sdavidcs}; 1778316485Sdavidcs 1779316485Sdavidcs 1780316485Sdavidcsstruct e5_tstorm_rdma_task_ag_ctx 1781316485Sdavidcs{ 1782316485Sdavidcs u8 byte0 /* cdu_validation */; 1783316485Sdavidcs u8 byte1 /* state_and_core_id */; 1784316485Sdavidcs __le16 word0 /* icid */; 1785316485Sdavidcs u8 flags0; 1786316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_MASK 0xF /* connection_type */ 1787316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_NIBBLE0_SHIFT 0 1788316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1789316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT0_SHIFT 4 1790316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1791316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT1_SHIFT 5 1792316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1793316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT2_SHIFT 6 1794316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1795316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT3_SHIFT 7 1796316485Sdavidcs u8 flags1; 1797316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1798316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT4_SHIFT 0 1799316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1800316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_BIT5_SHIFT 1 1801316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1802316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0_SHIFT 2 1803316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1804316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1_SHIFT 4 1805316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1806316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2_SHIFT 6 1807316485Sdavidcs u8 flags2; 1808316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1809316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3_SHIFT 0 1810316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1811316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4_SHIFT 2 1812316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1813316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5_SHIFT 4 1814316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1815316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6_SHIFT 6 1816316485Sdavidcs u8 flags3; 1817316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1818316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7_SHIFT 0 1819316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1820316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF0EN_SHIFT 2 1821316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1822316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF1EN_SHIFT 3 1823316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1824316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF2EN_SHIFT 4 1825316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1826316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF3EN_SHIFT 5 1827316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1828316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF4EN_SHIFT 6 1829316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1830316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF5EN_SHIFT 7 1831316485Sdavidcs u8 flags4; 1832316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1833316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF6EN_SHIFT 0 1834316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1835316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_CF7EN_SHIFT 1 1836316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1837316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE0EN_SHIFT 2 1838316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1839316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE1EN_SHIFT 3 1840316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1841316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE2EN_SHIFT 4 1842316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1843316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE3EN_SHIFT 5 1844316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1845316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE4EN_SHIFT 6 1846316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1847316485Sdavidcs#define E5_TSTORM_RDMA_TASK_AG_CTX_RULE5EN_SHIFT 7 1848316485Sdavidcs u8 byte2 /* byte2 */; 1849316485Sdavidcs __le16 word1 /* word1 */; 1850316485Sdavidcs __le32 reg0 /* reg0 */; 1851316485Sdavidcs u8 byte3 /* regpair0 */; 1852316485Sdavidcs u8 byte4 /* byte4 */; 1853316485Sdavidcs __le16 word2 /* word2 */; 1854316485Sdavidcs __le16 word3 /* word3 */; 1855316485Sdavidcs __le16 word4 /* word4 */; 1856316485Sdavidcs __le32 reg1 /* regpair1 */; 1857316485Sdavidcs __le32 reg2 /* reg2 */; 1858316485Sdavidcs}; 1859316485Sdavidcs 1860316485Sdavidcs 1861316485Sdavidcsstruct e5_ustorm_rdma_conn_ag_ctx 1862316485Sdavidcs{ 1863316485Sdavidcs u8 reserved /* cdu_validation */; 1864316485Sdavidcs u8 byte1 /* state_and_core_id */; 1865316485Sdavidcs u8 flags0; 1866316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1867316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1868316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1869316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1870316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer0cf */ 1871316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 2 1872316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1873316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 1874316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1875316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 1876316485Sdavidcs u8 flags1; 1877316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1878316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 0 1879316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_MASK 0x3 /* cf4 */ 1880316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_SHIFT 2 1881316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_MASK 0x3 /* cf5 */ 1882316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_SHIFT 4 1883316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1884316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 6 1885316485Sdavidcs u8 flags2; 1886316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf0en */ 1887316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 0 1888316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1889316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 1890316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1891316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 1892316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1893316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 3 1894316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_MASK 0x1 /* cf4en */ 1895316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_SE_CF_EN_SHIFT 4 1896316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_MASK 0x1 /* cf5en */ 1897316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_ARM_CF_EN_SHIFT 5 1898316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1899316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 6 1900316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_MASK 0x1 /* rule0en */ 1901316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_SE_EN_SHIFT 7 1902316485Sdavidcs u8 flags3; 1903316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_MASK 0x1 /* rule1en */ 1904316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_CQ_EN_SHIFT 0 1905316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1906316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 1 1907316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1908316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 2 1909316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1910316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 3 1911316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1912316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 4 1913316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1914316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 5 1915316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1916316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 6 1917316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1918316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_RULE8EN_SHIFT 7 1919316485Sdavidcs u8 flags4; 1920316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1921316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1922316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1923316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1924316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1925316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1926316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1927316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1928316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1929316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1930316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1931316485Sdavidcs#define E5_USTORM_RDMA_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1932316485Sdavidcs u8 byte2 /* byte2 */; 1933316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 1934316485Sdavidcs __le16 word1 /* word1 */; 1935316485Sdavidcs __le32 cq_cons /* reg0 */; 1936316485Sdavidcs __le32 cq_se_prod /* reg1 */; 1937316485Sdavidcs __le32 cq_prod /* reg2 */; 1938316485Sdavidcs __le32 reg3 /* reg3 */; 1939316485Sdavidcs __le16 int_timeout /* word2 */; 1940316485Sdavidcs __le16 word3 /* word3 */; 1941316485Sdavidcs}; 1942316485Sdavidcs 1943316485Sdavidcs 1944316485Sdavidcs 1945316485Sdavidcsstruct e5_xstorm_rdma_conn_ag_ctx 1946316485Sdavidcs{ 1947316485Sdavidcs u8 reserved0 /* cdu_validation */; 1948316485Sdavidcs u8 state_and_core_id /* state_and_core_id */; 1949316485Sdavidcs u8 flags0; 1950316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1951316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1952316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1953316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 1954316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_MASK 0x1 /* exist_in_qm2 */ 1955316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT2_SHIFT 2 1956316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 1957316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 1958316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1959316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT4_SHIFT 4 1960316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_MASK 0x1 /* cf_array_active */ 1961316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT5_SHIFT 5 1962316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_MASK 0x1 /* bit6 */ 1963316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT6_SHIFT 6 1964316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_MASK 0x1 /* bit7 */ 1965316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT7_SHIFT 7 1966316485Sdavidcs u8 flags1; 1967316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_MASK 0x1 /* bit8 */ 1968316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT8_SHIFT 0 1969316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_MASK 0x1 /* bit9 */ 1970316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT9_SHIFT 1 1971316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_MASK 0x1 /* bit10 */ 1972316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT10_SHIFT 2 1973316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1974316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT11_SHIFT 3 1975316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1976316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT12_SHIFT 4 1977337519Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_MASK 0x1 /* bit13 */ 1978337519Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_MSTORM_FLUSH_SHIFT 5 1979316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 1980316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT14_SHIFT 6 1981316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_MASK 0x1 /* bit15 */ 1982316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_YSTORM_FLUSH_SHIFT 7 1983316485Sdavidcs u8 flags2; 1984316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1985316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 0 1986316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1987316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 2 1988316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1989316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 4 1990316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1991316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3_SHIFT 6 1992316485Sdavidcs u8 flags3; 1993316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1994316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4_SHIFT 0 1995316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1996316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5_SHIFT 2 1997316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1998316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6_SHIFT 4 1999316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* cf7 */ 2000316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 6 2001316485Sdavidcs u8 flags4; 2002316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 2003316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8_SHIFT 0 2004316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 2005316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9_SHIFT 2 2006316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 2007316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10_SHIFT 4 2008316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 2009316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11_SHIFT 6 2010316485Sdavidcs u8 flags5; 2011316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 2012316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12_SHIFT 0 2013316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 2014316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13_SHIFT 2 2015316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 2016316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14_SHIFT 4 2017316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 2018316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15_SHIFT 6 2019316485Sdavidcs u8 flags6; 2020316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 2021316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16_SHIFT 0 2022316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 2023316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17_SHIFT 2 2024316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 2025316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18_SHIFT 4 2026316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_MASK 0x3 /* cf19 */ 2027316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19_SHIFT 6 2028316485Sdavidcs u8 flags7; 2029316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_MASK 0x3 /* cf20 */ 2030316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20_SHIFT 0 2031316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_MASK 0x3 /* cf21 */ 2032316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21_SHIFT 2 2033316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 2034316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_SHIFT 4 2035316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2036316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 6 2037316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2038316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 7 2039316485Sdavidcs u8 flags8; 2040316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2041316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 0 2042316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 2043316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF3EN_SHIFT 1 2044316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 2045316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF4EN_SHIFT 2 2046316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 2047316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF5EN_SHIFT 3 2048316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 2049316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF6EN_SHIFT 4 2050316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf7en */ 2051316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 2052316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 2053316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF8EN_SHIFT 6 2054316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 2055316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF9EN_SHIFT 7 2056316485Sdavidcs u8 flags9; 2057316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 2058316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF10EN_SHIFT 0 2059316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 2060316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF11EN_SHIFT 1 2061316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 2062316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF12EN_SHIFT 2 2063316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 2064316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF13EN_SHIFT 3 2065316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 2066316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF14EN_SHIFT 4 2067316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 2068316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF15EN_SHIFT 5 2069316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 2070316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF16EN_SHIFT 6 2071316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 2072316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF17EN_SHIFT 7 2073316485Sdavidcs u8 flags10; 2074316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 2075316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF18EN_SHIFT 0 2076316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_MASK 0x1 /* cf19en */ 2077316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF19EN_SHIFT 1 2078316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_MASK 0x1 /* cf20en */ 2079316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF20EN_SHIFT 2 2080316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_MASK 0x1 /* cf21en */ 2081316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF21EN_SHIFT 3 2082316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 2083316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 2084316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 2085316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23EN_SHIFT 5 2086316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2087316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 6 2088316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2089316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 7 2090316485Sdavidcs u8 flags11; 2091316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2092316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 0 2093316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2094316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 1 2095316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2096316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 2 2097316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 2098316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE5EN_SHIFT 3 2099316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 2100316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE6EN_SHIFT 4 2101316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 2102316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE7EN_SHIFT 5 2103316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 2104316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 2105316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 2106316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE9EN_SHIFT 7 2107316485Sdavidcs u8 flags12; 2108316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 2109316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE10EN_SHIFT 0 2110316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 2111316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE11EN_SHIFT 1 2112316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 2113316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 2114316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 2115316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 2116316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 2117316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE14EN_SHIFT 4 2118316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 2119316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE15EN_SHIFT 5 2120316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 2121316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE16EN_SHIFT 6 2122316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 2123316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE17EN_SHIFT 7 2124316485Sdavidcs u8 flags13; 2125316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 2126316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE18EN_SHIFT 0 2127316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 2128316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RULE19EN_SHIFT 1 2129316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 2130316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 2131316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 2132316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 2133316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 2134316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 2135316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 2136316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 2137316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 2138316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 2139316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 2140316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 2141316485Sdavidcs u8 flags14; 2142316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_MASK 0x1 /* bit16 */ 2143316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_MIGRATION_SHIFT 0 2144316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 2145316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_BIT17_SHIFT 1 2146316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_MASK 0x3 /* bit18 */ 2147316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_DPM_PORT_NUM_SHIFT 2 2148316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_MASK 0x1 /* bit20 */ 2149316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_RESERVED_SHIFT 4 2150316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_MASK 0x1 /* bit21 */ 2151316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_ROCE_EDPM_ENABLE_SHIFT 5 2152316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 2153316485Sdavidcs#define E5_XSTORM_RDMA_CONN_AG_CTX_CF23_SHIFT 6 2154316485Sdavidcs u8 byte2 /* byte2 */; 2155316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 2156316485Sdavidcs __le16 word1 /* physical_q1 */; 2157316485Sdavidcs __le16 word2 /* physical_q2 */; 2158316485Sdavidcs __le16 word3 /* word3 */; 2159316485Sdavidcs __le16 word4 /* word4 */; 2160316485Sdavidcs __le16 word5 /* word5 */; 2161316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 2162316485Sdavidcs u8 byte3 /* byte3 */; 2163316485Sdavidcs u8 byte4 /* byte4 */; 2164316485Sdavidcs u8 byte5 /* byte5 */; 2165316485Sdavidcs u8 byte6 /* byte6 */; 2166316485Sdavidcs __le32 reg0 /* reg0 */; 2167316485Sdavidcs __le32 reg1 /* reg1 */; 2168316485Sdavidcs __le32 reg2 /* reg2 */; 2169316485Sdavidcs __le32 snd_nxt_psn /* reg3 */; 2170316485Sdavidcs __le32 reg4 /* reg4 */; 2171316485Sdavidcs __le32 reg5 /* cf_array0 */; 2172316485Sdavidcs __le32 reg6 /* cf_array1 */; 2173316485Sdavidcs}; 2174316485Sdavidcs 2175316485Sdavidcs 2176316485Sdavidcsstruct e5_ystorm_rdma_conn_ag_ctx 2177316485Sdavidcs{ 2178316485Sdavidcs u8 byte0 /* cdu_validation */; 2179316485Sdavidcs u8 byte1 /* state_and_core_id */; 2180316485Sdavidcs u8 flags0; 2181316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2182316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT0_SHIFT 0 2183316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2184316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_BIT1_SHIFT 1 2185316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2186316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0_SHIFT 2 2187316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2188316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1_SHIFT 4 2189316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2190316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2_SHIFT 6 2191316485Sdavidcs u8 flags1; 2192316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2193316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF0EN_SHIFT 0 2194316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2195316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF1EN_SHIFT 1 2196316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2197316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_CF2EN_SHIFT 2 2198316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2199316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE0EN_SHIFT 3 2200316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2201316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE1EN_SHIFT 4 2202316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2203316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE2EN_SHIFT 5 2204316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2205316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE3EN_SHIFT 6 2206316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2207316485Sdavidcs#define E5_YSTORM_RDMA_CONN_AG_CTX_RULE4EN_SHIFT 7 2208316485Sdavidcs u8 byte2 /* byte2 */; 2209316485Sdavidcs u8 byte3 /* byte3 */; 2210316485Sdavidcs __le16 word0 /* word0 */; 2211316485Sdavidcs __le32 reg0 /* reg0 */; 2212316485Sdavidcs __le32 reg1 /* reg1 */; 2213316485Sdavidcs __le16 word1 /* word1 */; 2214316485Sdavidcs __le16 word2 /* word2 */; 2215316485Sdavidcs __le16 word3 /* word3 */; 2216316485Sdavidcs __le16 word4 /* word4 */; 2217316485Sdavidcs __le32 reg2 /* reg2 */; 2218316485Sdavidcs __le32 reg3 /* reg3 */; 2219316485Sdavidcs}; 2220316485Sdavidcs 2221316485Sdavidcs 2222316485Sdavidcs#endif /* __ECORE_HSI_RDMA__ */ 2223