1272343Sngie/* 2272343Sngie * Copyright (c) 2017-2018 Cavium, Inc. 3272343Sngie * All rights reserved. 4272343Sngie * 5272343Sngie * Redistribution and use in source and binary forms, with or without 6272343Sngie * modification, are permitted provided that the following conditions 7272343Sngie * are met: 8272343Sngie * 9272343Sngie * 1. Redistributions of source code must retain the above copyright 10272343Sngie * notice, this list of conditions and the following disclaimer. 11272343Sngie * 2. Redistributions in binary form must reproduce the above copyright 12272343Sngie * notice, this list of conditions and the following disclaimer in the 13272343Sngie * documentation and/or other materials provided with the distribution. 14272343Sngie * 15272343Sngie * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16272343Sngie * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17272343Sngie * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18272343Sngie * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19272343Sngie * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20272343Sngie * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21272343Sngie * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22272343Sngie * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23272343Sngie * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24272343Sngie * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25272343Sngie * POSSIBILITY OF SUCH DAMAGE. 26272343Sngie * 27272343Sngie * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hsi_init_tool.h 337519 2018-08-09 01:39:47Z davidcs $ 28272343Sngie * 29272343Sngie */ 30272343Sngie 31272343Sngie 32272343Sngie#ifndef __ECORE_HSI_INIT_TOOL__ 33272343Sngie#define __ECORE_HSI_INIT_TOOL__ 34272343Sngie/**************************************/ 35272343Sngie/* Init Tool HSI constants and macros */ 36272343Sngie/**************************************/ 37272343Sngie 38272343Sngie/* Width of GRC address in bits (addresses are specified in dwords) */ 39272343Sngie#define GRC_ADDR_BITS 23 40272343Sngie#define MAX_GRC_ADDR ((1 << GRC_ADDR_BITS) - 1) 41272343Sngie 42272343Sngie/* indicates an init that should be applied to any phase ID */ 43272343Sngie#define ANY_PHASE_ID 0xffff 44272343Sngie 45272343Sngie/* Max size in dwords of a zipped array */ 46272343Sngie#define MAX_ZIPPED_SIZE 8192 47272343Sngie 48272343Sngie 49272343Sngieenum chip_ids 50272343Sngie{ 51272343Sngie CHIP_BB, 52272343Sngie CHIP_K2, 53272343Sngie CHIP_E5, 54272343Sngie MAX_CHIP_IDS 55272343Sngie}; 56272343Sngie 57272343Sngie 58272343Sngieenum init_modes 59272343Sngie{ 60272343Sngie MODE_BB_A0_DEPRECATED, 61272343Sngie MODE_BB, 62272343Sngie MODE_K2, 63272343Sngie MODE_ASIC, 64272343Sngie MODE_EMUL_REDUCED, 65272343Sngie MODE_EMUL_FULL, 66272343Sngie MODE_FPGA, 67272343Sngie MODE_CHIPSIM, 68272343Sngie MODE_SF, 69272343Sngie MODE_MF_SD, 70272343Sngie MODE_MF_SI, 71272343Sngie MODE_PORTS_PER_ENG_1, 72272343Sngie MODE_PORTS_PER_ENG_2, 73272343Sngie MODE_PORTS_PER_ENG_4, 74272343Sngie MODE_100G, 75272343Sngie MODE_E5, 76272343Sngie MAX_INIT_MODES 77272343Sngie}; 78272343Sngie 79272343Sngie 80272343Sngieenum init_phases 81272343Sngie{ 82272343Sngie PHASE_ENGINE, 83272343Sngie PHASE_PORT, 84272343Sngie PHASE_PF, 85272343Sngie PHASE_VF, 86272343Sngie PHASE_QM_PF, 87272343Sngie MAX_INIT_PHASES 88272343Sngie}; 89272343Sngie 90272343Sngie 91272343Sngieenum init_split_types 92272343Sngie{ 93272343Sngie SPLIT_TYPE_NONE, 94272343Sngie SPLIT_TYPE_PORT, 95272343Sngie SPLIT_TYPE_PF, 96272343Sngie SPLIT_TYPE_PORT_PF, 97272343Sngie SPLIT_TYPE_VF, 98272343Sngie MAX_INIT_SPLIT_TYPES 99272343Sngie}; 100272343Sngie 101272343Sngie 102272343Sngie/* 103272343Sngie * Binary buffer header 104272343Sngie */ 105272343Sngiestruct bin_buffer_hdr 106272343Sngie{ 107272343Sngie u32 offset /* buffer offset in bytes from the beginning of the binary file */; 108272343Sngie u32 length /* buffer length in bytes */; 109272343Sngie}; 110272343Sngie 111272343Sngie 112272343Sngie/* 113272343Sngie * binary init buffer types 114272343Sngie */ 115272343Sngieenum bin_init_buffer_type 116272343Sngie{ 117272343Sngie BIN_BUF_INIT_FW_VER_INFO /* fw_ver_info struct */, 118272343Sngie BIN_BUF_INIT_CMD /* init commands */, 119272343Sngie BIN_BUF_INIT_VAL /* init data */, 120272343Sngie BIN_BUF_INIT_MODE_TREE /* init modes tree */, 121272343Sngie BIN_BUF_INIT_IRO /* internal RAM offsets */, 122272343Sngie MAX_BIN_INIT_BUFFER_TYPE 123272343Sngie}; 124272343Sngie 125272343Sngie 126272343Sngie/* 127272343Sngie * init array header: raw 128272343Sngie */ 129272343Sngiestruct init_array_raw_hdr 130272343Sngie{ 131272343Sngie u32 data; 132272343Sngie#define INIT_ARRAY_RAW_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 133272343Sngie#define INIT_ARRAY_RAW_HDR_TYPE_SHIFT 0 134272343Sngie#define INIT_ARRAY_RAW_HDR_PARAMS_MASK 0xFFFFFFF /* init array params */ 135272343Sngie#define INIT_ARRAY_RAW_HDR_PARAMS_SHIFT 4 136272343Sngie}; 137272343Sngie 138272343Sngie/* 139272343Sngie * init array header: standard 140272343Sngie */ 141272343Sngiestruct init_array_standard_hdr 142272343Sngie{ 143272343Sngie u32 data; 144272343Sngie#define INIT_ARRAY_STANDARD_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 145272343Sngie#define INIT_ARRAY_STANDARD_HDR_TYPE_SHIFT 0 146272343Sngie#define INIT_ARRAY_STANDARD_HDR_SIZE_MASK 0xFFFFFFF /* Init array size (in dwords) */ 147272343Sngie#define INIT_ARRAY_STANDARD_HDR_SIZE_SHIFT 4 148272343Sngie}; 149272343Sngie 150272343Sngie/* 151272343Sngie * init array header: zipped 152272343Sngie */ 153272343Sngiestruct init_array_zipped_hdr 154272343Sngie{ 155272343Sngie u32 data; 156272343Sngie#define INIT_ARRAY_ZIPPED_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 157272343Sngie#define INIT_ARRAY_ZIPPED_HDR_TYPE_SHIFT 0 158272343Sngie#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_MASK 0xFFFFFFF /* Init array zipped size (in bytes) */ 159272343Sngie#define INIT_ARRAY_ZIPPED_HDR_ZIPPED_SIZE_SHIFT 4 160272343Sngie}; 161272343Sngie 162272343Sngie/* 163272343Sngie * init array header: pattern 164272343Sngie */ 165272343Sngiestruct init_array_pattern_hdr 166272343Sngie{ 167272343Sngie u32 data; 168272343Sngie#define INIT_ARRAY_PATTERN_HDR_TYPE_MASK 0xF /* Init array type, from init_array_types enum */ 169272343Sngie#define INIT_ARRAY_PATTERN_HDR_TYPE_SHIFT 0 170272343Sngie#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_MASK 0xF /* pattern size in dword */ 171272343Sngie#define INIT_ARRAY_PATTERN_HDR_PATTERN_SIZE_SHIFT 4 172272343Sngie#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_MASK 0xFFFFFF /* pattern repetitions */ 173272343Sngie#define INIT_ARRAY_PATTERN_HDR_REPETITIONS_SHIFT 8 174272343Sngie}; 175272343Sngie 176272343Sngie/* 177272343Sngie * init array header union 178272343Sngie */ 179272343Sngieunion init_array_hdr 180272343Sngie{ 181272343Sngie struct init_array_raw_hdr raw /* raw init array header */; 182272343Sngie struct init_array_standard_hdr standard /* standard init array header */; 183272343Sngie struct init_array_zipped_hdr zipped /* zipped init array header */; 184272343Sngie struct init_array_pattern_hdr pattern /* pattern init array header */; 185272343Sngie}; 186272343Sngie 187272343Sngie 188272343Sngie 189272343Sngie 190272343Sngie 191272343Sngie/* 192272343Sngie * init array types 193272343Sngie */ 194272343Sngieenum init_array_types 195272343Sngie{ 196272343Sngie INIT_ARR_STANDARD /* standard init array */, 197272343Sngie INIT_ARR_ZIPPED /* zipped init array */, 198272343Sngie INIT_ARR_PATTERN /* a repeated pattern */, 199272343Sngie MAX_INIT_ARRAY_TYPES 200272343Sngie}; 201 202 203 204/* 205 * init operation: callback 206 */ 207struct init_callback_op 208{ 209 u32 op_data; 210#define INIT_CALLBACK_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 211#define INIT_CALLBACK_OP_OP_SHIFT 0 212#define INIT_CALLBACK_OP_RESERVED_MASK 0xFFFFFFF 213#define INIT_CALLBACK_OP_RESERVED_SHIFT 4 214 u16 callback_id /* Callback ID */; 215 u16 block_id /* Blocks ID */; 216}; 217 218 219/* 220 * init operation: delay 221 */ 222struct init_delay_op 223{ 224 u32 op_data; 225#define INIT_DELAY_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 226#define INIT_DELAY_OP_OP_SHIFT 0 227#define INIT_DELAY_OP_RESERVED_MASK 0xFFFFFFF 228#define INIT_DELAY_OP_RESERVED_SHIFT 4 229 u32 delay /* delay in us */; 230}; 231 232 233/* 234 * init operation: if_mode 235 */ 236struct init_if_mode_op 237{ 238 u32 op_data; 239#define INIT_IF_MODE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 240#define INIT_IF_MODE_OP_OP_SHIFT 0 241#define INIT_IF_MODE_OP_RESERVED1_MASK 0xFFF 242#define INIT_IF_MODE_OP_RESERVED1_SHIFT 4 243#define INIT_IF_MODE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the modes dont match */ 244#define INIT_IF_MODE_OP_CMD_OFFSET_SHIFT 16 245 u16 reserved2; 246 u16 modes_buf_offset /* offset (in bytes) in modes expression buffer */; 247}; 248 249 250/* 251 * init operation: if_phase 252 */ 253struct init_if_phase_op 254{ 255 u32 op_data; 256#define INIT_IF_PHASE_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 257#define INIT_IF_PHASE_OP_OP_SHIFT 0 258#define INIT_IF_PHASE_OP_DMAE_ENABLE_MASK 0x1 /* Indicates if DMAE is enabled in this phase */ 259#define INIT_IF_PHASE_OP_DMAE_ENABLE_SHIFT 4 260#define INIT_IF_PHASE_OP_RESERVED1_MASK 0x7FF 261#define INIT_IF_PHASE_OP_RESERVED1_SHIFT 5 262#define INIT_IF_PHASE_OP_CMD_OFFSET_MASK 0xFFFF /* Commands to skip if the phases dont match */ 263#define INIT_IF_PHASE_OP_CMD_OFFSET_SHIFT 16 264 u32 phase_data; 265#define INIT_IF_PHASE_OP_PHASE_MASK 0xFF /* Init phase */ 266#define INIT_IF_PHASE_OP_PHASE_SHIFT 0 267#define INIT_IF_PHASE_OP_RESERVED2_MASK 0xFF 268#define INIT_IF_PHASE_OP_RESERVED2_SHIFT 8 269#define INIT_IF_PHASE_OP_PHASE_ID_MASK 0xFFFF /* Init phase ID */ 270#define INIT_IF_PHASE_OP_PHASE_ID_SHIFT 16 271}; 272 273 274/* 275 * init mode operators 276 */ 277enum init_mode_ops 278{ 279 INIT_MODE_OP_NOT /* init mode not operator */, 280 INIT_MODE_OP_OR /* init mode or operator */, 281 INIT_MODE_OP_AND /* init mode and operator */, 282 MAX_INIT_MODE_OPS 283}; 284 285 286/* 287 * init operation: raw 288 */ 289struct init_raw_op 290{ 291 u32 op_data; 292#define INIT_RAW_OP_OP_MASK 0xF /* Init operation, from init_op_types enum */ 293#define INIT_RAW_OP_OP_SHIFT 0 294#define INIT_RAW_OP_PARAM1_MASK 0xFFFFFFF /* init param 1 */ 295#define INIT_RAW_OP_PARAM1_SHIFT 4 296 u32 param2 /* Init param 2 */; 297}; 298 299/* 300 * init array params 301 */ 302struct init_op_array_params 303{ 304 u16 size /* array size in dwords */; 305 u16 offset /* array start offset in dwords */; 306}; 307 308/* 309 * Write init operation arguments 310 */ 311union init_write_args 312{ 313 u32 inline_val /* value to write, used when init source is INIT_SRC_INLINE */; 314 u32 zeros_count /* number of zeros to write, used when init source is INIT_SRC_ZEROS */; 315 u32 array_offset /* array offset to write, used when init source is INIT_SRC_ARRAY */; 316 struct init_op_array_params runtime /* runtime array params to write, used when init source is INIT_SRC_RUNTIME */; 317}; 318 319/* 320 * init operation: write 321 */ 322struct init_write_op 323{ 324 u32 data; 325#define INIT_WRITE_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 326#define INIT_WRITE_OP_OP_SHIFT 0 327#define INIT_WRITE_OP_SOURCE_MASK 0x7 /* init source type, taken from init_source_types enum */ 328#define INIT_WRITE_OP_SOURCE_SHIFT 4 329#define INIT_WRITE_OP_RESERVED_MASK 0x1 330#define INIT_WRITE_OP_RESERVED_SHIFT 7 331#define INIT_WRITE_OP_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 332#define INIT_WRITE_OP_WIDE_BUS_SHIFT 8 333#define INIT_WRITE_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 334#define INIT_WRITE_OP_ADDRESS_SHIFT 9 335 union init_write_args args /* Write init operation arguments */; 336}; 337 338/* 339 * init operation: read 340 */ 341struct init_read_op 342{ 343 u32 op_data; 344#define INIT_READ_OP_OP_MASK 0xF /* init operation, from init_op_types enum */ 345#define INIT_READ_OP_OP_SHIFT 0 346#define INIT_READ_OP_POLL_TYPE_MASK 0xF /* polling type, from init_poll_types enum */ 347#define INIT_READ_OP_POLL_TYPE_SHIFT 4 348#define INIT_READ_OP_RESERVED_MASK 0x1 349#define INIT_READ_OP_RESERVED_SHIFT 8 350#define INIT_READ_OP_ADDRESS_MASK 0x7FFFFF /* internal (absolute) GRC address, in dwords */ 351#define INIT_READ_OP_ADDRESS_SHIFT 9 352 u32 expected_val /* expected polling value, used only when polling is done */; 353}; 354 355/* 356 * Init operations union 357 */ 358union init_op 359{ 360 struct init_raw_op raw /* raw init operation */; 361 struct init_write_op write /* write init operation */; 362 struct init_read_op read /* read init operation */; 363 struct init_if_mode_op if_mode /* if_mode init operation */; 364 struct init_if_phase_op if_phase /* if_phase init operation */; 365 struct init_callback_op callback /* callback init operation */; 366 struct init_delay_op delay /* delay init operation */; 367}; 368 369 370 371/* 372 * Init command operation types 373 */ 374enum init_op_types 375{ 376 INIT_OP_READ /* GRC read init command */, 377 INIT_OP_WRITE /* GRC write init command */, 378 INIT_OP_IF_MODE /* Skip init commands if the init modes expression doesnt match */, 379 INIT_OP_IF_PHASE /* Skip init commands if the init phase doesnt match */, 380 INIT_OP_DELAY /* delay init command */, 381 INIT_OP_CALLBACK /* callback init command */, 382 MAX_INIT_OP_TYPES 383}; 384 385 386/* 387 * init polling types 388 */ 389enum init_poll_types 390{ 391 INIT_POLL_NONE /* No polling */, 392 INIT_POLL_EQ /* init value is included in the init command */, 393 INIT_POLL_OR /* init value is all zeros */, 394 INIT_POLL_AND /* init value is an array of values */, 395 MAX_INIT_POLL_TYPES 396}; 397 398 399 400 401/* 402 * init source types 403 */ 404enum init_source_types 405{ 406 INIT_SRC_INLINE /* init value is included in the init command */, 407 INIT_SRC_ZEROS /* init value is all zeros */, 408 INIT_SRC_ARRAY /* init value is an array of values */, 409 INIT_SRC_RUNTIME /* init value is provided during runtime */, 410 MAX_INIT_SOURCE_TYPES 411}; 412 413 414 415 416/* 417 * Internal RAM Offsets macro data 418 */ 419struct iro 420{ 421 u32 base /* RAM field offset */; 422 u16 m1 /* multiplier 1 */; 423 u16 m2 /* multiplier 2 */; 424 u16 m3 /* multiplier 3 */; 425 u16 size /* RAM field size */; 426}; 427 428#endif /* __ECORE_HSI_INIT_TOOL__ */ 429