ecore_hsi_fcoe.h revision 337519
1/* 2 * Copyright (c) 2017-2018 Cavium, Inc. 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19 * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25 * POSSIBILITY OF SUCH DAMAGE. 26 * 27 * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hsi_fcoe.h 337519 2018-08-09 01:39:47Z davidcs $ 28 * 29 */ 30 31#ifndef __ECORE_HSI_FCOE__ 32#define __ECORE_HSI_FCOE__ 33/****************************************/ 34/* Add include to common storage target */ 35/****************************************/ 36#include "storage_common.h" 37 38/************************************************************************/ 39/* Add include to common fcoe target for both eCore and protocol driver */ 40/************************************************************************/ 41#include "fcoe_common.h" 42 43 44/* 45 * The fcoe storm context of Ystorm 46 */ 47struct ystorm_fcoe_conn_st_ctx 48{ 49 u8 func_mode /* Function mode */; 50 u8 cos /* Transmission cos */; 51 u8 conf_version /* Is dcb_version or vntag_version changed */; 52 u8 eth_hdr_size /* Ethernet header size */; 53 __le16 stat_ram_addr /* Statistics ram adderss */; 54 __le16 mtu /* MTU limitation */; 55 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. 8 bytes aligned (required for protection fast-path) */; 56 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 57 u8 fcp_cmd_size /* FCP cmd size. for performance reasons */; 58 u8 fcp_rsp_size /* FCP RSP size. for performance reasons */; 59 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 60 struct regpair reserved; 61 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header) */; 62 u8 protection_info_flags; 63#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it�� ��������������s enough that one of them support protection) */ 64#define YSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 0 65#define YSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can�� ��������������t rely on this size �� �������������� it depends on vlan num) */ 66#define YSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 1 67#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_MASK 0x3F 68#define YSTORM_FCOE_CONN_ST_CTX_RESERVED1_SHIFT 2 69 u8 dst_protection_per_mss /* Destination Protection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */; 70 u8 src_protection_per_mss /* Source Protection data per mss (if we are not in perf mode it will be worse case). Source is the data validated by the nic (as opposed to destination which is data add/remove from the transmitted packet they might not be identical) */; 71 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 72 u8 flags; 73#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 74#define YSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 0 75#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 76#define YSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 1 77#define YSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x3F 78#define YSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 2 79 u8 fcp_xfer_size /* FCP xfer size. for performance reasons */; 80}; 81 82/* 83 * FCoE 16-bits vlan structure 84 */ 85struct fcoe_vlan_fields 86{ 87 __le16 fields; 88#define FCOE_VLAN_FIELDS_VID_MASK 0xFFF 89#define FCOE_VLAN_FIELDS_VID_SHIFT 0 90#define FCOE_VLAN_FIELDS_CLI_MASK 0x1 91#define FCOE_VLAN_FIELDS_CLI_SHIFT 12 92#define FCOE_VLAN_FIELDS_PRI_MASK 0x7 93#define FCOE_VLAN_FIELDS_PRI_SHIFT 13 94}; 95 96/* 97 * FCoE 16-bits vlan union 98 */ 99union fcoe_vlan_field_union 100{ 101 struct fcoe_vlan_fields fields /* Parameters field */; 102 __le16 val /* Global value */; 103}; 104 105/* 106 * FCoE 16-bits vlan, vif union 107 */ 108union fcoe_vlan_vif_field_union 109{ 110 union fcoe_vlan_field_union vlan /* Vlan */; 111 __le16 vif /* VIF */; 112}; 113 114/* 115 * Ethernet context section 116 */ 117struct pstorm_fcoe_eth_context_section 118{ 119 u8 remote_addr_3 /* Remote Mac Address, used in PBF Header Builder Command */; 120 u8 remote_addr_2 /* Remote Mac Address, used in PBF Header Builder Command */; 121 u8 remote_addr_1 /* Remote Mac Address, used in PBF Header Builder Command */; 122 u8 remote_addr_0 /* Remote Mac Address, used in PBF Header Builder Command */; 123 u8 local_addr_1 /* Local Mac Address, used in PBF Header Builder Command */; 124 u8 local_addr_0 /* Local Mac Address, used in PBF Header Builder Command */; 125 u8 remote_addr_5 /* Remote Mac Address, used in PBF Header Builder Command */; 126 u8 remote_addr_4 /* Remote Mac Address, used in PBF Header Builder Command */; 127 u8 local_addr_5 /* Local Mac Address, used in PBF Header Builder Command */; 128 u8 local_addr_4 /* Loca lMac Address, used in PBF Header Builder Command */; 129 u8 local_addr_3 /* Local Mac Address, used in PBF Header Builder Command */; 130 u8 local_addr_2 /* Local Mac Address, used in PBF Header Builder Command */; 131 union fcoe_vlan_vif_field_union vif_outer_vlan /* Union of VIF and outer vlan */; 132 __le16 vif_outer_eth_type /* reserved place for Ethernet type */; 133 union fcoe_vlan_vif_field_union inner_vlan /* inner vlan tag */; 134 __le16 inner_eth_type /* reserved place for Ethernet type */; 135}; 136 137/* 138 * The fcoe storm context of Pstorm 139 */ 140struct pstorm_fcoe_conn_st_ctx 141{ 142 u8 func_mode /* Function mode */; 143 u8 cos /* Transmission cos */; 144 u8 conf_version /* Is dcb_version or vntag_version changed */; 145 u8 rsrv; 146 __le16 stat_ram_addr /* Statistics ram adderss */; 147 __le16 mss /* MSS for PBF (MSS we negotiate with target - protection data per segment. If we are not in perf mode it will be according to worse case) */; 148 struct regpair abts_cleanup_addr /* Host addr of ABTS /Cleanup info. since we pass it through session context, we pass only the addr to save space */; 149 struct pstorm_fcoe_eth_context_section eth /* Source mac */; 150 u8 sid_2 /* SID FC address - Third byte that is sent to NW via PBF For example is SID is 01:02:03 then sid_2 is 0x03 */; 151 u8 sid_1 /* SID FC address - Second byte that is sent to NW via PBF */; 152 u8 sid_0 /* SID FC address - First byte that is sent to NW via PBF */; 153 u8 flags; 154#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_MASK 0x1 /* Is inner vlan taken from vntag default vlan (in this case I have to update inner vlan each time the default change) */ 155#define PSTORM_FCOE_CONN_ST_CTX_VNTAG_VLAN_SHIFT 0 156#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_MASK 0x1 /* AreSupport rec_tov timer */ 157#define PSTORM_FCOE_CONN_ST_CTX_SUPPORT_REC_RR_TOV_SHIFT 1 158#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner Vlan flag */ 159#define PSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 2 160#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_MASK 0x1 /* Outer Vlan flag */ 161#define PSTORM_FCOE_CONN_ST_CTX_OUTER_VLAN_FLAG_SHIFT 3 162#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_MASK 0x1 /* Indicaiton that there should be a single vlan (for UFP mode) */ 163#define PSTORM_FCOE_CONN_ST_CTX_SINGLE_VLAN_FLAG_SHIFT 4 164#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x7 165#define PSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 5 166 u8 did_2 /* DID FC address - Third byte that is sent to NW via PBF */; 167 u8 did_1 /* DID FC address - Second byte that is sent to NW via PBF */; 168 u8 did_0 /* DID FC address - First byte that is sent to NW via PBF */; 169 u8 src_mac_index; 170 __le16 rec_rr_tov_val /* REC_TOV value negotiated during PLOGI (in msec) */; 171 u8 q_relative_offset /* CQ, RQ (and CMDQ) relative offset for connection */; 172 u8 reserved1; 173}; 174 175/* 176 * The fcoe storm context of Xstorm 177 */ 178struct xstorm_fcoe_conn_st_ctx 179{ 180 u8 func_mode /* Function mode */; 181 u8 src_mac_index /* Index to the src_mac arr held in the xStorm RAM. Provided at the xStorm offload connection handler */; 182 u8 conf_version /* Advance if vntag/dcb version advance */; 183 u8 cached_wqes_avail /* Number of cached wqes available */; 184 __le16 stat_ram_addr /* Statistics ram adderss */; 185 u8 flags; 186#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_MASK 0x1 /* SQ deferred (happens when we wait for xfer wqe to complete cleanup/abts */ 187#define XSTORM_FCOE_CONN_ST_CTX_SQ_DEFERRED_SHIFT 0 188#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_MASK 0x1 /* Inner vlan flag ����� for calculating eth header size */ 189#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_SHIFT 1 190#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_MASK 0x1 /* Original vlan configuration. used when we switch from dcb enable to dcb disabled */ 191#define XSTORM_FCOE_CONN_ST_CTX_INNER_VLAN_FLAG_ORIG_SHIFT 2 192#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_MASK 0x3 193#define XSTORM_FCOE_CONN_ST_CTX_LAST_QUEUE_HANDLED_SHIFT 3 194#define XSTORM_FCOE_CONN_ST_CTX_RSRV_MASK 0x7 195#define XSTORM_FCOE_CONN_ST_CTX_RSRV_SHIFT 5 196 u8 cached_wqes_offset /* Offset of first valid cached wqe */; 197 u8 reserved2; 198 u8 eth_hdr_size /* Ethernet header size */; 199 u8 seq_id /* Sequence id */; 200 u8 max_conc_seqs /* Max concurrent sequence id */; 201 __le16 num_pages_in_pbl /* Num of pages in SQ/RESPQ/XFERQ Pbl */; 202 __le16 reserved; 203 struct regpair sq_pbl_addr /* SQ address */; 204 struct regpair sq_curr_page_addr /* SQ current page address */; 205 struct regpair sq_next_page_addr /* SQ next page address */; 206 struct regpair xferq_pbl_addr /* XFERQ address */; 207 struct regpair xferq_curr_page_addr /* XFERQ current page address */; 208 struct regpair xferq_next_page_addr /* XFERQ next page address */; 209 struct regpair respq_pbl_addr /* RESPQ address */; 210 struct regpair respq_curr_page_addr /* RESPQ current page address */; 211 struct regpair respq_next_page_addr /* RESPQ next page address */; 212 __le16 mtu /* MTU limitation */; 213 __le16 tx_max_fc_pay_len /* Max payload length according to target limitation */; 214 __le16 max_fc_payload_len /* Max payload length according to target limitation and mtu. Aligned to 4 bytes. */; 215 __le16 min_frame_size /* The minimum ETH frame size required for transmission (including ETH header, excluding ETH CRC */; 216 __le16 sq_pbl_next_index /* Next index of SQ Pbl */; 217 __le16 respq_pbl_next_index /* Next index of RESPQ Pbl */; 218 u8 fcp_cmd_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 219 u8 fcp_rsp_byte_credit /* Pre-calculated byte credit that single FCP RSP can consume. */; 220 __le16 protection_info; 221#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_MASK 0x1 /* Intend to accelerate the protection flows */ 222#define XSTORM_FCOE_CONN_ST_CTX_PROTECTION_PERF_SHIFT 0 223#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection is enough that one of them support protection) */ 224#define XSTORM_FCOE_CONN_ST_CTX_SUPPORT_PROTECTION_SHIFT 1 225#define XSTORM_FCOE_CONN_ST_CTX_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 226#define XSTORM_FCOE_CONN_ST_CTX_VALID_SHIFT 2 227#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_MASK 0x1 /* Is size of tx_max_pay_len_prot can be aligned to protection intervals. This means that pure data in each frame is 2k exactly, and protection intervals are no bigger than 2k */ 228#define XSTORM_FCOE_CONN_ST_CTX_FRAME_PROT_ALIGNED_SHIFT 3 229#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_MASK 0xF 230#define XSTORM_FCOE_CONN_ST_CTX_RESERVED3_SHIFT 4 231#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_MASK 0xFF /* Destination Pro tection data per mss (if we are not in perf mode it will be worse case). Destination is the data add/remove from the transmitted packet (as opposed to src which is data validate by the nic they might not be identical) */ 232#define XSTORM_FCOE_CONN_ST_CTX_DST_PROTECTION_PER_MSS_SHIFT 8 233 __le16 xferq_pbl_next_index /* Next index of XFERQ Pbl */; 234 __le16 page_size /* Page size (in bytes) */; 235 u8 mid_seq /* Equals 1 for Middle sequence indication, otherwise 0 */; 236 u8 fcp_xfer_byte_credit /* Pre-calculated byte credit that single FCP command can consume */; 237 u8 reserved1[2]; 238 struct fcoe_wqe cached_wqes[16] /* cached wqe (8) = 8*8*8Bytes */; 239}; 240 241struct e4_xstorm_fcoe_conn_ag_ctx 242{ 243 u8 reserved0 /* cdu_validation */; 244 u8 state /* state */; 245 u8 flags0; 246#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 247#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 248#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 249#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 250#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 251#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 252#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 253#define E4_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 254#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 255#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 256#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 257#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 258#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 259#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 260#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 261#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 262 u8 flags1; 263#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 264#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 265#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 266#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 267#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 268#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 269#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 270#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 271#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 272#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 273#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 274#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 275#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 276#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 277#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 278#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 279 u8 flags2; 280#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 281#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 282#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 283#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 284#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 285#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 286#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 287#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 288 u8 flags3; 289#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 290#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 291#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 292#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 293#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 294#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 295#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 296#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 297 u8 flags4; 298#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 299#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 300#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 301#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 302#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 303#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 304#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 305#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 306 u8 flags5; 307#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 308#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 309#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 310#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 311#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 312#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 313#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 314#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 315 u8 flags6; 316#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 317#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 318#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 319#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 320#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 321#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 322#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 323#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 324 u8 flags7; 325#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 326#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 327#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 328#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 329#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 330#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 331#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 332#define E4_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 333#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 334#define E4_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 335 u8 flags8; 336#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 337#define E4_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 338#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 339#define E4_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 340#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 341#define E4_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 342#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 343#define E4_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 344#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 345#define E4_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 346#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 347#define E4_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 348#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 349#define E4_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 350#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 351#define E4_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 352 u8 flags9; 353#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 354#define E4_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 355#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 356#define E4_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 357#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 358#define E4_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 359#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 360#define E4_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 361#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 362#define E4_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 363#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 364#define E4_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 365#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 366#define E4_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 367#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 368#define E4_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 369 u8 flags10; 370#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 371#define E4_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 372#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 373#define E4_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 374#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 375#define E4_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 376#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 377#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 378#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 379#define E4_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 380#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 381#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 382#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 383#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 384#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 385#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 386 u8 flags11; 387#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 388#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 389#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 390#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 391#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 392#define E4_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 393#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 394#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 395#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 396#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 397#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 398#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 399#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 400#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 401#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 402#define E4_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 403 u8 flags12; 404#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 405#define E4_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 406#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 407#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 408#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 409#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 410#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 411#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 412#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 413#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 414#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 415#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 416#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 417#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 418#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 419#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 420 u8 flags13; 421#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 422#define E4_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 423#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 424#define E4_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 425#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 426#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 427#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 428#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 429#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 430#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 431#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 432#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 433#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 434#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 435#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 436#define E4_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 437 u8 flags14; 438#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 439#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 440#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 441#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 442#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 443#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 444#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 445#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 446#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 447#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 448#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 449#define E4_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 450#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 451#define E4_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 452 u8 byte2 /* byte2 */; 453 __le16 physical_q0 /* physical_q0 */; 454 __le16 word1 /* physical_q1 */; 455 __le16 word2 /* physical_q2 */; 456 __le16 sq_cons /* word3 */; 457 __le16 sq_prod /* word4 */; 458 __le16 xferq_prod /* word5 */; 459 __le16 xferq_cons /* conn_dpi */; 460 u8 byte3 /* byte3 */; 461 u8 byte4 /* byte4 */; 462 u8 byte5 /* byte5 */; 463 u8 byte6 /* byte6 */; 464 __le32 remain_io /* reg0 */; 465 __le32 reg1 /* reg1 */; 466 __le32 reg2 /* reg2 */; 467 __le32 reg3 /* reg3 */; 468 __le32 reg4 /* reg4 */; 469 __le32 reg5 /* cf_array0 */; 470 __le32 reg6 /* cf_array1 */; 471 __le16 respq_prod /* word7 */; 472 __le16 respq_cons /* word8 */; 473 __le16 word9 /* word9 */; 474 __le16 word10 /* word10 */; 475 __le32 reg7 /* reg7 */; 476 __le32 reg8 /* reg8 */; 477}; 478 479/* 480 * The fcoe storm context of Ustorm 481 */ 482struct ustorm_fcoe_conn_st_ctx 483{ 484 struct regpair respq_pbl_addr /* RespQ Pbl base address */; 485 __le16 num_pages_in_pbl /* Number of RespQ pbl pages (both have same wqe size) */; 486 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 487 u8 log_page_size; 488 __le16 respq_prod /* RespQ producer */; 489 u8 reserved[2]; 490}; 491 492struct e4_tstorm_fcoe_conn_ag_ctx 493{ 494 u8 reserved0 /* cdu_validation */; 495 u8 state /* state */; 496 u8 flags0; 497#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 498#define E4_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 499#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 500#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 501#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 502#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 503#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 504#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 505#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 506#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 507#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 508#define E4_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 509#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 510#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 511 u8 flags1; 512#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 513#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 514#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 515#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 516#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 517#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 518#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 519#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 520 u8 flags2; 521#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 522#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 523#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 524#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 525#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 526#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 527#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 528#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 529 u8 flags3; 530#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 531#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 532#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 533#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 534#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 535#define E4_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 536#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 537#define E4_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 538#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 539#define E4_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 540#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 541#define E4_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 542 u8 flags4; 543#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 544#define E4_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 545#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 546#define E4_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 547#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 548#define E4_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 549#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 550#define E4_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 551#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 552#define E4_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 553#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 554#define E4_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 555#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 556#define E4_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 557#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 558#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 559 u8 flags5; 560#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 561#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 562#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 563#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 564#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 565#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 566#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 567#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 568#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 569#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 570#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 571#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 572#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 573#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 574#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 575#define E4_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 576 __le32 reg0 /* reg0 */; 577 __le32 reg1 /* reg1 */; 578}; 579 580struct e4_ustorm_fcoe_conn_ag_ctx 581{ 582 u8 byte0 /* cdu_validation */; 583 u8 byte1 /* state */; 584 u8 flags0; 585#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 586#define E4_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 587#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 588#define E4_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 589#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 590#define E4_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 591#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 592#define E4_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 593#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 594#define E4_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 595 u8 flags1; 596#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 597#define E4_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 598#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 599#define E4_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 600#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 601#define E4_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 602#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 603#define E4_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 604 u8 flags2; 605#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 606#define E4_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 607#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 608#define E4_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 609#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 610#define E4_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 611#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 612#define E4_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 613#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 614#define E4_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 615#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 616#define E4_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 617#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 618#define E4_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 619#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 620#define E4_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 621 u8 flags3; 622#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 623#define E4_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 624#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 625#define E4_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 626#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 627#define E4_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 628#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 629#define E4_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 630#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 631#define E4_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 632#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 633#define E4_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 634#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 635#define E4_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 636#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 637#define E4_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 638 u8 byte2 /* byte2 */; 639 u8 byte3 /* byte3 */; 640 __le16 word0 /* conn_dpi */; 641 __le16 word1 /* word1 */; 642 __le32 reg0 /* reg0 */; 643 __le32 reg1 /* reg1 */; 644 __le32 reg2 /* reg2 */; 645 __le32 reg3 /* reg3 */; 646 __le16 word2 /* word2 */; 647 __le16 word3 /* word3 */; 648}; 649 650/* 651 * The fcoe storm context of Tstorm 652 */ 653struct tstorm_fcoe_conn_st_ctx 654{ 655 __le16 stat_ram_addr /* Statistics ram adderss */; 656 __le16 rx_max_fc_payload_len /* Max rx fc payload length. provided in ramrod */; 657 __le16 e_d_tov_val /* E_D_TOV value negotiated during PLOGI (in msec) */; 658 u8 flags; 659#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_MASK 0x1 /* Does the target support increment sequence counter */ 660#define TSTORM_FCOE_CONN_ST_CTX_INC_SEQ_CNT_SHIFT 0 661#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_MASK 0x1 /* Does the connection support CONF REQ transmission */ 662#define TSTORM_FCOE_CONN_ST_CTX_SUPPORT_CONF_SHIFT 1 663#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_MASK 0x3F /* Default queue index the connection associated to */ 664#define TSTORM_FCOE_CONN_ST_CTX_DEF_Q_IDX_SHIFT 2 665 u8 timers_cleanup_invocation_cnt /* This variable is incremented each time the tStorm handler for timers cleanup is invoked within the same timers cleanup flow */; 666 __le32 reserved1[2]; 667 __le32 dstMacAddressBytes0To3 /* destination MAC address: Bytes 0-3. */; 668 __le16 dstMacAddressBytes4To5 /* destination MAC address: Bytes 4-5. */; 669 __le16 ramrodEcho /* Saved ramrod echo - needed for 2nd round of terminate_conn (flush Q0) */; 670 u8 flags1; 671#define TSTORM_FCOE_CONN_ST_CTX_MODE_MASK 0x3 /* Indicate the mode of the connection: Target or Initiator, use enum fcoe_mode_type */ 672#define TSTORM_FCOE_CONN_ST_CTX_MODE_SHIFT 0 673#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_MASK 0x3F 674#define TSTORM_FCOE_CONN_ST_CTX_RESERVED_SHIFT 2 675 u8 cq_relative_offset /* CQ relative offset for connection */; 676 u8 cmdq_relative_offset /* CmdQ relative offset for connection */; 677 u8 bdq_resource_id /* The BDQ resource ID to which this function is mapped */; 678 u8 reserved0[4] /* Alignment to 128b */; 679}; 680 681struct e4_mstorm_fcoe_conn_ag_ctx 682{ 683 u8 byte0 /* cdu_validation */; 684 u8 byte1 /* state */; 685 u8 flags0; 686#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 687#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 688#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 689#define E4_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 690#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 691#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 692#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 693#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 694#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 695#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 696 u8 flags1; 697#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 698#define E4_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 699#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 700#define E4_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 701#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 702#define E4_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 703#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 704#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 705#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 706#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 707#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 708#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 709#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 710#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 711#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 712#define E4_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 713 __le16 word0 /* word0 */; 714 __le16 word1 /* word1 */; 715 __le32 reg0 /* reg0 */; 716 __le32 reg1 /* reg1 */; 717}; 718 719/* 720 * Fast path part of the fcoe storm context of Mstorm 721 */ 722struct fcoe_mstorm_fcoe_conn_st_ctx_fp 723{ 724 __le16 xfer_prod /* XferQ producer */; 725 u8 num_cqs /* Number of CQs per function (internal to FW) */; 726 u8 reserved1; 727 u8 protection_info; 728#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_MASK 0x1 /* Does this connection support protection (if couple of GOS share this connection it is enough that one of them support protection) */ 729#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_SUPPORT_PROTECTION_SHIFT 0 730#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_MASK 0x1 /* Are we in protection perf mode (there is only one protection mode for this connection and we manage to create mss that contain fixed amount of protection segment and we are only restrict by the target limitation and not line mss ����� this is critical since if line mss restrict us we can��������t rely on this size ����� it depends on vlan num) */ 731#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_VALID_SHIFT 1 732#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_MASK 0x3F 733#define FCOE_MSTORM_FCOE_CONN_ST_CTX_FP_RESERVED0_SHIFT 2 734 u8 q_relative_offset /* CQ, RQ and CMDQ relative offset for connection */; 735 u8 reserved2[2]; 736}; 737 738/* 739 * Non fast path part of the fcoe storm context of Mstorm 740 */ 741struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp 742{ 743 __le16 conn_id /* Driver connection ID. To be used by slowpaths to fill EQ placement params */; 744 __le16 stat_ram_addr /* Statistics ram adderss */; 745 __le16 num_pages_in_pbl /* Number of XferQ/RespQ pbl pages (both have same wqe size) */; 746 u8 ptu_log_page_size /* 0-4K, 1-8K, 2-16K, 3-32K... */; 747 u8 log_page_size; 748 __le16 unsolicited_cq_count /* Counts number of CQs done due to unsolicited packets on this connection */; 749 __le16 cmdq_count /* Counts number of CMDQs done on this connection */; 750 u8 bdq_resource_id /* BDQ Resource ID */; 751 u8 reserved0[3] /* Padding bytes for 2nd RegPair */; 752 struct regpair xferq_pbl_addr /* XferQ Pbl base address */; 753 struct regpair reserved1; 754 struct regpair reserved2[3]; 755}; 756 757/* 758 * The fcoe storm context of Mstorm 759 */ 760struct mstorm_fcoe_conn_st_ctx 761{ 762 struct fcoe_mstorm_fcoe_conn_st_ctx_fp fp /* Fast path part of the fcoe storm context of Mstorm */; 763 struct fcoe_mstorm_fcoe_conn_st_ctx_non_fp non_fp /* Non fast path part of the fcoe storm context of Mstorm */; 764}; 765 766/* 767 * fcoe connection context 768 */ 769struct e4_fcoe_conn_context 770{ 771 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 772 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 773 struct regpair pstorm_st_padding[2] /* padding */; 774 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 775 struct e4_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 776 struct regpair xstorm_ag_padding[6] /* padding */; 777 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 778 struct regpair ustorm_st_padding[2] /* padding */; 779 struct e4_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 780 struct regpair tstorm_ag_padding[2] /* padding */; 781 struct timers_context timer_context /* timer context */; 782 struct e4_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 783 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 784 struct e4_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 785 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 786}; 787 788 789struct e5_xstorm_fcoe_conn_ag_ctx 790{ 791 u8 reserved0 /* cdu_validation */; 792 u8 state_and_core_id /* state_and_core_id */; 793 u8 flags0; 794#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 795#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 796#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 797#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED1_SHIFT 1 798#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 799#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED2_SHIFT 2 800#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 801#define E5_XSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 802#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 803#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED3_SHIFT 4 804#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 805#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED4_SHIFT 5 806#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 807#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED5_SHIFT 6 808#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 809#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED6_SHIFT 7 810 u8 flags1; 811#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 812#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED7_SHIFT 0 813#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 814#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED8_SHIFT 1 815#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 816#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED9_SHIFT 2 817#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 818#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT11_SHIFT 3 819#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 820#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT12_SHIFT 4 821#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 822#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT13_SHIFT 5 823#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_MASK 0x1 /* bit14 */ 824#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT14_SHIFT 6 825#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_MASK 0x1 /* bit15 */ 826#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT15_SHIFT 7 827 u8 flags2; 828#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 829#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 0 830#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 831#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 2 832#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 833#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 4 834#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 835#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 6 836 u8 flags3; 837#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 838#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 0 839#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 840#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 2 841#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 842#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 4 843#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 844#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 6 845 u8 flags4; 846#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 847#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 0 848#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 849#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 2 850#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 851#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 4 852#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 853#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11_SHIFT 6 854 u8 flags5; 855#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 856#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12_SHIFT 0 857#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 858#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13_SHIFT 2 859#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 860#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14_SHIFT 4 861#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 862#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15_SHIFT 6 863 u8 flags6; 864#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_MASK 0x3 /* cf16 */ 865#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16_SHIFT 0 866#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 867#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17_SHIFT 2 868#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_MASK 0x3 /* cf18 */ 869#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18_SHIFT 4 870#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf19 */ 871#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_SHIFT 6 872 u8 flags7; 873#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 874#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 875#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 876#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED10_SHIFT 2 877#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 878#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 879#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 880#define E5_XSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 6 881#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 882#define E5_XSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 7 883 u8 flags8; 884#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 885#define E5_XSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 0 886#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 887#define E5_XSTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 1 888#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 889#define E5_XSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 2 890#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 891#define E5_XSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 3 892#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 893#define E5_XSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 4 894#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 895#define E5_XSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 5 896#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 897#define E5_XSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 6 898#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 899#define E5_XSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 7 900 u8 flags9; 901#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 902#define E5_XSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 0 903#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 904#define E5_XSTORM_FCOE_CONN_AG_CTX_CF11EN_SHIFT 1 905#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 906#define E5_XSTORM_FCOE_CONN_AG_CTX_CF12EN_SHIFT 2 907#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 908#define E5_XSTORM_FCOE_CONN_AG_CTX_CF13EN_SHIFT 3 909#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 910#define E5_XSTORM_FCOE_CONN_AG_CTX_CF14EN_SHIFT 4 911#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 912#define E5_XSTORM_FCOE_CONN_AG_CTX_CF15EN_SHIFT 5 913#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_MASK 0x1 /* cf16en */ 914#define E5_XSTORM_FCOE_CONN_AG_CTX_CF16EN_SHIFT 6 915#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 916#define E5_XSTORM_FCOE_CONN_AG_CTX_CF17EN_SHIFT 7 917 u8 flags10; 918#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_MASK 0x1 /* cf18en */ 919#define E5_XSTORM_FCOE_CONN_AG_CTX_CF18EN_SHIFT 0 920#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf19en */ 921#define E5_XSTORM_FCOE_CONN_AG_CTX_DQ_CF_EN_SHIFT 1 922#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 923#define E5_XSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 924#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 925#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED11_SHIFT 3 926#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 927#define E5_XSTORM_FCOE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 928#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 929#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23EN_SHIFT 5 930#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 931#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED12_SHIFT 6 932#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 933#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED13_SHIFT 7 934 u8 flags11; 935#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 936#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED14_SHIFT 0 937#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 938#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED15_SHIFT 1 939#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_MASK 0x1 /* rule4en */ 940#define E5_XSTORM_FCOE_CONN_AG_CTX_RESERVED16_SHIFT 2 941#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 942#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 3 943#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 944#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 4 945#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 946#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 5 947#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 948#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 949#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_MASK 0x1 /* rule9en */ 950#define E5_XSTORM_FCOE_CONN_AG_CTX_XFERQ_DECISION_EN_SHIFT 7 951 u8 flags12; 952#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_MASK 0x1 /* rule10en */ 953#define E5_XSTORM_FCOE_CONN_AG_CTX_SQ_DECISION_EN_SHIFT 0 954#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 955#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE11EN_SHIFT 1 956#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 957#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 958#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 959#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 960#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 961#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE14EN_SHIFT 4 962#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 963#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE15EN_SHIFT 5 964#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 965#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE16EN_SHIFT 6 966#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 967#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE17EN_SHIFT 7 968 u8 flags13; 969#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_MASK 0x1 /* rule18en */ 970#define E5_XSTORM_FCOE_CONN_AG_CTX_RESPQ_DECISION_EN_SHIFT 0 971#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 972#define E5_XSTORM_FCOE_CONN_AG_CTX_RULE19EN_SHIFT 1 973#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 974#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 975#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 976#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 977#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 978#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 979#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 980#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 981#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 982#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 983#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 984#define E5_XSTORM_FCOE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 985 u8 flags14; 986#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 987#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT16_SHIFT 0 988#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 989#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT17_SHIFT 1 990#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 991#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT18_SHIFT 2 992#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 993#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT19_SHIFT 3 994#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 995#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT20_SHIFT 4 996#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 997#define E5_XSTORM_FCOE_CONN_AG_CTX_BIT21_SHIFT 5 998#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 999#define E5_XSTORM_FCOE_CONN_AG_CTX_CF23_SHIFT 6 1000 u8 byte2 /* byte2 */; 1001 __le16 physical_q0 /* physical_q0 */; 1002 __le16 word1 /* physical_q1 */; 1003 __le16 word2 /* physical_q2 */; 1004 __le16 sq_cons /* word3 */; 1005 __le16 sq_prod /* word4 */; 1006 __le16 xferq_prod /* word5 */; 1007 __le16 xferq_cons /* conn_dpi */; 1008 u8 byte3 /* byte3 */; 1009 u8 byte4 /* byte4 */; 1010 u8 byte5 /* byte5 */; 1011 u8 byte6 /* byte6 */; 1012 __le32 remain_io /* reg0 */; 1013 __le32 reg1 /* reg1 */; 1014 __le32 reg2 /* reg2 */; 1015 __le32 reg3 /* reg3 */; 1016 __le32 reg4 /* reg4 */; 1017 __le32 reg5 /* cf_array0 */; 1018 __le32 reg6 /* cf_array1 */; 1019 u8 flags15; 1020#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1021#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1022#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1023#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1024#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1025#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1026#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1027#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1028#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1029#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1030#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1031#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1032#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1033#define E5_XSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1034 u8 byte7 /* byte7 */; 1035 __le16 respq_prod /* word7 */; 1036 __le16 respq_cons /* word8 */; 1037 __le16 word9 /* word9 */; 1038 __le16 word10 /* word10 */; 1039 __le16 word11 /* word11 */; 1040 __le32 reg7 /* reg7 */; 1041}; 1042 1043struct e5_tstorm_fcoe_conn_ag_ctx 1044{ 1045 u8 reserved0 /* cdu_validation */; 1046 u8 state_and_core_id /* state_and_core_id */; 1047 u8 flags0; 1048#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 1049#define E5_TSTORM_FCOE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 1050#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1051#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1052#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1053#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT2_SHIFT 2 1054#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1055#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT3_SHIFT 3 1056#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1057#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT4_SHIFT 4 1058#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1059#define E5_TSTORM_FCOE_CONN_AG_CTX_BIT5_SHIFT 5 1060#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_MASK 0x3 /* timer0cf */ 1061#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_SHIFT 6 1062 u8 flags1; 1063#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_MASK 0x3 /* timer1cf */ 1064#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_SHIFT 0 1065#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1066#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 2 1067#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_MASK 0x3 /* timer_stop_all */ 1068#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_SHIFT 4 1069#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1070#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 6 1071 u8 flags2; 1072#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1073#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 0 1074#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1075#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 2 1076#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1077#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7_SHIFT 4 1078#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1079#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8_SHIFT 6 1080 u8 flags3; 1081#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1082#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9_SHIFT 0 1083#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1084#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10_SHIFT 2 1085#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_MASK 0x1 /* cf0en */ 1086#define E5_TSTORM_FCOE_CONN_AG_CTX_DUMMY_TIMER_CF_EN_SHIFT 4 1087#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_MASK 0x1 /* cf1en */ 1088#define E5_TSTORM_FCOE_CONN_AG_CTX_FLUSH_Q0_CF_EN_SHIFT 5 1089#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1090#define E5_TSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 6 1091#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_MASK 0x1 /* cf3en */ 1092#define E5_TSTORM_FCOE_CONN_AG_CTX_TIMER_STOP_ALL_CF_EN_SHIFT 7 1093 u8 flags4; 1094#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1095#define E5_TSTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 0 1096#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1097#define E5_TSTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 1 1098#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1099#define E5_TSTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 2 1100#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1101#define E5_TSTORM_FCOE_CONN_AG_CTX_CF7EN_SHIFT 3 1102#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1103#define E5_TSTORM_FCOE_CONN_AG_CTX_CF8EN_SHIFT 4 1104#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1105#define E5_TSTORM_FCOE_CONN_AG_CTX_CF9EN_SHIFT 5 1106#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1107#define E5_TSTORM_FCOE_CONN_AG_CTX_CF10EN_SHIFT 6 1108#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1109#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1110 u8 flags5; 1111#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1112#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1113#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1114#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1115#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1116#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1117#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1118#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1119#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1120#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1121#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1122#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1123#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1124#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1125#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1126#define E5_TSTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1127 u8 flags6; 1128#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1129#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1130#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1131#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1132#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1133#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1134#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1135#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1136#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1137#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1138#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1139#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1140#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1141#define E5_TSTORM_FCOE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1142 u8 byte2 /* byte2 */; 1143 __le16 word0 /* word0 */; 1144 __le32 reg0 /* reg0 */; 1145}; 1146 1147struct e5_ustorm_fcoe_conn_ag_ctx 1148{ 1149 u8 byte0 /* cdu_validation */; 1150 u8 byte1 /* state_and_core_id */; 1151 u8 flags0; 1152#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1153#define E5_USTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1154#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1155#define E5_USTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1156#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1157#define E5_USTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1158#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1159#define E5_USTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1160#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1161#define E5_USTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1162 u8 flags1; 1163#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1164#define E5_USTORM_FCOE_CONN_AG_CTX_CF3_SHIFT 0 1165#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1166#define E5_USTORM_FCOE_CONN_AG_CTX_CF4_SHIFT 2 1167#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1168#define E5_USTORM_FCOE_CONN_AG_CTX_CF5_SHIFT 4 1169#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1170#define E5_USTORM_FCOE_CONN_AG_CTX_CF6_SHIFT 6 1171 u8 flags2; 1172#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1173#define E5_USTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1174#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1175#define E5_USTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1176#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1177#define E5_USTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1178#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1179#define E5_USTORM_FCOE_CONN_AG_CTX_CF3EN_SHIFT 3 1180#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1181#define E5_USTORM_FCOE_CONN_AG_CTX_CF4EN_SHIFT 4 1182#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1183#define E5_USTORM_FCOE_CONN_AG_CTX_CF5EN_SHIFT 5 1184#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1185#define E5_USTORM_FCOE_CONN_AG_CTX_CF6EN_SHIFT 6 1186#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1187#define E5_USTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 7 1188 u8 flags3; 1189#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1190#define E5_USTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 0 1191#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1192#define E5_USTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 1 1193#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1194#define E5_USTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 2 1195#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1196#define E5_USTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 3 1197#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1198#define E5_USTORM_FCOE_CONN_AG_CTX_RULE5EN_SHIFT 4 1199#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1200#define E5_USTORM_FCOE_CONN_AG_CTX_RULE6EN_SHIFT 5 1201#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1202#define E5_USTORM_FCOE_CONN_AG_CTX_RULE7EN_SHIFT 6 1203#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1204#define E5_USTORM_FCOE_CONN_AG_CTX_RULE8EN_SHIFT 7 1205 u8 flags4; 1206#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1207#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1208#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1209#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1210#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1211#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1212#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1213#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1214#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1215#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1216#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1217#define E5_USTORM_FCOE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1218 u8 byte2 /* byte2 */; 1219 __le16 word0 /* conn_dpi */; 1220 __le16 word1 /* word1 */; 1221 __le32 reg0 /* reg0 */; 1222 __le32 reg1 /* reg1 */; 1223 __le32 reg2 /* reg2 */; 1224 __le32 reg3 /* reg3 */; 1225 __le16 word2 /* word2 */; 1226 __le16 word3 /* word3 */; 1227}; 1228 1229struct e5_mstorm_fcoe_conn_ag_ctx 1230{ 1231 u8 byte0 /* cdu_validation */; 1232 u8 byte1 /* state_and_core_id */; 1233 u8 flags0; 1234#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1235#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1236#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1237#define E5_MSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1238#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1239#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1240#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1241#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1242#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1243#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1244 u8 flags1; 1245#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1246#define E5_MSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1247#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1248#define E5_MSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1249#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1250#define E5_MSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1251#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1252#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1253#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1254#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1255#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1256#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1257#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1258#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1259#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1260#define E5_MSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1261 __le16 word0 /* word0 */; 1262 __le16 word1 /* word1 */; 1263 __le32 reg0 /* reg0 */; 1264 __le32 reg1 /* reg1 */; 1265}; 1266 1267/* 1268 * fcoe connection context 1269 */ 1270struct e5_fcoe_conn_context 1271{ 1272 struct ystorm_fcoe_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1273 struct pstorm_fcoe_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1274 struct regpair pstorm_st_padding[2] /* padding */; 1275 struct xstorm_fcoe_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1276 struct e5_xstorm_fcoe_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1277 struct ustorm_fcoe_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1278 struct regpair ustorm_st_padding[2] /* padding */; 1279 struct e5_tstorm_fcoe_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1280 struct regpair tstorm_ag_padding[2] /* padding */; 1281 struct timers_context timer_context /* timer context */; 1282 struct e5_ustorm_fcoe_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1283 struct tstorm_fcoe_conn_st_ctx tstorm_st_context /* tstorm storm context */; 1284 struct e5_mstorm_fcoe_conn_ag_ctx mstorm_ag_context /* mstorm aggregative context */; 1285 struct mstorm_fcoe_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1286}; 1287 1288 1289/* 1290 * FCoE connection offload params passed by driver to FW in FCoE offload ramrod 1291 */ 1292struct fcoe_conn_offload_ramrod_params 1293{ 1294 struct fcoe_conn_offload_ramrod_data offload_ramrod_data; 1295}; 1296 1297 1298/* 1299 * FCoE connection terminate params passed by driver to FW in FCoE terminate conn ramrod 1300 */ 1301struct fcoe_conn_terminate_ramrod_params 1302{ 1303 struct fcoe_conn_terminate_ramrod_data terminate_ramrod_data; 1304}; 1305 1306 1307/* 1308 * FCoE event type 1309 */ 1310enum fcoe_event_type 1311{ 1312 FCOE_EVENT_INIT_FUNC /* Slowpath completion on INIT_FUNC ramrod */, 1313 FCOE_EVENT_DESTROY_FUNC /* Slowpath completion on DESTROY_FUNC ramrod */, 1314 FCOE_EVENT_STAT_FUNC /* Slowpath completion on STAT_FUNC ramrod */, 1315 FCOE_EVENT_OFFLOAD_CONN /* Slowpath completion on OFFLOAD_CONN ramrod */, 1316 FCOE_EVENT_TERMINATE_CONN /* Slowpath completion on TERMINATE_CONN ramrod */, 1317 FCOE_EVENT_ERROR /* Error event */, 1318 MAX_FCOE_EVENT_TYPE 1319}; 1320 1321 1322/* 1323 * FCoE init params passed by driver to FW in FCoE init ramrod 1324 */ 1325struct fcoe_init_ramrod_params 1326{ 1327 struct fcoe_init_func_ramrod_data init_ramrod_data; 1328}; 1329 1330 1331 1332 1333/* 1334 * FCoE ramrod Command IDs 1335 */ 1336enum fcoe_ramrod_cmd_id 1337{ 1338 FCOE_RAMROD_CMD_ID_INIT_FUNC /* FCoE function init ramrod */, 1339 FCOE_RAMROD_CMD_ID_DESTROY_FUNC /* FCoE function destroy ramrod */, 1340 FCOE_RAMROD_CMD_ID_STAT_FUNC /* FCoE statistics ramrod */, 1341 FCOE_RAMROD_CMD_ID_OFFLOAD_CONN /* FCoE connection offload ramrod */, 1342 FCOE_RAMROD_CMD_ID_TERMINATE_CONN /* FCoE connection offload ramrod. Command ID known only to FW and VBD */, 1343 MAX_FCOE_RAMROD_CMD_ID 1344}; 1345 1346 1347/* 1348 * FCoE statistics params buffer passed by driver to FW in FCoE statistics ramrod 1349 */ 1350struct fcoe_stat_ramrod_params 1351{ 1352 struct fcoe_stat_ramrod_data stat_ramrod_data; 1353}; 1354 1355 1356 1357 1358 1359 1360 1361 1362 1363 1364 1365 1366 1367 1368 1369 1370struct e4_ystorm_fcoe_conn_ag_ctx 1371{ 1372 u8 byte0 /* cdu_validation */; 1373 u8 byte1 /* state */; 1374 u8 flags0; 1375#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1376#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1377#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1378#define E4_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1379#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1380#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1381#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1382#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1383#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1384#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1385 u8 flags1; 1386#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1387#define E4_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1388#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1389#define E4_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1390#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1391#define E4_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1392#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1393#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1394#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1395#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1396#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1397#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1398#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1399#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1400#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1401#define E4_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1402 u8 byte2 /* byte2 */; 1403 u8 byte3 /* byte3 */; 1404 __le16 word0 /* word0 */; 1405 __le32 reg0 /* reg0 */; 1406 __le32 reg1 /* reg1 */; 1407 __le16 word1 /* word1 */; 1408 __le16 word2 /* word2 */; 1409 __le16 word3 /* word3 */; 1410 __le16 word4 /* word4 */; 1411 __le32 reg2 /* reg2 */; 1412 __le32 reg3 /* reg3 */; 1413}; 1414 1415 1416 1417 1418 1419 1420struct e5_ystorm_fcoe_conn_ag_ctx 1421{ 1422 u8 byte0 /* cdu_validation */; 1423 u8 byte1 /* state_and_core_id */; 1424 u8 flags0; 1425#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1426#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT0_SHIFT 0 1427#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1428#define E5_YSTORM_FCOE_CONN_AG_CTX_BIT1_SHIFT 1 1429#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 1430#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0_SHIFT 2 1431#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 1432#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1_SHIFT 4 1433#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 1434#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2_SHIFT 6 1435 u8 flags1; 1436#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1437#define E5_YSTORM_FCOE_CONN_AG_CTX_CF0EN_SHIFT 0 1438#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1439#define E5_YSTORM_FCOE_CONN_AG_CTX_CF1EN_SHIFT 1 1440#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1441#define E5_YSTORM_FCOE_CONN_AG_CTX_CF2EN_SHIFT 2 1442#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1443#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE0EN_SHIFT 3 1444#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1445#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE1EN_SHIFT 4 1446#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1447#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE2EN_SHIFT 5 1448#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1449#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE3EN_SHIFT 6 1450#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1451#define E5_YSTORM_FCOE_CONN_AG_CTX_RULE4EN_SHIFT 7 1452 u8 byte2 /* byte2 */; 1453 u8 byte3 /* byte3 */; 1454 __le16 word0 /* word0 */; 1455 __le32 reg0 /* reg0 */; 1456 __le32 reg1 /* reg1 */; 1457 __le16 word1 /* word1 */; 1458 __le16 word2 /* word2 */; 1459 __le16 word3 /* word3 */; 1460 __le16 word4 /* word4 */; 1461 __le32 reg2 /* reg2 */; 1462 __le32 reg3 /* reg3 */; 1463}; 1464 1465#endif /* __ECORE_HSI_FCOE__ */ 1466