1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hsi_debug_tools.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs#ifndef __ECORE_HSI_DEBUG_TOOLS__ 32316485Sdavidcs#define __ECORE_HSI_DEBUG_TOOLS__ 33316485Sdavidcs/****************************************/ 34316485Sdavidcs/* Debug Tools HSI constants and macros */ 35316485Sdavidcs/****************************************/ 36316485Sdavidcs 37316485Sdavidcs 38316485Sdavidcsenum block_addr 39316485Sdavidcs{ 40316485Sdavidcs GRCBASE_GRC = 0x50000, 41316485Sdavidcs GRCBASE_MISCS = 0x9000, 42316485Sdavidcs GRCBASE_MISC = 0x8000, 43316485Sdavidcs GRCBASE_DBU = 0xa000, 44316485Sdavidcs GRCBASE_PGLUE_B = 0x2a8000, 45316485Sdavidcs GRCBASE_CNIG = 0x218000, 46316485Sdavidcs GRCBASE_CPMU = 0x30000, 47316485Sdavidcs GRCBASE_NCSI = 0x40000, 48316485Sdavidcs GRCBASE_OPTE = 0x53000, 49316485Sdavidcs GRCBASE_BMB = 0x540000, 50316485Sdavidcs GRCBASE_PCIE = 0x54000, 51316485Sdavidcs GRCBASE_MCP = 0xe00000, 52316485Sdavidcs GRCBASE_MCP2 = 0x52000, 53316485Sdavidcs GRCBASE_PSWHST = 0x2a0000, 54316485Sdavidcs GRCBASE_PSWHST2 = 0x29e000, 55316485Sdavidcs GRCBASE_PSWRD = 0x29c000, 56316485Sdavidcs GRCBASE_PSWRD2 = 0x29d000, 57316485Sdavidcs GRCBASE_PSWWR = 0x29a000, 58316485Sdavidcs GRCBASE_PSWWR2 = 0x29b000, 59316485Sdavidcs GRCBASE_PSWRQ = 0x280000, 60316485Sdavidcs GRCBASE_PSWRQ2 = 0x240000, 61316485Sdavidcs GRCBASE_PGLCS = 0x0, 62316485Sdavidcs GRCBASE_DMAE = 0xc000, 63316485Sdavidcs GRCBASE_PTU = 0x560000, 64316485Sdavidcs GRCBASE_TCM = 0x1180000, 65316485Sdavidcs GRCBASE_MCM = 0x1200000, 66316485Sdavidcs GRCBASE_UCM = 0x1280000, 67316485Sdavidcs GRCBASE_XCM = 0x1000000, 68316485Sdavidcs GRCBASE_YCM = 0x1080000, 69316485Sdavidcs GRCBASE_PCM = 0x1100000, 70316485Sdavidcs GRCBASE_QM = 0x2f0000, 71316485Sdavidcs GRCBASE_TM = 0x2c0000, 72316485Sdavidcs GRCBASE_DORQ = 0x100000, 73316485Sdavidcs GRCBASE_BRB = 0x340000, 74316485Sdavidcs GRCBASE_SRC = 0x238000, 75316485Sdavidcs GRCBASE_PRS = 0x1f0000, 76316485Sdavidcs GRCBASE_TSDM = 0xfb0000, 77316485Sdavidcs GRCBASE_MSDM = 0xfc0000, 78316485Sdavidcs GRCBASE_USDM = 0xfd0000, 79316485Sdavidcs GRCBASE_XSDM = 0xf80000, 80316485Sdavidcs GRCBASE_YSDM = 0xf90000, 81316485Sdavidcs GRCBASE_PSDM = 0xfa0000, 82316485Sdavidcs GRCBASE_TSEM = 0x1700000, 83316485Sdavidcs GRCBASE_MSEM = 0x1800000, 84316485Sdavidcs GRCBASE_USEM = 0x1900000, 85316485Sdavidcs GRCBASE_XSEM = 0x1400000, 86316485Sdavidcs GRCBASE_YSEM = 0x1500000, 87316485Sdavidcs GRCBASE_PSEM = 0x1600000, 88316485Sdavidcs GRCBASE_RSS = 0x238800, 89316485Sdavidcs GRCBASE_TMLD = 0x4d0000, 90316485Sdavidcs GRCBASE_MULD = 0x4e0000, 91316485Sdavidcs GRCBASE_YULD = 0x4c8000, 92316485Sdavidcs GRCBASE_XYLD = 0x4c0000, 93320162Sdavidcs GRCBASE_PTLD = 0x5a0000, 94320162Sdavidcs GRCBASE_YPLD = 0x5c0000, 95316485Sdavidcs GRCBASE_PRM = 0x230000, 96316485Sdavidcs GRCBASE_PBF_PB1 = 0xda0000, 97316485Sdavidcs GRCBASE_PBF_PB2 = 0xda4000, 98316485Sdavidcs GRCBASE_RPB = 0x23c000, 99316485Sdavidcs GRCBASE_BTB = 0xdb0000, 100316485Sdavidcs GRCBASE_PBF = 0xd80000, 101316485Sdavidcs GRCBASE_RDIF = 0x300000, 102316485Sdavidcs GRCBASE_TDIF = 0x310000, 103316485Sdavidcs GRCBASE_CDU = 0x580000, 104316485Sdavidcs GRCBASE_CCFC = 0x2e0000, 105316485Sdavidcs GRCBASE_TCFC = 0x2d0000, 106316485Sdavidcs GRCBASE_IGU = 0x180000, 107316485Sdavidcs GRCBASE_CAU = 0x1c0000, 108316485Sdavidcs GRCBASE_RGFS = 0xf00000, 109316485Sdavidcs GRCBASE_RGSRC = 0x320000, 110316485Sdavidcs GRCBASE_TGFS = 0xd00000, 111316485Sdavidcs GRCBASE_TGSRC = 0x322000, 112316485Sdavidcs GRCBASE_UMAC = 0x51000, 113316485Sdavidcs GRCBASE_XMAC = 0x210000, 114316485Sdavidcs GRCBASE_DBG = 0x10000, 115316485Sdavidcs GRCBASE_NIG = 0x500000, 116316485Sdavidcs GRCBASE_WOL = 0x600000, 117316485Sdavidcs GRCBASE_BMBN = 0x610000, 118316485Sdavidcs GRCBASE_IPC = 0x20000, 119316485Sdavidcs GRCBASE_NWM = 0x800000, 120316485Sdavidcs GRCBASE_NWS = 0x700000, 121316485Sdavidcs GRCBASE_MS = 0x6a0000, 122316485Sdavidcs GRCBASE_PHY_PCIE = 0x620000, 123316485Sdavidcs GRCBASE_LED = 0x6b8000, 124316485Sdavidcs GRCBASE_AVS_WRAP = 0x6b0000, 125337519Sdavidcs GRCBASE_PXPREQBUS = 0x56000, 126316485Sdavidcs GRCBASE_MISC_AEU = 0x8000, 127316485Sdavidcs GRCBASE_BAR0_MAP = 0x1c00000, 128316485Sdavidcs MAX_BLOCK_ADDR 129316485Sdavidcs}; 130316485Sdavidcs 131316485Sdavidcs 132316485Sdavidcsenum block_id 133316485Sdavidcs{ 134316485Sdavidcs BLOCK_GRC, 135316485Sdavidcs BLOCK_MISCS, 136316485Sdavidcs BLOCK_MISC, 137316485Sdavidcs BLOCK_DBU, 138316485Sdavidcs BLOCK_PGLUE_B, 139316485Sdavidcs BLOCK_CNIG, 140316485Sdavidcs BLOCK_CPMU, 141316485Sdavidcs BLOCK_NCSI, 142316485Sdavidcs BLOCK_OPTE, 143316485Sdavidcs BLOCK_BMB, 144316485Sdavidcs BLOCK_PCIE, 145316485Sdavidcs BLOCK_MCP, 146316485Sdavidcs BLOCK_MCP2, 147316485Sdavidcs BLOCK_PSWHST, 148316485Sdavidcs BLOCK_PSWHST2, 149316485Sdavidcs BLOCK_PSWRD, 150316485Sdavidcs BLOCK_PSWRD2, 151316485Sdavidcs BLOCK_PSWWR, 152316485Sdavidcs BLOCK_PSWWR2, 153316485Sdavidcs BLOCK_PSWRQ, 154316485Sdavidcs BLOCK_PSWRQ2, 155316485Sdavidcs BLOCK_PGLCS, 156316485Sdavidcs BLOCK_DMAE, 157316485Sdavidcs BLOCK_PTU, 158316485Sdavidcs BLOCK_TCM, 159316485Sdavidcs BLOCK_MCM, 160316485Sdavidcs BLOCK_UCM, 161316485Sdavidcs BLOCK_XCM, 162316485Sdavidcs BLOCK_YCM, 163316485Sdavidcs BLOCK_PCM, 164316485Sdavidcs BLOCK_QM, 165316485Sdavidcs BLOCK_TM, 166316485Sdavidcs BLOCK_DORQ, 167316485Sdavidcs BLOCK_BRB, 168316485Sdavidcs BLOCK_SRC, 169316485Sdavidcs BLOCK_PRS, 170316485Sdavidcs BLOCK_TSDM, 171316485Sdavidcs BLOCK_MSDM, 172316485Sdavidcs BLOCK_USDM, 173316485Sdavidcs BLOCK_XSDM, 174316485Sdavidcs BLOCK_YSDM, 175316485Sdavidcs BLOCK_PSDM, 176316485Sdavidcs BLOCK_TSEM, 177316485Sdavidcs BLOCK_MSEM, 178316485Sdavidcs BLOCK_USEM, 179316485Sdavidcs BLOCK_XSEM, 180316485Sdavidcs BLOCK_YSEM, 181316485Sdavidcs BLOCK_PSEM, 182316485Sdavidcs BLOCK_RSS, 183316485Sdavidcs BLOCK_TMLD, 184316485Sdavidcs BLOCK_MULD, 185316485Sdavidcs BLOCK_YULD, 186316485Sdavidcs BLOCK_XYLD, 187316485Sdavidcs BLOCK_PTLD, 188316485Sdavidcs BLOCK_YPLD, 189316485Sdavidcs BLOCK_PRM, 190316485Sdavidcs BLOCK_PBF_PB1, 191316485Sdavidcs BLOCK_PBF_PB2, 192316485Sdavidcs BLOCK_RPB, 193316485Sdavidcs BLOCK_BTB, 194316485Sdavidcs BLOCK_PBF, 195316485Sdavidcs BLOCK_RDIF, 196316485Sdavidcs BLOCK_TDIF, 197316485Sdavidcs BLOCK_CDU, 198316485Sdavidcs BLOCK_CCFC, 199316485Sdavidcs BLOCK_TCFC, 200316485Sdavidcs BLOCK_IGU, 201316485Sdavidcs BLOCK_CAU, 202316485Sdavidcs BLOCK_RGFS, 203316485Sdavidcs BLOCK_RGSRC, 204316485Sdavidcs BLOCK_TGFS, 205316485Sdavidcs BLOCK_TGSRC, 206316485Sdavidcs BLOCK_UMAC, 207316485Sdavidcs BLOCK_XMAC, 208316485Sdavidcs BLOCK_DBG, 209316485Sdavidcs BLOCK_NIG, 210316485Sdavidcs BLOCK_WOL, 211316485Sdavidcs BLOCK_BMBN, 212316485Sdavidcs BLOCK_IPC, 213316485Sdavidcs BLOCK_NWM, 214316485Sdavidcs BLOCK_NWS, 215316485Sdavidcs BLOCK_MS, 216316485Sdavidcs BLOCK_PHY_PCIE, 217316485Sdavidcs BLOCK_LED, 218316485Sdavidcs BLOCK_AVS_WRAP, 219337519Sdavidcs BLOCK_PXPREQBUS, 220316485Sdavidcs BLOCK_MISC_AEU, 221316485Sdavidcs BLOCK_BAR0_MAP, 222316485Sdavidcs MAX_BLOCK_ID 223316485Sdavidcs}; 224316485Sdavidcs 225316485Sdavidcs 226316485Sdavidcs/* 227316485Sdavidcs * binary debug buffer types 228316485Sdavidcs */ 229316485Sdavidcsenum bin_dbg_buffer_type 230316485Sdavidcs{ 231316485Sdavidcs BIN_BUF_DBG_MODE_TREE /* init modes tree */, 232316485Sdavidcs BIN_BUF_DBG_DUMP_REG /* GRC Dump registers */, 233316485Sdavidcs BIN_BUF_DBG_DUMP_MEM /* GRC Dump memories */, 234316485Sdavidcs BIN_BUF_DBG_IDLE_CHK_REGS /* Idle Check registers */, 235316485Sdavidcs BIN_BUF_DBG_IDLE_CHK_IMMS /* Idle Check immediates */, 236316485Sdavidcs BIN_BUF_DBG_IDLE_CHK_RULES /* Idle Check rules */, 237316485Sdavidcs BIN_BUF_DBG_IDLE_CHK_PARSING_DATA /* Idle Check parsing data */, 238316485Sdavidcs BIN_BUF_DBG_ATTN_BLOCKS /* Attention blocks */, 239316485Sdavidcs BIN_BUF_DBG_ATTN_REGS /* Attention registers */, 240316485Sdavidcs BIN_BUF_DBG_ATTN_INDEXES /* Attention indexes */, 241316485Sdavidcs BIN_BUF_DBG_ATTN_NAME_OFFSETS /* Attention name offsets */, 242316485Sdavidcs BIN_BUF_DBG_BUS_BLOCKS /* Debug Bus blocks */, 243316485Sdavidcs BIN_BUF_DBG_BUS_LINES /* Debug Bus lines */, 244316485Sdavidcs BIN_BUF_DBG_BUS_BLOCKS_USER_DATA /* Debug Bus blocks user data */, 245316485Sdavidcs BIN_BUF_DBG_BUS_LINE_NAME_OFFSETS /* Debug Bus line name offsets */, 246316485Sdavidcs BIN_BUF_DBG_PARSING_STRINGS /* Debug Tools parsing strings */, 247316485Sdavidcs MAX_BIN_DBG_BUFFER_TYPE 248316485Sdavidcs}; 249316485Sdavidcs 250316485Sdavidcs 251316485Sdavidcs/* 252316485Sdavidcs * Attention bit mapping 253316485Sdavidcs */ 254316485Sdavidcsstruct dbg_attn_bit_mapping 255316485Sdavidcs{ 256337519Sdavidcs u16 data; 257316485Sdavidcs#define DBG_ATTN_BIT_MAPPING_VAL_MASK 0x7FFF /* The index of an attention in the blocks attentions list (if is_unused_bit_cnt=0), or a number of consecutive unused attention bits (if is_unused_bit_cnt=1) */ 258316485Sdavidcs#define DBG_ATTN_BIT_MAPPING_VAL_SHIFT 0 259316485Sdavidcs#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_MASK 0x1 /* if set, the val field indicates the number of consecutive unused attention bits */ 260316485Sdavidcs#define DBG_ATTN_BIT_MAPPING_IS_UNUSED_BIT_CNT_SHIFT 15 261316485Sdavidcs}; 262316485Sdavidcs 263316485Sdavidcs 264316485Sdavidcs/* 265316485Sdavidcs * Attention block per-type data 266316485Sdavidcs */ 267316485Sdavidcsstruct dbg_attn_block_type_data 268316485Sdavidcs{ 269337519Sdavidcs u16 names_offset /* Offset of this block attention names in the debug attention name offsets array */; 270337519Sdavidcs u16 reserved1; 271316485Sdavidcs u8 num_regs /* Number of attention registers in this block */; 272316485Sdavidcs u8 reserved2; 273337519Sdavidcs u16 regs_offset /* Offset of this blocks attention registers in the attention registers array (in dbg_attn_reg units) */; 274316485Sdavidcs}; 275316485Sdavidcs 276316485Sdavidcs/* 277316485Sdavidcs * Block attentions 278316485Sdavidcs */ 279316485Sdavidcsstruct dbg_attn_block 280316485Sdavidcs{ 281316485Sdavidcs struct dbg_attn_block_type_data per_type_data[2] /* attention block per-type data. Count must match the number of elements in dbg_attn_type. */; 282316485Sdavidcs}; 283316485Sdavidcs 284316485Sdavidcs 285316485Sdavidcs/* 286316485Sdavidcs * Attention register result 287316485Sdavidcs */ 288316485Sdavidcsstruct dbg_attn_reg_result 289316485Sdavidcs{ 290337519Sdavidcs u32 data; 291316485Sdavidcs#define DBG_ATTN_REG_RESULT_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 292316485Sdavidcs#define DBG_ATTN_REG_RESULT_STS_ADDRESS_SHIFT 0 293316485Sdavidcs#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_MASK 0xFF /* Number of attention indexes in this register */ 294316485Sdavidcs#define DBG_ATTN_REG_RESULT_NUM_REG_ATTN_SHIFT 24 295337519Sdavidcs u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 296337519Sdavidcs u16 reserved; 297337519Sdavidcs u32 sts_val /* Value read from the STS attention register */; 298337519Sdavidcs u32 mask_val /* Value read from the MASK attention register */; 299316485Sdavidcs}; 300316485Sdavidcs 301316485Sdavidcs/* 302316485Sdavidcs * Attention block result 303316485Sdavidcs */ 304316485Sdavidcsstruct dbg_attn_block_result 305316485Sdavidcs{ 306316485Sdavidcs u8 block_id /* Registers block ID */; 307316485Sdavidcs u8 data; 308316485Sdavidcs#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_MASK 0x3 /* Value from dbg_attn_type enum */ 309316485Sdavidcs#define DBG_ATTN_BLOCK_RESULT_ATTN_TYPE_SHIFT 0 310316485Sdavidcs#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_MASK 0x3F /* Number of registers in the block in which at least one attention bit is set */ 311316485Sdavidcs#define DBG_ATTN_BLOCK_RESULT_NUM_REGS_SHIFT 2 312337519Sdavidcs u16 names_offset /* Offset of this registers block attention names in the attention name offsets array */; 313316485Sdavidcs struct dbg_attn_reg_result reg_results[15] /* result data for each register in the block in which at least one attention bit is set */; 314316485Sdavidcs}; 315316485Sdavidcs 316316485Sdavidcs 317316485Sdavidcs 318316485Sdavidcs/* 319316485Sdavidcs * mode header 320316485Sdavidcs */ 321316485Sdavidcsstruct dbg_mode_hdr 322316485Sdavidcs{ 323337519Sdavidcs u16 data; 324316485Sdavidcs#define DBG_MODE_HDR_EVAL_MODE_MASK 0x1 /* indicates if a mode expression should be evaluated (0/1) */ 325316485Sdavidcs#define DBG_MODE_HDR_EVAL_MODE_SHIFT 0 326316485Sdavidcs#define DBG_MODE_HDR_MODES_BUF_OFFSET_MASK 0x7FFF /* offset (in bytes) in modes expression buffer. valid only if eval_mode is set. */ 327316485Sdavidcs#define DBG_MODE_HDR_MODES_BUF_OFFSET_SHIFT 1 328316485Sdavidcs}; 329316485Sdavidcs 330316485Sdavidcs/* 331316485Sdavidcs * Attention register 332316485Sdavidcs */ 333316485Sdavidcsstruct dbg_attn_reg 334316485Sdavidcs{ 335316485Sdavidcs struct dbg_mode_hdr mode /* Mode header */; 336337519Sdavidcs u16 block_attn_offset /* The offset of this registers attentions within the blocks attentions list (a value in the range 0..number of block attentions-1) */; 337337519Sdavidcs u32 data; 338316485Sdavidcs#define DBG_ATTN_REG_STS_ADDRESS_MASK 0xFFFFFF /* STS attention register GRC address (in dwords) */ 339316485Sdavidcs#define DBG_ATTN_REG_STS_ADDRESS_SHIFT 0 340316485Sdavidcs#define DBG_ATTN_REG_NUM_REG_ATTN_MASK 0xFF /* Number of attention in this register */ 341316485Sdavidcs#define DBG_ATTN_REG_NUM_REG_ATTN_SHIFT 24 342337519Sdavidcs u32 sts_clr_address /* STS_CLR attention register GRC address (in dwords) */; 343337519Sdavidcs u32 mask_address /* MASK attention register GRC address (in dwords) */; 344316485Sdavidcs}; 345316485Sdavidcs 346316485Sdavidcs 347316485Sdavidcs 348316485Sdavidcs/* 349316485Sdavidcs * attention types 350316485Sdavidcs */ 351316485Sdavidcsenum dbg_attn_type 352316485Sdavidcs{ 353316485Sdavidcs ATTN_TYPE_INTERRUPT, 354316485Sdavidcs ATTN_TYPE_PARITY, 355316485Sdavidcs MAX_DBG_ATTN_TYPE 356316485Sdavidcs}; 357316485Sdavidcs 358316485Sdavidcs 359316485Sdavidcs/* 360316485Sdavidcs * Debug Bus block data 361316485Sdavidcs */ 362316485Sdavidcsstruct dbg_bus_block 363316485Sdavidcs{ 364316485Sdavidcs u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 365316485Sdavidcs u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 366337519Sdavidcs u16 lines_offset /* Offset of this blocks lines in the Debug Bus lines array. */; 367316485Sdavidcs}; 368316485Sdavidcs 369316485Sdavidcs 370316485Sdavidcs/* 371316485Sdavidcs * Debug Bus block user data 372316485Sdavidcs */ 373316485Sdavidcsstruct dbg_bus_block_user_data 374316485Sdavidcs{ 375316485Sdavidcs u8 num_of_lines /* Number of debug lines in this block (excluding signature and latency events). */; 376316485Sdavidcs u8 has_latency_events /* Indicates if this block has a latency events debug line (0/1). */; 377337519Sdavidcs u16 names_offset /* Offset of this blocks lines in the debug bus line name offsets array. */; 378316485Sdavidcs}; 379316485Sdavidcs 380316485Sdavidcs 381316485Sdavidcs/* 382316485Sdavidcs * Block Debug line data 383316485Sdavidcs */ 384316485Sdavidcsstruct dbg_bus_line 385316485Sdavidcs{ 386316485Sdavidcs u8 data; 387316485Sdavidcs#define DBG_BUS_LINE_NUM_OF_GROUPS_MASK 0xF /* Number of groups in the line (0-3) */ 388316485Sdavidcs#define DBG_BUS_LINE_NUM_OF_GROUPS_SHIFT 0 389316485Sdavidcs#define DBG_BUS_LINE_IS_256B_MASK 0x1 /* Indicates if this is a 128b line (0) or a 256b line (1). */ 390316485Sdavidcs#define DBG_BUS_LINE_IS_256B_SHIFT 4 391316485Sdavidcs#define DBG_BUS_LINE_RESERVED_MASK 0x7 392316485Sdavidcs#define DBG_BUS_LINE_RESERVED_SHIFT 5 393316485Sdavidcs u8 group_sizes /* Four 2-bit values, indicating the size of each group minus 1 (i.e. value=0 means size=1, value=1 means size=2, etc), starting from lsb. The sizes are in dwords (if is_256b=0) or in qwords (if is_256b=1). */; 394316485Sdavidcs}; 395316485Sdavidcs 396316485Sdavidcs 397316485Sdavidcs/* 398316485Sdavidcs * condition header for registers dump 399316485Sdavidcs */ 400316485Sdavidcsstruct dbg_dump_cond_hdr 401316485Sdavidcs{ 402316485Sdavidcs struct dbg_mode_hdr mode /* Mode header */; 403316485Sdavidcs u8 block_id /* block ID */; 404316485Sdavidcs u8 data_size /* size in dwords of the data following this header */; 405316485Sdavidcs}; 406316485Sdavidcs 407316485Sdavidcs 408316485Sdavidcs/* 409316485Sdavidcs * memory data for registers dump 410316485Sdavidcs */ 411316485Sdavidcsstruct dbg_dump_mem 412316485Sdavidcs{ 413337519Sdavidcs u32 dword0; 414316485Sdavidcs#define DBG_DUMP_MEM_ADDRESS_MASK 0xFFFFFF /* register address (in dwords) */ 415316485Sdavidcs#define DBG_DUMP_MEM_ADDRESS_SHIFT 0 416316485Sdavidcs#define DBG_DUMP_MEM_MEM_GROUP_ID_MASK 0xFF /* memory group ID */ 417316485Sdavidcs#define DBG_DUMP_MEM_MEM_GROUP_ID_SHIFT 24 418337519Sdavidcs u32 dword1; 419316485Sdavidcs#define DBG_DUMP_MEM_LENGTH_MASK 0xFFFFFF /* register size (in dwords) */ 420316485Sdavidcs#define DBG_DUMP_MEM_LENGTH_SHIFT 0 421316485Sdavidcs#define DBG_DUMP_MEM_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 422316485Sdavidcs#define DBG_DUMP_MEM_WIDE_BUS_SHIFT 24 423316485Sdavidcs#define DBG_DUMP_MEM_RESERVED_MASK 0x7F 424316485Sdavidcs#define DBG_DUMP_MEM_RESERVED_SHIFT 25 425316485Sdavidcs}; 426316485Sdavidcs 427316485Sdavidcs 428316485Sdavidcs/* 429316485Sdavidcs * register data for registers dump 430316485Sdavidcs */ 431316485Sdavidcsstruct dbg_dump_reg 432316485Sdavidcs{ 433337519Sdavidcs u32 data; 434316485Sdavidcs#define DBG_DUMP_REG_ADDRESS_MASK 0x7FFFFF /* register address (in dwords) */ 435316485Sdavidcs#define DBG_DUMP_REG_ADDRESS_SHIFT 0 436316485Sdavidcs#define DBG_DUMP_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 437316485Sdavidcs#define DBG_DUMP_REG_WIDE_BUS_SHIFT 23 438316485Sdavidcs#define DBG_DUMP_REG_LENGTH_MASK 0xFF /* register size (in dwords) */ 439316485Sdavidcs#define DBG_DUMP_REG_LENGTH_SHIFT 24 440316485Sdavidcs}; 441316485Sdavidcs 442316485Sdavidcs 443316485Sdavidcs/* 444316485Sdavidcs * split header for registers dump 445316485Sdavidcs */ 446316485Sdavidcsstruct dbg_dump_split_hdr 447316485Sdavidcs{ 448337519Sdavidcs u32 hdr; 449316485Sdavidcs#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_MASK 0xFFFFFF /* size in dwords of the data following this header */ 450316485Sdavidcs#define DBG_DUMP_SPLIT_HDR_DATA_SIZE_SHIFT 0 451316485Sdavidcs#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_MASK 0xFF /* split type ID */ 452316485Sdavidcs#define DBG_DUMP_SPLIT_HDR_SPLIT_TYPE_ID_SHIFT 24 453316485Sdavidcs}; 454316485Sdavidcs 455316485Sdavidcs 456316485Sdavidcs/* 457316485Sdavidcs * condition header for idle check 458316485Sdavidcs */ 459316485Sdavidcsstruct dbg_idle_chk_cond_hdr 460316485Sdavidcs{ 461316485Sdavidcs struct dbg_mode_hdr mode /* Mode header */; 462337519Sdavidcs u16 data_size /* size in dwords of the data following this header */; 463316485Sdavidcs}; 464316485Sdavidcs 465316485Sdavidcs 466316485Sdavidcs/* 467316485Sdavidcs * Idle Check condition register 468316485Sdavidcs */ 469316485Sdavidcsstruct dbg_idle_chk_cond_reg 470316485Sdavidcs{ 471337519Sdavidcs u32 data; 472316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 473316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_ADDRESS_SHIFT 0 474316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 475316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_WIDE_BUS_SHIFT 23 476316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 477316485Sdavidcs#define DBG_IDLE_CHK_COND_REG_BLOCK_ID_SHIFT 24 478337519Sdavidcs u16 num_entries /* number of registers entries to check */; 479316485Sdavidcs u8 entry_size /* size of registers entry (in dwords) */; 480316485Sdavidcs u8 start_entry /* index of the first entry to check */; 481316485Sdavidcs}; 482316485Sdavidcs 483316485Sdavidcs 484316485Sdavidcs/* 485316485Sdavidcs * Idle Check info register 486316485Sdavidcs */ 487316485Sdavidcsstruct dbg_idle_chk_info_reg 488316485Sdavidcs{ 489337519Sdavidcs u32 data; 490316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_ADDRESS_MASK 0x7FFFFF /* Register GRC address (in dwords) */ 491316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_ADDRESS_SHIFT 0 492316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_MASK 0x1 /* indicates if the register is wide-bus */ 493316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_WIDE_BUS_SHIFT 23 494316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_MASK 0xFF /* value from block_id enum */ 495316485Sdavidcs#define DBG_IDLE_CHK_INFO_REG_BLOCK_ID_SHIFT 24 496337519Sdavidcs u16 size /* register size in dwords */; 497316485Sdavidcs struct dbg_mode_hdr mode /* Mode header */; 498316485Sdavidcs}; 499316485Sdavidcs 500316485Sdavidcs 501316485Sdavidcs/* 502316485Sdavidcs * Idle Check register 503316485Sdavidcs */ 504316485Sdavidcsunion dbg_idle_chk_reg 505316485Sdavidcs{ 506316485Sdavidcs struct dbg_idle_chk_cond_reg cond_reg /* condition register */; 507316485Sdavidcs struct dbg_idle_chk_info_reg info_reg /* info register */; 508316485Sdavidcs}; 509316485Sdavidcs 510316485Sdavidcs 511316485Sdavidcs/* 512316485Sdavidcs * Idle Check result header 513316485Sdavidcs */ 514316485Sdavidcsstruct dbg_idle_chk_result_hdr 515316485Sdavidcs{ 516337519Sdavidcs u16 rule_id /* Failing rule index */; 517337519Sdavidcs u16 mem_entry_id /* Failing memory entry index */; 518316485Sdavidcs u8 num_dumped_cond_regs /* number of dumped condition registers */; 519316485Sdavidcs u8 num_dumped_info_regs /* number of dumped condition registers */; 520316485Sdavidcs u8 severity /* from dbg_idle_chk_severity_types enum */; 521316485Sdavidcs u8 reserved; 522316485Sdavidcs}; 523316485Sdavidcs 524316485Sdavidcs 525316485Sdavidcs/* 526316485Sdavidcs * Idle Check result register header 527316485Sdavidcs */ 528316485Sdavidcsstruct dbg_idle_chk_result_reg_hdr 529316485Sdavidcs{ 530316485Sdavidcs u8 data; 531316485Sdavidcs#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_MASK 0x1 /* indicates if this register is a memory */ 532316485Sdavidcs#define DBG_IDLE_CHK_RESULT_REG_HDR_IS_MEM_SHIFT 0 533316485Sdavidcs#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_MASK 0x7F /* register index within the failing rule */ 534316485Sdavidcs#define DBG_IDLE_CHK_RESULT_REG_HDR_REG_ID_SHIFT 1 535316485Sdavidcs u8 start_entry /* index of the first checked entry */; 536337519Sdavidcs u16 size /* register size in dwords */; 537316485Sdavidcs}; 538316485Sdavidcs 539316485Sdavidcs 540316485Sdavidcs/* 541316485Sdavidcs * Idle Check rule 542316485Sdavidcs */ 543316485Sdavidcsstruct dbg_idle_chk_rule 544316485Sdavidcs{ 545337519Sdavidcs u16 rule_id /* Idle Check rule ID */; 546316485Sdavidcs u8 severity /* value from dbg_idle_chk_severity_types enum */; 547316485Sdavidcs u8 cond_id /* Condition ID */; 548316485Sdavidcs u8 num_cond_regs /* number of condition registers */; 549316485Sdavidcs u8 num_info_regs /* number of info registers */; 550316485Sdavidcs u8 num_imms /* number of immediates in the condition */; 551316485Sdavidcs u8 reserved1; 552337519Sdavidcs u16 reg_offset /* offset of this rules registers in the idle check register array (in dbg_idle_chk_reg units) */; 553337519Sdavidcs u16 imm_offset /* offset of this rules immediate values in the immediate values array (in dwords) */; 554316485Sdavidcs}; 555316485Sdavidcs 556316485Sdavidcs 557316485Sdavidcs/* 558316485Sdavidcs * Idle Check rule parsing data 559316485Sdavidcs */ 560316485Sdavidcsstruct dbg_idle_chk_rule_parsing_data 561316485Sdavidcs{ 562337519Sdavidcs u32 data; 563316485Sdavidcs#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_MASK 0x1 /* indicates if this register has a FW message */ 564316485Sdavidcs#define DBG_IDLE_CHK_RULE_PARSING_DATA_HAS_FW_MSG_SHIFT 0 565316485Sdavidcs#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_MASK 0x7FFFFFFF /* Offset of this rules strings in the debug strings array (in bytes) */ 566316485Sdavidcs#define DBG_IDLE_CHK_RULE_PARSING_DATA_STR_OFFSET_SHIFT 1 567316485Sdavidcs}; 568316485Sdavidcs 569316485Sdavidcs 570316485Sdavidcs/* 571316485Sdavidcs * idle check severity types 572316485Sdavidcs */ 573316485Sdavidcsenum dbg_idle_chk_severity_types 574316485Sdavidcs{ 575316485Sdavidcs IDLE_CHK_SEVERITY_ERROR /* idle check failure should cause an error */, 576316485Sdavidcs IDLE_CHK_SEVERITY_ERROR_NO_TRAFFIC /* idle check failure should cause an error only if theres no traffic */, 577316485Sdavidcs IDLE_CHK_SEVERITY_WARNING /* idle check failure should cause a warning */, 578316485Sdavidcs MAX_DBG_IDLE_CHK_SEVERITY_TYPES 579316485Sdavidcs}; 580316485Sdavidcs 581316485Sdavidcs 582316485Sdavidcs 583316485Sdavidcs/* 584316485Sdavidcs * Debug Bus block data 585316485Sdavidcs */ 586316485Sdavidcsstruct dbg_bus_block_data 587316485Sdavidcs{ 588337519Sdavidcs u16 data; 589316485Sdavidcs#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is enabled. */ 590316485Sdavidcs#define DBG_BUS_BLOCK_DATA_ENABLE_MASK_SHIFT 0 591316485Sdavidcs#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_MASK 0xF /* Number of dwords/qwords to shift right the debug data (0-3) */ 592316485Sdavidcs#define DBG_BUS_BLOCK_DATA_RIGHT_SHIFT_SHIFT 4 593316485Sdavidcs#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i is forced valid. */ 594316485Sdavidcs#define DBG_BUS_BLOCK_DATA_FORCE_VALID_MASK_SHIFT 8 595316485Sdavidcs#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_MASK 0xF /* 4-bit value: bit i set -> dword/qword i frame bit is forced. */ 596316485Sdavidcs#define DBG_BUS_BLOCK_DATA_FORCE_FRAME_MASK_SHIFT 12 597316485Sdavidcs u8 line_num /* Debug line number to select */; 598316485Sdavidcs u8 hw_id /* HW ID associated with the block */; 599316485Sdavidcs}; 600316485Sdavidcs 601316485Sdavidcs 602316485Sdavidcs/* 603316485Sdavidcs * Debug Bus Clients 604316485Sdavidcs */ 605316485Sdavidcsenum dbg_bus_clients 606316485Sdavidcs{ 607316485Sdavidcs DBG_BUS_CLIENT_RBCN, 608316485Sdavidcs DBG_BUS_CLIENT_RBCP, 609316485Sdavidcs DBG_BUS_CLIENT_RBCR, 610316485Sdavidcs DBG_BUS_CLIENT_RBCT, 611316485Sdavidcs DBG_BUS_CLIENT_RBCU, 612316485Sdavidcs DBG_BUS_CLIENT_RBCF, 613316485Sdavidcs DBG_BUS_CLIENT_RBCX, 614316485Sdavidcs DBG_BUS_CLIENT_RBCS, 615316485Sdavidcs DBG_BUS_CLIENT_RBCH, 616316485Sdavidcs DBG_BUS_CLIENT_RBCZ, 617316485Sdavidcs DBG_BUS_CLIENT_OTHER_ENGINE, 618316485Sdavidcs DBG_BUS_CLIENT_TIMESTAMP, 619316485Sdavidcs DBG_BUS_CLIENT_CPU, 620316485Sdavidcs DBG_BUS_CLIENT_RBCY, 621316485Sdavidcs DBG_BUS_CLIENT_RBCQ, 622316485Sdavidcs DBG_BUS_CLIENT_RBCM, 623316485Sdavidcs DBG_BUS_CLIENT_RBCB, 624316485Sdavidcs DBG_BUS_CLIENT_RBCW, 625316485Sdavidcs DBG_BUS_CLIENT_RBCV, 626316485Sdavidcs MAX_DBG_BUS_CLIENTS 627316485Sdavidcs}; 628316485Sdavidcs 629316485Sdavidcs 630316485Sdavidcs/* 631316485Sdavidcs * Debug Bus constraint operation types 632316485Sdavidcs */ 633316485Sdavidcsenum dbg_bus_constraint_ops 634316485Sdavidcs{ 635316485Sdavidcs DBG_BUS_CONSTRAINT_OP_EQ /* equal */, 636316485Sdavidcs DBG_BUS_CONSTRAINT_OP_NE /* not equal */, 637316485Sdavidcs DBG_BUS_CONSTRAINT_OP_LT /* less than */, 638316485Sdavidcs DBG_BUS_CONSTRAINT_OP_LTC /* less than (cyclic) */, 639316485Sdavidcs DBG_BUS_CONSTRAINT_OP_LE /* less than or equal */, 640316485Sdavidcs DBG_BUS_CONSTRAINT_OP_LEC /* less than or equal (cyclic) */, 641316485Sdavidcs DBG_BUS_CONSTRAINT_OP_GT /* greater than */, 642316485Sdavidcs DBG_BUS_CONSTRAINT_OP_GTC /* greater than (cyclic) */, 643316485Sdavidcs DBG_BUS_CONSTRAINT_OP_GE /* greater than or equal */, 644316485Sdavidcs DBG_BUS_CONSTRAINT_OP_GEC /* greater than or equal (cyclic) */, 645316485Sdavidcs MAX_DBG_BUS_CONSTRAINT_OPS 646316485Sdavidcs}; 647316485Sdavidcs 648316485Sdavidcs 649316485Sdavidcs/* 650316485Sdavidcs * Debug Bus trigger state data 651316485Sdavidcs */ 652316485Sdavidcsstruct dbg_bus_trigger_state_data 653316485Sdavidcs{ 654316485Sdavidcs u8 data; 655316485Sdavidcs#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i of the trigger state block (after right shift) is enabled. */ 656316485Sdavidcs#define DBG_BUS_TRIGGER_STATE_DATA_BLOCK_SHIFTED_ENABLE_MASK_SHIFT 0 657316485Sdavidcs#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_MASK 0xF /* 4-bit value: bit i set -> dword i is compared by a constraint */ 658316485Sdavidcs#define DBG_BUS_TRIGGER_STATE_DATA_CONSTRAINT_DWORD_MASK_SHIFT 4 659316485Sdavidcs}; 660316485Sdavidcs 661316485Sdavidcs/* 662316485Sdavidcs * Debug Bus memory address 663316485Sdavidcs */ 664316485Sdavidcsstruct dbg_bus_mem_addr 665316485Sdavidcs{ 666337519Sdavidcs u32 lo; 667337519Sdavidcs u32 hi; 668316485Sdavidcs}; 669316485Sdavidcs 670316485Sdavidcs/* 671316485Sdavidcs * Debug Bus PCI buffer data 672316485Sdavidcs */ 673316485Sdavidcsstruct dbg_bus_pci_buf_data 674316485Sdavidcs{ 675316485Sdavidcs struct dbg_bus_mem_addr phys_addr /* PCI buffer physical address */; 676316485Sdavidcs struct dbg_bus_mem_addr virt_addr /* PCI buffer virtual address */; 677337519Sdavidcs u32 size /* PCI buffer size in bytes */; 678316485Sdavidcs}; 679316485Sdavidcs 680316485Sdavidcs/* 681316485Sdavidcs * Debug Bus Storm EID range filter params 682316485Sdavidcs */ 683316485Sdavidcsstruct dbg_bus_storm_eid_range_params 684316485Sdavidcs{ 685316485Sdavidcs u8 min /* Minimal event ID to filter on */; 686316485Sdavidcs u8 max /* Maximal event ID to filter on */; 687316485Sdavidcs}; 688316485Sdavidcs 689316485Sdavidcs/* 690316485Sdavidcs * Debug Bus Storm EID mask filter params 691316485Sdavidcs */ 692316485Sdavidcsstruct dbg_bus_storm_eid_mask_params 693316485Sdavidcs{ 694316485Sdavidcs u8 val /* Event ID value */; 695316485Sdavidcs u8 mask /* Event ID mask. 1s in the mask = dont care bits. */; 696316485Sdavidcs}; 697316485Sdavidcs 698316485Sdavidcs/* 699316485Sdavidcs * Debug Bus Storm EID filter params 700316485Sdavidcs */ 701316485Sdavidcsunion dbg_bus_storm_eid_params 702316485Sdavidcs{ 703316485Sdavidcs struct dbg_bus_storm_eid_range_params range /* EID range filter params */; 704316485Sdavidcs struct dbg_bus_storm_eid_mask_params mask /* EID mask filter params */; 705316485Sdavidcs}; 706316485Sdavidcs 707316485Sdavidcs/* 708316485Sdavidcs * Debug Bus Storm data 709316485Sdavidcs */ 710316485Sdavidcsstruct dbg_bus_storm_data 711316485Sdavidcs{ 712316485Sdavidcs u8 enabled /* indicates if the Storm is enabled for recording */; 713337519Sdavidcs u8 mode /* Storm debug mode, valid only if the Storm is enabled (use enum dbg_bus_storm_modes) */; 714316485Sdavidcs u8 hw_id /* HW ID associated with the Storm */; 715316485Sdavidcs u8 eid_filter_en /* Indicates if EID filtering is performed (0/1) */; 716316485Sdavidcs u8 eid_range_not_mask /* 1 = EID range filter, 0 = EID mask filter. Valid only if eid_filter_en is set, */; 717316485Sdavidcs u8 cid_filter_en /* Indicates if CID filtering is performed (0/1) */; 718316485Sdavidcs union dbg_bus_storm_eid_params eid_filter_params /* EID filter params to filter on. Valid only if eid_filter_en is set. */; 719337519Sdavidcs u32 cid /* CID to filter on. Valid only if cid_filter_en is set. */; 720316485Sdavidcs}; 721316485Sdavidcs 722316485Sdavidcs/* 723316485Sdavidcs * Debug Bus data 724316485Sdavidcs */ 725316485Sdavidcsstruct dbg_bus_data 726316485Sdavidcs{ 727337519Sdavidcs u32 app_version /* The tools version number of the application */; 728337519Sdavidcs u8 state /* The current debug bus state (use enum dbg_bus_states) */; 729316485Sdavidcs u8 hw_dwords /* HW dwords per cycle */; 730337519Sdavidcs u16 hw_id_mask /* The HW IDs of the recorded HW blocks, where bits i*3..i*3+2 contain the HW ID of dword/qword i */; 731316485Sdavidcs u8 num_enabled_blocks /* Number of blocks enabled for recording */; 732316485Sdavidcs u8 num_enabled_storms /* Number of Storms enabled for recording */; 733337519Sdavidcs u8 target /* Output target (use enum dbg_bus_targets) */; 734316485Sdavidcs u8 one_shot_en /* Indicates if one-shot mode is enabled (0/1) */; 735316485Sdavidcs u8 grc_input_en /* Indicates if GRC recording is enabled (0/1) */; 736316485Sdavidcs u8 timestamp_input_en /* Indicates if timestamp recording is enabled (0/1) */; 737316485Sdavidcs u8 filter_en /* Indicates if the recording filter is enabled (0/1) */; 738316485Sdavidcs u8 adding_filter /* If true, the next added constraint belong to the filter. Otherwise, it belongs to the last added trigger state. Valid only if either filter or triggers are enabled. */; 739316485Sdavidcs u8 filter_pre_trigger /* Indicates if the recording filter should be applied before the trigger. Valid only if both filter and trigger are enabled (0/1) */; 740316485Sdavidcs u8 filter_post_trigger /* Indicates if the recording filter should be applied after the trigger. Valid only if both filter and trigger are enabled (0/1) */; 741337519Sdavidcs u16 reserved; 742316485Sdavidcs u8 trigger_en /* Indicates if the recording trigger is enabled (0/1) */; 743316485Sdavidcs struct dbg_bus_trigger_state_data trigger_states[3] /* trigger states data */; 744316485Sdavidcs u8 next_trigger_state /* ID of next trigger state to be added */; 745316485Sdavidcs u8 next_constraint_id /* ID of next filter/trigger constraint to be added */; 746316485Sdavidcs u8 unify_inputs /* If true, all inputs are associated with HW ID 0. Otherwise, each input is assigned a different HW ID (0/1) */; 747316485Sdavidcs u8 rcv_from_other_engine /* Indicates if the other engine sends it NW recording to this engine (0/1) */; 748316485Sdavidcs struct dbg_bus_pci_buf_data pci_buf /* Debug Bus PCI buffer data. Valid only when the target is DBG_BUS_TARGET_ID_PCI. */; 749316485Sdavidcs struct dbg_bus_block_data blocks[88] /* Debug Bus data for each block */; 750316485Sdavidcs struct dbg_bus_storm_data storms[6] /* Debug Bus data for each block */; 751316485Sdavidcs}; 752316485Sdavidcs 753316485Sdavidcs 754316485Sdavidcs/* 755316485Sdavidcs * Debug bus filter types 756316485Sdavidcs */ 757316485Sdavidcsenum dbg_bus_filter_types 758316485Sdavidcs{ 759316485Sdavidcs DBG_BUS_FILTER_TYPE_OFF /* filter always off */, 760316485Sdavidcs DBG_BUS_FILTER_TYPE_PRE /* filter before trigger only */, 761316485Sdavidcs DBG_BUS_FILTER_TYPE_POST /* filter after trigger only */, 762316485Sdavidcs DBG_BUS_FILTER_TYPE_ON /* filter always on */, 763316485Sdavidcs MAX_DBG_BUS_FILTER_TYPES 764316485Sdavidcs}; 765316485Sdavidcs 766316485Sdavidcs 767316485Sdavidcs/* 768316485Sdavidcs * Debug bus frame modes 769316485Sdavidcs */ 770316485Sdavidcsenum dbg_bus_frame_modes 771316485Sdavidcs{ 772316485Sdavidcs DBG_BUS_FRAME_MODE_0HW_4ST=0 /* 0 HW dwords, 4 Storm dwords */, 773316485Sdavidcs DBG_BUS_FRAME_MODE_4HW_0ST=3 /* 4 HW dwords, 0 Storm dwords */, 774316485Sdavidcs DBG_BUS_FRAME_MODE_8HW_0ST=4 /* 8 HW dwords, 0 Storm dwords */, 775316485Sdavidcs MAX_DBG_BUS_FRAME_MODES 776316485Sdavidcs}; 777316485Sdavidcs 778316485Sdavidcs 779316485Sdavidcs 780316485Sdavidcs/* 781316485Sdavidcs * Debug bus other engine mode 782316485Sdavidcs */ 783316485Sdavidcsenum dbg_bus_other_engine_modes 784316485Sdavidcs{ 785316485Sdavidcs DBG_BUS_OTHER_ENGINE_MODE_NONE, 786316485Sdavidcs DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_TX, 787316485Sdavidcs DBG_BUS_OTHER_ENGINE_MODE_DOUBLE_BW_RX, 788316485Sdavidcs DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_TX, 789316485Sdavidcs DBG_BUS_OTHER_ENGINE_MODE_CROSS_ENGINE_RX, 790316485Sdavidcs MAX_DBG_BUS_OTHER_ENGINE_MODES 791316485Sdavidcs}; 792316485Sdavidcs 793316485Sdavidcs 794316485Sdavidcs 795316485Sdavidcs/* 796316485Sdavidcs * Debug bus post-trigger recording types 797316485Sdavidcs */ 798316485Sdavidcsenum dbg_bus_post_trigger_types 799316485Sdavidcs{ 800316485Sdavidcs DBG_BUS_POST_TRIGGER_RECORD /* start recording after trigger */, 801316485Sdavidcs DBG_BUS_POST_TRIGGER_DROP /* drop data after trigger */, 802316485Sdavidcs MAX_DBG_BUS_POST_TRIGGER_TYPES 803316485Sdavidcs}; 804316485Sdavidcs 805316485Sdavidcs 806316485Sdavidcs/* 807316485Sdavidcs * Debug bus pre-trigger recording types 808316485Sdavidcs */ 809316485Sdavidcsenum dbg_bus_pre_trigger_types 810316485Sdavidcs{ 811316485Sdavidcs DBG_BUS_PRE_TRIGGER_START_FROM_ZERO /* start recording from time 0 */, 812316485Sdavidcs DBG_BUS_PRE_TRIGGER_NUM_CHUNKS /* start recording some chunks before trigger */, 813316485Sdavidcs DBG_BUS_PRE_TRIGGER_DROP /* drop data before trigger */, 814316485Sdavidcs MAX_DBG_BUS_PRE_TRIGGER_TYPES 815316485Sdavidcs}; 816316485Sdavidcs 817316485Sdavidcs 818316485Sdavidcs/* 819316485Sdavidcs * Debug bus SEMI frame modes 820316485Sdavidcs */ 821316485Sdavidcsenum dbg_bus_semi_frame_modes 822316485Sdavidcs{ 823316485Sdavidcs DBG_BUS_SEMI_FRAME_MODE_0SLOW_4FAST=0 /* 0 slow dwords, 4 fast dwords */, 824316485Sdavidcs DBG_BUS_SEMI_FRAME_MODE_4SLOW_0FAST=3 /* 4 slow dwords, 0 fast dwords */, 825316485Sdavidcs MAX_DBG_BUS_SEMI_FRAME_MODES 826316485Sdavidcs}; 827316485Sdavidcs 828316485Sdavidcs 829316485Sdavidcs/* 830316485Sdavidcs * Debug bus states 831316485Sdavidcs */ 832316485Sdavidcsenum dbg_bus_states 833316485Sdavidcs{ 834316485Sdavidcs DBG_BUS_STATE_IDLE /* debug bus idle state (not recording) */, 835316485Sdavidcs DBG_BUS_STATE_READY /* debug bus is ready for configuration and recording */, 836316485Sdavidcs DBG_BUS_STATE_RECORDING /* debug bus is currently recording */, 837316485Sdavidcs DBG_BUS_STATE_STOPPED /* debug bus recording has stopped */, 838316485Sdavidcs MAX_DBG_BUS_STATES 839316485Sdavidcs}; 840316485Sdavidcs 841316485Sdavidcs 842316485Sdavidcs 843316485Sdavidcs 844316485Sdavidcs 845316485Sdavidcs 846316485Sdavidcs/* 847316485Sdavidcs * Debug Bus Storm modes 848316485Sdavidcs */ 849316485Sdavidcsenum dbg_bus_storm_modes 850316485Sdavidcs{ 851316485Sdavidcs DBG_BUS_STORM_MODE_PRINTF /* store data (fast debug) */, 852316485Sdavidcs DBG_BUS_STORM_MODE_PRAM_ADDR /* pram address (fast debug) */, 853316485Sdavidcs DBG_BUS_STORM_MODE_DRA_RW /* DRA read/write data (fast debug) */, 854316485Sdavidcs DBG_BUS_STORM_MODE_DRA_W /* DRA write data (fast debug) */, 855316485Sdavidcs DBG_BUS_STORM_MODE_LD_ST_ADDR /* load/store address (fast debug) */, 856316485Sdavidcs DBG_BUS_STORM_MODE_DRA_FSM /* DRA state machines (fast debug) */, 857316485Sdavidcs DBG_BUS_STORM_MODE_RH /* recording handlers (fast debug) */, 858316485Sdavidcs DBG_BUS_STORM_MODE_FOC /* FOC: FIN + DRA Rd (slow debug) */, 859316485Sdavidcs DBG_BUS_STORM_MODE_EXT_STORE /* FOC: External Store (slow) */, 860316485Sdavidcs MAX_DBG_BUS_STORM_MODES 861316485Sdavidcs}; 862316485Sdavidcs 863316485Sdavidcs 864316485Sdavidcs/* 865316485Sdavidcs * Debug bus target IDs 866316485Sdavidcs */ 867316485Sdavidcsenum dbg_bus_targets 868316485Sdavidcs{ 869316485Sdavidcs DBG_BUS_TARGET_ID_INT_BUF /* records debug bus to DBG block internal buffer */, 870316485Sdavidcs DBG_BUS_TARGET_ID_NIG /* records debug bus to the NW */, 871316485Sdavidcs DBG_BUS_TARGET_ID_PCI /* records debug bus to a PCI buffer */, 872316485Sdavidcs MAX_DBG_BUS_TARGETS 873316485Sdavidcs}; 874316485Sdavidcs 875316485Sdavidcs 876316485Sdavidcs 877316485Sdavidcs/* 878316485Sdavidcs * GRC Dump data 879316485Sdavidcs */ 880316485Sdavidcsstruct dbg_grc_data 881316485Sdavidcs{ 882316485Sdavidcs u8 params_initialized /* Indicates if the GRC parameters were initialized */; 883316485Sdavidcs u8 reserved1; 884337519Sdavidcs u16 reserved2; 885337519Sdavidcs u32 param_val[48] /* Value of each GRC parameter. Array size must match the enum dbg_grc_params. */; 886316485Sdavidcs}; 887316485Sdavidcs 888316485Sdavidcs 889316485Sdavidcs/* 890316485Sdavidcs * Debug GRC params 891316485Sdavidcs */ 892316485Sdavidcsenum dbg_grc_params 893316485Sdavidcs{ 894316485Sdavidcs DBG_GRC_PARAM_DUMP_TSTORM /* dump Tstorm memories (0/1) */, 895316485Sdavidcs DBG_GRC_PARAM_DUMP_MSTORM /* dump Mstorm memories (0/1) */, 896316485Sdavidcs DBG_GRC_PARAM_DUMP_USTORM /* dump Ustorm memories (0/1) */, 897316485Sdavidcs DBG_GRC_PARAM_DUMP_XSTORM /* dump Xstorm memories (0/1) */, 898316485Sdavidcs DBG_GRC_PARAM_DUMP_YSTORM /* dump Ystorm memories (0/1) */, 899316485Sdavidcs DBG_GRC_PARAM_DUMP_PSTORM /* dump Pstorm memories (0/1) */, 900316485Sdavidcs DBG_GRC_PARAM_DUMP_REGS /* dump non-memory registers (0/1) */, 901316485Sdavidcs DBG_GRC_PARAM_DUMP_RAM /* dump Storm internal RAMs (0/1) */, 902316485Sdavidcs DBG_GRC_PARAM_DUMP_PBUF /* dump Storm passive buffer (0/1) */, 903316485Sdavidcs DBG_GRC_PARAM_DUMP_IOR /* dump Storm IORs (0/1) */, 904316485Sdavidcs DBG_GRC_PARAM_DUMP_VFC /* dump VFC memories (0/1) */, 905316485Sdavidcs DBG_GRC_PARAM_DUMP_CM_CTX /* dump CM contexts (0/1) */, 906316485Sdavidcs DBG_GRC_PARAM_DUMP_PXP /* dump PXP memories (0/1) */, 907316485Sdavidcs DBG_GRC_PARAM_DUMP_RSS /* dump RSS memories (0/1) */, 908316485Sdavidcs DBG_GRC_PARAM_DUMP_CAU /* dump CAU memories (0/1) */, 909316485Sdavidcs DBG_GRC_PARAM_DUMP_QM /* dump QM memories (0/1) */, 910316485Sdavidcs DBG_GRC_PARAM_DUMP_MCP /* dump MCP memories (0/1) */, 911316485Sdavidcs DBG_GRC_PARAM_RESERVED /* reserved */, 912316485Sdavidcs DBG_GRC_PARAM_DUMP_CFC /* dump CFC memories (0/1) */, 913316485Sdavidcs DBG_GRC_PARAM_DUMP_IGU /* dump IGU memories (0/1) */, 914316485Sdavidcs DBG_GRC_PARAM_DUMP_BRB /* dump BRB memories (0/1) */, 915316485Sdavidcs DBG_GRC_PARAM_DUMP_BTB /* dump BTB memories (0/1) */, 916316485Sdavidcs DBG_GRC_PARAM_DUMP_BMB /* dump BMB memories (0/1) */, 917316485Sdavidcs DBG_GRC_PARAM_DUMP_NIG /* dump NIG memories (0/1) */, 918316485Sdavidcs DBG_GRC_PARAM_DUMP_MULD /* dump MULD memories (0/1) */, 919316485Sdavidcs DBG_GRC_PARAM_DUMP_PRS /* dump PRS memories (0/1) */, 920316485Sdavidcs DBG_GRC_PARAM_DUMP_DMAE /* dump PRS memories (0/1) */, 921316485Sdavidcs DBG_GRC_PARAM_DUMP_TM /* dump TM (timers) memories (0/1) */, 922316485Sdavidcs DBG_GRC_PARAM_DUMP_SDM /* dump SDM memories (0/1) */, 923316485Sdavidcs DBG_GRC_PARAM_DUMP_DIF /* dump DIF memories (0/1) */, 924316485Sdavidcs DBG_GRC_PARAM_DUMP_STATIC /* dump static debug data (0/1) */, 925316485Sdavidcs DBG_GRC_PARAM_UNSTALL /* un-stall Storms after dump (0/1) */, 926316485Sdavidcs DBG_GRC_PARAM_NUM_LCIDS /* number of LCIDs (0..320) */, 927316485Sdavidcs DBG_GRC_PARAM_NUM_LTIDS /* number of LTIDs (0..320) */, 928316485Sdavidcs DBG_GRC_PARAM_EXCLUDE_ALL /* preset: exclude all memories from dump (1 only) */, 929316485Sdavidcs DBG_GRC_PARAM_CRASH /* preset: include memories for crash dump (1 only) */, 930316485Sdavidcs DBG_GRC_PARAM_PARITY_SAFE /* perform dump only if MFW is responding (0/1) */, 931316485Sdavidcs DBG_GRC_PARAM_DUMP_CM /* dump CM memories (0/1) */, 932316485Sdavidcs DBG_GRC_PARAM_DUMP_PHY /* dump PHY memories (0/1) */, 933316485Sdavidcs DBG_GRC_PARAM_NO_MCP /* dont perform MCP commands (0/1) */, 934316485Sdavidcs DBG_GRC_PARAM_NO_FW_VER /* dont read FW/MFW version (0/1) */, 935316485Sdavidcs MAX_DBG_GRC_PARAMS 936316485Sdavidcs}; 937316485Sdavidcs 938316485Sdavidcs 939316485Sdavidcs/* 940316485Sdavidcs * Debug reset registers 941316485Sdavidcs */ 942316485Sdavidcsenum dbg_reset_regs 943316485Sdavidcs{ 944316485Sdavidcs DBG_RESET_REG_MISCS_PL_UA, 945316485Sdavidcs DBG_RESET_REG_MISCS_PL_HV, 946316485Sdavidcs DBG_RESET_REG_MISCS_PL_HV_2, 947316485Sdavidcs DBG_RESET_REG_MISC_PL_UA, 948316485Sdavidcs DBG_RESET_REG_MISC_PL_HV, 949316485Sdavidcs DBG_RESET_REG_MISC_PL_PDA_VMAIN_1, 950316485Sdavidcs DBG_RESET_REG_MISC_PL_PDA_VMAIN_2, 951316485Sdavidcs DBG_RESET_REG_MISC_PL_PDA_VAUX, 952316485Sdavidcs MAX_DBG_RESET_REGS 953316485Sdavidcs}; 954316485Sdavidcs 955316485Sdavidcs 956316485Sdavidcs/* 957316485Sdavidcs * Debug status codes 958316485Sdavidcs */ 959316485Sdavidcsenum dbg_status 960316485Sdavidcs{ 961316485Sdavidcs DBG_STATUS_OK, 962316485Sdavidcs DBG_STATUS_APP_VERSION_NOT_SET, 963316485Sdavidcs DBG_STATUS_UNSUPPORTED_APP_VERSION, 964316485Sdavidcs DBG_STATUS_DBG_BLOCK_NOT_RESET, 965316485Sdavidcs DBG_STATUS_INVALID_ARGS, 966316485Sdavidcs DBG_STATUS_OUTPUT_ALREADY_SET, 967316485Sdavidcs DBG_STATUS_INVALID_PCI_BUF_SIZE, 968316485Sdavidcs DBG_STATUS_PCI_BUF_ALLOC_FAILED, 969316485Sdavidcs DBG_STATUS_PCI_BUF_NOT_ALLOCATED, 970316485Sdavidcs DBG_STATUS_TOO_MANY_INPUTS, 971316485Sdavidcs DBG_STATUS_INPUT_OVERLAP, 972316485Sdavidcs DBG_STATUS_HW_ONLY_RECORDING, 973316485Sdavidcs DBG_STATUS_STORM_ALREADY_ENABLED, 974316485Sdavidcs DBG_STATUS_STORM_NOT_ENABLED, 975316485Sdavidcs DBG_STATUS_BLOCK_ALREADY_ENABLED, 976316485Sdavidcs DBG_STATUS_BLOCK_NOT_ENABLED, 977316485Sdavidcs DBG_STATUS_NO_INPUT_ENABLED, 978316485Sdavidcs DBG_STATUS_NO_FILTER_TRIGGER_64B, 979316485Sdavidcs DBG_STATUS_FILTER_ALREADY_ENABLED, 980316485Sdavidcs DBG_STATUS_TRIGGER_ALREADY_ENABLED, 981316485Sdavidcs DBG_STATUS_TRIGGER_NOT_ENABLED, 982316485Sdavidcs DBG_STATUS_CANT_ADD_CONSTRAINT, 983316485Sdavidcs DBG_STATUS_TOO_MANY_TRIGGER_STATES, 984316485Sdavidcs DBG_STATUS_TOO_MANY_CONSTRAINTS, 985316485Sdavidcs DBG_STATUS_RECORDING_NOT_STARTED, 986316485Sdavidcs DBG_STATUS_DATA_DIDNT_TRIGGER, 987316485Sdavidcs DBG_STATUS_NO_DATA_RECORDED, 988316485Sdavidcs DBG_STATUS_DUMP_BUF_TOO_SMALL, 989316485Sdavidcs DBG_STATUS_DUMP_NOT_CHUNK_ALIGNED, 990316485Sdavidcs DBG_STATUS_UNKNOWN_CHIP, 991316485Sdavidcs DBG_STATUS_VIRT_MEM_ALLOC_FAILED, 992316485Sdavidcs DBG_STATUS_BLOCK_IN_RESET, 993316485Sdavidcs DBG_STATUS_INVALID_TRACE_SIGNATURE, 994316485Sdavidcs DBG_STATUS_INVALID_NVRAM_BUNDLE, 995316485Sdavidcs DBG_STATUS_NVRAM_GET_IMAGE_FAILED, 996316485Sdavidcs DBG_STATUS_NON_ALIGNED_NVRAM_IMAGE, 997316485Sdavidcs DBG_STATUS_NVRAM_READ_FAILED, 998316485Sdavidcs DBG_STATUS_IDLE_CHK_PARSE_FAILED, 999316485Sdavidcs DBG_STATUS_MCP_TRACE_BAD_DATA, 1000316485Sdavidcs DBG_STATUS_MCP_TRACE_NO_META, 1001316485Sdavidcs DBG_STATUS_MCP_COULD_NOT_HALT, 1002316485Sdavidcs DBG_STATUS_MCP_COULD_NOT_RESUME, 1003337519Sdavidcs DBG_STATUS_RESERVED2, 1004316485Sdavidcs DBG_STATUS_SEMI_FIFO_NOT_EMPTY, 1005316485Sdavidcs DBG_STATUS_IGU_FIFO_BAD_DATA, 1006316485Sdavidcs DBG_STATUS_MCP_COULD_NOT_MASK_PRTY, 1007316485Sdavidcs DBG_STATUS_FW_ASSERTS_PARSE_FAILED, 1008316485Sdavidcs DBG_STATUS_REG_FIFO_BAD_DATA, 1009316485Sdavidcs DBG_STATUS_PROTECTION_OVERRIDE_BAD_DATA, 1010316485Sdavidcs DBG_STATUS_DBG_ARRAY_NOT_SET, 1011316485Sdavidcs DBG_STATUS_FILTER_BUG, 1012316485Sdavidcs DBG_STATUS_NON_MATCHING_LINES, 1013316485Sdavidcs DBG_STATUS_INVALID_TRIGGER_DWORD_OFFSET, 1014316485Sdavidcs DBG_STATUS_DBG_BUS_IN_USE, 1015316485Sdavidcs MAX_DBG_STATUS 1016316485Sdavidcs}; 1017316485Sdavidcs 1018316485Sdavidcs 1019316485Sdavidcs/* 1020316485Sdavidcs * Debug Storms IDs 1021316485Sdavidcs */ 1022316485Sdavidcsenum dbg_storms 1023316485Sdavidcs{ 1024316485Sdavidcs DBG_TSTORM_ID, 1025316485Sdavidcs DBG_MSTORM_ID, 1026316485Sdavidcs DBG_USTORM_ID, 1027316485Sdavidcs DBG_XSTORM_ID, 1028316485Sdavidcs DBG_YSTORM_ID, 1029316485Sdavidcs DBG_PSTORM_ID, 1030316485Sdavidcs MAX_DBG_STORMS 1031316485Sdavidcs}; 1032316485Sdavidcs 1033316485Sdavidcs 1034316485Sdavidcs/* 1035316485Sdavidcs * Idle Check data 1036316485Sdavidcs */ 1037316485Sdavidcsstruct idle_chk_data 1038316485Sdavidcs{ 1039337519Sdavidcs u32 buf_size /* Idle check buffer size in dwords */; 1040316485Sdavidcs u8 buf_size_set /* Indicates if the idle check buffer size was set (0/1) */; 1041316485Sdavidcs u8 reserved1; 1042337519Sdavidcs u16 reserved2; 1043316485Sdavidcs}; 1044316485Sdavidcs 1045316485Sdavidcs/* 1046316485Sdavidcs * Debug Tools data (per HW function) 1047316485Sdavidcs */ 1048316485Sdavidcsstruct dbg_tools_data 1049316485Sdavidcs{ 1050316485Sdavidcs struct dbg_grc_data grc /* GRC Dump data */; 1051316485Sdavidcs struct dbg_bus_data bus /* Debug Bus data */; 1052316485Sdavidcs struct idle_chk_data idle_chk /* Idle Check data */; 1053316485Sdavidcs u8 mode_enable[40] /* Indicates if a mode is enabled (0/1) */; 1054316485Sdavidcs u8 block_in_reset[88] /* Indicates if a block is in reset state (0/1) */; 1055316485Sdavidcs u8 chip_id /* Chip ID (from enum chip_ids) */; 1056316485Sdavidcs u8 platform_id /* Platform ID */; 1057316485Sdavidcs u8 initialized /* Indicates if the data was initialized */; 1058337519Sdavidcs u8 use_dmae /* Indicates if DMAE should be used */; 1059337519Sdavidcs u32 num_regs_read /* Numbers of registers that were read since last log */; 1060316485Sdavidcs}; 1061316485Sdavidcs 1062316485Sdavidcs 1063316485Sdavidcs#endif /* __ECORE_HSI_DEBUG_TOOLS__ */ 1064