1316485Sdavidcs/* 2316485Sdavidcs * Copyright (c) 2017-2018 Cavium, Inc. 3316485Sdavidcs * All rights reserved. 4316485Sdavidcs * 5316485Sdavidcs * Redistribution and use in source and binary forms, with or without 6316485Sdavidcs * modification, are permitted provided that the following conditions 7316485Sdavidcs * are met: 8316485Sdavidcs * 9316485Sdavidcs * 1. Redistributions of source code must retain the above copyright 10316485Sdavidcs * notice, this list of conditions and the following disclaimer. 11316485Sdavidcs * 2. Redistributions in binary form must reproduce the above copyright 12316485Sdavidcs * notice, this list of conditions and the following disclaimer in the 13316485Sdavidcs * documentation and/or other materials provided with the distribution. 14316485Sdavidcs * 15316485Sdavidcs * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 16316485Sdavidcs * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17316485Sdavidcs * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18316485Sdavidcs * ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 19316485Sdavidcs * LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 20316485Sdavidcs * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 21316485Sdavidcs * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 22316485Sdavidcs * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 23316485Sdavidcs * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 24316485Sdavidcs * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 25316485Sdavidcs * POSSIBILITY OF SUCH DAMAGE. 26316485Sdavidcs * 27316485Sdavidcs * $FreeBSD: stable/10/sys/dev/qlnx/qlnxe/ecore_hsi_common.h 337519 2018-08-09 01:39:47Z davidcs $ 28316485Sdavidcs * 29316485Sdavidcs */ 30316485Sdavidcs 31316485Sdavidcs#ifndef __ECORE_HSI_COMMON__ 32316485Sdavidcs#define __ECORE_HSI_COMMON__ 33316485Sdavidcs/********************************/ 34316485Sdavidcs/* Add include to common target */ 35316485Sdavidcs/********************************/ 36316485Sdavidcs#include "common_hsi.h" 37316485Sdavidcs 38316485Sdavidcs 39316485Sdavidcs/* 40316485Sdavidcs * opcodes for the event ring 41316485Sdavidcs */ 42316485Sdavidcsenum common_event_opcode 43316485Sdavidcs{ 44316485Sdavidcs COMMON_EVENT_PF_START, 45316485Sdavidcs COMMON_EVENT_PF_STOP, 46316485Sdavidcs COMMON_EVENT_VF_START, 47316485Sdavidcs COMMON_EVENT_VF_STOP, 48316485Sdavidcs COMMON_EVENT_VF_PF_CHANNEL, 49316485Sdavidcs COMMON_EVENT_VF_FLR, 50316485Sdavidcs COMMON_EVENT_PF_UPDATE, 51316485Sdavidcs COMMON_EVENT_MALICIOUS_VF, 52316485Sdavidcs COMMON_EVENT_RL_UPDATE, 53316485Sdavidcs COMMON_EVENT_EMPTY, 54316485Sdavidcs MAX_COMMON_EVENT_OPCODE 55316485Sdavidcs}; 56316485Sdavidcs 57316485Sdavidcs 58316485Sdavidcs/* 59316485Sdavidcs * Common Ramrod Command IDs 60316485Sdavidcs */ 61316485Sdavidcsenum common_ramrod_cmd_id 62316485Sdavidcs{ 63316485Sdavidcs COMMON_RAMROD_UNUSED, 64316485Sdavidcs COMMON_RAMROD_PF_START /* PF Function Start Ramrod */, 65316485Sdavidcs COMMON_RAMROD_PF_STOP /* PF Function Stop Ramrod */, 66316485Sdavidcs COMMON_RAMROD_VF_START /* VF Function Start */, 67316485Sdavidcs COMMON_RAMROD_VF_STOP /* VF Function Stop Ramrod */, 68316485Sdavidcs COMMON_RAMROD_PF_UPDATE /* PF update Ramrod */, 69316485Sdavidcs COMMON_RAMROD_RL_UPDATE /* QCN/DCQCN RL update Ramrod */, 70316485Sdavidcs COMMON_RAMROD_EMPTY /* Empty Ramrod */, 71316485Sdavidcs MAX_COMMON_RAMROD_CMD_ID 72316485Sdavidcs}; 73316485Sdavidcs 74316485Sdavidcs 75316485Sdavidcs/* 76320162Sdavidcs * How ll2 should deal with packet upon errors 77320162Sdavidcs */ 78320162Sdavidcsenum core_error_handle 79320162Sdavidcs{ 80320162Sdavidcs LL2_DROP_PACKET /* If error occurs drop packet */, 81320162Sdavidcs LL2_DO_NOTHING /* If error occurs do nothing */, 82320162Sdavidcs LL2_ASSERT /* If error occurs assert */, 83320162Sdavidcs MAX_CORE_ERROR_HANDLE 84320162Sdavidcs}; 85320162Sdavidcs 86320162Sdavidcs 87320162Sdavidcs/* 88320162Sdavidcs * opcodes for the event ring 89320162Sdavidcs */ 90320162Sdavidcsenum core_event_opcode 91320162Sdavidcs{ 92320162Sdavidcs CORE_EVENT_TX_QUEUE_START, 93320162Sdavidcs CORE_EVENT_TX_QUEUE_STOP, 94320162Sdavidcs CORE_EVENT_RX_QUEUE_START, 95320162Sdavidcs CORE_EVENT_RX_QUEUE_STOP, 96320162Sdavidcs CORE_EVENT_RX_QUEUE_FLUSH, 97337519Sdavidcs CORE_EVENT_TX_QUEUE_UPDATE, 98320162Sdavidcs MAX_CORE_EVENT_OPCODE 99320162Sdavidcs}; 100320162Sdavidcs 101320162Sdavidcs 102320162Sdavidcs/* 103320162Sdavidcs * The L4 pseudo checksum mode for Core 104320162Sdavidcs */ 105320162Sdavidcsenum core_l4_pseudo_checksum_mode 106320162Sdavidcs{ 107320162Sdavidcs CORE_L4_PSEUDO_CSUM_CORRECT_LENGTH /* Pseudo Checksum on packet is calculated with the correct packet length. */, 108320162Sdavidcs CORE_L4_PSEUDO_CSUM_ZERO_LENGTH /* Pseudo Checksum on packet is calculated with zero length. */, 109320162Sdavidcs MAX_CORE_L4_PSEUDO_CHECKSUM_MODE 110320162Sdavidcs}; 111320162Sdavidcs 112320162Sdavidcs 113320162Sdavidcs/* 114320162Sdavidcs * Light-L2 RX Producers in Tstorm RAM 115320162Sdavidcs */ 116320162Sdavidcsstruct core_ll2_port_stats 117320162Sdavidcs{ 118320162Sdavidcs struct regpair gsi_invalid_hdr; 119320162Sdavidcs struct regpair gsi_invalid_pkt_length; 120320162Sdavidcs struct regpair gsi_unsupported_pkt_typ; 121320162Sdavidcs struct regpair gsi_crcchksm_error; 122320162Sdavidcs}; 123320162Sdavidcs 124320162Sdavidcs 125320162Sdavidcs/* 126320162Sdavidcs * Ethernet TX Per Queue Stats 127320162Sdavidcs */ 128320162Sdavidcsstruct core_ll2_pstorm_per_queue_stat 129320162Sdavidcs{ 130320162Sdavidcs struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 131320162Sdavidcs struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 132320162Sdavidcs struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 133320162Sdavidcs struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 134320162Sdavidcs struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 135320162Sdavidcs struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 136320162Sdavidcs}; 137320162Sdavidcs 138320162Sdavidcs 139320162Sdavidcs/* 140320162Sdavidcs * Light-L2 RX Producers in Tstorm RAM 141320162Sdavidcs */ 142320162Sdavidcsstruct core_ll2_rx_prod 143320162Sdavidcs{ 144320162Sdavidcs __le16 bd_prod /* BD Producer */; 145320162Sdavidcs __le16 cqe_prod /* CQE Producer */; 146320162Sdavidcs __le32 reserved; 147320162Sdavidcs}; 148320162Sdavidcs 149320162Sdavidcs 150320162Sdavidcsstruct core_ll2_tstorm_per_queue_stat 151320162Sdavidcs{ 152320162Sdavidcs struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 153320162Sdavidcs struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers */; 154320162Sdavidcs}; 155320162Sdavidcs 156320162Sdavidcs 157320162Sdavidcsstruct core_ll2_ustorm_per_queue_stat 158320162Sdavidcs{ 159320162Sdavidcs struct regpair rcv_ucast_bytes; 160320162Sdavidcs struct regpair rcv_mcast_bytes; 161320162Sdavidcs struct regpair rcv_bcast_bytes; 162320162Sdavidcs struct regpair rcv_ucast_pkts; 163320162Sdavidcs struct regpair rcv_mcast_pkts; 164320162Sdavidcs struct regpair rcv_bcast_pkts; 165320162Sdavidcs}; 166320162Sdavidcs 167320162Sdavidcs 168320162Sdavidcs/* 169320162Sdavidcs * Core Ramrod Command IDs (light L2) 170320162Sdavidcs */ 171320162Sdavidcsenum core_ramrod_cmd_id 172320162Sdavidcs{ 173320162Sdavidcs CORE_RAMROD_UNUSED, 174320162Sdavidcs CORE_RAMROD_RX_QUEUE_START /* RX Queue Start Ramrod */, 175320162Sdavidcs CORE_RAMROD_TX_QUEUE_START /* TX Queue Start Ramrod */, 176320162Sdavidcs CORE_RAMROD_RX_QUEUE_STOP /* RX Queue Stop Ramrod */, 177320162Sdavidcs CORE_RAMROD_TX_QUEUE_STOP /* TX Queue Stop Ramrod */, 178320162Sdavidcs CORE_RAMROD_RX_QUEUE_FLUSH /* RX Flush queue Ramrod */, 179337519Sdavidcs CORE_RAMROD_TX_QUEUE_UPDATE /* TX Queue Update Ramrod */, 180320162Sdavidcs MAX_CORE_RAMROD_CMD_ID 181320162Sdavidcs}; 182320162Sdavidcs 183320162Sdavidcs 184320162Sdavidcs/* 185320162Sdavidcs * Core RX CQE Type for Light L2 186320162Sdavidcs */ 187320162Sdavidcsenum core_roce_flavor_type 188320162Sdavidcs{ 189320162Sdavidcs CORE_ROCE, 190320162Sdavidcs CORE_RROCE, 191320162Sdavidcs MAX_CORE_ROCE_FLAVOR_TYPE 192320162Sdavidcs}; 193320162Sdavidcs 194320162Sdavidcs 195320162Sdavidcs/* 196320162Sdavidcs * Specifies how ll2 should deal with packets errors: packet_too_big and no_buff 197320162Sdavidcs */ 198320162Sdavidcsstruct core_rx_action_on_error 199320162Sdavidcs{ 200320162Sdavidcs u8 error_type; 201320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_MASK 0x3 /* ll2 how to handle error packet_too_big (use enum core_error_handle) */ 202320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_PACKET_TOO_BIG_SHIFT 0 203320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_MASK 0x3 /* ll2 how to handle error with no_buff (use enum core_error_handle) */ 204320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_NO_BUFF_SHIFT 2 205320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_RESERVED_MASK 0xF 206320162Sdavidcs#define CORE_RX_ACTION_ON_ERROR_RESERVED_SHIFT 4 207320162Sdavidcs}; 208320162Sdavidcs 209320162Sdavidcs 210320162Sdavidcs/* 211320162Sdavidcs * Core RX BD for Light L2 212320162Sdavidcs */ 213320162Sdavidcsstruct core_rx_bd 214320162Sdavidcs{ 215320162Sdavidcs struct regpair addr; 216320162Sdavidcs __le16 reserved[4]; 217320162Sdavidcs}; 218320162Sdavidcs 219320162Sdavidcs 220320162Sdavidcs/* 221320162Sdavidcs * Core RX CM offload BD for Light L2 222320162Sdavidcs */ 223320162Sdavidcsstruct core_rx_bd_with_buff_len 224320162Sdavidcs{ 225320162Sdavidcs struct regpair addr; 226320162Sdavidcs __le16 buff_length; 227320162Sdavidcs __le16 reserved[3]; 228320162Sdavidcs}; 229320162Sdavidcs 230320162Sdavidcs/* 231320162Sdavidcs * Core RX CM offload BD for Light L2 232320162Sdavidcs */ 233320162Sdavidcsunion core_rx_bd_union 234320162Sdavidcs{ 235320162Sdavidcs struct core_rx_bd rx_bd /* Core Rx Bd static buffer size */; 236320162Sdavidcs struct core_rx_bd_with_buff_len rx_bd_with_len /* Core Rx Bd with dynamic buffer length */; 237320162Sdavidcs}; 238320162Sdavidcs 239320162Sdavidcs 240320162Sdavidcs 241320162Sdavidcs/* 242320162Sdavidcs * Opaque Data for Light L2 RX CQE . 243320162Sdavidcs */ 244320162Sdavidcsstruct core_rx_cqe_opaque_data 245320162Sdavidcs{ 246320162Sdavidcs __le32 data[2] /* Opaque CQE Data */; 247320162Sdavidcs}; 248320162Sdavidcs 249320162Sdavidcs 250320162Sdavidcs/* 251320162Sdavidcs * Core RX CQE Type for Light L2 252320162Sdavidcs */ 253320162Sdavidcsenum core_rx_cqe_type 254320162Sdavidcs{ 255320162Sdavidcs CORE_RX_CQE_ILLIGAL_TYPE /* Bad RX Cqe type */, 256320162Sdavidcs CORE_RX_CQE_TYPE_REGULAR /* Regular Core RX CQE */, 257320162Sdavidcs CORE_RX_CQE_TYPE_GSI_OFFLOAD /* Fp Gsi offload RX CQE */, 258320162Sdavidcs CORE_RX_CQE_TYPE_SLOW_PATH /* Slow path Core RX CQE */, 259320162Sdavidcs MAX_CORE_RX_CQE_TYPE 260320162Sdavidcs}; 261320162Sdavidcs 262320162Sdavidcs 263320162Sdavidcs/* 264320162Sdavidcs * Core RX CQE for Light L2 . 265320162Sdavidcs */ 266320162Sdavidcsstruct core_rx_fast_path_cqe 267320162Sdavidcs{ 268337519Sdavidcs u8 type /* CQE type (use enum core_rx_cqe_type) */; 269320162Sdavidcs u8 placement_offset /* Offset (in bytes) of the packet from start of the buffer */; 270320162Sdavidcs struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 271320162Sdavidcs __le16 packet_length /* Total packet length (from the parser) */; 272320162Sdavidcs __le16 vlan /* 802.1q VLAN tag */; 273320162Sdavidcs struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 274320162Sdavidcs struct parsing_err_flags err_flags /* bit- map: each bit represents a specific error. errors indications are provided by the cracker. see spec for detailed description */; 275320162Sdavidcs __le16 reserved0; 276320162Sdavidcs __le32 reserved1[3]; 277320162Sdavidcs}; 278320162Sdavidcs 279320162Sdavidcs/* 280320162Sdavidcs * Core Rx CM offload CQE . 281320162Sdavidcs */ 282320162Sdavidcsstruct core_rx_gsi_offload_cqe 283320162Sdavidcs{ 284337519Sdavidcs u8 type /* CQE type (use enum core_rx_cqe_type) */; 285320162Sdavidcs u8 data_length_error /* set if gsi data is bigger than buff */; 286320162Sdavidcs struct parsing_and_err_flags parse_flags /* Parsing and error flags from the parser */; 287320162Sdavidcs __le16 data_length /* Total packet length (from the parser) */; 288320162Sdavidcs __le16 vlan /* 802.1q VLAN tag */; 289320162Sdavidcs __le32 src_mac_addrhi /* hi 4 bytes source mac address */; 290320162Sdavidcs __le16 src_mac_addrlo /* lo 2 bytes of source mac address */; 291320162Sdavidcs __le16 qp_id /* These are the lower 16 bit of QP id in RoCE BTH header */; 292337519Sdavidcs __le32 src_qp /* Source QP from DETH header */; 293337519Sdavidcs __le32 reserved[3]; 294320162Sdavidcs}; 295320162Sdavidcs 296320162Sdavidcs/* 297320162Sdavidcs * Core RX CQE for Light L2 . 298320162Sdavidcs */ 299320162Sdavidcsstruct core_rx_slow_path_cqe 300320162Sdavidcs{ 301337519Sdavidcs u8 type /* CQE type (use enum core_rx_cqe_type) */; 302320162Sdavidcs u8 ramrod_cmd_id; 303320162Sdavidcs __le16 echo; 304320162Sdavidcs struct core_rx_cqe_opaque_data opaque_data /* Opaque Data */; 305320162Sdavidcs __le32 reserved1[5]; 306320162Sdavidcs}; 307320162Sdavidcs 308320162Sdavidcs/* 309320162Sdavidcs * Core RX CM offload BD for Light L2 310320162Sdavidcs */ 311320162Sdavidcsunion core_rx_cqe_union 312320162Sdavidcs{ 313320162Sdavidcs struct core_rx_fast_path_cqe rx_cqe_fp /* Fast path CQE */; 314320162Sdavidcs struct core_rx_gsi_offload_cqe rx_cqe_gsi /* GSI offload CQE */; 315320162Sdavidcs struct core_rx_slow_path_cqe rx_cqe_sp /* Slow path CQE */; 316320162Sdavidcs}; 317320162Sdavidcs 318320162Sdavidcs 319320162Sdavidcs 320320162Sdavidcs 321320162Sdavidcs 322320162Sdavidcs/* 323320162Sdavidcs * Ramrod data for rx queue start ramrod 324320162Sdavidcs */ 325320162Sdavidcsstruct core_rx_start_ramrod_data 326320162Sdavidcs{ 327320162Sdavidcs struct regpair bd_base /* bd address of the first bd page */; 328320162Sdavidcs struct regpair cqe_pbl_addr /* Base address on host of CQE PBL */; 329320162Sdavidcs __le16 mtu /* Maximum transmission unit */; 330320162Sdavidcs __le16 sb_id /* Status block ID */; 331320162Sdavidcs u8 sb_index /* index of the protocol index */; 332320162Sdavidcs u8 complete_cqe_flg /* post completion to the CQE ring if set */; 333320162Sdavidcs u8 complete_event_flg /* post completion to the event ring if set */; 334320162Sdavidcs u8 drop_ttl0_flg /* drop packet with ttl0 if set */; 335320162Sdavidcs __le16 num_of_pbl_pages /* Num of pages in CQE PBL */; 336337519Sdavidcs u8 inner_vlan_stripping_en /* if set, 802.1q tags will be removed and copied to CQE */; 337337519Sdavidcs u8 report_outer_vlan /* if set and inner vlan does not exist, the outer vlan will copied to CQE as inner vlan. should be used in MF_OVLAN mode only. */; 338320162Sdavidcs u8 queue_id /* Light L2 RX Queue ID */; 339320162Sdavidcs u8 main_func_queue /* Is this the main queue for the PF */; 340320162Sdavidcs u8 mf_si_bcast_accept_all /* Duplicate broadcast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 341320162Sdavidcs u8 mf_si_mcast_accept_all /* Duplicate multicast packets to LL2 main queue in mf_si mode. Valid if main_func_queue is set. */; 342320162Sdavidcs struct core_rx_action_on_error action_on_error /* Specifies how ll2 should deal with packets errors: packet_too_big and no_buff */; 343320162Sdavidcs u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 344337519Sdavidcs u8 reserved[6]; 345320162Sdavidcs}; 346320162Sdavidcs 347320162Sdavidcs 348320162Sdavidcs/* 349320162Sdavidcs * Ramrod data for rx queue stop ramrod 350320162Sdavidcs */ 351320162Sdavidcsstruct core_rx_stop_ramrod_data 352320162Sdavidcs{ 353320162Sdavidcs u8 complete_cqe_flg /* post completion to the CQE ring if set */; 354320162Sdavidcs u8 complete_event_flg /* post completion to the event ring if set */; 355320162Sdavidcs u8 queue_id /* Light L2 RX Queue ID */; 356320162Sdavidcs u8 reserved1; 357320162Sdavidcs __le16 reserved2[2]; 358320162Sdavidcs}; 359320162Sdavidcs 360320162Sdavidcs 361320162Sdavidcs/* 362320162Sdavidcs * Flags for Core TX BD 363320162Sdavidcs */ 364320162Sdavidcsstruct core_tx_bd_data 365320162Sdavidcs{ 366320162Sdavidcs __le16 as_bitfield; 367337519Sdavidcs#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_MASK 0x1 /* Do not allow additional VLAN manipulations on this packet (DCB) */ 368337519Sdavidcs#define CORE_TX_BD_DATA_FORCE_VLAN_MODE_SHIFT 0 369337519Sdavidcs#define CORE_TX_BD_DATA_VLAN_INSERTION_MASK 0x1 /* Insert VLAN into packet. Cannot be set for LB packets (tx_dst == CORE_TX_DEST_LB) */ 370337519Sdavidcs#define CORE_TX_BD_DATA_VLAN_INSERTION_SHIFT 1 371337519Sdavidcs#define CORE_TX_BD_DATA_START_BD_MASK 0x1 /* This is the first BD of the packet (for debug) */ 372337519Sdavidcs#define CORE_TX_BD_DATA_START_BD_SHIFT 2 373337519Sdavidcs#define CORE_TX_BD_DATA_IP_CSUM_MASK 0x1 /* Calculate the IP checksum for the packet */ 374337519Sdavidcs#define CORE_TX_BD_DATA_IP_CSUM_SHIFT 3 375337519Sdavidcs#define CORE_TX_BD_DATA_L4_CSUM_MASK 0x1 /* Calculate the L4 checksum for the packet */ 376337519Sdavidcs#define CORE_TX_BD_DATA_L4_CSUM_SHIFT 4 377337519Sdavidcs#define CORE_TX_BD_DATA_IPV6_EXT_MASK 0x1 /* Packet is IPv6 with extensions */ 378337519Sdavidcs#define CORE_TX_BD_DATA_IPV6_EXT_SHIFT 5 379337519Sdavidcs#define CORE_TX_BD_DATA_L4_PROTOCOL_MASK 0x1 /* If IPv6+ext, and if l4_csum is 1, than this field indicates L4 protocol: 0-TCP, 1-UDP */ 380337519Sdavidcs#define CORE_TX_BD_DATA_L4_PROTOCOL_SHIFT 6 381337519Sdavidcs#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_MASK 0x1 /* The pseudo checksum mode to place in the L4 checksum field. Required only when IPv6+ext and l4_csum is set. (use enum core_l4_pseudo_checksum_mode) */ 382337519Sdavidcs#define CORE_TX_BD_DATA_L4_PSEUDO_CSUM_MODE_SHIFT 7 383337519Sdavidcs#define CORE_TX_BD_DATA_NBDS_MASK 0xF /* Number of BDs that make up one packet - width wide enough to present CORE_LL2_TX_MAX_BDS_PER_PACKET */ 384337519Sdavidcs#define CORE_TX_BD_DATA_NBDS_SHIFT 8 385337519Sdavidcs#define CORE_TX_BD_DATA_ROCE_FLAV_MASK 0x1 /* Use roce_flavor enum - Differentiate between Roce flavors is valid when connType is ROCE (use enum core_roce_flavor_type) */ 386337519Sdavidcs#define CORE_TX_BD_DATA_ROCE_FLAV_SHIFT 12 387337519Sdavidcs#define CORE_TX_BD_DATA_IP_LEN_MASK 0x1 /* Calculate ip length */ 388337519Sdavidcs#define CORE_TX_BD_DATA_IP_LEN_SHIFT 13 389337519Sdavidcs#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_MASK 0x1 /* disables the STAG insertion, relevant only in MF OVLAN mode. */ 390337519Sdavidcs#define CORE_TX_BD_DATA_DISABLE_STAG_INSERTION_SHIFT 14 391337519Sdavidcs#define CORE_TX_BD_DATA_RESERVED0_MASK 0x1 392337519Sdavidcs#define CORE_TX_BD_DATA_RESERVED0_SHIFT 15 393320162Sdavidcs}; 394320162Sdavidcs 395320162Sdavidcs/* 396320162Sdavidcs * Core TX BD for Light L2 397320162Sdavidcs */ 398320162Sdavidcsstruct core_tx_bd 399320162Sdavidcs{ 400320162Sdavidcs struct regpair addr /* Buffer Address */; 401320162Sdavidcs __le16 nbytes /* Number of Bytes in Buffer */; 402320162Sdavidcs __le16 nw_vlan_or_lb_echo /* Network packets: VLAN to insert to packet (if insertion flag set) LoopBack packets: echo data to pass to Rx */; 403320162Sdavidcs struct core_tx_bd_data bd_data /* BD flags */; 404320162Sdavidcs __le16 bitfield1; 405320162Sdavidcs#define CORE_TX_BD_L4_HDR_OFFSET_W_MASK 0x3FFF /* L4 Header Offset from start of packet (in Words). This is needed if both l4_csum and ipv6_ext are set */ 406320162Sdavidcs#define CORE_TX_BD_L4_HDR_OFFSET_W_SHIFT 0 407320162Sdavidcs#define CORE_TX_BD_TX_DST_MASK 0x3 /* Packet destination - Network, Loopback or Drop (use enum core_tx_dest) */ 408320162Sdavidcs#define CORE_TX_BD_TX_DST_SHIFT 14 409320162Sdavidcs}; 410320162Sdavidcs 411320162Sdavidcs 412320162Sdavidcs 413320162Sdavidcs/* 414320162Sdavidcs * Light L2 TX Destination 415320162Sdavidcs */ 416320162Sdavidcsenum core_tx_dest 417320162Sdavidcs{ 418320162Sdavidcs CORE_TX_DEST_NW /* TX Destination to the Network */, 419320162Sdavidcs CORE_TX_DEST_LB /* TX Destination to the Loopback */, 420320162Sdavidcs CORE_TX_DEST_RESERVED, 421320162Sdavidcs CORE_TX_DEST_DROP /* TX Drop */, 422320162Sdavidcs MAX_CORE_TX_DEST 423320162Sdavidcs}; 424320162Sdavidcs 425320162Sdavidcs 426320162Sdavidcs/* 427320162Sdavidcs * Ramrod data for tx queue start ramrod 428320162Sdavidcs */ 429320162Sdavidcsstruct core_tx_start_ramrod_data 430320162Sdavidcs{ 431320162Sdavidcs struct regpair pbl_base_addr /* Address of the pbl page */; 432320162Sdavidcs __le16 mtu /* Maximum transmission unit */; 433320162Sdavidcs __le16 sb_id /* Status block ID */; 434320162Sdavidcs u8 sb_index /* Status block protocol index */; 435320162Sdavidcs u8 stats_en /* Statistics Enable */; 436320162Sdavidcs u8 stats_id /* Statistics Counter ID */; 437337519Sdavidcs u8 conn_type /* connection type that loaded ll2 (use enum protocol_type) */; 438320162Sdavidcs __le16 pbl_size /* Number of BD pages pointed by PBL */; 439320162Sdavidcs __le16 qm_pq_id /* QM PQ ID */; 440320162Sdavidcs u8 gsi_offload_flag /* set when in GSI offload mode on ROCE connection */; 441320162Sdavidcs u8 resrved[3]; 442320162Sdavidcs}; 443320162Sdavidcs 444320162Sdavidcs 445320162Sdavidcs/* 446320162Sdavidcs * Ramrod data for tx queue stop ramrod 447320162Sdavidcs */ 448320162Sdavidcsstruct core_tx_stop_ramrod_data 449320162Sdavidcs{ 450320162Sdavidcs __le32 reserved0[2]; 451320162Sdavidcs}; 452320162Sdavidcs 453320162Sdavidcs 454320162Sdavidcs/* 455337519Sdavidcs * Ramrod data for tx queue update ramrod 456320162Sdavidcs */ 457337519Sdavidcsstruct core_tx_update_ramrod_data 458337519Sdavidcs{ 459337519Sdavidcs u8 update_qm_pq_id_flg /* Flag to Update QM PQ ID */; 460337519Sdavidcs u8 reserved0; 461337519Sdavidcs __le16 qm_pq_id /* Updated QM PQ ID */; 462337519Sdavidcs __le32 reserved1[1]; 463337519Sdavidcs}; 464337519Sdavidcs 465337519Sdavidcs 466337519Sdavidcs/* 467337519Sdavidcs * Enum flag for what type of DCB data to update 468337519Sdavidcs */ 469320162Sdavidcsenum dcb_dscp_update_mode 470320162Sdavidcs{ 471337519Sdavidcs DONT_UPDATE_DCB_DSCP /* use when no change should be done to DCB data */, 472337519Sdavidcs UPDATE_DCB /* use to update only L2 (vlan) priority */, 473337519Sdavidcs UPDATE_DSCP /* use to update only IP DSCP */, 474337519Sdavidcs UPDATE_DCB_DSCP /* update vlan pri and DSCP */, 475320162Sdavidcs MAX_DCB_DSCP_UPDATE_MODE 476320162Sdavidcs}; 477320162Sdavidcs 478320162Sdavidcs 479320162Sdavidcs/* 480316485Sdavidcs * The core storm context for the Ystorm 481316485Sdavidcs */ 482316485Sdavidcsstruct ystorm_core_conn_st_ctx 483316485Sdavidcs{ 484316485Sdavidcs __le32 reserved[4]; 485316485Sdavidcs}; 486316485Sdavidcs 487316485Sdavidcs/* 488316485Sdavidcs * The core storm context for the Pstorm 489316485Sdavidcs */ 490316485Sdavidcsstruct pstorm_core_conn_st_ctx 491316485Sdavidcs{ 492316485Sdavidcs __le32 reserved[4]; 493316485Sdavidcs}; 494316485Sdavidcs 495316485Sdavidcs/* 496316485Sdavidcs * Core Slowpath Connection storm context of Xstorm 497316485Sdavidcs */ 498316485Sdavidcsstruct xstorm_core_conn_st_ctx 499316485Sdavidcs{ 500316485Sdavidcs __le32 spq_base_lo /* SPQ Ring Base Address low dword */; 501316485Sdavidcs __le32 spq_base_hi /* SPQ Ring Base Address high dword */; 502316485Sdavidcs struct regpair consolid_base_addr /* Consolidation Ring Base Address */; 503316485Sdavidcs __le16 spq_cons /* SPQ Ring Consumer */; 504316485Sdavidcs __le16 consolid_cons /* Consolidation Ring Consumer */; 505316485Sdavidcs __le32 reserved0[55] /* Pad to 15 cycles */; 506316485Sdavidcs}; 507316485Sdavidcs 508316485Sdavidcsstruct e4_xstorm_core_conn_ag_ctx 509316485Sdavidcs{ 510316485Sdavidcs u8 reserved0 /* cdu_validation */; 511337519Sdavidcs u8 state /* state */; 512316485Sdavidcs u8 flags0; 513316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 514316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 515316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 516316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 517316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 518316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 519316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 520316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 521316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 522316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 523316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 524316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 525316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 526316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 527316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 528316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 529316485Sdavidcs u8 flags1; 530316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 531316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 532316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 533316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 534316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 535316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 536316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 537316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 538316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 539316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 540316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 541316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 542316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 543316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 544316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 545316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 546316485Sdavidcs u8 flags2; 547316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 548316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 549316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 550316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 551316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 552316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 553316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 554316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 555316485Sdavidcs u8 flags3; 556316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 557316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 558316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 559316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 560316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 561316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 562316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 563316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 564316485Sdavidcs u8 flags4; 565316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 566316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 567316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 568316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 569316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 570316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 571316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 572316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 573316485Sdavidcs u8 flags5; 574316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 575316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 576316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 577316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 578316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 579316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 580316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 581316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 582316485Sdavidcs u8 flags6; 583316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 584316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 585316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 586316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 587316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 588316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 589316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 590316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 591316485Sdavidcs u8 flags7; 592316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 593316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 594316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 595316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 596316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 597316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 598316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 599316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 600316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 601316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 602316485Sdavidcs u8 flags8; 603316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 604316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 605316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 606316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 607316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 608316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 609316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 610316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 611316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 612316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 613316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 614316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 615316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 616316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 617316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 618316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 619316485Sdavidcs u8 flags9; 620316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 621316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 622316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 623316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 624316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 625316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 626316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 627316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 628316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 629316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 630316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 631316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 632316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 633316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 634316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 635316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 636316485Sdavidcs u8 flags10; 637316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 638316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 639316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 640316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 641316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 642316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 643316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 644316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 645316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 646316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 647316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 648316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 649316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 650316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 651316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 652316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 653316485Sdavidcs u8 flags11; 654316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 655316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 656316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 657316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 658316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 659316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 660316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 661316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 662316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 663316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 664316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 665316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 666316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 667316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 668316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 669316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 670316485Sdavidcs u8 flags12; 671316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 672316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 673316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 674316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 675316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 676316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 677316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 678316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 679316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 680316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 681316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 682316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 683316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 684316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 685316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 686316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 687316485Sdavidcs u8 flags13; 688316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 689316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 690316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 691316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 692316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 693316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 694316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 695316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 696316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 697316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 698316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 699316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 700316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 701316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 702316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 703316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 704316485Sdavidcs u8 flags14; 705316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 706316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 707316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 708316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 709316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 710316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 711316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 712316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 713316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 714316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 715316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 716316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 717316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 718316485Sdavidcs#define E4_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 719316485Sdavidcs u8 byte2 /* byte2 */; 720316485Sdavidcs __le16 physical_q0 /* physical_q0 */; 721316485Sdavidcs __le16 consolid_prod /* physical_q1 */; 722316485Sdavidcs __le16 reserved16 /* physical_q2 */; 723316485Sdavidcs __le16 tx_bd_cons /* word3 */; 724316485Sdavidcs __le16 tx_bd_or_spq_prod /* word4 */; 725316485Sdavidcs __le16 word5 /* word5 */; 726316485Sdavidcs __le16 conn_dpi /* conn_dpi */; 727316485Sdavidcs u8 byte3 /* byte3 */; 728316485Sdavidcs u8 byte4 /* byte4 */; 729316485Sdavidcs u8 byte5 /* byte5 */; 730316485Sdavidcs u8 byte6 /* byte6 */; 731316485Sdavidcs __le32 reg0 /* reg0 */; 732316485Sdavidcs __le32 reg1 /* reg1 */; 733316485Sdavidcs __le32 reg2 /* reg2 */; 734316485Sdavidcs __le32 reg3 /* reg3 */; 735316485Sdavidcs __le32 reg4 /* reg4 */; 736316485Sdavidcs __le32 reg5 /* cf_array0 */; 737316485Sdavidcs __le32 reg6 /* cf_array1 */; 738316485Sdavidcs __le16 word7 /* word7 */; 739316485Sdavidcs __le16 word8 /* word8 */; 740316485Sdavidcs __le16 word9 /* word9 */; 741316485Sdavidcs __le16 word10 /* word10 */; 742316485Sdavidcs __le32 reg7 /* reg7 */; 743316485Sdavidcs __le32 reg8 /* reg8 */; 744316485Sdavidcs __le32 reg9 /* reg9 */; 745316485Sdavidcs u8 byte7 /* byte7 */; 746316485Sdavidcs u8 byte8 /* byte8 */; 747316485Sdavidcs u8 byte9 /* byte9 */; 748316485Sdavidcs u8 byte10 /* byte10 */; 749316485Sdavidcs u8 byte11 /* byte11 */; 750316485Sdavidcs u8 byte12 /* byte12 */; 751316485Sdavidcs u8 byte13 /* byte13 */; 752316485Sdavidcs u8 byte14 /* byte14 */; 753316485Sdavidcs u8 byte15 /* byte15 */; 754316485Sdavidcs u8 e5_reserved /* e5_reserved */; 755316485Sdavidcs __le16 word11 /* word11 */; 756316485Sdavidcs __le32 reg10 /* reg10 */; 757316485Sdavidcs __le32 reg11 /* reg11 */; 758316485Sdavidcs __le32 reg12 /* reg12 */; 759316485Sdavidcs __le32 reg13 /* reg13 */; 760316485Sdavidcs __le32 reg14 /* reg14 */; 761316485Sdavidcs __le32 reg15 /* reg15 */; 762316485Sdavidcs __le32 reg16 /* reg16 */; 763316485Sdavidcs __le32 reg17 /* reg17 */; 764316485Sdavidcs __le32 reg18 /* reg18 */; 765316485Sdavidcs __le32 reg19 /* reg19 */; 766316485Sdavidcs __le16 word12 /* word12 */; 767316485Sdavidcs __le16 word13 /* word13 */; 768316485Sdavidcs __le16 word14 /* word14 */; 769316485Sdavidcs __le16 word15 /* word15 */; 770316485Sdavidcs}; 771316485Sdavidcs 772316485Sdavidcsstruct e4_tstorm_core_conn_ag_ctx 773316485Sdavidcs{ 774316485Sdavidcs u8 byte0 /* cdu_validation */; 775316485Sdavidcs u8 byte1 /* state */; 776316485Sdavidcs u8 flags0; 777316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 778316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 779316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 780316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 781316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 782316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 783316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 784316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 785316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 786316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 787316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 788316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 789316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 790316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 791316485Sdavidcs u8 flags1; 792316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 793316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 794316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 795316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 796316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 797316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 798316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 799316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 800316485Sdavidcs u8 flags2; 801316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 802316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 803316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 804316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 805316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 806316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 807316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 808316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 809316485Sdavidcs u8 flags3; 810316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 811316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 812316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 813316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 814316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 815316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 816316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 817316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 818316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 819316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 820316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 821316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 822316485Sdavidcs u8 flags4; 823316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 824316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 825316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 826316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 827316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 828316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 829316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 830316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 831316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 832316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 833316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 834316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 835316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 836316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 837316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 838316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 839316485Sdavidcs u8 flags5; 840316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 841316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 842316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 843316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 844316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 845316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 846316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 847316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 848316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 849316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 850316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 851316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 852316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 853316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 854316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 855316485Sdavidcs#define E4_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 856316485Sdavidcs __le32 reg0 /* reg0 */; 857316485Sdavidcs __le32 reg1 /* reg1 */; 858316485Sdavidcs __le32 reg2 /* reg2 */; 859316485Sdavidcs __le32 reg3 /* reg3 */; 860316485Sdavidcs __le32 reg4 /* reg4 */; 861316485Sdavidcs __le32 reg5 /* reg5 */; 862316485Sdavidcs __le32 reg6 /* reg6 */; 863316485Sdavidcs __le32 reg7 /* reg7 */; 864316485Sdavidcs __le32 reg8 /* reg8 */; 865316485Sdavidcs u8 byte2 /* byte2 */; 866316485Sdavidcs u8 byte3 /* byte3 */; 867316485Sdavidcs __le16 word0 /* word0 */; 868316485Sdavidcs u8 byte4 /* byte4 */; 869316485Sdavidcs u8 byte5 /* byte5 */; 870316485Sdavidcs __le16 word1 /* word1 */; 871316485Sdavidcs __le16 word2 /* conn_dpi */; 872316485Sdavidcs __le16 word3 /* word3 */; 873316485Sdavidcs __le32 reg9 /* reg9 */; 874316485Sdavidcs __le32 reg10 /* reg10 */; 875316485Sdavidcs}; 876316485Sdavidcs 877316485Sdavidcsstruct e4_ustorm_core_conn_ag_ctx 878316485Sdavidcs{ 879316485Sdavidcs u8 reserved /* cdu_validation */; 880316485Sdavidcs u8 byte1 /* state */; 881316485Sdavidcs u8 flags0; 882316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 883316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 884316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 885316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 886316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 887316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 888316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 889316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 890316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 891316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 892316485Sdavidcs u8 flags1; 893316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 894316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 895316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 896316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 897316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 898316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 899316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 900316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 901316485Sdavidcs u8 flags2; 902316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 903316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 904316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 905316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 906316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 907316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 908316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 909316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 910316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 911316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 912316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 913316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 914316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 915316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 916316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 917316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 918316485Sdavidcs u8 flags3; 919316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 920316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 921316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 922316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 923316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 924316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 925316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 926316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 927316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 928316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 929316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 930316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 931316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 932316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 933316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 934316485Sdavidcs#define E4_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 935316485Sdavidcs u8 byte2 /* byte2 */; 936316485Sdavidcs u8 byte3 /* byte3 */; 937316485Sdavidcs __le16 word0 /* conn_dpi */; 938316485Sdavidcs __le16 word1 /* word1 */; 939316485Sdavidcs __le32 rx_producers /* reg0 */; 940316485Sdavidcs __le32 reg1 /* reg1 */; 941316485Sdavidcs __le32 reg2 /* reg2 */; 942316485Sdavidcs __le32 reg3 /* reg3 */; 943316485Sdavidcs __le16 word2 /* word2 */; 944316485Sdavidcs __le16 word3 /* word3 */; 945316485Sdavidcs}; 946316485Sdavidcs 947316485Sdavidcs/* 948316485Sdavidcs * The core storm context for the Mstorm 949316485Sdavidcs */ 950316485Sdavidcsstruct mstorm_core_conn_st_ctx 951316485Sdavidcs{ 952316485Sdavidcs __le32 reserved[24]; 953316485Sdavidcs}; 954316485Sdavidcs 955316485Sdavidcs/* 956316485Sdavidcs * The core storm context for the Ustorm 957316485Sdavidcs */ 958316485Sdavidcsstruct ustorm_core_conn_st_ctx 959316485Sdavidcs{ 960316485Sdavidcs __le32 reserved[4]; 961316485Sdavidcs}; 962316485Sdavidcs 963316485Sdavidcs/* 964316485Sdavidcs * core connection context 965316485Sdavidcs */ 966320162Sdavidcsstruct e4_core_conn_context 967316485Sdavidcs{ 968316485Sdavidcs struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 969316485Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 970316485Sdavidcs struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 971316485Sdavidcs struct regpair pstorm_st_padding[2] /* padding */; 972316485Sdavidcs struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 973316485Sdavidcs struct e4_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 974316485Sdavidcs struct e4_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 975316485Sdavidcs struct e4_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 976316485Sdavidcs struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 977316485Sdavidcs struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 978316485Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 979316485Sdavidcs}; 980316485Sdavidcs 981316485Sdavidcs 982320162Sdavidcsstruct e5_xstorm_core_conn_ag_ctx 983316485Sdavidcs{ 984320162Sdavidcs u8 reserved0 /* cdu_validation */; 985320162Sdavidcs u8 state_and_core_id /* state_and_core_id */; 986320162Sdavidcs u8 flags0; 987320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_MASK 0x1 /* exist_in_qm0 */ 988320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM0_SHIFT 0 989320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_MASK 0x1 /* exist_in_qm1 */ 990320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED1_SHIFT 1 991320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_MASK 0x1 /* exist_in_qm2 */ 992320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED2_SHIFT 2 993320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_MASK 0x1 /* exist_in_qm3 */ 994320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_EXIST_IN_QM3_SHIFT 3 995320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_MASK 0x1 /* bit4 */ 996320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED3_SHIFT 4 997320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_MASK 0x1 /* cf_array_active */ 998320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED4_SHIFT 5 999320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_MASK 0x1 /* bit6 */ 1000320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED5_SHIFT 6 1001320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_MASK 0x1 /* bit7 */ 1002320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED6_SHIFT 7 1003320162Sdavidcs u8 flags1; 1004320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_MASK 0x1 /* bit8 */ 1005320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED7_SHIFT 0 1006320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_MASK 0x1 /* bit9 */ 1007320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED8_SHIFT 1 1008320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_MASK 0x1 /* bit10 */ 1009320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED9_SHIFT 2 1010320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_MASK 0x1 /* bit11 */ 1011320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT11_SHIFT 3 1012320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_MASK 0x1 /* bit12 */ 1013320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT12_SHIFT 4 1014320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_MASK 0x1 /* bit13 */ 1015320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT13_SHIFT 5 1016320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_MASK 0x1 /* bit14 */ 1017320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TX_RULE_ACTIVE_SHIFT 6 1018320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_MASK 0x1 /* bit15 */ 1019320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_ACTIVE_SHIFT 7 1020320162Sdavidcs u8 flags2; 1021320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1022320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 0 1023320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1024320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 2 1025320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1026320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 4 1027320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1028320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 6 1029320162Sdavidcs u8 flags3; 1030320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1031320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 0 1032320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1033320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 2 1034320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1035320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 4 1036320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1037320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 6 1038320162Sdavidcs u8 flags4; 1039320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1040320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 0 1041320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1042320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 2 1043320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1044320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 4 1045320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF11_MASK 0x3 /* cf11 */ 1046320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF11_SHIFT 6 1047320162Sdavidcs u8 flags5; 1048320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF12_MASK 0x3 /* cf12 */ 1049320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF12_SHIFT 0 1050320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF13_MASK 0x3 /* cf13 */ 1051320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF13_SHIFT 2 1052320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF14_MASK 0x3 /* cf14 */ 1053320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF14_SHIFT 4 1054320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF15_MASK 0x3 /* cf15 */ 1055320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF15_SHIFT 6 1056320162Sdavidcs u8 flags6; 1057320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_MASK 0x3 /* cf16 */ 1058320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_SHIFT 0 1059320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF17_MASK 0x3 /* cf_array_cf */ 1060320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF17_SHIFT 2 1061320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_MASK 0x3 /* cf18 */ 1062320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_SHIFT 4 1063320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_MASK 0x3 /* cf19 */ 1064320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_SHIFT 6 1065320162Sdavidcs u8 flags7; 1066320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_MASK 0x3 /* cf20 */ 1067320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_SHIFT 0 1068320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_MASK 0x3 /* cf21 */ 1069320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED10_SHIFT 2 1070320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_MASK 0x3 /* cf22 */ 1071320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_SHIFT 4 1072320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1073320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 6 1074320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1075320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 7 1076320162Sdavidcs u8 flags8; 1077320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1078320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 0 1079320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1080320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 1 1081320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1082320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 2 1083320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1084320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 3 1085320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1086320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 4 1087320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1088320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 5 1089320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1090320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 6 1091320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1092320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 7 1093320162Sdavidcs u8 flags9; 1094320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1095320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 0 1096320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_MASK 0x1 /* cf11en */ 1097320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF11EN_SHIFT 1 1098320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_MASK 0x1 /* cf12en */ 1099320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF12EN_SHIFT 2 1100320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_MASK 0x1 /* cf13en */ 1101320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF13EN_SHIFT 3 1102320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_MASK 0x1 /* cf14en */ 1103320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF14EN_SHIFT 4 1104320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_MASK 0x1 /* cf15en */ 1105320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF15EN_SHIFT 5 1106320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_MASK 0x1 /* cf16en */ 1107320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CONSOLID_PROD_CF_EN_SHIFT 6 1108320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_MASK 0x1 /* cf_array_cf_en */ 1109320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF17EN_SHIFT 7 1110320162Sdavidcs u8 flags10; 1111320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_MASK 0x1 /* cf18en */ 1112320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_DQ_CF_EN_SHIFT 0 1113320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_MASK 0x1 /* cf19en */ 1114320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TERMINATE_CF_EN_SHIFT 1 1115320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_MASK 0x1 /* cf20en */ 1116320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_FLUSH_Q0_EN_SHIFT 2 1117320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_MASK 0x1 /* cf21en */ 1118320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED11_SHIFT 3 1119320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_MASK 0x1 /* cf22en */ 1120320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_SLOW_PATH_EN_SHIFT 4 1121320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_MASK 0x1 /* cf23en */ 1122320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF23EN_SHIFT 5 1123320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_MASK 0x1 /* rule0en */ 1124320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED12_SHIFT 6 1125320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_MASK 0x1 /* rule1en */ 1126320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED13_SHIFT 7 1127320162Sdavidcs u8 flags11; 1128320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_MASK 0x1 /* rule2en */ 1129320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED14_SHIFT 0 1130320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_MASK 0x1 /* rule3en */ 1131320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RESERVED15_SHIFT 1 1132320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_MASK 0x1 /* rule4en */ 1133320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_TX_DEC_RULE_EN_SHIFT 2 1134320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1135320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 3 1136320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1137320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 4 1138320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1139320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 5 1140320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_MASK 0x1 /* rule8en */ 1141320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED1_SHIFT 6 1142320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_MASK 0x1 /* rule9en */ 1143320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE9EN_SHIFT 7 1144320162Sdavidcs u8 flags12; 1145320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_MASK 0x1 /* rule10en */ 1146320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE10EN_SHIFT 0 1147320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_MASK 0x1 /* rule11en */ 1148320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE11EN_SHIFT 1 1149320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_MASK 0x1 /* rule12en */ 1150320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED2_SHIFT 2 1151320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_MASK 0x1 /* rule13en */ 1152320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED3_SHIFT 3 1153320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_MASK 0x1 /* rule14en */ 1154320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE14EN_SHIFT 4 1155320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_MASK 0x1 /* rule15en */ 1156320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE15EN_SHIFT 5 1157320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_MASK 0x1 /* rule16en */ 1158320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE16EN_SHIFT 6 1159320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_MASK 0x1 /* rule17en */ 1160320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE17EN_SHIFT 7 1161320162Sdavidcs u8 flags13; 1162320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_MASK 0x1 /* rule18en */ 1163320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE18EN_SHIFT 0 1164320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_MASK 0x1 /* rule19en */ 1165320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_RULE19EN_SHIFT 1 1166320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_MASK 0x1 /* rule20en */ 1167320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED4_SHIFT 2 1168320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_MASK 0x1 /* rule21en */ 1169320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED5_SHIFT 3 1170320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_MASK 0x1 /* rule22en */ 1171320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED6_SHIFT 4 1172320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_MASK 0x1 /* rule23en */ 1173320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED7_SHIFT 5 1174320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_MASK 0x1 /* rule24en */ 1175320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED8_SHIFT 6 1176320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_MASK 0x1 /* rule25en */ 1177320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_A0_RESERVED9_SHIFT 7 1178320162Sdavidcs u8 flags14; 1179320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_MASK 0x1 /* bit16 */ 1180320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT16_SHIFT 0 1181320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_MASK 0x1 /* bit17 */ 1182320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT17_SHIFT 1 1183320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_MASK 0x1 /* bit18 */ 1184320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT18_SHIFT 2 1185320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_MASK 0x1 /* bit19 */ 1186320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT19_SHIFT 3 1187320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_MASK 0x1 /* bit20 */ 1188320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT20_SHIFT 4 1189320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_MASK 0x1 /* bit21 */ 1190320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_BIT21_SHIFT 5 1191320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF23_MASK 0x3 /* cf23 */ 1192320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_CF23_SHIFT 6 1193320162Sdavidcs u8 byte2 /* byte2 */; 1194320162Sdavidcs __le16 physical_q0 /* physical_q0 */; 1195320162Sdavidcs __le16 consolid_prod /* physical_q1 */; 1196320162Sdavidcs __le16 reserved16 /* physical_q2 */; 1197320162Sdavidcs __le16 tx_bd_cons /* word3 */; 1198320162Sdavidcs __le16 tx_bd_or_spq_prod /* word4 */; 1199320162Sdavidcs __le16 word5 /* word5 */; 1200320162Sdavidcs __le16 conn_dpi /* conn_dpi */; 1201320162Sdavidcs u8 byte3 /* byte3 */; 1202320162Sdavidcs u8 byte4 /* byte4 */; 1203320162Sdavidcs u8 byte5 /* byte5 */; 1204320162Sdavidcs u8 byte6 /* byte6 */; 1205320162Sdavidcs __le32 reg0 /* reg0 */; 1206320162Sdavidcs __le32 reg1 /* reg1 */; 1207320162Sdavidcs __le32 reg2 /* reg2 */; 1208320162Sdavidcs __le32 reg3 /* reg3 */; 1209320162Sdavidcs __le32 reg4 /* reg4 */; 1210320162Sdavidcs __le32 reg5 /* cf_array0 */; 1211320162Sdavidcs __le32 reg6 /* cf_array1 */; 1212320162Sdavidcs u8 flags15; 1213320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit22 */ 1214320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1215320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit23 */ 1216320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1217320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit24 */ 1218320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1219320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf24 */ 1220320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1221320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf24en */ 1222320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1223320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule26en */ 1224320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1225320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule27en */ 1226320162Sdavidcs#define E5_XSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1227320162Sdavidcs u8 byte7 /* byte7 */; 1228320162Sdavidcs __le16 word7 /* word7 */; 1229320162Sdavidcs __le16 word8 /* word8 */; 1230320162Sdavidcs __le16 word9 /* word9 */; 1231320162Sdavidcs __le16 word10 /* word10 */; 1232320162Sdavidcs __le16 word11 /* word11 */; 1233320162Sdavidcs __le32 reg7 /* reg7 */; 1234320162Sdavidcs __le32 reg8 /* reg8 */; 1235320162Sdavidcs __le32 reg9 /* reg9 */; 1236320162Sdavidcs u8 byte8 /* byte8 */; 1237320162Sdavidcs u8 byte9 /* byte9 */; 1238320162Sdavidcs u8 byte10 /* byte10 */; 1239320162Sdavidcs u8 byte11 /* byte11 */; 1240320162Sdavidcs u8 byte12 /* byte12 */; 1241320162Sdavidcs u8 byte13 /* byte13 */; 1242320162Sdavidcs u8 byte14 /* byte14 */; 1243320162Sdavidcs u8 byte15 /* byte15 */; 1244320162Sdavidcs __le32 reg10 /* reg10 */; 1245320162Sdavidcs __le32 reg11 /* reg11 */; 1246320162Sdavidcs __le32 reg12 /* reg12 */; 1247320162Sdavidcs __le32 reg13 /* reg13 */; 1248320162Sdavidcs __le32 reg14 /* reg14 */; 1249320162Sdavidcs __le32 reg15 /* reg15 */; 1250320162Sdavidcs __le32 reg16 /* reg16 */; 1251320162Sdavidcs __le32 reg17 /* reg17 */; 1252320162Sdavidcs __le32 reg18 /* reg18 */; 1253320162Sdavidcs __le32 reg19 /* reg19 */; 1254320162Sdavidcs __le16 word12 /* word12 */; 1255320162Sdavidcs __le16 word13 /* word13 */; 1256320162Sdavidcs __le16 word14 /* word14 */; 1257320162Sdavidcs __le16 word15 /* word15 */; 1258316485Sdavidcs}; 1259316485Sdavidcs 1260320162Sdavidcsstruct e5_tstorm_core_conn_ag_ctx 1261316485Sdavidcs{ 1262320162Sdavidcs u8 byte0 /* cdu_validation */; 1263320162Sdavidcs u8 byte1 /* state_and_core_id */; 1264320162Sdavidcs u8 flags0; 1265320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1266320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1267320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1268320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1269320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_MASK 0x1 /* bit2 */ 1270320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT2_SHIFT 2 1271320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_MASK 0x1 /* bit3 */ 1272320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT3_SHIFT 3 1273320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_MASK 0x1 /* bit4 */ 1274320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT4_SHIFT 4 1275320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_MASK 0x1 /* bit5 */ 1276320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_BIT5_SHIFT 5 1277320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1278320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 6 1279320162Sdavidcs u8 flags1; 1280320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1281320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 0 1282320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1283320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 2 1284320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1285320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF3_SHIFT 4 1286320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1287320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF4_SHIFT 6 1288320162Sdavidcs u8 flags2; 1289320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1290320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF5_SHIFT 0 1291320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1292320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF6_SHIFT 2 1293320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF7_MASK 0x3 /* cf7 */ 1294320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF7_SHIFT 4 1295320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF8_MASK 0x3 /* cf8 */ 1296320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF8_SHIFT 6 1297320162Sdavidcs u8 flags3; 1298320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF9_MASK 0x3 /* cf9 */ 1299320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF9_SHIFT 0 1300320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF10_MASK 0x3 /* cf10 */ 1301320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF10_SHIFT 2 1302320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1303320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 4 1304320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1305320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 5 1306320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1307320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 6 1308320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1309320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 7 1310320162Sdavidcs u8 flags4; 1311320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1312320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 0 1313320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1314320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 1 1315320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1316320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 2 1317320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_MASK 0x1 /* cf7en */ 1318320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF7EN_SHIFT 3 1319320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_MASK 0x1 /* cf8en */ 1320320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF8EN_SHIFT 4 1321320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_MASK 0x1 /* cf9en */ 1322320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF9EN_SHIFT 5 1323320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_MASK 0x1 /* cf10en */ 1324320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_CF10EN_SHIFT 6 1325320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1326320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 1327320162Sdavidcs u8 flags5; 1328320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1329320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 1330320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1331320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 1332320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1333320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 1334320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1335320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 1336320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1337320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 1338320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1339320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 1340320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1341320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 1342320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1343320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 1344320162Sdavidcs u8 flags6; 1345320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit6 */ 1346320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1347320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit7 */ 1348320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1349320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x1 /* bit8 */ 1350320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1351320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf11 */ 1352320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 3 1353320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf11en */ 1354320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 5 1355320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* rule9en */ 1356320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 6 1357320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_MASK 0x1 /* rule10en */ 1358320162Sdavidcs#define E5_TSTORM_CORE_CONN_AG_CTX_E4_RESERVED7_SHIFT 7 1359320162Sdavidcs u8 byte2 /* byte2 */; 1360320162Sdavidcs __le16 word0 /* word0 */; 1361320162Sdavidcs __le32 reg0 /* reg0 */; 1362320162Sdavidcs __le32 reg1 /* reg1 */; 1363320162Sdavidcs __le32 reg2 /* reg2 */; 1364320162Sdavidcs __le32 reg3 /* reg3 */; 1365320162Sdavidcs __le32 reg4 /* reg4 */; 1366320162Sdavidcs __le32 reg5 /* reg5 */; 1367320162Sdavidcs __le32 reg6 /* reg6 */; 1368320162Sdavidcs __le32 reg7 /* reg7 */; 1369320162Sdavidcs __le32 reg8 /* reg8 */; 1370320162Sdavidcs u8 byte3 /* byte3 */; 1371320162Sdavidcs u8 byte4 /* byte4 */; 1372320162Sdavidcs u8 byte5 /* byte5 */; 1373320162Sdavidcs u8 e4_reserved8 /* byte6 */; 1374320162Sdavidcs __le16 word1 /* word1 */; 1375320162Sdavidcs __le16 word2 /* conn_dpi */; 1376320162Sdavidcs __le32 reg9 /* reg9 */; 1377320162Sdavidcs __le16 word3 /* word3 */; 1378320162Sdavidcs __le16 e4_reserved9 /* word4 */; 1379316485Sdavidcs}; 1380316485Sdavidcs 1381320162Sdavidcsstruct e5_ustorm_core_conn_ag_ctx 1382316485Sdavidcs{ 1383320162Sdavidcs u8 reserved /* cdu_validation */; 1384320162Sdavidcs u8 byte1 /* state_and_core_id */; 1385320162Sdavidcs u8 flags0; 1386320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 1387320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 1388320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 1389320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 1390320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* timer0cf */ 1391320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 1392320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* timer1cf */ 1393320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 1394320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* timer2cf */ 1395320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 1396320162Sdavidcs u8 flags1; 1397320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF3_MASK 0x3 /* timer_stop_all */ 1398320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF3_SHIFT 0 1399320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF4_MASK 0x3 /* cf4 */ 1400320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF4_SHIFT 2 1401320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF5_MASK 0x3 /* cf5 */ 1402320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF5_SHIFT 4 1403320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF6_MASK 0x3 /* cf6 */ 1404320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF6_SHIFT 6 1405320162Sdavidcs u8 flags2; 1406320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 1407320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 1408320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 1409320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 1410320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 1411320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 1412320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_MASK 0x1 /* cf3en */ 1413320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF3EN_SHIFT 3 1414320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_MASK 0x1 /* cf4en */ 1415320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF4EN_SHIFT 4 1416320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_MASK 0x1 /* cf5en */ 1417320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF5EN_SHIFT 5 1418320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_MASK 0x1 /* cf6en */ 1419320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_CF6EN_SHIFT 6 1420320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 1421320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 7 1422320162Sdavidcs u8 flags3; 1423320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 1424320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 0 1425320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 1426320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 1 1427320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 1428320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 2 1429320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 1430320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 3 1431320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_MASK 0x1 /* rule5en */ 1432320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE5EN_SHIFT 4 1433320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_MASK 0x1 /* rule6en */ 1434320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE6EN_SHIFT 5 1435320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_MASK 0x1 /* rule7en */ 1436320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE7EN_SHIFT 6 1437320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_MASK 0x1 /* rule8en */ 1438320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_RULE8EN_SHIFT 7 1439320162Sdavidcs u8 flags4; 1440320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_MASK 0x1 /* bit2 */ 1441320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED1_SHIFT 0 1442320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_MASK 0x1 /* bit3 */ 1443320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED2_SHIFT 1 1444320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_MASK 0x3 /* cf7 */ 1445320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED3_SHIFT 2 1446320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_MASK 0x3 /* cf8 */ 1447320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED4_SHIFT 4 1448320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_MASK 0x1 /* cf7en */ 1449320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED5_SHIFT 6 1450320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_MASK 0x1 /* cf8en */ 1451320162Sdavidcs#define E5_USTORM_CORE_CONN_AG_CTX_E4_RESERVED6_SHIFT 7 1452320162Sdavidcs u8 byte2 /* byte2 */; 1453320162Sdavidcs __le16 word0 /* conn_dpi */; 1454320162Sdavidcs __le16 word1 /* word1 */; 1455320162Sdavidcs __le32 rx_producers /* reg0 */; 1456320162Sdavidcs __le32 reg1 /* reg1 */; 1457320162Sdavidcs __le32 reg2 /* reg2 */; 1458320162Sdavidcs __le32 reg3 /* reg3 */; 1459320162Sdavidcs __le16 word2 /* word2 */; 1460320162Sdavidcs __le16 word3 /* word3 */; 1461316485Sdavidcs}; 1462316485Sdavidcs 1463316485Sdavidcs/* 1464320162Sdavidcs * core connection context 1465316485Sdavidcs */ 1466320162Sdavidcsstruct e5_core_conn_context 1467316485Sdavidcs{ 1468320162Sdavidcs struct ystorm_core_conn_st_ctx ystorm_st_context /* ystorm storm context */; 1469320162Sdavidcs struct regpair ystorm_st_padding[2] /* padding */; 1470320162Sdavidcs struct pstorm_core_conn_st_ctx pstorm_st_context /* pstorm storm context */; 1471320162Sdavidcs struct regpair pstorm_st_padding[2] /* padding */; 1472320162Sdavidcs struct xstorm_core_conn_st_ctx xstorm_st_context /* xstorm storm context */; 1473337519Sdavidcs struct regpair xstorm_st_padding[2] /* padding */; 1474320162Sdavidcs struct e5_xstorm_core_conn_ag_ctx xstorm_ag_context /* xstorm aggregative context */; 1475320162Sdavidcs struct e5_tstorm_core_conn_ag_ctx tstorm_ag_context /* tstorm aggregative context */; 1476320162Sdavidcs struct e5_ustorm_core_conn_ag_ctx ustorm_ag_context /* ustorm aggregative context */; 1477320162Sdavidcs struct mstorm_core_conn_st_ctx mstorm_st_context /* mstorm storm context */; 1478320162Sdavidcs struct ustorm_core_conn_st_ctx ustorm_st_context /* ustorm storm context */; 1479320162Sdavidcs struct regpair ustorm_st_padding[2] /* padding */; 1480316485Sdavidcs}; 1481316485Sdavidcs 1482316485Sdavidcs 1483316485Sdavidcsstruct eth_mstorm_per_pf_stat 1484316485Sdavidcs{ 1485316485Sdavidcs struct regpair gre_discard_pkts /* Dropped GRE RX packets */; 1486316485Sdavidcs struct regpair vxlan_discard_pkts /* Dropped VXLAN RX packets */; 1487316485Sdavidcs struct regpair geneve_discard_pkts /* Dropped GENEVE RX packets */; 1488316485Sdavidcs struct regpair lb_discard_pkts /* Dropped Tx switched packets */; 1489316485Sdavidcs}; 1490316485Sdavidcs 1491316485Sdavidcs 1492316485Sdavidcsstruct eth_mstorm_per_queue_stat 1493316485Sdavidcs{ 1494316485Sdavidcs struct regpair ttl0_discard /* Number of packets discarded because TTL=0 (in IPv4) or hopLimit=0 (in IPv6) */; 1495316485Sdavidcs struct regpair packet_too_big_discard /* Number of packets discarded because they are bigger than MTU */; 1496316485Sdavidcs struct regpair no_buff_discard /* Number of packets discarded due to lack of host buffers (BDs/SGEs/CQEs) */; 1497316485Sdavidcs struct regpair not_active_discard /* Number of packets discarded because of no active Rx connection */; 1498316485Sdavidcs struct regpair tpa_coalesced_pkts /* number of coalesced packets in all TPA aggregations */; 1499316485Sdavidcs struct regpair tpa_coalesced_events /* total number of TPA aggregations */; 1500316485Sdavidcs struct regpair tpa_aborts_num /* number of aggregations, which abnormally ended */; 1501316485Sdavidcs struct regpair tpa_coalesced_bytes /* total TCP payload length in all TPA aggregations */; 1502316485Sdavidcs}; 1503316485Sdavidcs 1504316485Sdavidcs 1505316485Sdavidcs/* 1506316485Sdavidcs * Ethernet TX Per PF 1507316485Sdavidcs */ 1508316485Sdavidcsstruct eth_pstorm_per_pf_stat 1509316485Sdavidcs{ 1510316485Sdavidcs struct regpair sent_lb_ucast_bytes /* number of total ucast bytes sent on loopback port without errors */; 1511316485Sdavidcs struct regpair sent_lb_mcast_bytes /* number of total mcast bytes sent on loopback port without errors */; 1512316485Sdavidcs struct regpair sent_lb_bcast_bytes /* number of total bcast bytes sent on loopback port without errors */; 1513316485Sdavidcs struct regpair sent_lb_ucast_pkts /* number of total ucast packets sent on loopback port without errors */; 1514316485Sdavidcs struct regpair sent_lb_mcast_pkts /* number of total mcast packets sent on loopback port without errors */; 1515316485Sdavidcs struct regpair sent_lb_bcast_pkts /* number of total bcast packets sent on loopback port without errors */; 1516316485Sdavidcs struct regpair sent_gre_bytes /* Sent GRE bytes */; 1517316485Sdavidcs struct regpair sent_vxlan_bytes /* Sent VXLAN bytes */; 1518316485Sdavidcs struct regpair sent_geneve_bytes /* Sent GENEVE bytes */; 1519316485Sdavidcs struct regpair sent_gre_pkts /* Sent GRE packets */; 1520316485Sdavidcs struct regpair sent_vxlan_pkts /* Sent VXLAN packets */; 1521316485Sdavidcs struct regpair sent_geneve_pkts /* Sent GENEVE packets */; 1522316485Sdavidcs struct regpair gre_drop_pkts /* Dropped GRE TX packets */; 1523316485Sdavidcs struct regpair vxlan_drop_pkts /* Dropped VXLAN TX packets */; 1524316485Sdavidcs struct regpair geneve_drop_pkts /* Dropped GENEVE TX packets */; 1525316485Sdavidcs}; 1526316485Sdavidcs 1527316485Sdavidcs 1528316485Sdavidcs/* 1529316485Sdavidcs * Ethernet TX Per Queue Stats 1530316485Sdavidcs */ 1531316485Sdavidcsstruct eth_pstorm_per_queue_stat 1532316485Sdavidcs{ 1533316485Sdavidcs struct regpair sent_ucast_bytes /* number of total bytes sent without errors */; 1534316485Sdavidcs struct regpair sent_mcast_bytes /* number of total bytes sent without errors */; 1535316485Sdavidcs struct regpair sent_bcast_bytes /* number of total bytes sent without errors */; 1536316485Sdavidcs struct regpair sent_ucast_pkts /* number of total packets sent without errors */; 1537316485Sdavidcs struct regpair sent_mcast_pkts /* number of total packets sent without errors */; 1538316485Sdavidcs struct regpair sent_bcast_pkts /* number of total packets sent without errors */; 1539316485Sdavidcs struct regpair error_drop_pkts /* number of total packets dropped due to errors */; 1540316485Sdavidcs}; 1541316485Sdavidcs 1542316485Sdavidcs 1543316485Sdavidcs/* 1544316485Sdavidcs * ETH Rx producers data 1545316485Sdavidcs */ 1546316485Sdavidcsstruct eth_rx_rate_limit 1547316485Sdavidcs{ 1548316485Sdavidcs __le16 mult /* Rate Limit Multiplier - (Storm Clock (MHz) * 8 / Desired Bandwidth (MB/s)) */; 1549316485Sdavidcs __le16 cnst /* Constant term to add (or subtract from number of cycles) */; 1550316485Sdavidcs u8 add_sub_cnst /* Add (1) or subtract (0) constant term */; 1551316485Sdavidcs u8 reserved0; 1552316485Sdavidcs __le16 reserved1; 1553316485Sdavidcs}; 1554316485Sdavidcs 1555316485Sdavidcs 1556316485Sdavidcsstruct eth_ustorm_per_pf_stat 1557316485Sdavidcs{ 1558316485Sdavidcs struct regpair rcv_lb_ucast_bytes /* number of total ucast bytes received on loopback port without errors */; 1559316485Sdavidcs struct regpair rcv_lb_mcast_bytes /* number of total mcast bytes received on loopback port without errors */; 1560316485Sdavidcs struct regpair rcv_lb_bcast_bytes /* number of total bcast bytes received on loopback port without errors */; 1561316485Sdavidcs struct regpair rcv_lb_ucast_pkts /* number of total ucast packets received on loopback port without errors */; 1562316485Sdavidcs struct regpair rcv_lb_mcast_pkts /* number of total mcast packets received on loopback port without errors */; 1563316485Sdavidcs struct regpair rcv_lb_bcast_pkts /* number of total bcast packets received on loopback port without errors */; 1564316485Sdavidcs struct regpair rcv_gre_bytes /* Received GRE bytes */; 1565316485Sdavidcs struct regpair rcv_vxlan_bytes /* Received VXLAN bytes */; 1566316485Sdavidcs struct regpair rcv_geneve_bytes /* Received GENEVE bytes */; 1567316485Sdavidcs struct regpair rcv_gre_pkts /* Received GRE packets */; 1568316485Sdavidcs struct regpair rcv_vxlan_pkts /* Received VXLAN packets */; 1569316485Sdavidcs struct regpair rcv_geneve_pkts /* Received GENEVE packets */; 1570316485Sdavidcs}; 1571316485Sdavidcs 1572316485Sdavidcs 1573316485Sdavidcsstruct eth_ustorm_per_queue_stat 1574316485Sdavidcs{ 1575316485Sdavidcs struct regpair rcv_ucast_bytes; 1576316485Sdavidcs struct regpair rcv_mcast_bytes; 1577316485Sdavidcs struct regpair rcv_bcast_bytes; 1578316485Sdavidcs struct regpair rcv_ucast_pkts; 1579316485Sdavidcs struct regpair rcv_mcast_pkts; 1580316485Sdavidcs struct regpair rcv_bcast_pkts; 1581316485Sdavidcs}; 1582316485Sdavidcs 1583316485Sdavidcs 1584316485Sdavidcs/* 1585337519Sdavidcs * Event Ring VF-PF Channel data 1586337519Sdavidcs */ 1587337519Sdavidcsstruct vf_pf_channel_eqe_data 1588337519Sdavidcs{ 1589337519Sdavidcs struct regpair msg_addr /* VF-PF message address */; 1590337519Sdavidcs}; 1591337519Sdavidcs 1592337519Sdavidcs/* 1593337519Sdavidcs * Event Ring malicious VF data 1594337519Sdavidcs */ 1595337519Sdavidcsstruct malicious_vf_eqe_data 1596337519Sdavidcs{ 1597337519Sdavidcs u8 vf_id /* Malicious VF ID */; 1598337519Sdavidcs u8 err_id /* Malicious VF error (use enum malicious_vf_error_id) */; 1599337519Sdavidcs __le16 reserved[3]; 1600337519Sdavidcs}; 1601337519Sdavidcs 1602337519Sdavidcs/* 1603337519Sdavidcs * Event Ring initial cleanup data 1604337519Sdavidcs */ 1605337519Sdavidcsstruct initial_cleanup_eqe_data 1606337519Sdavidcs{ 1607337519Sdavidcs u8 vf_id /* VF ID */; 1608337519Sdavidcs u8 reserved[7]; 1609337519Sdavidcs}; 1610337519Sdavidcs 1611337519Sdavidcs/* 1612337519Sdavidcs * Event Data Union 1613337519Sdavidcs */ 1614337519Sdavidcsunion event_ring_data 1615337519Sdavidcs{ 1616337519Sdavidcs u8 bytes[8] /* Byte Array */; 1617337519Sdavidcs struct vf_pf_channel_eqe_data vf_pf_channel /* VF-PF Channel data */; 1618337519Sdavidcs struct iscsi_eqe_data iscsi_info /* Dedicated fields to iscsi data */; 1619337519Sdavidcs struct iscsi_connect_done_results iscsi_conn_done_info /* Dedicated fields to iscsi connect done results */; 1620337519Sdavidcs union rdma_eqe_data rdma_data /* Dedicated field for RDMA data */; 1621337519Sdavidcs struct malicious_vf_eqe_data malicious_vf /* Malicious VF data */; 1622337519Sdavidcs struct initial_cleanup_eqe_data vf_init_cleanup /* VF Initial Cleanup data */; 1623337519Sdavidcs}; 1624337519Sdavidcs 1625337519Sdavidcs 1626337519Sdavidcs/* 1627337519Sdavidcs * Event Ring Entry 1628337519Sdavidcs */ 1629337519Sdavidcsstruct event_ring_entry 1630337519Sdavidcs{ 1631337519Sdavidcs u8 protocol_id /* Event Protocol ID (use enum protocol_type) */; 1632337519Sdavidcs u8 opcode /* Event Opcode */; 1633337519Sdavidcs __le16 reserved0 /* Reserved */; 1634337519Sdavidcs __le16 echo /* Echo value from ramrod data on the host */; 1635337519Sdavidcs u8 fw_return_code /* FW return code for SP ramrods */; 1636337519Sdavidcs u8 flags; 1637337519Sdavidcs#define EVENT_RING_ENTRY_ASYNC_MASK 0x1 /* 0: synchronous EQE - a completion of SP message. 1: asynchronous EQE */ 1638337519Sdavidcs#define EVENT_RING_ENTRY_ASYNC_SHIFT 0 1639337519Sdavidcs#define EVENT_RING_ENTRY_RESERVED1_MASK 0x7F 1640337519Sdavidcs#define EVENT_RING_ENTRY_RESERVED1_SHIFT 1 1641337519Sdavidcs union event_ring_data data; 1642337519Sdavidcs}; 1643337519Sdavidcs 1644337519Sdavidcs/* 1645316485Sdavidcs * Event Ring Next Page Address 1646316485Sdavidcs */ 1647316485Sdavidcsstruct event_ring_next_addr 1648316485Sdavidcs{ 1649316485Sdavidcs struct regpair addr /* Next Page Address */; 1650316485Sdavidcs __le32 reserved[2] /* Reserved */; 1651316485Sdavidcs}; 1652316485Sdavidcs 1653316485Sdavidcs/* 1654316485Sdavidcs * Event Ring Element 1655316485Sdavidcs */ 1656316485Sdavidcsunion event_ring_element 1657316485Sdavidcs{ 1658316485Sdavidcs struct event_ring_entry entry /* Event Ring Entry */; 1659316485Sdavidcs struct event_ring_next_addr next_addr /* Event Ring Next Page Address */; 1660316485Sdavidcs}; 1661316485Sdavidcs 1662316485Sdavidcs 1663316485Sdavidcs 1664337519Sdavidcs 1665316485Sdavidcs/* 1666316485Sdavidcs * Ports mode 1667316485Sdavidcs */ 1668316485Sdavidcsenum fw_flow_ctrl_mode 1669316485Sdavidcs{ 1670316485Sdavidcs flow_ctrl_pause, 1671316485Sdavidcs flow_ctrl_pfc, 1672316485Sdavidcs MAX_FW_FLOW_CTRL_MODE 1673316485Sdavidcs}; 1674316485Sdavidcs 1675316485Sdavidcs 1676316485Sdavidcs/* 1677337519Sdavidcs * GFT profile type. 1678337519Sdavidcs */ 1679337519Sdavidcsenum gft_profile_type 1680337519Sdavidcs{ 1681337519Sdavidcs GFT_PROFILE_TYPE_4_TUPLE /* tunnel type, inner 4 tuple, IP type and L4 type match. */, 1682337519Sdavidcs GFT_PROFILE_TYPE_L4_DST_PORT /* tunnel type, inner L4 destination port, IP type and L4 type match. */, 1683337519Sdavidcs GFT_PROFILE_TYPE_IP_DST_ADDR /* tunnel type, inner IP destination address and IP type match. */, 1684337519Sdavidcs GFT_PROFILE_TYPE_IP_SRC_ADDR /* tunnel type, inner IP source address and IP type match. */, 1685337519Sdavidcs GFT_PROFILE_TYPE_TUNNEL_TYPE /* tunnel type and outer IP type match. */, 1686337519Sdavidcs MAX_GFT_PROFILE_TYPE 1687337519Sdavidcs}; 1688337519Sdavidcs 1689337519Sdavidcs 1690337519Sdavidcs/* 1691316485Sdavidcs * Major and Minor hsi Versions 1692316485Sdavidcs */ 1693316485Sdavidcsstruct hsi_fp_ver_struct 1694316485Sdavidcs{ 1695316485Sdavidcs u8 minor_ver_arr[2] /* Minor Version of hsi loading pf */; 1696316485Sdavidcs u8 major_ver_arr[2] /* Major Version of driver loading pf */; 1697316485Sdavidcs}; 1698316485Sdavidcs 1699316485Sdavidcs 1700337519Sdavidcs 1701316485Sdavidcs/* 1702316485Sdavidcs * Integration Phase 1703316485Sdavidcs */ 1704316485Sdavidcsenum integ_phase 1705316485Sdavidcs{ 1706316485Sdavidcs INTEG_PHASE_BB_A0_LATEST=3 /* BB A0 latest integration phase */, 1707316485Sdavidcs INTEG_PHASE_BB_B0_NO_MCP=10 /* BB B0 without MCP */, 1708316485Sdavidcs INTEG_PHASE_BB_B0_WITH_MCP=11 /* BB B0 with MCP */, 1709316485Sdavidcs MAX_INTEG_PHASE 1710316485Sdavidcs}; 1711316485Sdavidcs 1712316485Sdavidcs 1713316485Sdavidcs/* 1714316485Sdavidcs * Ports mode 1715316485Sdavidcs */ 1716316485Sdavidcsenum iwarp_ll2_tx_queues 1717316485Sdavidcs{ 1718316485Sdavidcs IWARP_LL2_IN_ORDER_TX_QUEUE=1 /* LL2 queue for OOO packets sent in-order by the driver */, 1719316485Sdavidcs IWARP_LL2_ALIGNED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned by the driver */, 1720316485Sdavidcs IWARP_LL2_ALIGNED_RIGHT_TRIMMED_TX_QUEUE /* LL2 queue for unaligned packets sent aligned and was right-trimmed by the driver */, 1721316485Sdavidcs IWARP_LL2_ERROR /* Error indication */, 1722316485Sdavidcs MAX_IWARP_LL2_TX_QUEUES 1723316485Sdavidcs}; 1724316485Sdavidcs 1725316485Sdavidcs 1726337519Sdavidcs 1727316485Sdavidcs/* 1728316485Sdavidcs * Malicious VF error ID 1729316485Sdavidcs */ 1730316485Sdavidcsenum malicious_vf_error_id 1731316485Sdavidcs{ 1732316485Sdavidcs MALICIOUS_VF_NO_ERROR /* Zero placeholder value */, 1733316485Sdavidcs VF_PF_CHANNEL_NOT_READY /* Writing to VF/PF channel when it is not ready */, 1734316485Sdavidcs VF_ZONE_MSG_NOT_VALID /* VF channel message is not valid */, 1735316485Sdavidcs VF_ZONE_FUNC_NOT_ENABLED /* Parent PF of VF channel is not active */, 1736316485Sdavidcs ETH_PACKET_TOO_SMALL /* TX packet is shorter then reported on BDs or from minimal size */, 1737316485Sdavidcs ETH_ILLEGAL_VLAN_MODE /* Tx packet with marked as insert VLAN when its illegal */, 1738316485Sdavidcs ETH_MTU_VIOLATION /* TX packet is greater then MTU */, 1739316485Sdavidcs ETH_ILLEGAL_INBAND_TAGS /* TX packet has illegal inband tags marked */, 1740316485Sdavidcs ETH_VLAN_INSERT_AND_INBAND_VLAN /* Vlan cant be added to inband tag */, 1741316485Sdavidcs ETH_ILLEGAL_NBDS /* indicated number of BDs for the packet is illegal */, 1742316485Sdavidcs ETH_FIRST_BD_WO_SOP /* 1st BD must have start_bd flag set */, 1743316485Sdavidcs ETH_INSUFFICIENT_BDS /* There are not enough BDs for transmission of even one packet */, 1744316485Sdavidcs ETH_ILLEGAL_LSO_HDR_NBDS /* Header NBDs value is illegal */, 1745316485Sdavidcs ETH_ILLEGAL_LSO_MSS /* LSO MSS value is more than allowed */, 1746316485Sdavidcs ETH_ZERO_SIZE_BD /* empty BD (which not contains control flags) is illegal */, 1747316485Sdavidcs ETH_ILLEGAL_LSO_HDR_LEN /* LSO header size is above the limit */, 1748316485Sdavidcs ETH_INSUFFICIENT_PAYLOAD /* In LSO its expected that on the local BD ring there will be at least MSS bytes of data */, 1749316485Sdavidcs ETH_EDPM_OUT_OF_SYNC /* Valid BDs on local ring after EDPM L2 sync */, 1750316485Sdavidcs ETH_TUNN_IPV6_EXT_NBD_ERR /* Tunneled packet with IPv6+Ext without a proper number of BDs */, 1751316485Sdavidcs ETH_CONTROL_PACKET_VIOLATION /* VF sent control frame such as PFC */, 1752316485Sdavidcs ETH_ANTI_SPOOFING_ERR /* Anti-Spoofing verification failure */, 1753337519Sdavidcs ETH_PACKET_SIZE_TOO_LARGE /* packet scanned is too large (can be 9700 at most) */, 1754316485Sdavidcs MAX_MALICIOUS_VF_ERROR_ID 1755316485Sdavidcs}; 1756316485Sdavidcs 1757316485Sdavidcs 1758316485Sdavidcs 1759316485Sdavidcs/* 1760316485Sdavidcs * Mstorm non-triggering VF zone 1761316485Sdavidcs */ 1762316485Sdavidcsstruct mstorm_non_trigger_vf_zone 1763316485Sdavidcs{ 1764316485Sdavidcs struct eth_mstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1765316485Sdavidcs struct eth_rx_prod_data eth_rx_queue_producers[ETH_MAX_NUM_RX_QUEUES_PER_VF_QUAD] /* VF RX queues producers */; 1766316485Sdavidcs}; 1767316485Sdavidcs 1768316485Sdavidcs 1769316485Sdavidcs/* 1770316485Sdavidcs * Mstorm VF zone 1771316485Sdavidcs */ 1772316485Sdavidcsstruct mstorm_vf_zone 1773316485Sdavidcs{ 1774316485Sdavidcs struct mstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1775316485Sdavidcs}; 1776316485Sdavidcs 1777316485Sdavidcs 1778316485Sdavidcs/* 1779337519Sdavidcs * vlan header including TPID and TCI fields 1780337519Sdavidcs */ 1781337519Sdavidcsstruct vlan_header 1782337519Sdavidcs{ 1783337519Sdavidcs __le16 tpid /* Tag Protocol Identifier */; 1784337519Sdavidcs __le16 tci /* Tag Control Information */; 1785337519Sdavidcs}; 1786337519Sdavidcs 1787337519Sdavidcs/* 1788337519Sdavidcs * outer tag configurations 1789337519Sdavidcs */ 1790337519Sdavidcsstruct outer_tag_config_struct 1791337519Sdavidcs{ 1792337519Sdavidcs u8 enable_stag_pri_change /* Enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette Davis, UFP with Host Control mode, and UFP with DCB over base interface. else - 0. */; 1793337519Sdavidcs u8 pri_map_valid /* If inner_to_outer_pri_map is initialize then set pri_map_valid */; 1794337519Sdavidcs u8 reserved[2]; 1795337519Sdavidcs struct vlan_header outer_tag /* In case mf_mode is MF_OVLAN, this field specifies the outer tag protocol identifier and outer tag control information */; 1796337519Sdavidcs u8 inner_to_outer_pri_map[8] /* Map from inner to outer priority. Set pri_map_valid when init map */; 1797337519Sdavidcs}; 1798337519Sdavidcs 1799337519Sdavidcs 1800337519Sdavidcs/* 1801316485Sdavidcs * personality per PF 1802316485Sdavidcs */ 1803316485Sdavidcsenum personality_type 1804316485Sdavidcs{ 1805316485Sdavidcs BAD_PERSONALITY_TYP, 1806316485Sdavidcs PERSONALITY_ISCSI /* iSCSI and LL2 */, 1807316485Sdavidcs PERSONALITY_FCOE /* Fcoe and LL2 */, 1808316485Sdavidcs PERSONALITY_RDMA_AND_ETH /* Roce or Iwarp, Eth and LL2 */, 1809316485Sdavidcs PERSONALITY_RDMA /* Roce and LL2 */, 1810316485Sdavidcs PERSONALITY_CORE /* CORE(LL2) */, 1811316485Sdavidcs PERSONALITY_ETH /* Ethernet */, 1812316485Sdavidcs PERSONALITY_TOE /* Toe and LL2 */, 1813316485Sdavidcs MAX_PERSONALITY_TYPE 1814316485Sdavidcs}; 1815316485Sdavidcs 1816316485Sdavidcs 1817316485Sdavidcs/* 1818316485Sdavidcs * tunnel configuration 1819316485Sdavidcs */ 1820316485Sdavidcsstruct pf_start_tunnel_config 1821316485Sdavidcs{ 1822316485Sdavidcs u8 set_vxlan_udp_port_flg /* Set VXLAN tunnel UDP destination port to vxlan_udp_port. If not set - FW will use a default port */; 1823316485Sdavidcs u8 set_geneve_udp_port_flg /* Set GENEVE tunnel UDP destination port to geneve_udp_port. If not set - FW will use a default port */; 1824337519Sdavidcs u8 tunnel_clss_vxlan /* Rx classification scheme for VXLAN tunnel. (use enum tunnel_clss) */; 1825337519Sdavidcs u8 tunnel_clss_l2geneve /* Rx classification scheme for l2 GENEVE tunnel. (use enum tunnel_clss) */; 1826337519Sdavidcs u8 tunnel_clss_ipgeneve /* Rx classification scheme for ip GENEVE tunnel. (use enum tunnel_clss) */; 1827337519Sdavidcs u8 tunnel_clss_l2gre /* Rx classification scheme for l2 GRE tunnel. (use enum tunnel_clss) */; 1828337519Sdavidcs u8 tunnel_clss_ipgre /* Rx classification scheme for ip GRE tunnel. (use enum tunnel_clss) */; 1829316485Sdavidcs u8 reserved; 1830316485Sdavidcs __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. Valid if set_vxlan_udp_port_flg=1 */; 1831316485Sdavidcs __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. Valid if set_geneve_udp_port_flg=1 */; 1832316485Sdavidcs}; 1833316485Sdavidcs 1834316485Sdavidcs/* 1835316485Sdavidcs * Ramrod data for PF start ramrod 1836316485Sdavidcs */ 1837316485Sdavidcsstruct pf_start_ramrod_data 1838316485Sdavidcs{ 1839316485Sdavidcs struct regpair event_ring_pbl_addr /* Address of event ring PBL */; 1840316485Sdavidcs struct regpair consolid_q_pbl_addr /* PBL address of consolidation queue */; 1841316485Sdavidcs struct pf_start_tunnel_config tunnel_config /* tunnel configuration. */; 1842316485Sdavidcs __le16 event_ring_sb_id /* Status block ID */; 1843316485Sdavidcs u8 base_vf_id /* All VfIds owned by Pf will be from baseVfId till baseVfId+numVfs */; 1844316485Sdavidcs u8 num_vfs /* Amount of vfs owned by PF */; 1845316485Sdavidcs u8 event_ring_num_pages /* Number of PBL pages in event ring */; 1846316485Sdavidcs u8 event_ring_sb_index /* Status block index */; 1847316485Sdavidcs u8 path_id /* HW path ID (engine ID) */; 1848316485Sdavidcs u8 warning_as_error /* In FW asserts, treat warning as error */; 1849316485Sdavidcs u8 dont_log_ramrods /* If not set - throw a warning for each ramrod (for debug) */; 1850337519Sdavidcs u8 personality /* define what type of personality is new PF (use enum personality_type) */; 1851316485Sdavidcs __le16 log_type_mask /* Log type mask. Each bit set enables a corresponding event type logging. Event types are defined as ASSERT_LOG_TYPE_xxx */; 1852337519Sdavidcs u8 mf_mode /* Multi function mode (use enum mf_mode) */; 1853337519Sdavidcs u8 integ_phase /* Integration phase (use enum integ_phase) */; 1854316485Sdavidcs u8 allow_npar_tx_switching /* If set, inter-pf tx switching is allowed in Switch Independent function mode */; 1855337519Sdavidcs u8 reserved0; 1856316485Sdavidcs struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 1857337519Sdavidcs struct outer_tag_config_struct outer_tag_config /* Outer tag configurations */; 1858316485Sdavidcs}; 1859316485Sdavidcs 1860316485Sdavidcs 1861316485Sdavidcs 1862316485Sdavidcs/* 1863337519Sdavidcs * Per protocol DCB data 1864316485Sdavidcs */ 1865316485Sdavidcsstruct protocol_dcb_data 1866316485Sdavidcs{ 1867337519Sdavidcs u8 dcb_enable_flag /* Enable DCB */; 1868337519Sdavidcs u8 dscp_enable_flag /* Enable updating DSCP value */; 1869337519Sdavidcs u8 dcb_priority /* DCB priority */; 1870337519Sdavidcs u8 dcb_tc /* DCB TC */; 1871337519Sdavidcs u8 dscp_val /* DSCP value to write if dscp_enable_flag is set */; 1872337519Sdavidcs u8 dcb_dont_add_vlan0 /* When DCB is enabled - if this flag is set, dont add VLAN 0 tag to untagged frames */; 1873316485Sdavidcs}; 1874316485Sdavidcs 1875316485Sdavidcs/* 1876316485Sdavidcs * Update tunnel configuration 1877316485Sdavidcs */ 1878316485Sdavidcsstruct pf_update_tunnel_config 1879316485Sdavidcs{ 1880316485Sdavidcs u8 update_rx_pf_clss /* Update RX per PF tunnel classification scheme. */; 1881316485Sdavidcs u8 update_rx_def_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with unknown unicast outer MAC in NPAR mode. */; 1882316485Sdavidcs u8 update_rx_def_non_ucast_clss /* Update per PORT default tunnel RX classification scheme for traffic with non unicast outer MAC in NPAR mode. */; 1883316485Sdavidcs u8 set_vxlan_udp_port_flg /* Update VXLAN tunnel UDP destination port. */; 1884316485Sdavidcs u8 set_geneve_udp_port_flg /* Update GENEVE tunnel UDP destination port. */; 1885337519Sdavidcs u8 tunnel_clss_vxlan /* Classification scheme for VXLAN tunnel. (use enum tunnel_clss) */; 1886337519Sdavidcs u8 tunnel_clss_l2geneve /* Classification scheme for l2 GENEVE tunnel. (use enum tunnel_clss) */; 1887337519Sdavidcs u8 tunnel_clss_ipgeneve /* Classification scheme for ip GENEVE tunnel. (use enum tunnel_clss) */; 1888337519Sdavidcs u8 tunnel_clss_l2gre /* Classification scheme for l2 GRE tunnel. (use enum tunnel_clss) */; 1889337519Sdavidcs u8 tunnel_clss_ipgre /* Classification scheme for ip GRE tunnel. (use enum tunnel_clss) */; 1890316485Sdavidcs __le16 vxlan_udp_port /* VXLAN tunnel UDP destination port. */; 1891316485Sdavidcs __le16 geneve_udp_port /* GENEVE tunnel UDP destination port. */; 1892316485Sdavidcs __le16 reserved; 1893316485Sdavidcs}; 1894316485Sdavidcs 1895316485Sdavidcs/* 1896316485Sdavidcs * Data for port update ramrod 1897316485Sdavidcs */ 1898316485Sdavidcsstruct pf_update_ramrod_data 1899316485Sdavidcs{ 1900337519Sdavidcs u8 update_eth_dcb_data_mode /* Update Eth DCB data indication (use enum dcb_dscp_update_mode) */; 1901337519Sdavidcs u8 update_fcoe_dcb_data_mode /* Update FCOE DCB data indication (use enum dcb_dscp_update_mode) */; 1902337519Sdavidcs u8 update_iscsi_dcb_data_mode /* Update iSCSI DCB data indication (use enum dcb_dscp_update_mode) */; 1903337519Sdavidcs u8 update_roce_dcb_data_mode /* Update ROCE DCB data indication (use enum dcb_dscp_update_mode) */; 1904337519Sdavidcs u8 update_rroce_dcb_data_mode /* Update RROCE (RoceV2) DCB data indication (use enum dcb_dscp_update_mode) */; 1905337519Sdavidcs u8 update_iwarp_dcb_data_mode /* Update IWARP DCB data indication (use enum dcb_dscp_update_mode) */; 1906316485Sdavidcs u8 update_mf_vlan_flag /* Update MF outer vlan Id */; 1907337519Sdavidcs u8 update_enable_stag_pri_change /* Update Enable STAG Priority Change indication */; 1908316485Sdavidcs struct protocol_dcb_data eth_dcb_data /* core eth related fields */; 1909316485Sdavidcs struct protocol_dcb_data fcoe_dcb_data /* core fcoe related fields */; 1910316485Sdavidcs struct protocol_dcb_data iscsi_dcb_data /* core iscsi related fields */; 1911316485Sdavidcs struct protocol_dcb_data roce_dcb_data /* core roce related fields */; 1912316485Sdavidcs struct protocol_dcb_data rroce_dcb_data /* core roce related fields */; 1913316485Sdavidcs struct protocol_dcb_data iwarp_dcb_data /* core iwarp related fields */; 1914316485Sdavidcs __le16 mf_vlan /* new outer vlan id value */; 1915337519Sdavidcs u8 enable_stag_pri_change /* enables updating S-tag priority from inner tag or DCB. Should be 1 for Bette Davis, UFP with Host Control mode, and UFP with DCB over base interface. else - 0. */; 1916337519Sdavidcs u8 reserved; 1917316485Sdavidcs struct pf_update_tunnel_config tunnel_config /* tunnel configuration. */; 1918316485Sdavidcs}; 1919316485Sdavidcs 1920316485Sdavidcs 1921316485Sdavidcs 1922316485Sdavidcs/* 1923316485Sdavidcs * Ports mode 1924316485Sdavidcs */ 1925316485Sdavidcsenum ports_mode 1926316485Sdavidcs{ 1927316485Sdavidcs ENGX2_PORTX1 /* 2 engines x 1 port */, 1928316485Sdavidcs ENGX2_PORTX2 /* 2 engines x 2 ports */, 1929316485Sdavidcs ENGX1_PORTX1 /* 1 engine x 1 port */, 1930316485Sdavidcs ENGX1_PORTX2 /* 1 engine x 2 ports */, 1931316485Sdavidcs ENGX1_PORTX4 /* 1 engine x 4 ports */, 1932316485Sdavidcs MAX_PORTS_MODE 1933316485Sdavidcs}; 1934316485Sdavidcs 1935316485Sdavidcs 1936316485Sdavidcs 1937316485Sdavidcs/* 1938316485Sdavidcs * use to index in hsi_fp_[major|minor]_ver_arr per protocol 1939316485Sdavidcs */ 1940316485Sdavidcsenum protocol_version_array_key 1941316485Sdavidcs{ 1942316485Sdavidcs ETH_VER_KEY=0, 1943316485Sdavidcs ROCE_VER_KEY, 1944316485Sdavidcs MAX_PROTOCOL_VERSION_ARRAY_KEY 1945316485Sdavidcs}; 1946316485Sdavidcs 1947316485Sdavidcs 1948316485Sdavidcs 1949316485Sdavidcs/* 1950316485Sdavidcs * RDMA TX Stats 1951316485Sdavidcs */ 1952316485Sdavidcsstruct rdma_sent_stats 1953316485Sdavidcs{ 1954316485Sdavidcs struct regpair sent_bytes /* number of total RDMA bytes sent */; 1955316485Sdavidcs struct regpair sent_pkts /* number of total RDMA packets sent */; 1956316485Sdavidcs}; 1957316485Sdavidcs 1958316485Sdavidcs/* 1959316485Sdavidcs * Pstorm non-triggering VF zone 1960316485Sdavidcs */ 1961316485Sdavidcsstruct pstorm_non_trigger_vf_zone 1962316485Sdavidcs{ 1963316485Sdavidcs struct eth_pstorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 1964316485Sdavidcs struct rdma_sent_stats rdma_stats /* RoCE sent statistics */; 1965316485Sdavidcs}; 1966316485Sdavidcs 1967316485Sdavidcs 1968316485Sdavidcs/* 1969316485Sdavidcs * Pstorm VF zone 1970316485Sdavidcs */ 1971316485Sdavidcsstruct pstorm_vf_zone 1972316485Sdavidcs{ 1973316485Sdavidcs struct pstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 1974316485Sdavidcs struct regpair reserved[7] /* vf_zone size mus be power of 2 */; 1975316485Sdavidcs}; 1976316485Sdavidcs 1977316485Sdavidcs 1978316485Sdavidcs/* 1979316485Sdavidcs * Ramrod Header of SPQE 1980316485Sdavidcs */ 1981316485Sdavidcsstruct ramrod_header 1982316485Sdavidcs{ 1983316485Sdavidcs __le32 cid /* Slowpath Connection CID */; 1984316485Sdavidcs u8 cmd_id /* Ramrod Cmd (Per Protocol Type) */; 1985337519Sdavidcs u8 protocol_id /* Ramrod Protocol ID (use enum protocol_type) */; 1986316485Sdavidcs __le16 echo /* Ramrod echo */; 1987316485Sdavidcs}; 1988316485Sdavidcs 1989316485Sdavidcs 1990316485Sdavidcs/* 1991316485Sdavidcs * RDMA RX Stats 1992316485Sdavidcs */ 1993316485Sdavidcsstruct rdma_rcv_stats 1994316485Sdavidcs{ 1995316485Sdavidcs struct regpair rcv_bytes /* number of total RDMA bytes received */; 1996316485Sdavidcs struct regpair rcv_pkts /* number of total RDMA packets received */; 1997316485Sdavidcs}; 1998316485Sdavidcs 1999316485Sdavidcs 2000316485Sdavidcs 2001316485Sdavidcs/* 2002316485Sdavidcs * Data for update QCN/DCQCN RL ramrod 2003316485Sdavidcs */ 2004316485Sdavidcsstruct rl_update_ramrod_data 2005316485Sdavidcs{ 2006316485Sdavidcs u8 qcn_update_param_flg /* Update QCN global params: timeout. */; 2007316485Sdavidcs u8 dcqcn_update_param_flg /* Update DCQCN global params: timeout, g, k. */; 2008316485Sdavidcs u8 rl_init_flg /* Init RL parameters, when RL disabled. */; 2009316485Sdavidcs u8 rl_start_flg /* Start RL in IDLE state. Set rate to maximum. */; 2010316485Sdavidcs u8 rl_stop_flg /* Stop RL. */; 2011316485Sdavidcs u8 rl_id_first /* ID of first or single RL, that will be updated. */; 2012316485Sdavidcs u8 rl_id_last /* ID of last RL, that will be updated. If clear, single RL will updated. */; 2013316485Sdavidcs u8 rl_dc_qcn_flg /* If set, RL will used for DCQCN. */; 2014316485Sdavidcs __le32 rl_bc_rate /* Byte Counter Limit. */; 2015316485Sdavidcs __le16 rl_max_rate /* Maximum rate in 1.6 Mbps resolution. */; 2016316485Sdavidcs __le16 rl_r_ai /* Active increase rate. */; 2017316485Sdavidcs __le16 rl_r_hai /* Hyper active increase rate. */; 2018316485Sdavidcs __le16 dcqcn_g /* DCQCN Alpha update gain in 1/64K resolution . */; 2019316485Sdavidcs __le32 dcqcn_k_us /* DCQCN Alpha update interval. */; 2020316485Sdavidcs __le32 dcqcn_timeuot_us /* DCQCN timeout. */; 2021316485Sdavidcs __le32 qcn_timeuot_us /* QCN timeout. */; 2022316485Sdavidcs __le32 reserved[2]; 2023316485Sdavidcs}; 2024316485Sdavidcs 2025316485Sdavidcs 2026316485Sdavidcs/* 2027316485Sdavidcs * Slowpath Element (SPQE) 2028316485Sdavidcs */ 2029316485Sdavidcsstruct slow_path_element 2030316485Sdavidcs{ 2031316485Sdavidcs struct ramrod_header hdr /* Ramrod Header */; 2032316485Sdavidcs struct regpair data_ptr /* Pointer to the Ramrod Data on the Host */; 2033316485Sdavidcs}; 2034316485Sdavidcs 2035316485Sdavidcs 2036316485Sdavidcs/* 2037316485Sdavidcs * Tstorm non-triggering VF zone 2038316485Sdavidcs */ 2039316485Sdavidcsstruct tstorm_non_trigger_vf_zone 2040316485Sdavidcs{ 2041316485Sdavidcs struct rdma_rcv_stats rdma_stats /* RoCE received statistics */; 2042316485Sdavidcs}; 2043316485Sdavidcs 2044316485Sdavidcs 2045316485Sdavidcsstruct tstorm_per_port_stat 2046316485Sdavidcs{ 2047316485Sdavidcs struct regpair trunc_error_discard /* packet is dropped because it was truncated in NIG */; 2048316485Sdavidcs struct regpair mac_error_discard /* packet is dropped because of Ethernet FCS error */; 2049316485Sdavidcs struct regpair mftag_filter_discard /* packet is dropped because classification was unsuccessful */; 2050316485Sdavidcs struct regpair eth_mac_filter_discard /* packet was passed to Ethernet and dropped because of no mac filter match */; 2051316485Sdavidcs struct regpair ll2_mac_filter_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 2052316485Sdavidcs struct regpair ll2_conn_disabled_discard /* packet passed to Light L2 and dropped because Light L2 is not configured for this PF */; 2053316485Sdavidcs struct regpair iscsi_irregular_pkt /* packet is an ISCSI irregular packet */; 2054316485Sdavidcs struct regpair fcoe_irregular_pkt /* packet is an FCOE irregular packet */; 2055316485Sdavidcs struct regpair roce_irregular_pkt /* packet is an ROCE irregular packet */; 2056316485Sdavidcs struct regpair iwarp_irregular_pkt /* packet is an IWARP irregular packet */; 2057316485Sdavidcs struct regpair eth_irregular_pkt /* packet is an ETH irregular packet */; 2058316485Sdavidcs struct regpair toe_irregular_pkt /* packet is an TOE irregular packet */; 2059316485Sdavidcs struct regpair preroce_irregular_pkt /* packet is an PREROCE irregular packet */; 2060316485Sdavidcs struct regpair eth_gre_tunn_filter_discard /* GRE dropped packets */; 2061316485Sdavidcs struct regpair eth_vxlan_tunn_filter_discard /* VXLAN dropped packets */; 2062316485Sdavidcs struct regpair eth_geneve_tunn_filter_discard /* GENEVE dropped packets */; 2063337519Sdavidcs struct regpair eth_gft_drop_pkt /* GFT dropped packets */; 2064316485Sdavidcs}; 2065316485Sdavidcs 2066316485Sdavidcs 2067316485Sdavidcs/* 2068316485Sdavidcs * Tstorm VF zone 2069316485Sdavidcs */ 2070316485Sdavidcsstruct tstorm_vf_zone 2071316485Sdavidcs{ 2072316485Sdavidcs struct tstorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 2073316485Sdavidcs}; 2074316485Sdavidcs 2075316485Sdavidcs 2076316485Sdavidcs/* 2077316485Sdavidcs * Tunnel classification scheme 2078316485Sdavidcs */ 2079316485Sdavidcsenum tunnel_clss 2080316485Sdavidcs{ 2081316485Sdavidcs TUNNEL_CLSS_MAC_VLAN=0 /* Use MAC and VLAN from first L2 header for vport classification. */, 2082316485Sdavidcs TUNNEL_CLSS_MAC_VNI /* Use MAC from first L2 header and VNI from tunnel header for vport classification */, 2083316485Sdavidcs TUNNEL_CLSS_INNER_MAC_VLAN /* Use MAC and VLAN from last L2 header for vport classification */, 2084316485Sdavidcs TUNNEL_CLSS_INNER_MAC_VNI /* Use MAC from last L2 header and VNI from tunnel header for vport classification */, 2085316485Sdavidcs TUNNEL_CLSS_MAC_VLAN_DUAL_STAGE /* Use MAC and VLAN from last L2 header for vport classification. If no exact match, use MAC and VLAN from first L2 header for classification. */, 2086316485Sdavidcs MAX_TUNNEL_CLSS 2087316485Sdavidcs}; 2088316485Sdavidcs 2089316485Sdavidcs 2090316485Sdavidcs 2091316485Sdavidcs/* 2092316485Sdavidcs * Ustorm non-triggering VF zone 2093316485Sdavidcs */ 2094316485Sdavidcsstruct ustorm_non_trigger_vf_zone 2095316485Sdavidcs{ 2096316485Sdavidcs struct eth_ustorm_per_queue_stat eth_queue_stat /* VF statistic bucket */; 2097316485Sdavidcs struct regpair vf_pf_msg_addr /* VF-PF message address */; 2098316485Sdavidcs}; 2099316485Sdavidcs 2100316485Sdavidcs 2101316485Sdavidcs/* 2102316485Sdavidcs * Ustorm triggering VF zone 2103316485Sdavidcs */ 2104316485Sdavidcsstruct ustorm_trigger_vf_zone 2105316485Sdavidcs{ 2106316485Sdavidcs u8 vf_pf_msg_valid /* VF-PF message valid flag */; 2107316485Sdavidcs u8 reserved[7]; 2108316485Sdavidcs}; 2109316485Sdavidcs 2110316485Sdavidcs 2111316485Sdavidcs/* 2112316485Sdavidcs * Ustorm VF zone 2113316485Sdavidcs */ 2114316485Sdavidcsstruct ustorm_vf_zone 2115316485Sdavidcs{ 2116316485Sdavidcs struct ustorm_non_trigger_vf_zone non_trigger /* non-interrupt-triggering zone */; 2117316485Sdavidcs struct ustorm_trigger_vf_zone trigger /* interrupt triggering zone */; 2118316485Sdavidcs}; 2119316485Sdavidcs 2120316485Sdavidcs 2121316485Sdavidcs/* 2122316485Sdavidcs * VF-PF channel data 2123316485Sdavidcs */ 2124316485Sdavidcsstruct vf_pf_channel_data 2125316485Sdavidcs{ 2126316485Sdavidcs __le32 ready /* 0: VF-PF Channel NOT ready. Waiting for ack from PF driver. 1: VF-PF Channel is ready for a new transaction. */; 2127316485Sdavidcs u8 valid /* 0: VF-PF Channel is invalid because of malicious VF. 1: VF-PF Channel is valid. */; 2128316485Sdavidcs u8 reserved0; 2129316485Sdavidcs __le16 reserved1; 2130316485Sdavidcs}; 2131316485Sdavidcs 2132316485Sdavidcs 2133337519Sdavidcs 2134316485Sdavidcs/* 2135316485Sdavidcs * Ramrod data for VF start ramrod 2136316485Sdavidcs */ 2137316485Sdavidcsstruct vf_start_ramrod_data 2138316485Sdavidcs{ 2139316485Sdavidcs u8 vf_id /* VF ID */; 2140316485Sdavidcs u8 enable_flr_ack /* If set, initial cleanup ack will be sent to parent PF SP event queue */; 2141316485Sdavidcs __le16 opaque_fid /* VF opaque FID */; 2142337519Sdavidcs u8 personality /* define what type of personality is new VF (use enum personality_type) */; 2143316485Sdavidcs u8 reserved[7]; 2144316485Sdavidcs struct hsi_fp_ver_struct hsi_fp_ver /* FP HSI version to be used by FW */; 2145316485Sdavidcs}; 2146316485Sdavidcs 2147316485Sdavidcs 2148316485Sdavidcs/* 2149316485Sdavidcs * Ramrod data for VF start ramrod 2150316485Sdavidcs */ 2151316485Sdavidcsstruct vf_stop_ramrod_data 2152316485Sdavidcs{ 2153316485Sdavidcs u8 vf_id /* VF ID */; 2154316485Sdavidcs u8 reserved0; 2155316485Sdavidcs __le16 reserved1; 2156316485Sdavidcs __le32 reserved2; 2157316485Sdavidcs}; 2158316485Sdavidcs 2159316485Sdavidcs 2160316485Sdavidcs/* 2161316485Sdavidcs * VF zone size mode. 2162316485Sdavidcs */ 2163316485Sdavidcsenum vf_zone_size_mode 2164316485Sdavidcs{ 2165316485Sdavidcs VF_ZONE_SIZE_MODE_DEFAULT /* Default VF zone size. Up to 192 VF supported. */, 2166316485Sdavidcs VF_ZONE_SIZE_MODE_DOUBLE /* Doubled VF zone size. Up to 96 VF supported. */, 2167316485Sdavidcs VF_ZONE_SIZE_MODE_QUAD /* Quad VF zone size. Up to 48 VF supported. */, 2168316485Sdavidcs MAX_VF_ZONE_SIZE_MODE 2169316485Sdavidcs}; 2170316485Sdavidcs 2171316485Sdavidcs 2172316485Sdavidcs 2173316485Sdavidcs 2174337519Sdavidcs 2175316485Sdavidcs/* 2176316485Sdavidcs * Attentions status block 2177316485Sdavidcs */ 2178316485Sdavidcsstruct atten_status_block 2179316485Sdavidcs{ 2180316485Sdavidcs __le32 atten_bits; 2181316485Sdavidcs __le32 atten_ack; 2182316485Sdavidcs __le16 reserved0; 2183316485Sdavidcs __le16 sb_index /* status block running index */; 2184316485Sdavidcs __le32 reserved1; 2185316485Sdavidcs}; 2186316485Sdavidcs 2187316485Sdavidcs 2188316485Sdavidcs/* 2189316485Sdavidcs * DMAE command 2190316485Sdavidcs */ 2191316485Sdavidcsstruct dmae_cmd 2192316485Sdavidcs{ 2193316485Sdavidcs __le32 opcode; 2194316485Sdavidcs#define DMAE_CMD_SRC_MASK 0x1 /* DMA Source. 0 - PCIe, 1 - GRC (use enum dmae_cmd_src_enum) */ 2195316485Sdavidcs#define DMAE_CMD_SRC_SHIFT 0 2196316485Sdavidcs#define DMAE_CMD_DST_MASK 0x3 /* DMA destination. 0 - None, 1 - PCIe, 2 - GRC, 3 - None (use enum dmae_cmd_dst_enum) */ 2197316485Sdavidcs#define DMAE_CMD_DST_SHIFT 1 2198316485Sdavidcs#define DMAE_CMD_C_DST_MASK 0x1 /* Completion destination. 0 - PCie, 1 - GRC (use enum dmae_cmd_c_dst_enum) */ 2199316485Sdavidcs#define DMAE_CMD_C_DST_SHIFT 3 2200316485Sdavidcs#define DMAE_CMD_CRC_RESET_MASK 0x1 /* Reset the CRC result (do not use the previous result as the seed) */ 2201316485Sdavidcs#define DMAE_CMD_CRC_RESET_SHIFT 4 2202316485Sdavidcs#define DMAE_CMD_SRC_ADDR_RESET_MASK 0x1 /* Reset the source address in the next go to the same source address of the previous go */ 2203316485Sdavidcs#define DMAE_CMD_SRC_ADDR_RESET_SHIFT 5 2204316485Sdavidcs#define DMAE_CMD_DST_ADDR_RESET_MASK 0x1 /* Reset the destination address in the next go to the same destination address of the previous go */ 2205316485Sdavidcs#define DMAE_CMD_DST_ADDR_RESET_SHIFT 6 2206316485Sdavidcs#define DMAE_CMD_COMP_FUNC_MASK 0x1 /* 0 completion function is the same as src function, 1 - 0 completion function is the same as dst function (use enum dmae_cmd_comp_func_enum) */ 2207316485Sdavidcs#define DMAE_CMD_COMP_FUNC_SHIFT 7 2208316485Sdavidcs#define DMAE_CMD_COMP_WORD_EN_MASK 0x1 /* 0 - Do not write a completion word, 1 - Write a completion word (use enum dmae_cmd_comp_word_en_enum) */ 2209316485Sdavidcs#define DMAE_CMD_COMP_WORD_EN_SHIFT 8 2210316485Sdavidcs#define DMAE_CMD_COMP_CRC_EN_MASK 0x1 /* 0 - Do not write a CRC word, 1 - Write a CRC word (use enum dmae_cmd_comp_crc_en_enum) */ 2211316485Sdavidcs#define DMAE_CMD_COMP_CRC_EN_SHIFT 9 2212316485Sdavidcs#define DMAE_CMD_COMP_CRC_OFFSET_MASK 0x7 /* The CRC word should be taken from the DMAE address space from address 9+X, where X is the value in these bits. */ 2213316485Sdavidcs#define DMAE_CMD_COMP_CRC_OFFSET_SHIFT 10 2214316485Sdavidcs#define DMAE_CMD_RESERVED1_MASK 0x1 2215316485Sdavidcs#define DMAE_CMD_RESERVED1_SHIFT 13 2216316485Sdavidcs#define DMAE_CMD_ENDIANITY_MODE_MASK 0x3 2217316485Sdavidcs#define DMAE_CMD_ENDIANITY_MODE_SHIFT 14 2218316485Sdavidcs#define DMAE_CMD_ERR_HANDLING_MASK 0x3 /* The field specifies how the completion word is affected by PCIe read error. 0 Send a regular completion, 1 - Send a completion with an error indication, 2 do not send a completion (use enum dmae_cmd_error_handling_enum) */ 2219316485Sdavidcs#define DMAE_CMD_ERR_HANDLING_SHIFT 16 2220316485Sdavidcs#define DMAE_CMD_PORT_ID_MASK 0x3 /* The port ID to be placed on the RF FID field of the GRC bus. this field is used both when GRC is the destination and when it is the source of the DMAE transaction. */ 2221316485Sdavidcs#define DMAE_CMD_PORT_ID_SHIFT 18 2222316485Sdavidcs#define DMAE_CMD_SRC_PF_ID_MASK 0xF /* Source PCI function number [3:0] */ 2223316485Sdavidcs#define DMAE_CMD_SRC_PF_ID_SHIFT 20 2224316485Sdavidcs#define DMAE_CMD_DST_PF_ID_MASK 0xF /* Destination PCI function number [3:0] */ 2225316485Sdavidcs#define DMAE_CMD_DST_PF_ID_SHIFT 24 2226316485Sdavidcs#define DMAE_CMD_SRC_VF_ID_VALID_MASK 0x1 /* Source VFID valid */ 2227316485Sdavidcs#define DMAE_CMD_SRC_VF_ID_VALID_SHIFT 28 2228316485Sdavidcs#define DMAE_CMD_DST_VF_ID_VALID_MASK 0x1 /* Destination VFID valid */ 2229316485Sdavidcs#define DMAE_CMD_DST_VF_ID_VALID_SHIFT 29 2230316485Sdavidcs#define DMAE_CMD_RESERVED2_MASK 0x3 2231316485Sdavidcs#define DMAE_CMD_RESERVED2_SHIFT 30 2232316485Sdavidcs __le32 src_addr_lo /* PCIe source address low in bytes or GRC source address in DW */; 2233316485Sdavidcs __le32 src_addr_hi /* PCIe source address high in bytes or reserved (if source is GRC) */; 2234316485Sdavidcs __le32 dst_addr_lo /* PCIe destination address low in bytes or GRC destination address in DW */; 2235316485Sdavidcs __le32 dst_addr_hi /* PCIe destination address high in bytes or reserved (if destination is GRC) */; 2236316485Sdavidcs __le16 length_dw /* Length in DW */; 2237316485Sdavidcs __le16 opcode_b; 2238316485Sdavidcs#define DMAE_CMD_SRC_VF_ID_MASK 0xFF /* Source VF id */ 2239316485Sdavidcs#define DMAE_CMD_SRC_VF_ID_SHIFT 0 2240316485Sdavidcs#define DMAE_CMD_DST_VF_ID_MASK 0xFF /* Destination VF id */ 2241316485Sdavidcs#define DMAE_CMD_DST_VF_ID_SHIFT 8 2242316485Sdavidcs __le32 comp_addr_lo /* PCIe completion address low in bytes or GRC completion address in DW */; 2243316485Sdavidcs __le32 comp_addr_hi /* PCIe completion address high in bytes or reserved (if completion address is GRC) */; 2244316485Sdavidcs __le32 comp_val /* Value to write to completion address */; 2245316485Sdavidcs __le32 crc32 /* crc16 result */; 2246316485Sdavidcs __le32 crc_32_c /* crc32_c result */; 2247316485Sdavidcs __le16 crc16 /* crc16 result */; 2248316485Sdavidcs __le16 crc16_c /* crc16_c result */; 2249316485Sdavidcs __le16 crc10 /* crc_t10 result */; 2250316485Sdavidcs __le16 reserved; 2251316485Sdavidcs __le16 xsum16 /* checksum16 result */; 2252316485Sdavidcs __le16 xsum8 /* checksum8 result */; 2253316485Sdavidcs}; 2254316485Sdavidcs 2255316485Sdavidcs 2256316485Sdavidcsenum dmae_cmd_comp_crc_en_enum 2257316485Sdavidcs{ 2258316485Sdavidcs dmae_cmd_comp_crc_disabled /* Do not write a CRC word */, 2259316485Sdavidcs dmae_cmd_comp_crc_enabled /* Write a CRC word */, 2260316485Sdavidcs MAX_DMAE_CMD_COMP_CRC_EN_ENUM 2261316485Sdavidcs}; 2262316485Sdavidcs 2263316485Sdavidcs 2264316485Sdavidcsenum dmae_cmd_comp_func_enum 2265316485Sdavidcs{ 2266316485Sdavidcs dmae_cmd_comp_func_to_src /* completion word and/or CRC will be sent to SRC-PCI function/SRC VFID */, 2267316485Sdavidcs dmae_cmd_comp_func_to_dst /* completion word and/or CRC will be sent to DST-PCI function/DST VFID */, 2268316485Sdavidcs MAX_DMAE_CMD_COMP_FUNC_ENUM 2269316485Sdavidcs}; 2270316485Sdavidcs 2271316485Sdavidcs 2272316485Sdavidcsenum dmae_cmd_comp_word_en_enum 2273316485Sdavidcs{ 2274316485Sdavidcs dmae_cmd_comp_word_disabled /* Do not write a completion word */, 2275316485Sdavidcs dmae_cmd_comp_word_enabled /* Write the completion word */, 2276316485Sdavidcs MAX_DMAE_CMD_COMP_WORD_EN_ENUM 2277316485Sdavidcs}; 2278316485Sdavidcs 2279316485Sdavidcs 2280316485Sdavidcsenum dmae_cmd_c_dst_enum 2281316485Sdavidcs{ 2282316485Sdavidcs dmae_cmd_c_dst_pcie, 2283316485Sdavidcs dmae_cmd_c_dst_grc, 2284316485Sdavidcs MAX_DMAE_CMD_C_DST_ENUM 2285316485Sdavidcs}; 2286316485Sdavidcs 2287316485Sdavidcs 2288316485Sdavidcsenum dmae_cmd_dst_enum 2289316485Sdavidcs{ 2290316485Sdavidcs dmae_cmd_dst_none_0, 2291316485Sdavidcs dmae_cmd_dst_pcie, 2292316485Sdavidcs dmae_cmd_dst_grc, 2293316485Sdavidcs dmae_cmd_dst_none_3, 2294316485Sdavidcs MAX_DMAE_CMD_DST_ENUM 2295316485Sdavidcs}; 2296316485Sdavidcs 2297316485Sdavidcs 2298316485Sdavidcsenum dmae_cmd_error_handling_enum 2299316485Sdavidcs{ 2300316485Sdavidcs dmae_cmd_error_handling_send_regular_comp /* Send a regular completion (with no error indication) */, 2301316485Sdavidcs dmae_cmd_error_handling_send_comp_with_err /* Send a completion with an error indication (i.e. set bit 31 of the completion word) */, 2302316485Sdavidcs dmae_cmd_error_handling_dont_send_comp /* Do not send a completion */, 2303316485Sdavidcs MAX_DMAE_CMD_ERROR_HANDLING_ENUM 2304316485Sdavidcs}; 2305316485Sdavidcs 2306316485Sdavidcs 2307316485Sdavidcsenum dmae_cmd_src_enum 2308316485Sdavidcs{ 2309316485Sdavidcs dmae_cmd_src_pcie /* The source is the PCIe */, 2310316485Sdavidcs dmae_cmd_src_grc /* The source is the GRC */, 2311316485Sdavidcs MAX_DMAE_CMD_SRC_ENUM 2312316485Sdavidcs}; 2313316485Sdavidcs 2314316485Sdavidcs 2315316485Sdavidcsstruct e4_mstorm_core_conn_ag_ctx 2316316485Sdavidcs{ 2317316485Sdavidcs u8 byte0 /* cdu_validation */; 2318316485Sdavidcs u8 byte1 /* state */; 2319316485Sdavidcs u8 flags0; 2320316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2321316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2322316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2323316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2324316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2325316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2326316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2327316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2328316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2329316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2330316485Sdavidcs u8 flags1; 2331316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2332316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2333316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2334316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2335316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2336316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2337316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2338316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2339316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2340316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2341316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2342316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2343316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2344316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2345316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2346316485Sdavidcs#define E4_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2347316485Sdavidcs __le16 word0 /* word0 */; 2348316485Sdavidcs __le16 word1 /* word1 */; 2349316485Sdavidcs __le32 reg0 /* reg0 */; 2350316485Sdavidcs __le32 reg1 /* reg1 */; 2351316485Sdavidcs}; 2352316485Sdavidcs 2353316485Sdavidcs 2354316485Sdavidcs 2355316485Sdavidcs 2356316485Sdavidcs 2357316485Sdavidcsstruct e4_ystorm_core_conn_ag_ctx 2358316485Sdavidcs{ 2359316485Sdavidcs u8 byte0 /* cdu_validation */; 2360316485Sdavidcs u8 byte1 /* state */; 2361316485Sdavidcs u8 flags0; 2362316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2363316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2364316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2365316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2366316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2367316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2368316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2369316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2370316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2371316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2372316485Sdavidcs u8 flags1; 2373316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2374316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2375316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2376316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2377316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2378316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2379316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2380316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2381316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2382316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2383316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2384316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2385316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2386316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2387316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2388316485Sdavidcs#define E4_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2389316485Sdavidcs u8 byte2 /* byte2 */; 2390316485Sdavidcs u8 byte3 /* byte3 */; 2391316485Sdavidcs __le16 word0 /* word0 */; 2392316485Sdavidcs __le32 reg0 /* reg0 */; 2393316485Sdavidcs __le32 reg1 /* reg1 */; 2394316485Sdavidcs __le16 word1 /* word1 */; 2395316485Sdavidcs __le16 word2 /* word2 */; 2396316485Sdavidcs __le16 word3 /* word3 */; 2397316485Sdavidcs __le16 word4 /* word4 */; 2398316485Sdavidcs __le32 reg2 /* reg2 */; 2399316485Sdavidcs __le32 reg3 /* reg3 */; 2400316485Sdavidcs}; 2401316485Sdavidcs 2402316485Sdavidcs 2403316485Sdavidcsstruct e5_mstorm_core_conn_ag_ctx 2404316485Sdavidcs{ 2405316485Sdavidcs u8 byte0 /* cdu_validation */; 2406316485Sdavidcs u8 byte1 /* state_and_core_id */; 2407316485Sdavidcs u8 flags0; 2408316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2409316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2410316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2411316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2412316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2413316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2414316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2415316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2416316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2417316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2418316485Sdavidcs u8 flags1; 2419316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2420316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2421316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2422316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2423316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2424316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2425316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2426316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2427316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2428316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2429316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2430316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2431316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2432316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2433316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2434316485Sdavidcs#define E5_MSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2435316485Sdavidcs __le16 word0 /* word0 */; 2436316485Sdavidcs __le16 word1 /* word1 */; 2437316485Sdavidcs __le32 reg0 /* reg0 */; 2438316485Sdavidcs __le32 reg1 /* reg1 */; 2439316485Sdavidcs}; 2440316485Sdavidcs 2441316485Sdavidcs 2442316485Sdavidcs 2443316485Sdavidcs 2444316485Sdavidcs 2445316485Sdavidcsstruct e5_ystorm_core_conn_ag_ctx 2446316485Sdavidcs{ 2447316485Sdavidcs u8 byte0 /* cdu_validation */; 2448316485Sdavidcs u8 byte1 /* state_and_core_id */; 2449316485Sdavidcs u8 flags0; 2450316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_MASK 0x1 /* exist_in_qm0 */ 2451316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_BIT0_SHIFT 0 2452316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_MASK 0x1 /* exist_in_qm1 */ 2453316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_BIT1_SHIFT 1 2454316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF0_MASK 0x3 /* cf0 */ 2455316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF0_SHIFT 2 2456316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF1_MASK 0x3 /* cf1 */ 2457316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF1_SHIFT 4 2458316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF2_MASK 0x3 /* cf2 */ 2459316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF2_SHIFT 6 2460316485Sdavidcs u8 flags1; 2461316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_MASK 0x1 /* cf0en */ 2462316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF0EN_SHIFT 0 2463316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_MASK 0x1 /* cf1en */ 2464316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF1EN_SHIFT 1 2465316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_MASK 0x1 /* cf2en */ 2466316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_CF2EN_SHIFT 2 2467316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_MASK 0x1 /* rule0en */ 2468316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE0EN_SHIFT 3 2469316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_MASK 0x1 /* rule1en */ 2470316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE1EN_SHIFT 4 2471316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_MASK 0x1 /* rule2en */ 2472316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE2EN_SHIFT 5 2473316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_MASK 0x1 /* rule3en */ 2474316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE3EN_SHIFT 6 2475316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_MASK 0x1 /* rule4en */ 2476316485Sdavidcs#define E5_YSTORM_CORE_CONN_AG_CTX_RULE4EN_SHIFT 7 2477316485Sdavidcs u8 byte2 /* byte2 */; 2478316485Sdavidcs u8 byte3 /* byte3 */; 2479316485Sdavidcs __le16 word0 /* word0 */; 2480316485Sdavidcs __le32 reg0 /* reg0 */; 2481316485Sdavidcs __le32 reg1 /* reg1 */; 2482316485Sdavidcs __le16 word1 /* word1 */; 2483316485Sdavidcs __le16 word2 /* word2 */; 2484316485Sdavidcs __le16 word3 /* word3 */; 2485316485Sdavidcs __le16 word4 /* word4 */; 2486316485Sdavidcs __le32 reg2 /* reg2 */; 2487316485Sdavidcs __le32 reg3 /* reg3 */; 2488316485Sdavidcs}; 2489316485Sdavidcs 2490316485Sdavidcs 2491337519Sdavidcsstruct fw_asserts_ram_section 2492337519Sdavidcs{ 2493337519Sdavidcs __le16 section_ram_line_offset /* The offset of the section in the RAM in RAM lines (64-bit units) */; 2494337519Sdavidcs __le16 section_ram_line_size /* The size of the section in RAM lines (64-bit units) */; 2495337519Sdavidcs u8 list_dword_offset /* The offset of the asserts list within the section in dwords */; 2496337519Sdavidcs u8 list_element_dword_size /* The size of an assert list element in dwords */; 2497337519Sdavidcs u8 list_num_elements /* The number of elements in the asserts list */; 2498337519Sdavidcs u8 list_next_index_dword_offset /* The offset of the next list index field within the section in dwords */; 2499337519Sdavidcs}; 2500337519Sdavidcs 2501337519Sdavidcs 2502337519Sdavidcsstruct fw_ver_num 2503337519Sdavidcs{ 2504337519Sdavidcs u8 major /* Firmware major version number */; 2505337519Sdavidcs u8 minor /* Firmware minor version number */; 2506337519Sdavidcs u8 rev /* Firmware revision version number */; 2507337519Sdavidcs u8 eng /* Firmware engineering version number (for bootleg versions) */; 2508337519Sdavidcs}; 2509337519Sdavidcs 2510337519Sdavidcsstruct fw_ver_info 2511337519Sdavidcs{ 2512337519Sdavidcs __le16 tools_ver /* Tools version number */; 2513337519Sdavidcs u8 image_id /* FW image ID (e.g. main, l2b, kuku) */; 2514337519Sdavidcs u8 reserved1; 2515337519Sdavidcs struct fw_ver_num num /* FW version number */; 2516337519Sdavidcs __le32 timestamp /* FW Timestamp in unix time (sec. since 1970) */; 2517337519Sdavidcs __le32 reserved2; 2518337519Sdavidcs}; 2519337519Sdavidcs 2520337519Sdavidcsstruct fw_info 2521337519Sdavidcs{ 2522337519Sdavidcs struct fw_ver_info ver /* FW version information */; 2523337519Sdavidcs struct fw_asserts_ram_section fw_asserts_section /* Info regarding the FW asserts section in the Storm RAM */; 2524337519Sdavidcs}; 2525337519Sdavidcs 2526337519Sdavidcs 2527337519Sdavidcsstruct fw_info_location 2528337519Sdavidcs{ 2529337519Sdavidcs __le32 grc_addr /* GRC address where the fw_info struct is located. */; 2530337519Sdavidcs __le32 size /* Size of the fw_info structure (thats located at the grc_addr). */; 2531337519Sdavidcs}; 2532337519Sdavidcs 2533337519Sdavidcs 2534337519Sdavidcs 2535337519Sdavidcs 2536316485Sdavidcs/* 2537316485Sdavidcs * IGU cleanup command 2538316485Sdavidcs */ 2539316485Sdavidcsstruct igu_cleanup 2540316485Sdavidcs{ 2541316485Sdavidcs __le32 sb_id_and_flags; 2542316485Sdavidcs#define IGU_CLEANUP_RESERVED0_MASK 0x7FFFFFF 2543316485Sdavidcs#define IGU_CLEANUP_RESERVED0_SHIFT 0 2544316485Sdavidcs#define IGU_CLEANUP_CLEANUP_SET_MASK 0x1 /* cleanup clear - 0, set - 1 */ 2545316485Sdavidcs#define IGU_CLEANUP_CLEANUP_SET_SHIFT 27 2546316485Sdavidcs#define IGU_CLEANUP_CLEANUP_TYPE_MASK 0x7 2547316485Sdavidcs#define IGU_CLEANUP_CLEANUP_TYPE_SHIFT 28 2548316485Sdavidcs#define IGU_CLEANUP_COMMAND_TYPE_MASK 0x1 /* must always be set (use enum command_type_bit) */ 2549316485Sdavidcs#define IGU_CLEANUP_COMMAND_TYPE_SHIFT 31 2550316485Sdavidcs __le32 reserved1; 2551316485Sdavidcs}; 2552316485Sdavidcs 2553316485Sdavidcs 2554316485Sdavidcs/* 2555316485Sdavidcs * IGU firmware driver command 2556316485Sdavidcs */ 2557316485Sdavidcsunion igu_command 2558316485Sdavidcs{ 2559316485Sdavidcs struct igu_prod_cons_update prod_cons_update; 2560316485Sdavidcs struct igu_cleanup cleanup; 2561316485Sdavidcs}; 2562316485Sdavidcs 2563316485Sdavidcs 2564316485Sdavidcs/* 2565316485Sdavidcs * IGU firmware driver command 2566316485Sdavidcs */ 2567316485Sdavidcsstruct igu_command_reg_ctrl 2568316485Sdavidcs{ 2569316485Sdavidcs __le16 opaque_fid; 2570316485Sdavidcs __le16 igu_command_reg_ctrl_fields; 2571316485Sdavidcs#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_MASK 0xFFF 2572316485Sdavidcs#define IGU_COMMAND_REG_CTRL_PXP_BAR_ADDR_SHIFT 0 2573316485Sdavidcs#define IGU_COMMAND_REG_CTRL_RESERVED_MASK 0x7 2574316485Sdavidcs#define IGU_COMMAND_REG_CTRL_RESERVED_SHIFT 12 2575316485Sdavidcs#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_MASK 0x1 /* command typ: 0 - read, 1 - write */ 2576316485Sdavidcs#define IGU_COMMAND_REG_CTRL_COMMAND_TYPE_SHIFT 15 2577316485Sdavidcs}; 2578316485Sdavidcs 2579316485Sdavidcs 2580316485Sdavidcs/* 2581316485Sdavidcs * IGU mapping line structure 2582316485Sdavidcs */ 2583316485Sdavidcsstruct igu_mapping_line 2584316485Sdavidcs{ 2585316485Sdavidcs __le32 igu_mapping_line_fields; 2586316485Sdavidcs#define IGU_MAPPING_LINE_VALID_MASK 0x1 2587316485Sdavidcs#define IGU_MAPPING_LINE_VALID_SHIFT 0 2588316485Sdavidcs#define IGU_MAPPING_LINE_VECTOR_NUMBER_MASK 0xFF 2589316485Sdavidcs#define IGU_MAPPING_LINE_VECTOR_NUMBER_SHIFT 1 2590316485Sdavidcs#define IGU_MAPPING_LINE_FUNCTION_NUMBER_MASK 0xFF /* In BB: VF-0-120, PF-0-7; In K2: VF-0-191, PF-0-15 */ 2591316485Sdavidcs#define IGU_MAPPING_LINE_FUNCTION_NUMBER_SHIFT 9 2592316485Sdavidcs#define IGU_MAPPING_LINE_PF_VALID_MASK 0x1 /* PF-1, VF-0 */ 2593316485Sdavidcs#define IGU_MAPPING_LINE_PF_VALID_SHIFT 17 2594316485Sdavidcs#define IGU_MAPPING_LINE_IPS_GROUP_MASK 0x3F 2595316485Sdavidcs#define IGU_MAPPING_LINE_IPS_GROUP_SHIFT 18 2596316485Sdavidcs#define IGU_MAPPING_LINE_RESERVED_MASK 0xFF 2597316485Sdavidcs#define IGU_MAPPING_LINE_RESERVED_SHIFT 24 2598316485Sdavidcs}; 2599316485Sdavidcs 2600316485Sdavidcs 2601316485Sdavidcs/* 2602316485Sdavidcs * IGU MSIX line structure 2603316485Sdavidcs */ 2604316485Sdavidcsstruct igu_msix_vector 2605316485Sdavidcs{ 2606316485Sdavidcs struct regpair address; 2607316485Sdavidcs __le32 data; 2608316485Sdavidcs __le32 msix_vector_fields; 2609316485Sdavidcs#define IGU_MSIX_VECTOR_MASK_BIT_MASK 0x1 2610316485Sdavidcs#define IGU_MSIX_VECTOR_MASK_BIT_SHIFT 0 2611316485Sdavidcs#define IGU_MSIX_VECTOR_RESERVED0_MASK 0x7FFF 2612316485Sdavidcs#define IGU_MSIX_VECTOR_RESERVED0_SHIFT 1 2613316485Sdavidcs#define IGU_MSIX_VECTOR_STEERING_TAG_MASK 0xFF 2614316485Sdavidcs#define IGU_MSIX_VECTOR_STEERING_TAG_SHIFT 16 2615316485Sdavidcs#define IGU_MSIX_VECTOR_RESERVED1_MASK 0xFF 2616316485Sdavidcs#define IGU_MSIX_VECTOR_RESERVED1_SHIFT 24 2617316485Sdavidcs}; 2618316485Sdavidcs 2619316485Sdavidcs 2620316485Sdavidcs/* 2621316485Sdavidcs * per encapsulation type enabling flags 2622316485Sdavidcs */ 2623316485Sdavidcsstruct prs_reg_encapsulation_type_en 2624316485Sdavidcs{ 2625316485Sdavidcs u8 flags; 2626316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GRE (L2 GRE) encapsulation. */ 2627316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GRE_ENABLE_SHIFT 0 2628316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GRE (IP GRE) encapsulation. */ 2629316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GRE_ENABLE_SHIFT 1 2630316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_MASK 0x1 /* Enable bit for VXLAN encapsulation. */ 2631316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_VXLAN_ENABLE_SHIFT 2 2632316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_MASK 0x1 /* Enable bit for T-Tag encapsulation. */ 2633316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_T_TAG_ENABLE_SHIFT 3 2634316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for Ethernet-over-GENEVE (L2 GENEVE) encapsulation. */ 2635316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_ETH_OVER_GENEVE_ENABLE_SHIFT 4 2636316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_MASK 0x1 /* Enable bit for IP-over-GENEVE (IP GENEVE) encapsulation. */ 2637316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_IP_OVER_GENEVE_ENABLE_SHIFT 5 2638316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_MASK 0x3 2639316485Sdavidcs#define PRS_REG_ENCAPSULATION_TYPE_EN_RESERVED_SHIFT 6 2640316485Sdavidcs}; 2641316485Sdavidcs 2642316485Sdavidcs 2643316485Sdavidcsenum pxp_tph_st_hint 2644316485Sdavidcs{ 2645316485Sdavidcs TPH_ST_HINT_BIDIR /* Read/Write access by Host and Device */, 2646316485Sdavidcs TPH_ST_HINT_REQUESTER /* Read/Write access by Device */, 2647316485Sdavidcs TPH_ST_HINT_TARGET /* Device Write and Host Read, or Host Write and Device Read */, 2648316485Sdavidcs TPH_ST_HINT_TARGET_PRIO /* Device Write and Host Read, or Host Write and Device Read - with temporal reuse */, 2649316485Sdavidcs MAX_PXP_TPH_ST_HINT 2650316485Sdavidcs}; 2651316485Sdavidcs 2652316485Sdavidcs 2653316485Sdavidcs/* 2654316485Sdavidcs * QM hardware structure of enable bypass credit mask 2655316485Sdavidcs */ 2656316485Sdavidcsstruct qm_rf_bypass_mask 2657316485Sdavidcs{ 2658316485Sdavidcs u8 flags; 2659316485Sdavidcs#define QM_RF_BYPASS_MASK_LINEVOQ_MASK 0x1 2660316485Sdavidcs#define QM_RF_BYPASS_MASK_LINEVOQ_SHIFT 0 2661316485Sdavidcs#define QM_RF_BYPASS_MASK_RESERVED0_MASK 0x1 2662316485Sdavidcs#define QM_RF_BYPASS_MASK_RESERVED0_SHIFT 1 2663316485Sdavidcs#define QM_RF_BYPASS_MASK_PFWFQ_MASK 0x1 2664316485Sdavidcs#define QM_RF_BYPASS_MASK_PFWFQ_SHIFT 2 2665316485Sdavidcs#define QM_RF_BYPASS_MASK_VPWFQ_MASK 0x1 2666316485Sdavidcs#define QM_RF_BYPASS_MASK_VPWFQ_SHIFT 3 2667316485Sdavidcs#define QM_RF_BYPASS_MASK_PFRL_MASK 0x1 2668316485Sdavidcs#define QM_RF_BYPASS_MASK_PFRL_SHIFT 4 2669316485Sdavidcs#define QM_RF_BYPASS_MASK_VPQCNRL_MASK 0x1 2670316485Sdavidcs#define QM_RF_BYPASS_MASK_VPQCNRL_SHIFT 5 2671316485Sdavidcs#define QM_RF_BYPASS_MASK_FWPAUSE_MASK 0x1 2672316485Sdavidcs#define QM_RF_BYPASS_MASK_FWPAUSE_SHIFT 6 2673316485Sdavidcs#define QM_RF_BYPASS_MASK_RESERVED1_MASK 0x1 2674316485Sdavidcs#define QM_RF_BYPASS_MASK_RESERVED1_SHIFT 7 2675316485Sdavidcs}; 2676316485Sdavidcs 2677316485Sdavidcs 2678316485Sdavidcs/* 2679316485Sdavidcs * QM hardware structure of opportunistic credit mask 2680316485Sdavidcs */ 2681316485Sdavidcsstruct qm_rf_opportunistic_mask 2682316485Sdavidcs{ 2683316485Sdavidcs __le16 flags; 2684316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_MASK 0x1 2685316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_LINEVOQ_SHIFT 0 2686316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_MASK 0x1 2687316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_BYTEVOQ_SHIFT 1 2688316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_MASK 0x1 2689316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_PFWFQ_SHIFT 2 2690316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_MASK 0x1 2691316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_VPWFQ_SHIFT 3 2692316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_PFRL_MASK 0x1 2693316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_PFRL_SHIFT 4 2694316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_MASK 0x1 2695316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_VPQCNRL_SHIFT 5 2696316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_MASK 0x1 2697316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_FWPAUSE_SHIFT 6 2698316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_MASK 0x1 2699316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_RESERVED0_SHIFT 7 2700316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_MASK 0x1 2701316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_QUEUEEMPTY_SHIFT 8 2702316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_MASK 0x7F 2703316485Sdavidcs#define QM_RF_OPPORTUNISTIC_MASK_RESERVED1_SHIFT 9 2704316485Sdavidcs}; 2705316485Sdavidcs 2706316485Sdavidcs 2707316485Sdavidcs/* 2708320162Sdavidcs * E4 QM hardware structure of QM map memory 2709316485Sdavidcs */ 2710320162Sdavidcsstruct qm_rf_pq_map_e4 2711316485Sdavidcs{ 2712316485Sdavidcs __le32 reg; 2713320162Sdavidcs#define QM_RF_PQ_MAP_E4_PQ_VALID_MASK 0x1 /* PQ active */ 2714320162Sdavidcs#define QM_RF_PQ_MAP_E4_PQ_VALID_SHIFT 0 2715320162Sdavidcs#define QM_RF_PQ_MAP_E4_RL_ID_MASK 0xFF /* RL ID */ 2716320162Sdavidcs#define QM_RF_PQ_MAP_E4_RL_ID_SHIFT 1 2717320162Sdavidcs#define QM_RF_PQ_MAP_E4_VP_PQ_ID_MASK 0x1FF /* the first PQ associated with the VPORT and VOQ of this PQ */ 2718320162Sdavidcs#define QM_RF_PQ_MAP_E4_VP_PQ_ID_SHIFT 9 2719320162Sdavidcs#define QM_RF_PQ_MAP_E4_VOQ_MASK 0x1F /* VOQ */ 2720320162Sdavidcs#define QM_RF_PQ_MAP_E4_VOQ_SHIFT 18 2721320162Sdavidcs#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */ 2722320162Sdavidcs#define QM_RF_PQ_MAP_E4_WRR_WEIGHT_GROUP_SHIFT 23 2723320162Sdavidcs#define QM_RF_PQ_MAP_E4_RL_VALID_MASK 0x1 /* RL active */ 2724320162Sdavidcs#define QM_RF_PQ_MAP_E4_RL_VALID_SHIFT 25 2725320162Sdavidcs#define QM_RF_PQ_MAP_E4_RESERVED_MASK 0x3F 2726320162Sdavidcs#define QM_RF_PQ_MAP_E4_RESERVED_SHIFT 26 2727316485Sdavidcs}; 2728316485Sdavidcs 2729316485Sdavidcs 2730316485Sdavidcs/* 2731320162Sdavidcs * E5 QM hardware structure of QM map memory 2732320162Sdavidcs */ 2733320162Sdavidcsstruct qm_rf_pq_map_e5 2734320162Sdavidcs{ 2735320162Sdavidcs __le32 reg; 2736320162Sdavidcs#define QM_RF_PQ_MAP_E5_PQ_VALID_MASK 0x1 /* PQ active */ 2737320162Sdavidcs#define QM_RF_PQ_MAP_E5_PQ_VALID_SHIFT 0 2738320162Sdavidcs#define QM_RF_PQ_MAP_E5_RL_ID_MASK 0xFF /* RL ID */ 2739320162Sdavidcs#define QM_RF_PQ_MAP_E5_RL_ID_SHIFT 1 2740320162Sdavidcs#define QM_RF_PQ_MAP_E5_VP_PQ_ID_MASK 0x1FF /* the first PQ associated with the VPORT and VOQ of this PQ */ 2741320162Sdavidcs#define QM_RF_PQ_MAP_E5_VP_PQ_ID_SHIFT 9 2742320162Sdavidcs#define QM_RF_PQ_MAP_E5_VOQ_MASK 0x3F /* VOQ */ 2743320162Sdavidcs#define QM_RF_PQ_MAP_E5_VOQ_SHIFT 18 2744320162Sdavidcs#define QM_RF_PQ_MAP_E5_WRR_WEIGHT_GROUP_MASK 0x3 /* WRR weight */ 2745320162Sdavidcs#define QM_RF_PQ_MAP_E5_WRR_WEIGHT_GROUP_SHIFT 24 2746320162Sdavidcs#define QM_RF_PQ_MAP_E5_RL_VALID_MASK 0x1 /* RL active */ 2747320162Sdavidcs#define QM_RF_PQ_MAP_E5_RL_VALID_SHIFT 26 2748320162Sdavidcs#define QM_RF_PQ_MAP_E5_RESERVED_MASK 0x1F 2749320162Sdavidcs#define QM_RF_PQ_MAP_E5_RESERVED_SHIFT 27 2750320162Sdavidcs}; 2751320162Sdavidcs 2752320162Sdavidcs 2753320162Sdavidcs/* 2754316485Sdavidcs * Completion params for aggregated interrupt completion 2755316485Sdavidcs */ 2756316485Sdavidcsstruct sdm_agg_int_comp_params 2757316485Sdavidcs{ 2758316485Sdavidcs __le16 params; 2759316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_MASK 0x3F /* the number of aggregated interrupt, 0-31 */ 2760316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_INT_INDEX_SHIFT 0 2761316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_MASK 0x1 /* 1 - set a bit in aggregated vector, 0 - dont set */ 2762316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_ENABLE_SHIFT 6 2763316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_MASK 0x1FF /* Number of bit in the aggregated vector, 0-279 (TBD) */ 2764316485Sdavidcs#define SDM_AGG_INT_COMP_PARAMS_AGG_VECTOR_BIT_SHIFT 7 2765316485Sdavidcs}; 2766316485Sdavidcs 2767316485Sdavidcs 2768316485Sdavidcs/* 2769316485Sdavidcs * SDM operation gen command (generate aggregative interrupt) 2770316485Sdavidcs */ 2771316485Sdavidcsstruct sdm_op_gen 2772316485Sdavidcs{ 2773316485Sdavidcs __le32 command; 2774316485Sdavidcs#define SDM_OP_GEN_COMP_PARAM_MASK 0xFFFF /* completion parameters 0-15 */ 2775316485Sdavidcs#define SDM_OP_GEN_COMP_PARAM_SHIFT 0 2776316485Sdavidcs#define SDM_OP_GEN_COMP_TYPE_MASK 0xF /* completion type 16-19 */ 2777316485Sdavidcs#define SDM_OP_GEN_COMP_TYPE_SHIFT 16 2778316485Sdavidcs#define SDM_OP_GEN_RESERVED_MASK 0xFFF /* reserved 20-31 */ 2779316485Sdavidcs#define SDM_OP_GEN_RESERVED_SHIFT 20 2780316485Sdavidcs}; 2781316485Sdavidcs 2782316485Sdavidcs#endif /* __ECORE_HSI_COMMON__ */ 2783