1139749Simp/*- 2158124Smarcel * Copyright (c) 2006 Marcel Moolenaar 3158124Smarcel * All rights reserved. 490731Sjhay * 590731Sjhay * Redistribution and use in source and binary forms, with or without 690731Sjhay * modification, are permitted provided that the following conditions 790731Sjhay * are met: 8158124Smarcel * 990731Sjhay * 1. Redistributions of source code must retain the above copyright 1090731Sjhay * notice, this list of conditions and the following disclaimer. 1190731Sjhay * 2. Redistributions in binary form must reproduce the above copyright 1290731Sjhay * notice, this list of conditions and the following disclaimer in the 1390731Sjhay * documentation and/or other materials provided with the distribution. 1490731Sjhay * 1590731Sjhay * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 1690731Sjhay * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 1790731Sjhay * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 1890731Sjhay * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 1990731Sjhay * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 2090731Sjhay * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 2190731Sjhay * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 2290731Sjhay * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 2390731Sjhay * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 2490731Sjhay * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 2590731Sjhay */ 2690731Sjhay 2790731Sjhay#include <sys/cdefs.h> 2890731Sjhay__FBSDID("$FreeBSD: stable/10/sys/dev/puc/pucdata.c 318151 2017-05-10 20:12:23Z marius $"); 2990731Sjhay 3090731Sjhay/* 3190731Sjhay * PCI "universal" communications card driver configuration data (used to 3290731Sjhay * match/attach the cards). 3390731Sjhay */ 3490731Sjhay 3590731Sjhay#include <sys/param.h> 36158124Smarcel#include <sys/systm.h> 37158124Smarcel#include <sys/kernel.h> 38158124Smarcel#include <sys/bus.h> 39287926Srstone#include <sys/sysctl.h> 4090731Sjhay 41158124Smarcel#include <machine/resource.h> 42159545Simp#include <machine/bus.h> 43158124Smarcel#include <sys/rman.h> 44158124Smarcel 45318151Smarius#include <dev/ic/ns16550.h> 46318151Smarius 47318151Smarius#include <dev/pci/pcireg.h> 4890731Sjhay#include <dev/pci/pcivar.h> 4990731Sjhay 50158124Smarcel#include <dev/puc/puc_bus.h> 51158124Smarcel#include <dev/puc/puc_cfg.h> 52160030Sobrien#include <dev/puc/puc_bfe.h> 5390731Sjhay 54318151Smariusstatic puc_config_f puc_config_advantech; 55158124Smarcelstatic puc_config_f puc_config_amc; 56158124Smarcelstatic puc_config_f puc_config_diva; 57222660Sjhbstatic puc_config_f puc_config_exar; 58248340Srstonestatic puc_config_f puc_config_exar_pcie; 59158124Smarcelstatic puc_config_f puc_config_icbook; 60227457Seadlerstatic puc_config_f puc_config_moxa; 61251715Smariusstatic puc_config_f puc_config_oxford_pci954; 62222760Sjhbstatic puc_config_f puc_config_oxford_pcie; 63158124Smarcelstatic puc_config_f puc_config_quatech; 64158124Smarcelstatic puc_config_f puc_config_syba; 65158124Smarcelstatic puc_config_f puc_config_siig; 66264761Smariusstatic puc_config_f puc_config_sunix; 67158124Smarcelstatic puc_config_f puc_config_timedia; 68158124Smarcelstatic puc_config_f puc_config_titan; 69119814Smarcel 70158124Smarcelconst struct puc_cfg puc_pci_devices[] = { 71158124Smarcel { 0x0009, 0x7168, 0xffff, 0, 72158124Smarcel "Sunix SUN1889", 73158124Smarcel DEFAULT_RCLK * 8, 74158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 75128380Sbde }, 76128380Sbde 77158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1049, 78158124Smarcel "HP Diva Serial [GSP] Multiport UART - Tosca Console", 79158124Smarcel DEFAULT_RCLK, 80158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 81158124Smarcel .config_function = puc_config_diva 82119814Smarcel }, 83119814Smarcel 84158124Smarcel { 0x103c, 0x1048, 0x103c, 0x104a, 85158124Smarcel "HP Diva Serial [GSP] Multiport UART - Tosca Secondary", 86158124Smarcel DEFAULT_RCLK, 87158124Smarcel PUC_PORT_2S, 0x10, 0, -1, 88158124Smarcel .config_function = puc_config_diva 8998376Sobrien }, 9098376Sobrien 91158124Smarcel { 0x103c, 0x1048, 0x103c, 0x104b, 92158124Smarcel "HP Diva Serial [GSP] Multiport UART - Maestro SP2", 93158124Smarcel DEFAULT_RCLK, 94158124Smarcel PUC_PORT_4S, 0x10, 0, -1, 95158124Smarcel .config_function = puc_config_diva 9698376Sobrien }, 9798376Sobrien 98158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1223, 99158124Smarcel "HP Diva Serial [GSP] Multiport UART - Superdome Console", 100158124Smarcel DEFAULT_RCLK, 101158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 102158124Smarcel .config_function = puc_config_diva 10398376Sobrien }, 104158124Smarcel 105158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1226, 106158124Smarcel "HP Diva Serial [GSP] Multiport UART - Keystone SP2", 107158124Smarcel DEFAULT_RCLK, 108158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 109158124Smarcel .config_function = puc_config_diva 11098376Sobrien }, 11198376Sobrien 112158124Smarcel { 0x103c, 0x1048, 0x103c, 0x1282, 113158124Smarcel "HP Diva Serial [GSP] Multiport UART - Everest SP2", 114158124Smarcel DEFAULT_RCLK, 115158124Smarcel PUC_PORT_3S, 0x10, 0, -1, 116158124Smarcel .config_function = puc_config_diva 11798376Sobrien }, 118158124Smarcel 119158124Smarcel { 0x10b5, 0x1076, 0x10b5, 0x1076, 120158124Smarcel "VScom PCI-800", 121158124Smarcel DEFAULT_RCLK * 8, 122158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 12398376Sobrien }, 12498376Sobrien 125158124Smarcel { 0x10b5, 0x1077, 0x10b5, 0x1077, 126158124Smarcel "VScom PCI-400", 127158124Smarcel DEFAULT_RCLK * 8, 128158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 12998376Sobrien }, 13098376Sobrien 131158124Smarcel { 0x10b5, 0x1103, 0x10b5, 0x1103, 132158124Smarcel "VScom PCI-200", 133158124Smarcel DEFAULT_RCLK * 8, 134158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 13598374Sobrien }, 13698376Sobrien 13790731Sjhay /* 138158124Smarcel * Boca Research Turbo Serial 658 (8 serial port) card. 139158124Smarcel * Appears to be the same as Chase Research PLC PCI-FAST8 140158124Smarcel * and Perle PCI-FAST8 Multi-Port serial cards. 14190731Sjhay */ 142158124Smarcel { 0x10b5, 0x9050, 0x12e0, 0x0021, 143158124Smarcel "Boca Research Turbo Serial 658", 144158124Smarcel DEFAULT_RCLK * 4, 145158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 146158124Smarcel }, 14790731Sjhay 148158124Smarcel { 0x10b5, 0x9050, 0x12e0, 0x0031, 149158124Smarcel "Boca Research Turbo Serial 654", 150158124Smarcel DEFAULT_RCLK * 4, 151158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 152158124Smarcel }, 153158124Smarcel 15490731Sjhay /* 155158124Smarcel * Dolphin Peripherals 4035 (dual serial port) card. PLX 9050, with 15690731Sjhay * a seemingly-lame EEPROM setup that puts the Dolphin IDs 15790731Sjhay * into the subsystem fields, and claims that it's a 15890731Sjhay * network/misc (0x02/0x80) device. 15990731Sjhay */ 160158124Smarcel { 0x10b5, 0x9050, 0xd84d, 0x6808, 161158124Smarcel "Dolphin Peripherals 4035", 162158124Smarcel DEFAULT_RCLK, 163158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 16490731Sjhay }, 16590731Sjhay 16690731Sjhay /* 167158124Smarcel * Dolphin Peripherals 4014 (dual parallel port) card. PLX 9050, with 16890731Sjhay * a seemingly-lame EEPROM setup that puts the Dolphin IDs 16990731Sjhay * into the subsystem fields, and claims that it's a 17090731Sjhay * network/misc (0x02/0x80) device. 17190731Sjhay */ 172158124Smarcel { 0x10b5, 0x9050, 0xd84d, 0x6810, 173158124Smarcel "Dolphin Peripherals 4014", 174158124Smarcel 0, 175158124Smarcel PUC_PORT_2P, 0x20, 4, 0, 17690731Sjhay }, 17790731Sjhay 178158124Smarcel { 0x10e8, 0x818e, 0xffff, 0, 179158124Smarcel "Applied Micro Circuits 8 Port UART", 180200230Smarcel DEFAULT_RCLK, 181200230Smarcel PUC_PORT_8S, 0x14, -1, -1, 182158124Smarcel .config_function = puc_config_amc 183200230Smarcel }, 184158124Smarcel 185294961Smarius /* 186294961Smarius * The following members of the Digi International Neo series are 187294961Smarius * based on Exar PCI chips, f. e. the 8 port variants on XR17V258IV. 188294961Smarius * Accordingly, the PCIe versions of these cards incorporate a PLX 189294961Smarius * PCIe-PCI-bridge. 190294961Smarius */ 191294961Smarius 192294961Smarius { 0x114f, 0x00b0, 0xffff, 0, 193294961Smarius "Digi Neo PCI 4 Port", 194294961Smarius DEFAULT_RCLK * 8, 195294961Smarius PUC_PORT_4S, 0x10, 0, -1, 196294961Smarius .config_function = puc_config_exar 197294961Smarius }, 198294961Smarius 199294961Smarius { 0x114f, 0x00b1, 0xffff, 0, 200294961Smarius "Digi Neo PCI 8 Port", 201294961Smarius DEFAULT_RCLK * 8, 202294961Smarius PUC_PORT_8S, 0x10, 0, -1, 203294961Smarius .config_function = puc_config_exar 204294961Smarius }, 205294961Smarius 206294961Smarius { 0x114f, 0x00f0, 0xffff, 0, 207294961Smarius "Digi Neo PCIe 8 Port", 208294961Smarius DEFAULT_RCLK * 8, 209294961Smarius PUC_PORT_8S, 0x10, 0, -1, 210294961Smarius .config_function = puc_config_exar 211294961Smarius }, 212294961Smarius 213294961Smarius { 0x114f, 0x00f1, 0xffff, 0, 214294961Smarius "Digi Neo PCIe 4 Port", 215294961Smarius DEFAULT_RCLK * 8, 216294961Smarius PUC_PORT_4S, 0x10, 0, -1, 217294961Smarius .config_function = puc_config_exar 218294961Smarius }, 219294961Smarius 220294961Smarius { 0x114f, 0x00f2, 0xffff, 0, 221294961Smarius "Digi Neo PCIe 4 Port RJ45", 222294961Smarius DEFAULT_RCLK * 8, 223294961Smarius PUC_PORT_4S, 0x10, 0, -1, 224294961Smarius .config_function = puc_config_exar 225294961Smarius }, 226294961Smarius 227294961Smarius { 0x114f, 0x00f3, 0xffff, 0, 228294961Smarius "Digi Neo PCIe 8 Port RJ45", 229294961Smarius DEFAULT_RCLK * 8, 230294961Smarius PUC_PORT_8S, 0x10, 0, -1, 231294961Smarius .config_function = puc_config_exar 232294961Smarius }, 233294961Smarius 234158124Smarcel { 0x11fe, 0x8010, 0xffff, 0, 235158124Smarcel "Comtrol RocketPort 550/8 RJ11 part A", 236158124Smarcel DEFAULT_RCLK * 4, 237158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 23890731Sjhay }, 23990731Sjhay 240158124Smarcel { 0x11fe, 0x8011, 0xffff, 0, 241158124Smarcel "Comtrol RocketPort 550/8 RJ11 part B", 242158124Smarcel DEFAULT_RCLK * 4, 243158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 244158124Smarcel }, 24590731Sjhay 246158124Smarcel { 0x11fe, 0x8012, 0xffff, 0, 247158124Smarcel "Comtrol RocketPort 550/8 Octa part A", 248158124Smarcel DEFAULT_RCLK * 4, 249158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 250158124Smarcel }, 25190731Sjhay 252158124Smarcel { 0x11fe, 0x8013, 0xffff, 0, 253158124Smarcel "Comtrol RocketPort 550/8 Octa part B", 254158124Smarcel DEFAULT_RCLK * 4, 255158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 256158124Smarcel }, 257158124Smarcel 258158124Smarcel { 0x11fe, 0x8014, 0xffff, 0, 259158124Smarcel "Comtrol RocketPort 550/4 RJ45", 260158124Smarcel DEFAULT_RCLK * 4, 261158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 262158124Smarcel }, 263158124Smarcel 264158124Smarcel { 0x11fe, 0x8015, 0xffff, 0, 265158124Smarcel "Comtrol RocketPort 550/Quad", 266158124Smarcel DEFAULT_RCLK * 4, 267158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 268158124Smarcel }, 269158124Smarcel 270158124Smarcel { 0x11fe, 0x8016, 0xffff, 0, 271158124Smarcel "Comtrol RocketPort 550/16 part A", 272158124Smarcel DEFAULT_RCLK * 4, 273158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 274158124Smarcel }, 275158124Smarcel 276158124Smarcel { 0x11fe, 0x8017, 0xffff, 0, 277158124Smarcel "Comtrol RocketPort 550/16 part B", 278158124Smarcel DEFAULT_RCLK * 4, 279158124Smarcel PUC_PORT_12S, 0x10, 0, 8, 280158124Smarcel }, 281158124Smarcel 282158124Smarcel { 0x11fe, 0x8018, 0xffff, 0, 283158124Smarcel "Comtrol RocketPort 550/8 part A", 284158124Smarcel DEFAULT_RCLK * 4, 285158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 286158124Smarcel }, 287158124Smarcel 288158124Smarcel { 0x11fe, 0x8019, 0xffff, 0, 289158124Smarcel "Comtrol RocketPort 550/8 part B", 290158124Smarcel DEFAULT_RCLK * 4, 291158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 292158124Smarcel }, 293158124Smarcel 29490731Sjhay /* 295193305Srwatson * IBM SurePOS 300 Series (481033H) serial ports 296193305Srwatson * Details can be found on the IBM RSS websites 297193305Srwatson */ 298193305Srwatson 299193305Srwatson { 0x1014, 0x0297, 0xffff, 0, 300193305Srwatson "IBM SurePOS 300 Series (481033H) serial ports", 301193305Srwatson DEFAULT_RCLK, 302193305Srwatson PUC_PORT_4S, 0x10, 4, 0 303193305Srwatson }, 304193305Srwatson 305193305Srwatson /* 30690731Sjhay * SIIG Boards. 30790731Sjhay * 30890731Sjhay * SIIG provides documentation for their boards at: 309158124Smarcel * <URL:http://www.siig.com/downloads.asp> 31090731Sjhay */ 31190731Sjhay 312158124Smarcel { 0x131f, 0x1010, 0xffff, 0, 313158124Smarcel "SIIG Cyber I/O PCI 16C550 (10x family)", 314158124Smarcel DEFAULT_RCLK, 315158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 316158124Smarcel }, 31790731Sjhay 318158124Smarcel { 0x131f, 0x1011, 0xffff, 0, 319158124Smarcel "SIIG Cyber I/O PCI 16C650 (10x family)", 320158124Smarcel DEFAULT_RCLK, 321158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 32290731Sjhay }, 32390731Sjhay 324158124Smarcel { 0x131f, 0x1012, 0xffff, 0, 325158124Smarcel "SIIG Cyber I/O PCI 16C850 (10x family)", 326158124Smarcel DEFAULT_RCLK, 327158124Smarcel PUC_PORT_1S1P, 0x18, 4, 0, 32890731Sjhay }, 32990731Sjhay 330158124Smarcel { 0x131f, 0x1021, 0xffff, 0, 331158124Smarcel "SIIG Cyber Parallel Dual PCI (10x family)", 332158124Smarcel 0, 333158124Smarcel PUC_PORT_2P, 0x18, 8, 0, 33490731Sjhay }, 33590731Sjhay 336158124Smarcel { 0x131f, 0x1030, 0xffff, 0, 337158124Smarcel "SIIG Cyber Serial Dual PCI 16C550 (10x family)", 338158124Smarcel DEFAULT_RCLK, 339158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 34090731Sjhay }, 34190731Sjhay 342158124Smarcel { 0x131f, 0x1031, 0xffff, 0, 343158124Smarcel "SIIG Cyber Serial Dual PCI 16C650 (10x family)", 344158124Smarcel DEFAULT_RCLK, 345158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 34690731Sjhay }, 34790731Sjhay 348158124Smarcel { 0x131f, 0x1032, 0xffff, 0, 349158124Smarcel "SIIG Cyber Serial Dual PCI 16C850 (10x family)", 350158124Smarcel DEFAULT_RCLK, 351158124Smarcel PUC_PORT_2S, 0x18, 4, 0, 35290731Sjhay }, 35390731Sjhay 354158124Smarcel { 0x131f, 0x1034, 0xffff, 0, /* XXX really? */ 355158124Smarcel "SIIG Cyber 2S1P PCI 16C550 (10x family)", 356158124Smarcel DEFAULT_RCLK, 357158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 35890731Sjhay }, 35990731Sjhay 360158124Smarcel { 0x131f, 0x1035, 0xffff, 0, /* XXX really? */ 361158124Smarcel "SIIG Cyber 2S1P PCI 16C650 (10x family)", 362158124Smarcel DEFAULT_RCLK, 363158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 36490731Sjhay }, 36590731Sjhay 366158124Smarcel { 0x131f, 0x1036, 0xffff, 0, /* XXX really? */ 367158124Smarcel "SIIG Cyber 2S1P PCI 16C850 (10x family)", 368158124Smarcel DEFAULT_RCLK, 369158124Smarcel PUC_PORT_2S1P, 0x18, 4, 0, 37090731Sjhay }, 37190731Sjhay 372158124Smarcel { 0x131f, 0x1050, 0xffff, 0, 373158124Smarcel "SIIG Cyber 4S PCI 16C550 (10x family)", 374158124Smarcel DEFAULT_RCLK, 375158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 37690731Sjhay }, 37790731Sjhay 378158124Smarcel { 0x131f, 0x1051, 0xffff, 0, 379158124Smarcel "SIIG Cyber 4S PCI 16C650 (10x family)", 380158124Smarcel DEFAULT_RCLK, 381158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 38290731Sjhay }, 38390731Sjhay 384158124Smarcel { 0x131f, 0x1052, 0xffff, 0, 385158124Smarcel "SIIG Cyber 4S PCI 16C850 (10x family)", 386158124Smarcel DEFAULT_RCLK, 387158124Smarcel PUC_PORT_4S, 0x18, 4, 0, 38890731Sjhay }, 38990731Sjhay 390158124Smarcel { 0x131f, 0x2010, 0xffff, 0, 391158124Smarcel "SIIG Cyber I/O PCI 16C550 (20x family)", 392158124Smarcel DEFAULT_RCLK, 393158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 39490731Sjhay }, 39590731Sjhay 396158124Smarcel { 0x131f, 0x2011, 0xffff, 0, 397158124Smarcel "SIIG Cyber I/O PCI 16C650 (20x family)", 398158124Smarcel DEFAULT_RCLK, 399158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 40090731Sjhay }, 40190731Sjhay 402158124Smarcel { 0x131f, 0x2012, 0xffff, 0, 403158124Smarcel "SIIG Cyber I/O PCI 16C850 (20x family)", 404158124Smarcel DEFAULT_RCLK, 405158124Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 40690731Sjhay }, 40790731Sjhay 408158124Smarcel { 0x131f, 0x2021, 0xffff, 0, 409158124Smarcel "SIIG Cyber Parallel Dual PCI (20x family)", 410158124Smarcel 0, 411158124Smarcel PUC_PORT_2P, 0x10, 8, 0, 41290731Sjhay }, 41390731Sjhay 414158124Smarcel { 0x131f, 0x2030, 0xffff, 0, 415158124Smarcel "SIIG Cyber Serial Dual PCI 16C550 (20x family)", 416158124Smarcel DEFAULT_RCLK, 417158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 41890731Sjhay }, 41990731Sjhay 420158124Smarcel { 0x131f, 0x2031, 0xffff, 0, 421158124Smarcel "SIIG Cyber Serial Dual PCI 16C650 (20x family)", 422158124Smarcel DEFAULT_RCLK, 423158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 424158124Smarcel }, 42590731Sjhay 426158124Smarcel { 0x131f, 0x2032, 0xffff, 0, 427158124Smarcel "SIIG Cyber Serial Dual PCI 16C850 (20x family)", 428158124Smarcel DEFAULT_RCLK, 429158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 43090731Sjhay }, 43190731Sjhay 432158124Smarcel { 0x131f, 0x2040, 0xffff, 0, 433158124Smarcel "SIIG Cyber 2P1S PCI 16C550 (20x family)", 434158124Smarcel DEFAULT_RCLK, 435158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 436158124Smarcel .config_function = puc_config_siig 43790731Sjhay }, 43890731Sjhay 439158124Smarcel { 0x131f, 0x2041, 0xffff, 0, 440158124Smarcel "SIIG Cyber 2P1S PCI 16C650 (20x family)", 441158124Smarcel DEFAULT_RCLK, 442158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 443158124Smarcel .config_function = puc_config_siig 44490731Sjhay }, 44590731Sjhay 446158124Smarcel { 0x131f, 0x2042, 0xffff, 0, 447158124Smarcel "SIIG Cyber 2P1S PCI 16C850 (20x family)", 448158124Smarcel DEFAULT_RCLK, 449158124Smarcel PUC_PORT_1S2P, 0x10, -1, 0, 450158124Smarcel .config_function = puc_config_siig 45190731Sjhay }, 45290731Sjhay 453158124Smarcel { 0x131f, 0x2050, 0xffff, 0, 454158124Smarcel "SIIG Cyber 4S PCI 16C550 (20x family)", 455158124Smarcel DEFAULT_RCLK, 456158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 45790731Sjhay }, 45890731Sjhay 459158124Smarcel { 0x131f, 0x2051, 0xffff, 0, 460158124Smarcel "SIIG Cyber 4S PCI 16C650 (20x family)", 461158124Smarcel DEFAULT_RCLK, 462158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 46390731Sjhay }, 46490731Sjhay 465158124Smarcel { 0x131f, 0x2052, 0xffff, 0, 466158124Smarcel "SIIG Cyber 4S PCI 16C850 (20x family)", 467158124Smarcel DEFAULT_RCLK, 468158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 46990731Sjhay }, 47090731Sjhay 471158124Smarcel { 0x131f, 0x2060, 0xffff, 0, 472158124Smarcel "SIIG Cyber 2S1P PCI 16C550 (20x family)", 473158124Smarcel DEFAULT_RCLK, 474158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 47590731Sjhay }, 47690731Sjhay 477158124Smarcel { 0x131f, 0x2061, 0xffff, 0, 478158124Smarcel "SIIG Cyber 2S1P PCI 16C650 (20x family)", 479158124Smarcel DEFAULT_RCLK, 480158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 48190731Sjhay }, 48290731Sjhay 483158124Smarcel { 0x131f, 0x2062, 0xffff, 0, 484158124Smarcel "SIIG Cyber 2S1P PCI 16C850 (20x family)", 485158124Smarcel DEFAULT_RCLK, 486158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 48790731Sjhay }, 48890731Sjhay 489158124Smarcel { 0x131f, 0x2081, 0xffff, 0, 490158124Smarcel "SIIG PS8000 8S PCI 16C650 (20x family)", 491158124Smarcel DEFAULT_RCLK, 492158124Smarcel PUC_PORT_8S, 0x10, -1, -1, 493158124Smarcel .config_function = puc_config_siig 49490731Sjhay }, 49590731Sjhay 496158124Smarcel { 0x135c, 0x0010, 0xffff, 0, 497158124Smarcel "Quatech QSC-100", 498158124Smarcel -3, /* max 8x clock rate */ 499158124Smarcel PUC_PORT_4S, 0x14, 0, 8, 500158124Smarcel .config_function = puc_config_quatech 50190731Sjhay }, 50290731Sjhay 503158124Smarcel { 0x135c, 0x0020, 0xffff, 0, 504158124Smarcel "Quatech DSC-100", 505158124Smarcel -1, /* max 2x clock rate */ 506158124Smarcel PUC_PORT_2S, 0x14, 0, 8, 507158124Smarcel .config_function = puc_config_quatech 50890731Sjhay }, 50990731Sjhay 510158124Smarcel { 0x135c, 0x0030, 0xffff, 0, 511158124Smarcel "Quatech DSC-200/300", 512158124Smarcel -1, /* max 2x clock rate */ 513158124Smarcel PUC_PORT_2S, 0x14, 0, 8, 514158124Smarcel .config_function = puc_config_quatech 51590731Sjhay }, 51690731Sjhay 517158124Smarcel { 0x135c, 0x0040, 0xffff, 0, 518158124Smarcel "Quatech QSC-200/300", 519158124Smarcel -3, /* max 8x clock rate */ 520158124Smarcel PUC_PORT_4S, 0x14, 0, 8, 521158124Smarcel .config_function = puc_config_quatech 52290731Sjhay }, 52390731Sjhay 524158124Smarcel { 0x135c, 0x0050, 0xffff, 0, 525158124Smarcel "Quatech ESC-100D", 526158124Smarcel -3, /* max 8x clock rate */ 527158124Smarcel PUC_PORT_8S, 0x14, 0, 8, 528158124Smarcel .config_function = puc_config_quatech 52990731Sjhay }, 53090731Sjhay 531158124Smarcel { 0x135c, 0x0060, 0xffff, 0, 532158124Smarcel "Quatech ESC-100M", 533158124Smarcel -3, /* max 8x clock rate */ 534158124Smarcel PUC_PORT_8S, 0x14, 0, 8, 535158124Smarcel .config_function = puc_config_quatech 53690731Sjhay }, 53790731Sjhay 538158124Smarcel { 0x135c, 0x0170, 0xffff, 0, 539158124Smarcel "Quatech QSCLP-100", 540158124Smarcel -1, /* max 2x clock rate */ 541158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 542158124Smarcel .config_function = puc_config_quatech 54390731Sjhay }, 54490731Sjhay 545158124Smarcel { 0x135c, 0x0180, 0xffff, 0, 546158124Smarcel "Quatech DSCLP-100", 547158124Smarcel -1, /* max 3x clock rate */ 548158124Smarcel PUC_PORT_2S, 0x18, 0, 8, 549158124Smarcel .config_function = puc_config_quatech 55090731Sjhay }, 55190731Sjhay 552158124Smarcel { 0x135c, 0x01b0, 0xffff, 0, 553158124Smarcel "Quatech DSCLP-200/300", 554158124Smarcel -1, /* max 2x clock rate */ 555158124Smarcel PUC_PORT_2S, 0x18, 0, 8, 556158124Smarcel .config_function = puc_config_quatech 55790731Sjhay }, 55890731Sjhay 559158124Smarcel { 0x135c, 0x01e0, 0xffff, 0, 560158124Smarcel "Quatech ESCLP-100", 561158124Smarcel -3, /* max 8x clock rate */ 562158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 563158124Smarcel .config_function = puc_config_quatech 564102259Sjhay }, 565102259Sjhay 566237350Sfjoe { 0x1393, 0x1024, 0xffff, 0, 567237350Sfjoe "Moxa Technologies, Smartio CP-102E/PCIe", 568237350Sfjoe DEFAULT_RCLK * 8, 569238933Sfjoe PUC_PORT_2S, 0x14, 0, -1, 570251713Smarius .config_function = puc_config_moxa 571237350Sfjoe }, 572237350Sfjoe 573237350Sfjoe { 0x1393, 0x1025, 0xffff, 0, 574237350Sfjoe "Moxa Technologies, Smartio CP-102EL/PCIe", 575237350Sfjoe DEFAULT_RCLK * 8, 576238933Sfjoe PUC_PORT_2S, 0x14, 0, -1, 577251713Smarius .config_function = puc_config_moxa 578237350Sfjoe }, 579237350Sfjoe 580158124Smarcel { 0x1393, 0x1040, 0xffff, 0, 581158124Smarcel "Moxa Technologies, Smartio C104H/PCI", 582158124Smarcel DEFAULT_RCLK * 8, 583158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 58490731Sjhay }, 58590731Sjhay 586158124Smarcel { 0x1393, 0x1041, 0xffff, 0, 587158124Smarcel "Moxa Technologies, Smartio CP-104UL/PCI", 588158124Smarcel DEFAULT_RCLK * 8, 589158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 59090731Sjhay }, 591158124Smarcel 592227457Seadler { 0x1393, 0x1042, 0xffff, 0, 593227457Seadler "Moxa Technologies, Smartio CP-104JU/PCI", 594227457Seadler DEFAULT_RCLK * 8, 595227457Seadler PUC_PORT_4S, 0x18, 0, 8, 596227457Seadler }, 597227457Seadler 598175245Smaxim { 0x1393, 0x1043, 0xffff, 0, 599175245Smaxim "Moxa Technologies, Smartio CP-104EL/PCIe", 600175245Smaxim DEFAULT_RCLK * 8, 601175245Smaxim PUC_PORT_4S, 0x18, 0, 8, 602175245Smaxim }, 603175245Smaxim 604227457Seadler { 0x1393, 0x1045, 0xffff, 0, 605227457Seadler "Moxa Technologies, Smartio CP-104EL-A/PCIe", 606227457Seadler DEFAULT_RCLK * 8, 607227457Seadler PUC_PORT_4S, 0x14, 0, -1, 608251713Smarius .config_function = puc_config_moxa 609227457Seadler }, 610227457Seadler 611224898Sjhb { 0x1393, 0x1120, 0xffff, 0, 612224898Sjhb "Moxa Technologies, CP-112UL", 613224898Sjhb DEFAULT_RCLK * 8, 614224898Sjhb PUC_PORT_2S, 0x18, 0, 8, 615224898Sjhb }, 616224898Sjhb 617158124Smarcel { 0x1393, 0x1141, 0xffff, 0, 618158124Smarcel "Moxa Technologies, Industio CP-114", 619158124Smarcel DEFAULT_RCLK * 8, 620158124Smarcel PUC_PORT_4S, 0x18, 0, 8, 62190731Sjhay }, 622158124Smarcel 623237350Sfjoe { 0x1393, 0x1144, 0xffff, 0, 624237350Sfjoe "Moxa Technologies, Smartio CP-114EL/PCIe", 625237350Sfjoe DEFAULT_RCLK * 8, 626237350Sfjoe PUC_PORT_4S, 0x14, 0, -1, 627251713Smarius .config_function = puc_config_moxa 628237350Sfjoe }, 629237350Sfjoe 630237350Sfjoe { 0x1393, 0x1182, 0xffff, 0, 631237350Sfjoe "Moxa Technologies, Smartio CP-118EL-A/PCIe", 632237350Sfjoe DEFAULT_RCLK * 8, 633238933Sfjoe PUC_PORT_8S, 0x14, 0, -1, 634251713Smarius .config_function = puc_config_moxa 635237350Sfjoe }, 636237350Sfjoe 637158124Smarcel { 0x1393, 0x1680, 0xffff, 0, 638158124Smarcel "Moxa Technologies, C168H/PCI", 639158124Smarcel DEFAULT_RCLK * 8, 640158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 64190731Sjhay }, 64290731Sjhay 643158124Smarcel { 0x1393, 0x1681, 0xffff, 0, 644158124Smarcel "Moxa Technologies, C168U/PCI", 645158124Smarcel DEFAULT_RCLK * 8, 646158124Smarcel PUC_PORT_8S, 0x18, 0, 8, 647118357Sbde }, 648118357Sbde 649187766Sstas { 0x1393, 0x1682, 0xffff, 0, 650187766Sstas "Moxa Technologies, CP-168EL/PCIe", 651187766Sstas DEFAULT_RCLK * 8, 652187766Sstas PUC_PORT_8S, 0x18, 0, 8, 653187766Sstas }, 654187766Sstas 655237350Sfjoe { 0x1393, 0x1683, 0xffff, 0, 656237350Sfjoe "Moxa Technologies, Smartio CP-168EL-A/PCIe", 657237350Sfjoe DEFAULT_RCLK * 8, 658238933Sfjoe PUC_PORT_8S, 0x14, 0, -1, 659251713Smarius .config_function = puc_config_moxa 660237350Sfjoe }, 661237350Sfjoe 662222660Sjhb { 0x13a8, 0x0152, 0xffff, 0, 663222660Sjhb "Exar XR17C/D152", 664222660Sjhb DEFAULT_RCLK * 8, 665222660Sjhb PUC_PORT_2S, 0x10, 0, -1, 666222660Sjhb .config_function = puc_config_exar 667222660Sjhb }, 668222660Sjhb 669222660Sjhb { 0x13a8, 0x0154, 0xffff, 0, 670222660Sjhb "Exar XR17C154", 671222660Sjhb DEFAULT_RCLK * 8, 672222660Sjhb PUC_PORT_4S, 0x10, 0, -1, 673222660Sjhb .config_function = puc_config_exar 674222660Sjhb }, 675222660Sjhb 676158124Smarcel { 0x13a8, 0x0158, 0xffff, 0, 677222660Sjhb "Exar XR17C158", 678158124Smarcel DEFAULT_RCLK * 8, 679158124Smarcel PUC_PORT_8S, 0x10, 0, -1, 680222660Sjhb .config_function = puc_config_exar 68190731Sjhay }, 68290731Sjhay 683216513Semaste { 0x13a8, 0x0258, 0xffff, 0, 684216513Semaste "Exar XR17V258IV", 685216513Semaste DEFAULT_RCLK * 8, 686216513Semaste PUC_PORT_8S, 0x10, 0, -1, 687248472Srstone .config_function = puc_config_exar 688216513Semaste }, 689216513Semaste 690248340Srstone /* The XR17V358 uses the 125MHz PCIe clock as its reference clock. */ 691248340Srstone { 0x13a8, 0x0358, 0xffff, 0, 692248340Srstone "Exar XR17V358", 693248340Srstone 125000000, 694248340Srstone PUC_PORT_8S, 0x10, 0, -1, 695248340Srstone .config_function = puc_config_exar_pcie 696248340Srstone }, 697248340Srstone 698318151Smarius /* 699318151Smarius * The Advantech PCI-1602 Rev. A use the first two ports of an Oxford 700318151Smarius * Semiconductor OXuPCI954. Note these boards have a hardware bug in 701318151Smarius * that they drive the RS-422/485 transmitters after power-on until a 702318151Smarius * driver initalizes the UARTs. 703318151Smarius */ 704242814Seadler { 0x13fe, 0x1600, 0x1602, 0x0002, 705318151Smarius "Advantech PCI-1602 Rev. A", 706242814Seadler DEFAULT_RCLK * 8, 707242814Seadler PUC_PORT_2S, 0x10, 0, 8, 708318151Smarius .config_function = puc_config_advantech 709242814Seadler }, 710242814Seadler 711318151Smarius /* Advantech PCI-1602 Rev. B1/PCI-1603 are also based on OXuPCI952. */ 712318151Smarius { 0x13fe, 0xa102, 0x13fe, 0xa102, 713318151Smarius "Advantech 2-port PCI (PCI-1602 Rev. B1/PCI-1603)", 714318151Smarius DEFAULT_RCLK * 8, 715318151Smarius PUC_PORT_2S, 0x10, 4, 0, 716318151Smarius .config_function = puc_config_advantech 717318151Smarius }, 718318151Smarius 719158124Smarcel { 0x1407, 0x0100, 0xffff, 0, 720158124Smarcel "Lava Computers Dual Serial", 721158124Smarcel DEFAULT_RCLK, 722158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 72390731Sjhay }, 72490731Sjhay 725158124Smarcel { 0x1407, 0x0101, 0xffff, 0, 726158124Smarcel "Lava Computers Quatro A", 727158124Smarcel DEFAULT_RCLK, 728158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 72990731Sjhay }, 73090731Sjhay 731158124Smarcel { 0x1407, 0x0102, 0xffff, 0, 732158124Smarcel "Lava Computers Quatro B", 733158124Smarcel DEFAULT_RCLK, 734158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 73590731Sjhay }, 73690731Sjhay 737158124Smarcel { 0x1407, 0x0120, 0xffff, 0, 738158124Smarcel "Lava Computers Quattro-PCI A", 739158124Smarcel DEFAULT_RCLK, 740158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 74195394Sjhay }, 74295394Sjhay 743158124Smarcel { 0x1407, 0x0121, 0xffff, 0, 744158124Smarcel "Lava Computers Quattro-PCI B", 745158124Smarcel DEFAULT_RCLK, 746158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 74790731Sjhay }, 74890731Sjhay 749158124Smarcel { 0x1407, 0x0180, 0xffff, 0, 750158124Smarcel "Lava Computers Octo A", 751158124Smarcel DEFAULT_RCLK, 752158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 75390731Sjhay }, 75490731Sjhay 755158124Smarcel { 0x1407, 0x0181, 0xffff, 0, 756158124Smarcel "Lava Computers Octo B", 757158124Smarcel DEFAULT_RCLK, 758158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 75990731Sjhay }, 76090731Sjhay 761188511Skevlo { 0x1409, 0x7268, 0xffff, 0, 762188511Skevlo "Sunix SUN1888", 763188511Skevlo 0, 764188511Skevlo PUC_PORT_2P, 0x10, 0, 8, 765188511Skevlo }, 766188511Skevlo 767158124Smarcel { 0x1409, 0x7168, 0xffff, 0, 768158124Smarcel NULL, 769158124Smarcel DEFAULT_RCLK * 8, 770158124Smarcel PUC_PORT_NONSTANDARD, 0x10, -1, -1, 771158124Smarcel .config_function = puc_config_timedia 77290731Sjhay }, 77390731Sjhay 77490731Sjhay /* 77590731Sjhay * Boards with an Oxford Semiconductor chip. 77690731Sjhay * 77790731Sjhay * Oxford Semiconductor provides documentation for their chip at: 778221182Sjhb * <URL:http://www.plxtech.com/products/uart/> 77990731Sjhay * 78090731Sjhay * As sold by Kouwell <URL:http://www.kouwell.com/>. 78190731Sjhay * I/O Flex PCI I/O Card Model-223 with 4 serial and 1 parallel ports. 78290731Sjhay */ 783226404Seadler { 784251713Smarius 0x1415, 0x9501, 0x10fc, 0xc070, 785251713Smarius "I-O DATA RSA-PCI2/R", 786251713Smarius DEFAULT_RCLK * 8, 787251713Smarius PUC_PORT_2S, 0x10, 0, 8, 788226404Seadler }, 78990731Sjhay 790184258Sdes { 0x1415, 0x9501, 0x131f, 0x2050, 791184258Sdes "SIIG Cyber 4 PCI 16550", 792184258Sdes DEFAULT_RCLK * 10, 793184258Sdes PUC_PORT_4S, 0x10, 0, 8, 794184258Sdes }, 795184258Sdes 796162007Smarcel { 0x1415, 0x9501, 0x131f, 0x2051, 797162007Smarcel "SIIG Cyber 4S PCI 16C650 (20x family)", 798162007Smarcel DEFAULT_RCLK * 10, 799162007Smarcel PUC_PORT_4S, 0x10, 0, 8, 800162007Smarcel }, 801162007Smarcel 802221731Sjhb { 0x1415, 0x9501, 0x131f, 0x2052, 803221731Sjhb "SIIG Quartet Serial 850", 804221731Sjhb DEFAULT_RCLK * 10, 805221731Sjhb PUC_PORT_4S, 0x10, 0, 8, 806221731Sjhb }, 807221731Sjhb 808221326Sjhb { 0x1415, 0x9501, 0x14db, 0x2150, 809221326Sjhb "Kuroutoshikou SERIAL4P-LPPCI2", 810221326Sjhb DEFAULT_RCLK * 10, 811221326Sjhb PUC_PORT_4S, 0x10, 0, 8, 812221326Sjhb }, 813221326Sjhb 814158124Smarcel { 0x1415, 0x9501, 0xffff, 0, 815183817Sdes "Oxford Semiconductor OX16PCI954 UARTs", 816251715Smarius 0, 817158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 818251715Smarius .config_function = puc_config_oxford_pci954 819145391Simp }, 820145391Simp 821222093Sjhb { 0x1415, 0x950a, 0x131f, 0x2030, 822222093Sjhb "SIIG Cyber 2S PCIe", 823222093Sjhb DEFAULT_RCLK * 10, 824222093Sjhb PUC_PORT_2S, 0x10, 0, 8, 825222093Sjhb }, 826222093Sjhb 827239076Seadler { 0x1415, 0x950a, 0x131f, 0x2032, 828239076Seadler "SIIG Cyber Serial Dual PCI 16C850", 829239076Seadler DEFAULT_RCLK * 10, 830239076Seadler PUC_PORT_4S, 0x10, 0, 8, 831239076Seadler }, 832239076Seadler 833294961Smarius { 0x1415, 0x950a, 0x131f, 0x2061, 834294961Smarius "SIIG Cyber 2SP1 PCIe", 835294961Smarius DEFAULT_RCLK * 10, 836294961Smarius PUC_PORT_2S, 0x10, 0, 8, 837294961Smarius }, 838294961Smarius 839158124Smarcel { 0x1415, 0x950a, 0xffff, 0, 840183817Sdes "Oxford Semiconductor OX16PCI954 UARTs", 841183817Sdes DEFAULT_RCLK, 842158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 84390731Sjhay }, 84490731Sjhay 845158124Smarcel { 0x1415, 0x9511, 0xffff, 0, 846158124Smarcel "Oxford Semiconductor OX9160/OX16PCI954 UARTs (function 1)", 847158124Smarcel DEFAULT_RCLK, 848158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 849121488Sambrisko }, 850121488Sambrisko 851158124Smarcel { 0x1415, 0x9521, 0xffff, 0, 852158124Smarcel "Oxford Semiconductor OX16PCI952 UARTs", 853158124Smarcel DEFAULT_RCLK, 854158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 85590731Sjhay }, 85690731Sjhay 857186520Srik { 0x1415, 0x9538, 0xffff, 0, 858186520Srik "Oxford Semiconductor OX16PCI958 UARTs", 859247571Smarius DEFAULT_RCLK, 860186520Srik PUC_PORT_8S, 0x18, 0, 8, 861186520Srik }, 862186520Srik 863208350Sjhb /* 864208350Sjhb * Perle boards use Oxford Semiconductor chips, but they store the 865208350Sjhb * Oxford Semiconductor device ID as a subvendor device ID and use 866208350Sjhb * their own device IDs. 867208350Sjhb */ 868208350Sjhb 869208350Sjhb { 0x155f, 0x0331, 0xffff, 0, 870239048Seadler "Perle Ultraport4 Express", 871239048Seadler DEFAULT_RCLK * 8, 872239048Seadler PUC_PORT_4S, 0x10, 0, 8, 873239048Seadler }, 874239048Seadler 875239048Seadler { 0x155f, 0xB012, 0xffff, 0, 876239048Seadler "Perle Speed2 LE", 877239048Seadler DEFAULT_RCLK * 8, 878239048Seadler PUC_PORT_2S, 0x10, 0, 8, 879239048Seadler }, 880239048Seadler 881239048Seadler { 0x155f, 0xB022, 0xffff, 0, 882239048Seadler "Perle Speed2 LE", 883239048Seadler DEFAULT_RCLK * 8, 884239048Seadler PUC_PORT_2S, 0x10, 0, 8, 885239048Seadler }, 886239048Seadler 887239048Seadler { 0x155f, 0xB004, 0xffff, 0, 888208350Sjhb "Perle Speed4 LE", 889208350Sjhb DEFAULT_RCLK * 8, 890208350Sjhb PUC_PORT_4S, 0x10, 0, 8, 891208350Sjhb }, 892208350Sjhb 893239048Seadler { 0x155f, 0xB008, 0xffff, 0, 894239048Seadler "Perle Speed8 LE", 895239048Seadler DEFAULT_RCLK * 8, 896239048Seadler PUC_PORT_8S, 0x10, 0, 8, 897239048Seadler }, 898239048Seadler 899239048Seadler 900221182Sjhb /* 901221182Sjhb * Oxford Semiconductor PCI Express Expresso family 902221182Sjhb * 903221182Sjhb * Found in many 'native' PCI Express serial boards such as: 904221182Sjhb * 905221182Sjhb * eMegatech MP954ER4 (4 port) and MP958ER8 (8 port) 906221182Sjhb * <URL:http://www.emegatech.com.tw/pdrs232pcie.html> 907221182Sjhb * 908221182Sjhb * Lindy 51189 (4 port) 909221182Sjhb * <URL:http://www.lindy.com> <URL:http://tinyurl.com/lindy-51189> 910251713Smarius * 911221182Sjhb * StarTech.com PEX4S952 (4 port) and PEX8S952 (8 port) 912221182Sjhb * <URL:http://www.startech.com> 913221182Sjhb */ 914221182Sjhb 915273923Srpaulo { 0x1415, 0xc11b, 0xffff, 0, 916294961Smarius "Oxford Semiconductor OXPCIe952 1S1P", 917294961Smarius DEFAULT_RCLK * 0x22, 918294961Smarius PUC_PORT_NONSTANDARD, 0x10, 0, -1, 919273923Srpaulo .config_function = puc_config_oxford_pcie 920273923Srpaulo }, 921273923Srpaulo 922225878Sae { 0x1415, 0xc138, 0xffff, 0, 923225878Sae "Oxford Semiconductor OXPCIe952 UARTs", 924225878Sae DEFAULT_RCLK * 0x22, 925225878Sae PUC_PORT_NONSTANDARD, 0x10, 0, -1, 926225878Sae .config_function = puc_config_oxford_pcie 927225878Sae }, 928225878Sae 929221182Sjhb { 0x1415, 0xc158, 0xffff, 0, 930221182Sjhb "Oxford Semiconductor OXPCIe952 UARTs", 931221182Sjhb DEFAULT_RCLK * 0x22, 932221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 933221182Sjhb .config_function = puc_config_oxford_pcie 934221182Sjhb }, 935221182Sjhb 936221182Sjhb { 0x1415, 0xc15d, 0xffff, 0, 937221182Sjhb "Oxford Semiconductor OXPCIe952 UARTs (function 1)", 938221182Sjhb DEFAULT_RCLK * 0x22, 939221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 940221182Sjhb .config_function = puc_config_oxford_pcie 941221182Sjhb }, 942221182Sjhb 943221182Sjhb { 0x1415, 0xc208, 0xffff, 0, 944221182Sjhb "Oxford Semiconductor OXPCIe954 UARTs", 945221182Sjhb DEFAULT_RCLK * 0x22, 946221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 947221182Sjhb .config_function = puc_config_oxford_pcie 948221182Sjhb }, 949221182Sjhb 950221182Sjhb { 0x1415, 0xc20d, 0xffff, 0, 951221182Sjhb "Oxford Semiconductor OXPCIe954 UARTs (function 1)", 952221182Sjhb DEFAULT_RCLK * 0x22, 953221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 954221182Sjhb .config_function = puc_config_oxford_pcie 955221182Sjhb }, 956221182Sjhb 957221182Sjhb { 0x1415, 0xc308, 0xffff, 0, 958221182Sjhb "Oxford Semiconductor OXPCIe958 UARTs", 959221182Sjhb DEFAULT_RCLK * 0x22, 960221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 961221182Sjhb .config_function = puc_config_oxford_pcie 962221182Sjhb }, 963221182Sjhb 964221182Sjhb { 0x1415, 0xc30d, 0xffff, 0, 965221182Sjhb "Oxford Semiconductor OXPCIe958 UARTs (function 1)", 966221182Sjhb DEFAULT_RCLK * 0x22, 967221182Sjhb PUC_PORT_NONSTANDARD, 0x10, 0, -1, 968221182Sjhb .config_function = puc_config_oxford_pcie 969221182Sjhb }, 970221182Sjhb 971181974Sthompsa { 0x14d2, 0x8010, 0xffff, 0, 972181974Sthompsa "VScom PCI-100L", 973181974Sthompsa DEFAULT_RCLK * 8, 974181974Sthompsa PUC_PORT_1S, 0x14, 0, 0, 975181974Sthompsa }, 976181974Sthompsa 977158124Smarcel { 0x14d2, 0x8020, 0xffff, 0, 978158124Smarcel "VScom PCI-200L", 979158124Smarcel DEFAULT_RCLK * 8, 980158124Smarcel PUC_PORT_2S, 0x14, 4, 0, 981128354Scperciva }, 982128354Scperciva 983158124Smarcel { 0x14d2, 0x8028, 0xffff, 0, 984158124Smarcel "VScom 200Li", 985158124Smarcel DEFAULT_RCLK, 986158124Smarcel PUC_PORT_2S, 0x20, 0, 8, 987145391Simp }, 988145391Simp 989158124Smarcel /* 990158124Smarcel * VScom (Titan?) PCI-800L. More modern variant of the 991158124Smarcel * PCI-800. Uses 6 discrete 16550 UARTs, plus another 992158124Smarcel * two of them obviously implemented as macro cells in 993158124Smarcel * the ASIC. This causes the weird port access pattern 994158124Smarcel * below, where two of the IO port ranges each access 995158124Smarcel * one of the ASIC UARTs, and a block of IO addresses 996158124Smarcel * access the external UARTs. 997158124Smarcel */ 998158124Smarcel { 0x14d2, 0x8080, 0xffff, 0, 999158124Smarcel "Titan VScom PCI-800L", 1000158124Smarcel DEFAULT_RCLK * 8, 1001158124Smarcel PUC_PORT_8S, 0x14, -1, -1, 1002158124Smarcel .config_function = puc_config_titan 100390731Sjhay }, 100490731Sjhay 100590731Sjhay /* 1006158124Smarcel * VScom PCI-800H. Uses 8 16950 UART, behind a PCI chips that offers 1007158124Smarcel * 4 com port on PCI device 0 and 4 on PCI device 1. PCI device 0 has 1008158124Smarcel * device ID 3 and PCI device 1 device ID 4. 100990731Sjhay */ 1010158124Smarcel { 0x14d2, 0xa003, 0xffff, 0, 1011158124Smarcel "Titan PCI-800H", 1012158124Smarcel DEFAULT_RCLK * 8, 1013158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 101490731Sjhay }, 1015247571Smarius 1016158124Smarcel { 0x14d2, 0xa004, 0xffff, 0, 1017158124Smarcel "Titan PCI-800H", 1018158124Smarcel DEFAULT_RCLK * 8, 1019158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 102090731Sjhay }, 102190731Sjhay 1022158124Smarcel { 0x14d2, 0xa005, 0xffff, 0, 1023158124Smarcel "Titan PCI-200H", 1024158124Smarcel DEFAULT_RCLK * 8, 1025158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 1026113006Sphk }, 1027113006Sphk 1028158124Smarcel { 0x14d2, 0xe020, 0xffff, 0, 1029158124Smarcel "Titan VScom PCI-200HV2", 1030158124Smarcel DEFAULT_RCLK * 8, 1031158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 1032123360Sobrien }, 1033123360Sobrien 1034227535Seadler { 0x14d2, 0xa007, 0xffff, 0, 1035227535Seadler "Titan VScom PCIex-800H", 1036227535Seadler DEFAULT_RCLK * 8, 1037227535Seadler PUC_PORT_4S, 0x10, 0, 8, 1038227535Seadler }, 1039227535Seadler 1040227535Seadler { 0x14d2, 0xa008, 0xffff, 0, 1041227535Seadler "Titan VScom PCIex-800H", 1042227535Seadler DEFAULT_RCLK * 8, 1043227535Seadler PUC_PORT_4S, 0x10, 0, 8, 1044227535Seadler }, 1045227535Seadler 1046158124Smarcel { 0x14db, 0x2130, 0xffff, 0, 1047158124Smarcel "Avlab Technology, PCI IO 2S", 1048158124Smarcel DEFAULT_RCLK, 1049158124Smarcel PUC_PORT_2S, 0x10, 4, 0, 105090731Sjhay }, 105190731Sjhay 1052158124Smarcel { 0x14db, 0x2150, 0xffff, 0, 1053158124Smarcel "Avlab Low Profile PCI 4 Serial", 1054158124Smarcel DEFAULT_RCLK, 1055158124Smarcel PUC_PORT_4S, 0x10, 4, 0, 105690731Sjhay }, 105790731Sjhay 1058181973Sthompsa { 0x14db, 0x2152, 0xffff, 0, 1059181973Sthompsa "Avlab Low Profile PCI 4 Serial", 1060181973Sthompsa DEFAULT_RCLK, 1061181973Sthompsa PUC_PORT_4S, 0x10, 4, 0, 1062181973Sthompsa }, 1063181973Sthompsa 1064158124Smarcel { 0x1592, 0x0781, 0xffff, 0, 1065158124Smarcel "Syba Tech Ltd. PCI-4S2P-550-ECP", 1066158124Smarcel DEFAULT_RCLK, 1067158124Smarcel PUC_PORT_4S1P, 0x10, 0, -1, 1068158124Smarcel .config_function = puc_config_syba 1069118902Spb }, 1070118902Spb 1071264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0002, 1072264761Smarius "Sunix SER5xxxx 2-port serial", 1073236736Sjhay DEFAULT_RCLK * 8, 1074236736Sjhay PUC_PORT_2S, 0x10, 0, 8, 1075236736Sjhay }, 1076236736Sjhay 1077264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0004, 1078264761Smarius "Sunix SER5xxxx 4-port serial", 1079264761Smarius DEFAULT_RCLK * 8, 1080264761Smarius PUC_PORT_4S, 0x10, 0, 8, 1081264761Smarius }, 1082264761Smarius 1083264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0008, 1084264761Smarius "Sunix SER5xxxx 8-port serial", 1085264761Smarius DEFAULT_RCLK * 8, 1086264761Smarius PUC_PORT_8S, -1, -1, -1, 1087264761Smarius .config_function = puc_config_sunix 1088264761Smarius }, 1089264761Smarius 1090264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0101, 1091264761Smarius "Sunix MIO5xxxx 1-port serial and 1284 Printer port", 1092264761Smarius DEFAULT_RCLK * 8, 1093264761Smarius PUC_PORT_1S1P, -1, -1, -1, 1094264761Smarius .config_function = puc_config_sunix 1095264761Smarius }, 1096264761Smarius 1097264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0102, 1098264761Smarius "Sunix MIO5xxxx 2-port serial and 1284 Printer port", 1099264761Smarius DEFAULT_RCLK * 8, 1100264761Smarius PUC_PORT_2S1P, -1, -1, -1, 1101264761Smarius .config_function = puc_config_sunix 1102264761Smarius }, 1103264761Smarius 1104264761Smarius { 0x1fd4, 0x1999, 0x1fd4, 0x0104, 1105264761Smarius "Sunix MIO5xxxx 4-port serial and 1284 Printer port", 1106264761Smarius DEFAULT_RCLK * 8, 1107264761Smarius PUC_PORT_4S1P, -1, -1, -1, 1108264761Smarius .config_function = puc_config_sunix 1109264761Smarius }, 1110264761Smarius 1111276878Sloos { 0x5372, 0x6872, 0xffff, 0, 1112276878Sloos "Feasso PCI FPP-02 2S1P", 1113276878Sloos DEFAULT_RCLK, 1114276878Sloos PUC_PORT_2S1P, 0x10, 4, 0, 1115276878Sloos }, 1116276878Sloos 1117251713Smarius { 0x5372, 0x6873, 0xffff, 0, 1118251713Smarius "Sun 1040 PCI Quad Serial", 1119251713Smarius DEFAULT_RCLK, 1120251713Smarius PUC_PORT_4S, 0x10, 4, 0, 1121236282Seadler }, 1122236282Seadler 1123158124Smarcel { 0x6666, 0x0001, 0xffff, 0, 1124158124Smarcel "Decision Computer Inc, PCCOM 4-port serial", 1125158124Smarcel DEFAULT_RCLK, 1126158124Smarcel PUC_PORT_4S, 0x1c, 0, 8, 112791757Sjhay }, 112891757Sjhay 1129181975Sthompsa { 0x6666, 0x0002, 0xffff, 0, 1130181975Sthompsa "Decision Computer Inc, PCCOM 8-port serial", 1131181975Sthompsa DEFAULT_RCLK, 1132181975Sthompsa PUC_PORT_8S, 0x1c, 0, 8, 1133181975Sthompsa }, 1134181975Sthompsa 1135158124Smarcel { 0x6666, 0x0004, 0xffff, 0, 1136158124Smarcel "PCCOM dual port RS232/422/485", 1137158124Smarcel DEFAULT_RCLK, 1138158124Smarcel PUC_PORT_2S, 0x1c, 0, 8, 1139102261Sjhay }, 1140102261Sjhay 1141158124Smarcel { 0x9710, 0x9815, 0xffff, 0, 1142251713Smarius "NetMos NM9815 Dual 1284 Printer port", 1143158124Smarcel 0, 1144158124Smarcel PUC_PORT_2P, 0x10, 8, 0, 1145251713Smarius }, 114693330Smurray 1147189407Sjhb /* 1148264761Smarius * This is more specific than the generic NM9835 entry, and is placed 1149264761Smarius * here to _prevent_ puc(4) from claiming this single port card. 1150189407Sjhb * 1151189407Sjhb * uart(4) will claim this device. 1152189407Sjhb */ 1153189407Sjhb { 0x9710, 0x9835, 0x1000, 1, 1154189407Sjhb "NetMos NM9835 based 1-port serial", 1155189407Sjhb DEFAULT_RCLK, 1156189407Sjhb PUC_PORT_1S, 0x10, 4, 0, 1157189407Sjhb }, 1158189407Sjhb 1159194522Snp { 0x9710, 0x9835, 0x1000, 2, 1160194522Snp "NetMos NM9835 based 2-port serial", 1161194522Snp DEFAULT_RCLK, 1162194522Snp PUC_PORT_2S, 0x10, 4, 0, 1163194522Snp }, 1164194522Snp 1165158124Smarcel { 0x9710, 0x9835, 0xffff, 0, 1166158124Smarcel "NetMos NM9835 Dual UART and 1284 Printer port", 1167158124Smarcel DEFAULT_RCLK, 1168158124Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 116993533Sjhay }, 117093533Sjhay 1171158124Smarcel { 0x9710, 0x9845, 0x1000, 0x0006, 1172158124Smarcel "NetMos NM9845 6 Port UART", 1173158124Smarcel DEFAULT_RCLK, 1174158124Smarcel PUC_PORT_6S, 0x10, 4, 0, 1175128602Ssobomax }, 1176128602Ssobomax 1177158124Smarcel { 0x9710, 0x9845, 0xffff, 0, 1178158124Smarcel "NetMos NM9845 Quad UART and 1284 Printer port", 1179158124Smarcel DEFAULT_RCLK, 1180158124Smarcel PUC_PORT_4S1P, 0x10, 4, 0, 1181128602Ssobomax }, 1182128602Ssobomax 1183200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3002, 1184200230Smarcel "NetMos NM9865 Dual UART", 1185200230Smarcel DEFAULT_RCLK, 1186200230Smarcel PUC_PORT_2S, 0x10, 4, 0, 1187200230Smarcel }, 1188200230Smarcel 1189200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3003, 1190200230Smarcel "NetMos NM9865 Triple UART", 1191200230Smarcel DEFAULT_RCLK, 1192200230Smarcel PUC_PORT_3S, 0x10, 4, 0, 1193200230Smarcel }, 1194200230Smarcel 1195200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3004, 1196200230Smarcel "NetMos NM9865 Quad UART", 1197200230Smarcel DEFAULT_RCLK, 1198247571Smarius PUC_PORT_4S, 0x10, 4, 0, 1199200230Smarcel }, 1200200230Smarcel 1201200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3011, 1202200230Smarcel "NetMos NM9865 Single UART and 1284 Printer port", 1203200230Smarcel DEFAULT_RCLK, 1204200230Smarcel PUC_PORT_1S1P, 0x10, 4, 0, 1205200230Smarcel }, 1206200230Smarcel 1207200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3012, 1208200230Smarcel "NetMos NM9865 Dual UART and 1284 Printer port", 1209200230Smarcel DEFAULT_RCLK, 1210200230Smarcel PUC_PORT_2S1P, 0x10, 4, 0, 1211200230Smarcel }, 1212200230Smarcel 1213200230Smarcel { 0x9710, 0x9865, 0xa000, 0x3020, 1214200230Smarcel "NetMos NM9865 Dual 1284 Printer port", 1215200230Smarcel DEFAULT_RCLK, 1216200230Smarcel PUC_PORT_2P, 0x10, 4, 0, 1217200230Smarcel }, 1218200230Smarcel 1219158124Smarcel { 0xb00c, 0x021c, 0xffff, 0, 1220158124Smarcel "IC Book Labs Gunboat x4 Lite", 1221158124Smarcel DEFAULT_RCLK, 1222158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1223158124Smarcel .config_function = puc_config_icbook 1224128602Ssobomax }, 1225128602Ssobomax 1226158124Smarcel { 0xb00c, 0x031c, 0xffff, 0, 1227158124Smarcel "IC Book Labs Gunboat x4 Pro", 1228158124Smarcel DEFAULT_RCLK, 1229158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1230158124Smarcel .config_function = puc_config_icbook 1231128602Ssobomax }, 1232128602Ssobomax 1233158124Smarcel { 0xb00c, 0x041c, 0xffff, 0, 1234158124Smarcel "IC Book Labs Ironclad x8 Lite", 1235158124Smarcel DEFAULT_RCLK, 1236158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 1237158124Smarcel .config_function = puc_config_icbook 1238114344Ssobomax }, 1239114344Ssobomax 1240158124Smarcel { 0xb00c, 0x051c, 0xffff, 0, 1241158124Smarcel "IC Book Labs Ironclad x8 Pro", 1242158124Smarcel DEFAULT_RCLK, 1243158124Smarcel PUC_PORT_8S, 0x10, 0, 8, 1244158124Smarcel .config_function = puc_config_icbook 1245114344Ssobomax }, 1246114344Ssobomax 1247158124Smarcel { 0xb00c, 0x081c, 0xffff, 0, 1248158124Smarcel "IC Book Labs Dreadnought x16 Pro", 1249158124Smarcel DEFAULT_RCLK * 8, 1250158124Smarcel PUC_PORT_16S, 0x10, 0, 8, 1251158124Smarcel .config_function = puc_config_icbook 1252108346Ssobomax }, 1253108346Ssobomax 1254158124Smarcel { 0xb00c, 0x091c, 0xffff, 0, 1255158124Smarcel "IC Book Labs Dreadnought x16 Lite", 1256158124Smarcel DEFAULT_RCLK, 1257158124Smarcel PUC_PORT_16S, 0x10, 0, 8, 1258158124Smarcel .config_function = puc_config_icbook 1259112154Ssobomax }, 1260112154Ssobomax 1261158124Smarcel { 0xb00c, 0x0a1c, 0xffff, 0, 1262158124Smarcel "IC Book Labs Gunboat x2 Low Profile", 1263158124Smarcel DEFAULT_RCLK, 1264158124Smarcel PUC_PORT_2S, 0x10, 0, 8, 1265129337Srik }, 1266129337Srik 1267158124Smarcel { 0xb00c, 0x0b1c, 0xffff, 0, 1268158124Smarcel "IC Book Labs Gunboat x4 Low Profile", 1269158124Smarcel DEFAULT_RCLK, 1270158124Smarcel PUC_PORT_4S, 0x10, 0, 8, 1271158124Smarcel .config_function = puc_config_icbook 1272139728Swilko }, 1273139728Swilko 1274158124Smarcel { 0xffff, 0, 0xffff, 0, NULL, 0 } 1275158124Smarcel}; 1276139728Swilko 1277158124Smarcelstatic int 1278318151Smariuspuc_config_advantech(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1279318151Smarius intptr_t *res __unused) 1280318151Smarius{ 1281318151Smarius const struct puc_cfg *cfg; 1282318151Smarius struct resource *cres; 1283318151Smarius struct puc_bar *bar; 1284318151Smarius device_t cdev, dev; 1285318151Smarius bus_size_t off; 1286318151Smarius int base, crtype, fixed, high, i, oxpcie; 1287318151Smarius uint8_t acr, func, mask; 1288318151Smarius 1289318151Smarius if (cmd != PUC_CFG_SETUP) 1290318151Smarius return (ENXIO); 1291318151Smarius 1292318151Smarius base = fixed = oxpcie = 0; 1293318151Smarius crtype = SYS_RES_IOPORT; 1294318151Smarius acr = mask = 0x0; 1295318151Smarius func = high = 1; 1296318151Smarius off = 0x60; 1297318151Smarius 1298318151Smarius cfg = sc->sc_cfg; 1299318151Smarius switch (cfg->subvendor) { 1300318151Smarius case 0x13fe: 1301318151Smarius switch (cfg->device) { 1302318151Smarius case 0xa102: 1303318151Smarius high = 0; 1304318151Smarius break; 1305318151Smarius default: 1306318151Smarius break; 1307318151Smarius } 1308318151Smarius default: 1309318151Smarius break; 1310318151Smarius } 1311318151Smarius if (fixed == 1) 1312318151Smarius goto setup; 1313318151Smarius 1314318151Smarius dev = sc->sc_dev; 1315318151Smarius cdev = pci_find_dbsf(pci_get_domain(dev), pci_get_bus(dev), 1316318151Smarius pci_get_slot(dev), func); 1317318151Smarius if (cdev == NULL) { 1318318151Smarius device_printf(dev, "could not find config function\n"); 1319318151Smarius return (ENXIO); 1320318151Smarius } 1321318151Smarius 1322318151Smarius i = PCIR_BAR(0); 1323318151Smarius cres = bus_alloc_resource_any(cdev, crtype, &i, RF_ACTIVE); 1324318151Smarius if (cres == NULL) { 1325318151Smarius device_printf(dev, "could not allocate config resource\n"); 1326318151Smarius return (ENXIO); 1327318151Smarius } 1328318151Smarius 1329318151Smarius if (oxpcie == 0) { 1330318151Smarius mask = bus_read_1(cres, off); 1331318151Smarius if (pci_get_function(dev) == 1) 1332318151Smarius base = 4; 1333318151Smarius } 1334318151Smarius 1335318151Smarius setup: 1336318151Smarius for (i = 0; i < sc->sc_nports; ++i) { 1337318151Smarius device_printf(dev, "port %d: ", i); 1338318151Smarius bar = puc_get_bar(sc, cfg->rid + i * cfg->d_rid); 1339318151Smarius if (bar == NULL) { 1340318151Smarius printf("could not get BAR\n"); 1341318151Smarius continue; 1342318151Smarius } 1343318151Smarius 1344318151Smarius if (fixed == 0) { 1345318151Smarius if ((mask & (1 << (base + i))) == 0) { 1346318151Smarius acr = 0; 1347318151Smarius printf("RS-232\n"); 1348318151Smarius } else { 1349318151Smarius acr = (high == 1 ? 0x18 : 0x10); 1350318151Smarius printf("RS-422/RS-485, active-%s auto-DTR\n", 1351318151Smarius high == 1 ? "high" : "low"); 1352318151Smarius } 1353318151Smarius } 1354318151Smarius 1355318151Smarius bus_write_1(bar->b_res, REG_SPR, REG_ACR); 1356318151Smarius bus_write_1(bar->b_res, REG_ICR, acr); 1357318151Smarius } 1358318151Smarius 1359318151Smarius bus_release_resource(cdev, crtype, rman_get_rid(cres), cres); 1360318151Smarius return (0); 1361318151Smarius} 1362318151Smarius 1363318151Smariusstatic int 1364294961Smariuspuc_config_amc(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, int port, 1365158124Smarcel intptr_t *res) 1366158124Smarcel{ 1367294961Smarius 1368158124Smarcel switch (cmd) { 1369158124Smarcel case PUC_CFG_GET_OFS: 1370158124Smarcel *res = 8 * (port & 1); 1371158124Smarcel return (0); 1372158124Smarcel case PUC_CFG_GET_RID: 1373158124Smarcel *res = 0x14 + (port >> 1) * 4; 1374158124Smarcel return (0); 1375158124Smarcel default: 1376158124Smarcel break; 1377158124Smarcel } 1378158124Smarcel return (ENXIO); 1379158124Smarcel} 1380140513Sbms 1381158124Smarcelstatic int 1382222660Sjhbpuc_config_diva(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1383158124Smarcel intptr_t *res) 1384158124Smarcel{ 1385222660Sjhb const struct puc_cfg *cfg = sc->sc_cfg; 1386222660Sjhb 1387158124Smarcel if (cmd == PUC_CFG_GET_OFS) { 1388222660Sjhb if (cfg->subdevice == 0x1282) /* Everest SP */ 1389222660Sjhb port <<= 1; 1390222660Sjhb else if (cfg->subdevice == 0x104b) /* Maestro SP2 */ 1391222660Sjhb port = (port == 3) ? 4 : port; 1392222660Sjhb *res = port * 8 + ((port > 2) ? 0x18 : 0); 1393158124Smarcel return (0); 1394158124Smarcel } 1395158124Smarcel return (ENXIO); 1396158124Smarcel} 1397140882Sbms 1398158124Smarcelstatic int 1399294961Smariuspuc_config_exar(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1400294961Smarius int port, intptr_t *res) 1401158124Smarcel{ 1402294961Smarius 1403158124Smarcel if (cmd == PUC_CFG_GET_OFS) { 1404222660Sjhb *res = port * 0x200; 1405158124Smarcel return (0); 1406158124Smarcel } 1407158124Smarcel return (ENXIO); 1408158124Smarcel} 1409158124Smarcel 1410158124Smarcelstatic int 1411294961Smariuspuc_config_exar_pcie(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1412294961Smarius int port, intptr_t *res) 1413248340Srstone{ 1414294961Smarius 1415248340Srstone if (cmd == PUC_CFG_GET_OFS) { 1416248340Srstone *res = port * 0x400; 1417248340Srstone return (0); 1418248340Srstone } 1419248340Srstone return (ENXIO); 1420248340Srstone} 1421248340Srstone 1422248340Srstonestatic int 1423294961Smariuspuc_config_icbook(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1424294961Smarius int port __unused, intptr_t *res) 1425158124Smarcel{ 1426294961Smarius 1427158124Smarcel if (cmd == PUC_CFG_GET_ILR) { 1428158124Smarcel *res = PUC_ILR_DIGI; 1429158124Smarcel return (0); 1430158124Smarcel } 1431158124Smarcel return (ENXIO); 1432158124Smarcel} 1433158124Smarcel 1434158124Smarcelstatic int 1435227457Seadlerpuc_config_moxa(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1436227457Seadler intptr_t *res) 1437227457Seadler{ 1438294961Smarius const struct puc_cfg *cfg = sc->sc_cfg; 1439294961Smarius 1440237350Sfjoe if (cmd == PUC_CFG_GET_OFS) { 1441294961Smarius if (port == 3 && (cfg->device == 0x1045 || 1442294961Smarius cfg->device == 0x1144)) 1443238933Sfjoe port = 7; 1444238933Sfjoe *res = port * 0x200; 1445238933Sfjoe 1446227457Seadler return 0; 1447227457Seadler } 1448227457Seadler return (ENXIO); 1449227457Seadler} 1450227457Seadler 1451227457Seadlerstatic int 1452294961Smariuspuc_config_quatech(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1453294961Smarius int port __unused, intptr_t *res) 1454158124Smarcel{ 1455158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1456158124Smarcel struct puc_bar *bar; 1457158124Smarcel uint8_t v0, v1; 1458158124Smarcel 1459158124Smarcel switch (cmd) { 1460158124Smarcel case PUC_CFG_SETUP: 1461158124Smarcel /* 1462158124Smarcel * Check if the scratchpad register is enabled or if the 1463158124Smarcel * interrupt status and options registers are active. 1464158124Smarcel */ 1465158124Smarcel bar = puc_get_bar(sc, cfg->rid); 1466158124Smarcel if (bar == NULL) 1467158124Smarcel return (ENXIO); 1468318151Smarius bus_write_1(bar->b_res, REG_LCR, LCR_DLAB); 1469318151Smarius bus_write_1(bar->b_res, REG_SPR, 0); 1470318151Smarius v0 = bus_read_1(bar->b_res, REG_SPR); 1471318151Smarius bus_write_1(bar->b_res, REG_SPR, 0x80 + -cfg->clock); 1472318151Smarius v1 = bus_read_1(bar->b_res, REG_SPR); 1473318151Smarius bus_write_1(bar->b_res, REG_LCR, 0); 1474158124Smarcel sc->sc_cfg_data = (v0 << 8) | v1; 1475158124Smarcel if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1476158124Smarcel /* 1477158124Smarcel * The SPR register echoed the two values written 1478318151Smarius * by us. This means that the SPAD jumper is set. 1479158124Smarcel */ 1480158124Smarcel device_printf(sc->sc_dev, "warning: extra features " 1481158124Smarcel "not usable -- SPAD compatibility enabled\n"); 1482158124Smarcel return (0); 1483158124Smarcel } 1484158124Smarcel if (v0 != 0) { 1485158124Smarcel /* 1486318151Smarius * The first value doesn't match. This can only mean 1487158124Smarcel * that the SPAD jumper is not set and that a non- 1488158124Smarcel * standard fixed clock multiplier jumper is set. 1489158124Smarcel */ 1490158124Smarcel if (bootverbose) 1491158124Smarcel device_printf(sc->sc_dev, "fixed clock rate " 1492158124Smarcel "multiplier of %d\n", 1 << v0); 1493158124Smarcel if (v0 < -cfg->clock) 1494158124Smarcel device_printf(sc->sc_dev, "warning: " 1495158124Smarcel "suboptimal fixed clock rate multiplier " 1496158124Smarcel "setting\n"); 1497158124Smarcel return (0); 1498158124Smarcel } 1499158124Smarcel /* 1500318151Smarius * The first value matched, but the second didn't. We know 1501318151Smarius * that the SPAD jumper is not set. We also know that the 1502158124Smarcel * clock rate multiplier is software controlled *and* that 1503158124Smarcel * we just programmed it to the maximum allowed. 1504158124Smarcel */ 1505158124Smarcel if (bootverbose) 1506158124Smarcel device_printf(sc->sc_dev, "clock rate multiplier of " 1507158124Smarcel "%d selected\n", 1 << -cfg->clock); 1508158124Smarcel return (0); 1509158124Smarcel case PUC_CFG_GET_CLOCK: 1510158124Smarcel v0 = (sc->sc_cfg_data >> 8) & 0xff; 1511158124Smarcel v1 = sc->sc_cfg_data & 0xff; 1512158124Smarcel if (v0 == 0 && v1 == 0x80 + -cfg->clock) { 1513158124Smarcel /* 1514158124Smarcel * XXX With the SPAD jumper applied, there's no 1515158124Smarcel * easy way of knowing if there's also a clock 1516318151Smarius * rate multiplier jumper installed. Let's hope 1517318151Smarius * not ... 1518158124Smarcel */ 1519158124Smarcel *res = DEFAULT_RCLK; 1520158124Smarcel } else if (v0 == 0) { 1521158124Smarcel /* 1522158124Smarcel * No clock rate multiplier jumper installed, 1523158124Smarcel * so we programmed the board with the maximum 1524158124Smarcel * multiplier allowed as given to us in the 1525158124Smarcel * clock field of the config record (negated). 1526158124Smarcel */ 1527158124Smarcel *res = DEFAULT_RCLK << -cfg->clock; 1528158124Smarcel } else 1529158124Smarcel *res = DEFAULT_RCLK << v0; 1530158124Smarcel return (0); 1531158124Smarcel case PUC_CFG_GET_ILR: 1532158124Smarcel v0 = (sc->sc_cfg_data >> 8) & 0xff; 1533158124Smarcel v1 = sc->sc_cfg_data & 0xff; 1534294961Smarius *res = (v0 == 0 && v1 == 0x80 + -cfg->clock) ? 1535294961Smarius PUC_ILR_NONE : PUC_ILR_QUATECH; 1536158124Smarcel return (0); 1537158124Smarcel default: 1538158124Smarcel break; 1539158124Smarcel } 1540158124Smarcel return (ENXIO); 1541158124Smarcel} 1542158124Smarcel 1543158124Smarcelstatic int 1544158124Smarcelpuc_config_syba(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1545158124Smarcel intptr_t *res) 1546158124Smarcel{ 1547158124Smarcel static int base[] = { 0x251, 0x3f0, 0 }; 1548158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1549158124Smarcel struct puc_bar *bar; 1550158124Smarcel int efir, idx, ofs; 1551158124Smarcel uint8_t v; 1552158124Smarcel 1553158124Smarcel switch (cmd) { 1554158124Smarcel case PUC_CFG_SETUP: 1555158124Smarcel bar = puc_get_bar(sc, cfg->rid); 1556158124Smarcel if (bar == NULL) 1557158124Smarcel return (ENXIO); 1558158124Smarcel 1559158124Smarcel /* configure both W83877TFs */ 1560158124Smarcel bus_write_1(bar->b_res, 0x250, 0x89); 1561158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0x87); 1562158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0x87); 1563158124Smarcel idx = 0; 1564158124Smarcel while (base[idx] != 0) { 1565158124Smarcel efir = base[idx]; 1566158124Smarcel bus_write_1(bar->b_res, efir, 0x09); 1567158124Smarcel v = bus_read_1(bar->b_res, efir + 1); 1568158124Smarcel if ((v & 0x0f) != 0x0c) 1569158124Smarcel return (ENXIO); 1570158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1571158124Smarcel v = bus_read_1(bar->b_res, efir + 1); 1572158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1573158124Smarcel bus_write_1(bar->b_res, efir + 1, v | 0x04); 1574158124Smarcel bus_write_1(bar->b_res, efir, 0x16); 1575158124Smarcel bus_write_1(bar->b_res, efir + 1, v & ~0x04); 1576158124Smarcel ofs = base[idx] & 0x300; 1577158124Smarcel bus_write_1(bar->b_res, efir, 0x23); 1578158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0x78) >> 2); 1579158124Smarcel bus_write_1(bar->b_res, efir, 0x24); 1580158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0xf8) >> 2); 1581158124Smarcel bus_write_1(bar->b_res, efir, 0x25); 1582158124Smarcel bus_write_1(bar->b_res, efir + 1, (ofs + 0xe8) >> 2); 1583158124Smarcel bus_write_1(bar->b_res, efir, 0x17); 1584158124Smarcel bus_write_1(bar->b_res, efir + 1, 0x03); 1585158124Smarcel bus_write_1(bar->b_res, efir, 0x28); 1586158124Smarcel bus_write_1(bar->b_res, efir + 1, 0x43); 1587158124Smarcel idx++; 1588158124Smarcel } 1589158124Smarcel bus_write_1(bar->b_res, 0x250, 0xaa); 1590158124Smarcel bus_write_1(bar->b_res, 0x3f0, 0xaa); 1591158124Smarcel return (0); 1592158124Smarcel case PUC_CFG_GET_OFS: 1593158124Smarcel switch (port) { 1594158124Smarcel case 0: 1595158124Smarcel *res = 0x2f8; 1596158124Smarcel return (0); 1597158124Smarcel case 1: 1598158124Smarcel *res = 0x2e8; 1599158124Smarcel return (0); 1600158124Smarcel case 2: 1601158124Smarcel *res = 0x3f8; 1602158124Smarcel return (0); 1603158124Smarcel case 3: 1604158124Smarcel *res = 0x3e8; 1605158124Smarcel return (0); 1606158124Smarcel case 4: 1607158124Smarcel *res = 0x278; 1608158124Smarcel return (0); 1609158124Smarcel } 1610158124Smarcel break; 1611158124Smarcel default: 1612158124Smarcel break; 1613158124Smarcel } 1614158124Smarcel return (ENXIO); 1615158124Smarcel} 1616158124Smarcel 1617158124Smarcelstatic int 1618158124Smarcelpuc_config_siig(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1619158124Smarcel intptr_t *res) 1620158124Smarcel{ 1621158124Smarcel const struct puc_cfg *cfg = sc->sc_cfg; 1622158124Smarcel 1623158124Smarcel switch (cmd) { 1624158124Smarcel case PUC_CFG_GET_OFS: 1625158124Smarcel if (cfg->ports == PUC_PORT_8S) { 1626158124Smarcel *res = (port > 4) ? 8 * (port - 4) : 0; 1627158124Smarcel return (0); 1628158124Smarcel } 1629158124Smarcel break; 1630158124Smarcel case PUC_CFG_GET_RID: 1631158124Smarcel if (cfg->ports == PUC_PORT_8S) { 1632158124Smarcel *res = 0x10 + ((port > 4) ? 0x10 : 4 * port); 1633158124Smarcel return (0); 1634158124Smarcel } 1635158124Smarcel if (cfg->ports == PUC_PORT_2S1P) { 1636158124Smarcel switch (port) { 1637158124Smarcel case 0: *res = 0x10; return (0); 1638158124Smarcel case 1: *res = 0x14; return (0); 1639158124Smarcel case 2: *res = 0x1c; return (0); 1640158124Smarcel } 1641158124Smarcel } 1642158124Smarcel break; 1643158124Smarcel default: 1644158124Smarcel break; 1645158124Smarcel } 1646158124Smarcel return (ENXIO); 1647158124Smarcel} 1648158124Smarcel 1649158124Smarcelstatic int 1650158124Smarcelpuc_config_timedia(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1651158124Smarcel intptr_t *res) 1652158124Smarcel{ 1653247571Smarius static const uint16_t dual[] = { 1654158124Smarcel 0x0002, 0x4036, 0x4037, 0x4038, 0x4078, 0x4079, 0x4085, 1655251713Smarius 0x4088, 0x4089, 0x5037, 0x5078, 0x5079, 0x5085, 0x6079, 1656251713Smarius 0x7079, 0x8079, 0x8137, 0x8138, 0x8237, 0x8238, 0x9079, 1657158124Smarcel 0x9137, 0x9138, 0x9237, 0x9238, 0xA079, 0xB079, 0xC079, 1658158124Smarcel 0xD079, 0 1659158124Smarcel }; 1660247571Smarius static const uint16_t quad[] = { 1661251713Smarius 0x4055, 0x4056, 0x4095, 0x4096, 0x5056, 0x8156, 0x8157, 1662251713Smarius 0x8256, 0x8257, 0x9056, 0x9156, 0x9157, 0x9158, 0x9159, 1663158124Smarcel 0x9256, 0x9257, 0xA056, 0xA157, 0xA158, 0xA159, 0xB056, 1664158124Smarcel 0xB157, 0 1665158124Smarcel }; 1666247571Smarius static const uint16_t octa[] = { 1667251713Smarius 0x4065, 0x4066, 0x5065, 0x5066, 0x8166, 0x9066, 0x9166, 1668158124Smarcel 0x9167, 0x9168, 0xA066, 0xA167, 0xA168, 0 1669158124Smarcel }; 1670247571Smarius static const struct { 1671158124Smarcel int ports; 1672247571Smarius const uint16_t *ids; 1673158124Smarcel } subdevs[] = { 1674158124Smarcel { 2, dual }, 1675158124Smarcel { 4, quad }, 1676158124Smarcel { 8, octa }, 1677158124Smarcel { 0, NULL } 1678158124Smarcel }; 1679158124Smarcel static char desc[64]; 1680158124Smarcel int dev, id; 1681158124Smarcel uint16_t subdev; 1682158124Smarcel 1683158124Smarcel switch (cmd) { 1684222328Sjhb case PUC_CFG_GET_CLOCK: 1685222328Sjhb if (port < 2) 1686222328Sjhb *res = DEFAULT_RCLK * 8; 1687222328Sjhb else 1688222328Sjhb *res = DEFAULT_RCLK; 1689222328Sjhb return (0); 1690158124Smarcel case PUC_CFG_GET_DESC: 1691158124Smarcel snprintf(desc, sizeof(desc), 1692158124Smarcel "Timedia technology %d Port Serial", (int)sc->sc_cfg_data); 1693158124Smarcel *res = (intptr_t)desc; 1694158124Smarcel return (0); 1695158124Smarcel case PUC_CFG_GET_NPORTS: 1696158124Smarcel subdev = pci_get_subdevice(sc->sc_dev); 1697158124Smarcel dev = 0; 1698158124Smarcel while (subdevs[dev].ports != 0) { 1699158124Smarcel id = 0; 1700158124Smarcel while (subdevs[dev].ids[id] != 0) { 1701158124Smarcel if (subdev == subdevs[dev].ids[id]) { 1702158124Smarcel sc->sc_cfg_data = subdevs[dev].ports; 1703158124Smarcel *res = sc->sc_cfg_data; 1704158124Smarcel return (0); 1705158124Smarcel } 1706158124Smarcel id++; 1707158124Smarcel } 1708158124Smarcel dev++; 1709158124Smarcel } 1710158124Smarcel return (ENXIO); 1711158124Smarcel case PUC_CFG_GET_OFS: 1712158124Smarcel *res = (port == 1 || port == 3) ? 8 : 0; 1713158124Smarcel return (0); 1714158124Smarcel case PUC_CFG_GET_RID: 1715179050Smarcel *res = 0x10 + ((port > 3) ? port - 2 : port >> 1) * 4; 1716158124Smarcel return (0); 1717158124Smarcel case PUC_CFG_GET_TYPE: 1718158124Smarcel *res = PUC_TYPE_SERIAL; 1719158124Smarcel return (0); 1720158124Smarcel default: 1721158124Smarcel break; 1722158124Smarcel } 1723158124Smarcel return (ENXIO); 1724158124Smarcel} 1725158124Smarcel 1726158124Smarcelstatic int 1727251715Smariuspuc_config_oxford_pci954(struct puc_softc *sc, enum puc_cfg_cmd cmd, 1728251715Smarius int port __unused, intptr_t *res) 1729251715Smarius{ 1730251715Smarius 1731251715Smarius switch (cmd) { 1732251715Smarius case PUC_CFG_GET_CLOCK: 1733251715Smarius /* 1734251715Smarius * OXu16PCI954 use a 14.7456 MHz clock by default while 1735251715Smarius * OX16PCI954 and OXm16PCI954 employ a 1.8432 MHz one. 1736251715Smarius */ 1737251715Smarius if (pci_get_revid(sc->sc_dev) == 1) 1738251715Smarius *res = DEFAULT_RCLK * 8; 1739251715Smarius else 1740251715Smarius *res = DEFAULT_RCLK; 1741251715Smarius return (0); 1742251715Smarius default: 1743251715Smarius break; 1744251715Smarius } 1745251715Smarius return (ENXIO); 1746251715Smarius} 1747251715Smarius 1748251715Smariusstatic int 1749221182Sjhbpuc_config_oxford_pcie(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1750221182Sjhb intptr_t *res) 1751221182Sjhb{ 1752221182Sjhb const struct puc_cfg *cfg = sc->sc_cfg; 1753221182Sjhb int idx; 1754221182Sjhb struct puc_bar *bar; 1755221182Sjhb uint8_t value; 1756221182Sjhb 1757221182Sjhb switch (cmd) { 1758221182Sjhb case PUC_CFG_SETUP: 1759221182Sjhb device_printf(sc->sc_dev, "%d UARTs detected\n", 1760221182Sjhb sc->sc_nports); 1761221182Sjhb 1762221182Sjhb /* Set UARTs to enhanced mode */ 1763221182Sjhb bar = puc_get_bar(sc, cfg->rid); 1764221182Sjhb if (bar == NULL) 1765221182Sjhb return (ENXIO); 1766221182Sjhb for (idx = 0; idx < sc->sc_nports; idx++) { 1767222760Sjhb value = bus_read_1(bar->b_res, 0x1000 + (idx << 9) + 1768222760Sjhb 0x92); 1769221182Sjhb bus_write_1(bar->b_res, 0x1000 + (idx << 9) + 0x92, 1770222760Sjhb value | 0x10); 1771221182Sjhb } 1772221182Sjhb return (0); 1773221182Sjhb case PUC_CFG_GET_LEN: 1774221182Sjhb *res = 0x200; 1775221182Sjhb return (0); 1776221182Sjhb case PUC_CFG_GET_NPORTS: 1777221182Sjhb /* 1778221182Sjhb * Check if we are being called from puc_bfe_attach() 1779318151Smarius * or puc_bfe_probe(). If puc_bfe_probe(), we cannot 1780318151Smarius * puc_get_bar(), so we return a value of 16. This has 1781318151Smarius * cosmetic side-effects at worst; in PUC_CFG_GET_DESC, 1782318151Smarius * sc->sc_cfg_data will not contain the true number of 1783318151Smarius * ports in PUC_CFG_GET_DESC, but we are not implementing 1784318151Smarius * that call for this device family anyway. 1785221182Sjhb * 1786318151Smarius * The check is for initialization of sc->sc_bar[idx], 1787318151Smarius * which is only done in puc_bfe_attach(). 1788221182Sjhb */ 1789221182Sjhb idx = 0; 1790221182Sjhb do { 1791221182Sjhb if (sc->sc_bar[idx++].b_rid != -1) { 1792221182Sjhb sc->sc_cfg_data = 16; 1793221182Sjhb *res = sc->sc_cfg_data; 1794221182Sjhb return (0); 1795221182Sjhb } 1796221182Sjhb } while (idx < PUC_PCI_BARS); 1797221182Sjhb 1798221182Sjhb bar = puc_get_bar(sc, cfg->rid); 1799221182Sjhb if (bar == NULL) 1800221182Sjhb return (ENXIO); 1801221182Sjhb 1802221182Sjhb value = bus_read_1(bar->b_res, 0x04); 1803221182Sjhb if (value == 0) 1804221182Sjhb return (ENXIO); 1805221182Sjhb 1806221182Sjhb sc->sc_cfg_data = value; 1807221182Sjhb *res = sc->sc_cfg_data; 1808221182Sjhb return (0); 1809221182Sjhb case PUC_CFG_GET_OFS: 1810221182Sjhb *res = 0x1000 + (port << 9); 1811221182Sjhb return (0); 1812221182Sjhb case PUC_CFG_GET_TYPE: 1813221182Sjhb *res = PUC_TYPE_SERIAL; 1814221182Sjhb return (0); 1815221182Sjhb default: 1816221182Sjhb break; 1817221182Sjhb } 1818221182Sjhb return (ENXIO); 1819221182Sjhb} 1820221182Sjhb 1821221182Sjhbstatic int 1822264761Smariuspuc_config_sunix(struct puc_softc *sc, enum puc_cfg_cmd cmd, int port, 1823264761Smarius intptr_t *res) 1824264761Smarius{ 1825264761Smarius int error; 1826264761Smarius 1827264761Smarius switch (cmd) { 1828264761Smarius case PUC_CFG_GET_OFS: 1829264761Smarius error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1830264761Smarius if (error != 0) 1831264761Smarius return (error); 1832264761Smarius *res = (*res == PUC_TYPE_SERIAL) ? (port & 3) * 8 : 0; 1833264761Smarius return (0); 1834264761Smarius case PUC_CFG_GET_RID: 1835264761Smarius error = puc_config(sc, PUC_CFG_GET_TYPE, port, res); 1836264761Smarius if (error != 0) 1837264761Smarius return (error); 1838264761Smarius *res = (*res == PUC_TYPE_SERIAL && port <= 3) ? 0x10 : 0x14; 1839264761Smarius return (0); 1840264761Smarius default: 1841264761Smarius break; 1842264761Smarius } 1843264761Smarius return (ENXIO); 1844264761Smarius} 1845264761Smarius 1846264761Smariusstatic int 1847294961Smariuspuc_config_titan(struct puc_softc *sc __unused, enum puc_cfg_cmd cmd, 1848294961Smarius int port, intptr_t *res) 1849158124Smarcel{ 1850294961Smarius 1851158124Smarcel switch (cmd) { 1852158124Smarcel case PUC_CFG_GET_OFS: 1853158124Smarcel *res = (port < 3) ? 0 : (port - 2) << 3; 1854158124Smarcel return (0); 1855158124Smarcel case PUC_CFG_GET_RID: 1856158124Smarcel *res = 0x14 + ((port >= 2) ? 0x0c : port << 2); 1857158124Smarcel return (0); 1858158124Smarcel default: 1859158124Smarcel break; 1860158124Smarcel } 1861158124Smarcel return (ENXIO); 1862158124Smarcel} 1863