ppcreg.h revision 28259
1/*- 2 * Copyright (c) 1997 Nicolas Souchu 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice, this list of conditions and the following disclaimer. 10 * 2. Redistributions in binary form must reproduce the above copyright 11 * notice, this list of conditions and the following disclaimer in the 12 * documentation and/or other materials provided with the distribution. 13 * 14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 24 * SUCH DAMAGE. 25 * 26 * $Id: ppcreg.h,v 1.1 1997/08/14 14:01:36 msmith Exp $ 27 * 28 */ 29#ifndef __PPC_H 30#define __PPC_H 31 32/* 33 * Parallel Port Chipset type. 34 */ 35#define SMC_UNKNOWN 0x0 36#define SMC_37C665GT 0x1 37#define SMC_37C666GT 0x2 38#define NS_UNKNOWN 0x3 39#define NS_PC87332 0x4 40#define NS_PC87306 0x5 41#define INTEL_820191AA 0x6 42#define GENERIC 0x7 43 44/* 45 * Generic structure to hold parallel port chipset info. 46 */ 47struct ppc_data { 48 49 int ppc_unit; 50 int ppc_type; 51 52#define ppc_base ppc_link.base 53#define ppc_mode ppc_link.mode 54#define ppc_epp ppc_link.epp_protocol 55#define ppc_irq ppc_link.id_irq 56 57 unsigned char ppc_flags; 58 59 struct ppb_link ppc_link; 60}; 61 62/* 63 * Parallel Port Chipset errors. XXX 64 */ 65#define PPC_ENOPORT 9 66 67/* 68 * Parallel Port Chipset registers. 69 */ 70#define PPC_SPP_DTR 0 /* SPP data register */ 71#define PPC_SPP_STR 1 /* SPP status register */ 72#define PPC_SPP_CTR 2 /* SPP control register */ 73#define PPC_EPP_DATA 4 /* EPP data register (8, 16 or 32 bit) */ 74#define PPC_ECP_FIFO 0x400 /* ECP fifo register */ 75#define PPC_ECP_ECR 0x402 /* ECP extended control register */ 76 77#define r_dtr(ppc) inb((ppc)->ppc_base + PPC_SPP_DTR) 78#define r_str(ppc) inb((ppc)->ppc_base + PPC_SPP_STR) 79#define r_ctr(ppc) inb((ppc)->ppc_base + PPC_SPP_CTR) 80#define r_epp(ppc) inb((ppc)->ppc_base + PPC_EPP_DATA) 81#define r_ecr(ppc) inb((ppc)->ppc_base + PPC_ECP_ECR) 82#define r_fifo(ppc) inb((ppc)->ppc_base + PPC_ECP_FIFO) 83 84#define w_dtr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_DTR, byte) 85#define w_str(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_STR, byte) 86#define w_ctr(ppc,byte) outb((ppc)->ppc_base + PPC_SPP_CTR, byte) 87#define w_epp(ppc,byte) outb((ppc)->ppc_base + PPC_EPP_DATA, byte) 88#define w_ecr(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_ECR, byte) 89#define w_fifo(ppc,byte) outb((ppc)->ppc_base + PPC_ECP_FIFO, byte) 90 91/* 92 * Register defines for the PC873xx parts 93 */ 94 95#define PC873_FER 0x00 96#define PC873_PPENABLE (1<<0) 97#define PC873_FAR 0x01 98#define PC873_PTR 0x02 99#define PC873_CFGLOCK (1<<6) 100#define PC873_EPPRDIR (1<<7) 101#define PC873_FCR 0x03 102#define PC873_ZWS (1<<5) 103#define PC873_ZWSPWDN (1<<6) 104#define PC873_PCR 0x04 105#define PC873_EPPEN (1<<0) 106#define PC873_EPP19 (1<<1) 107#define PC873_ECPEN (1<<2) 108#define PC873_ECPCLK (1<<3) 109#define PC873_PMC 0x06 110#define PC873_TUP 0x07 111#define PC873_SID 0x08 112 113/* 114 * Register defines for the SMC FDC37C66xGT parts. 115 */ 116 117/* Init codes */ 118#define SMC665_iCODE 0x55 119#define SMC666_iCODE 0x44 120 121/* Base configuration ports */ 122#define SMC66x_CSR 0x3F0 123#define SMC666_CSR 0x370 /* hard-configured value for 666 */ 124 125/* Bits */ 126#define SMC_CR1_ADDR 0x3 /* bit 0 and 1 */ 127#define SMC_CR1_MODE 0x8 /* bit 3 */ 128#define SMC_CR4_EMODE 0x3 /* bits 0 and 1 */ 129#define SMC_CR4_EPPTYPE 0x40 /* bit 6 */ 130 131/* Extended modes */ 132#define SMC_SPP 0x0 /* SPP */ 133#define SMC_EPPSPP 0x1 /* EPP and SPP */ 134#define SMC_ECP 0x2 /* ECP */ 135#define SMC_ECPEPP 0x3 /* ECP and EPP */ 136 137#endif 138 139