ppcreg.h revision 182016 
1/*-
2 * Copyright (c) 2001 Alcove - Nicolas Souchu
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice, this list of conditions and the following disclaimer.
10 * 2. Redistributions in binary form must reproduce the above copyright
11 *    notice, this list of conditions and the following disclaimer in the
12 *    documentation and/or other materials provided with the distribution.
13 *
14 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
15 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
16 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
17 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
18 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
19 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
20 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
21 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
22 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
23 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
24 * SUCH DAMAGE.
25 *
26 * $FreeBSD: head/sys/dev/ppc/ppcreg.h 182016 2008-08-22 18:43:19Z jhb $
27 *
28 */
29#ifndef __PPCREG_H
30#define __PPCREG_H
31
32/*
33 * Parallel Port Chipset type.
34 */
35#define SMC_LIKE	0
36#define SMC_37C665GT	1
37#define SMC_37C666GT	2
38#define NS_PC87332	3
39#define NS_PC87306	4
40#define INTEL_820191AA	5	/* XXX not implemented */
41#define GENERIC		6
42#define WINB_W83877F	7
43#define WINB_W83877AF	8
44#define WINB_UNKNOWN	9
45#define NS_PC87334	10
46#define SMC_37C935	11
47#define NS_PC87303	12
48
49/*
50 * Parallel Port Chipset Type. SMC versus GENERIC (others)
51 */
52#define PPC_TYPE_SMCLIKE 0
53#define PPC_TYPE_GENERIC 1
54
55/*
56 * Generic structure to hold parallel port chipset info.
57 */
58struct ppc_data {
59
60	int ppc_unit;
61	int ppc_model;		/* chipset model if detected */
62	int ppc_type;		/* generic or smclike chipset type */
63
64	int ppc_mode;		/* chipset current mode */
65	int ppc_avm;		/* chipset available modes */
66	int ppc_dtm;		/* chipset detected modes */
67
68#define PPC_IRQ_NONE		0x0
69#define PPC_IRQ_nACK		0x1
70#define PPC_IRQ_DMA		0x2
71#define PPC_IRQ_FIFO		0x4
72#define PPC_IRQ_nFAULT		0x8
73	int ppc_irqstat;	/* remind irq settings */
74
75#define PPC_DMA_INIT		0x01
76#define PPC_DMA_STARTED		0x02
77#define PPC_DMA_COMPLETE	0x03
78#define PPC_DMA_INTERRUPTED	0x04
79#define PPC_DMA_ERROR		0x05
80	int ppc_dmastat;	/* dma state */
81	int ppc_dmachan;	/* dma channel */
82	int ppc_dmaflags;	/* dma transfer flags */
83	caddr_t ppc_dmaddr;	/* buffer address */
84	u_int ppc_dmacnt;	/* count of bytes sent with dma */
85	void (*ppc_dmadone)(struct ppc_data*);
86
87#define PPC_PWORD_MASK	0x30
88#define PPC_PWORD_16	0x00
89#define PPC_PWORD_8	0x10
90#define PPC_PWORD_32	0x20
91	char ppc_pword;		/* PWord size */
92	short ppc_fifo;		/* FIFO threshold */
93
94	short ppc_wthr;		/* writeIntrThresold */
95	short ppc_rthr;		/* readIntrThresold */
96
97	char *ppc_ptr;		/* microseq current pointer */
98	int ppc_accum;		/* microseq accumulator */
99	int ppc_base;		/* parallel port base address */
100	int ppc_epp;		/* EPP mode (1.7 or 1.9) */
101	int ppc_irq;
102
103	unsigned char ppc_flags;
104
105	device_t ppbus;		/* parallel port chipset corresponding ppbus */
106
107  	int rid_irq, rid_drq, rid_ioport;
108	struct resource *res_irq, *res_drq, *res_ioport;
109
110	void *intr_cookie;
111
112	int ppc_registered;	/* 1 if ppcintr() is the registered interrupt */
113};
114
115/*
116 * Parallel Port Chipset registers.
117 */
118#define PPC_SPP_DTR	0	/* SPP data register */
119#define PPC_ECP_A_FIFO	0	/* ECP Address fifo register */
120#define PPC_SPP_STR	1	/* SPP status register */
121#define PPC_SPP_CTR	2	/* SPP control register */
122#define PPC_EPP_ADDR	3	/* EPP address register (8 bit) */
123#define PPC_EPP_DATA	4	/* EPP data register (8, 16 or 32 bit) */
124#if defined(__i386__) && defined(PC98)
125#define PPC_1284_ENABLE	0x09	/* IEEE STD 1284 Enable register */
126#define PPC_ECP_D_FIFO	0x0c	/* ECP Data fifo register */
127#define PPC_ECP_CNFGA	0x0c	/* Configuration register A */
128#define PPC_ECP_CNFGB	0x0d	/* Configuration register B */
129#define PPC_ECP_ECR	0x0e	/* ECP extended control register */
130#else
131#define PPC_ECP_D_FIFO	0x400	/* ECP Data fifo register */
132#define PPC_ECP_CNFGA	0x400	/* Configuration register A */
133#define PPC_ECP_CNFGB	0x401	/* Configuration register B */
134#define PPC_ECP_ECR	0x402	/* ECP extended control register */
135#endif
136
137#define PPC_FIFO_EMPTY	0x1	/* ecr register - bit 0 */
138#define PPC_FIFO_FULL	0x2	/* ecr register - bit 1 */
139#define PPC_SERVICE_INTR 0x4	/* ecr register - bit 2 */
140#define PPC_ENABLE_DMA	0x8	/* ecr register - bit 3 */
141#define PPC_nFAULT_INTR	0x10	/* ecr register - bit 4 */
142#define PPC_ECR_STD	0x0
143#define PPC_ECR_PS2	0x20
144#define PPC_ECR_FIFO	0x40
145#define PPC_ECR_ECP	0x60
146#define PPC_ECR_EPP	0x80
147
148#define PPC_DISABLE_INTR	(PPC_SERVICE_INTR | PPC_nFAULT_INTR)
149#define PPC_ECR_RESET		(PPC_ECR_PS2 | PPC_DISABLE_INTR)
150
151#define r_dtr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_DTR))
152#define r_str(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_STR))
153#define r_ctr(ppc) (bus_read_1((ppc)->res_ioport, PPC_SPP_CTR))
154
155#define r_epp_A(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_ADDR))
156#define r_epp_D(ppc) (bus_read_1((ppc)->res_ioport, PPC_EPP_DATA))
157#define r_cnfgA(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGA))
158#define r_cnfgB(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_CNFGB))
159#define r_ecr(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_ECR))
160#define r_fifo(ppc) (bus_read_1((ppc)->res_ioport, PPC_ECP_D_FIFO))
161
162#define w_dtr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_DTR, byte))
163#define w_str(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_STR, byte))
164#define w_ctr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_SPP_CTR, byte))
165
166#define w_epp_A(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_ADDR, byte))
167#define w_epp_D(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_EPP_DATA, byte))
168#define w_ecr(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_ECR, byte))
169#define w_fifo(ppc, byte) (bus_write_1((ppc)->res_ioport, PPC_ECP_D_FIFO, byte))
170
171/*
172 * Register defines for the PC873xx parts
173 */
174
175#define PC873_FER	0x00
176#define PC873_PPENABLE	(1<<0)
177#define PC873_FAR	0x01
178#define PC873_PTR	0x02
179#define PC873_CFGLOCK	(1<<6)
180#define PC873_EPPRDIR	(1<<7)
181#define PC873_EXTENDED	(1<<7)
182#define PC873_LPTBIRQ7	(1<<3)
183#define PC873_FCR	0x03
184#define PC873_ZWS	(1<<5)
185#define PC873_ZWSPWDN	(1<<6)
186#define PC873_PCR	0x04
187#define PC873_EPPEN	(1<<0)
188#define PC873_EPP19	(1<<1)
189#define PC873_ECPEN	(1<<2)
190#define PC873_ECPCLK	(1<<3)
191#define PC873_PMC	0x06
192#define PC873_TUP	0x07
193#define PC873_SID	0x08
194#define PC873_PNP0	0x1b
195#define PC873_PNP1	0x1c
196#define PC873_LPTBA	0x19
197
198/*
199 * Register defines for the SMC FDC37C66xGT parts
200 */
201
202/* Init codes */
203#define SMC665_iCODE	0x55
204#define SMC666_iCODE	0x44
205
206/* Base configuration ports */
207#define SMC66x_CSR	0x3F0
208#define SMC666_CSR	0x370		/* hard-configured value for 666 */
209
210/* Bits */
211#define SMC_CR1_ADDR	0x3		/* bit 0 and 1 */
212#define SMC_CR1_MODE	(1<<3)		/* bit 3 */
213#define SMC_CR4_EMODE	0x3		/* bits 0 and 1 */
214#define SMC_CR4_EPPTYPE	(1<<6)		/* bit 6 */
215
216/* Extended modes */
217#define SMC_SPP		0x0		/* SPP */
218#define SMC_EPPSPP	0x1		/* EPP and SPP */
219#define SMC_ECP		0x2 		/* ECP */
220#define SMC_ECPEPP	0x3		/* ECP and EPP */
221
222/*
223 * Register defines for the SMC FDC37C935 parts
224 */
225
226/* Configuration ports */
227#define SMC935_CFG	0x370
228#define SMC935_IND	0x370
229#define SMC935_DAT	0x371
230
231/* Registers */
232#define SMC935_LOGDEV	0x7
233#define SMC935_ID	0x20
234#define SMC935_PORTHI	0x60
235#define SMC935_PORTLO	0x61
236#define SMC935_PPMODE	0xf0
237
238/* Parallel port modes */
239#define SMC935_SPP	0x38 + 0
240#define SMC935_EPP19SPP	0x38 + 1
241#define SMC935_ECP	0x38 + 2
242#define SMC935_ECPEPP19	0x38 + 3
243#define SMC935_CENT	0x38 + 4
244#define SMC935_EPP17SPP	0x38 + 5
245#define SMC935_UNUSED	0x38 + 6
246#define SMC935_ECPEPP17	0x38 + 7
247
248/*
249 * Register defines for the Winbond W83877F parts
250 */
251
252#define WINB_W83877F_ID		0xa
253#define WINB_W83877AF_ID	0xb
254
255/* Configuration bits */
256#define WINB_HEFERE	(1<<5)		/* CROC bit 5 */
257#define WINB_HEFRAS	(1<<0)		/* CR16 bit 0 */
258
259#define WINB_PNPCVS	(1<<2)		/* CR16 bit 2 */
260#define WINB_CHIPID	0xf		/* CR9 bits 0-3 */
261
262#define WINB_PRTMODS0	(1<<2)		/* CR0 bit 2 */
263#define WINB_PRTMODS1	(1<<3)		/* CR0 bit 3 */
264#define WINB_PRTMODS2	(1<<7)		/* CR9 bit 7 */
265
266/* W83877F modes: CR9/bit7 | CR0/bit3 | CR0/bit2 */
267#define WINB_W83757	0x0
268#define WINB_EXTFDC	0x4
269#define WINB_EXTADP	0x8
270#define WINB_EXT2FDD	0xc
271#define WINB_JOYSTICK	0x80
272
273#define WINB_PARALLEL	0x80
274#define WINB_EPP_SPP	0x4
275#define WINB_ECP	0x8
276#define WINB_ECP_EPP	0xc
277
278#endif
279