if_pcnreg.h revision 69067
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 * 33 * $FreeBSD: head/sys/pci/if_pcnreg.h 69067 2000-11-23 00:28:43Z wpaul $ 34 */ 35 36/* 37 * I/O map in 16-bit mode. To switch to 32-bit mode, 38 * you need to perform a 32-bit write to the RDP register 39 * (writing a 0 is recommended). 40 */ 41#define PCN_IO16_APROM00 0x00 42#define PCN_IO16_APROM01 0x02 43#define PCN_IO16_APROM02 0x04 44#define PCN_IO16_APROM03 0x06 45#define PCN_IO16_APROM04 0x08 46#define PCN_IO16_APROM05 0x0A 47#define PCN_IO16_APROM06 0x0C 48#define PCN_IO16_APROM07 0x0E 49#define PCN_IO16_RDP 0x10 50#define PCN_IO16_RAP 0x12 51#define PCN_IO16_RESET 0x14 52#define PCN_IO16_BDP 0x16 53 54/* 55 * I/O map in 32-bit mode. 56 */ 57#define PCN_IO32_APROM00 0x00 58#define PCN_IO32_APROM01 0x04 59#define PCN_IO32_APROM02 0x08 60#define PCN_IO32_APROM03 0x0C 61#define PCN_IO32_RDP 0x10 62#define PCN_IO32_RAP 0x14 63#define PCN_IO32_RESET 0x18 64#define PCN_IO32_BDP 0x1C 65 66/* 67 * CSR registers 68 */ 69#define PCN_CSR_CSR 0x00 70#define PCN_CSR_IAB0 0x01 71#define PCN_CSR_IAB1 0x02 72#define PCN_CSR_IMR 0x03 73#define PCN_CSR_TFEAT 0x04 74#define PCN_CSR_EXTCTL1 0x05 75#define PCN_CSR_DTBLLEN 0x06 76#define PCN_CSR_EXTCTL2 0x07 77#define PCN_CSR_MAR0 0x08 78#define PCN_CSR_MAR1 0x09 79#define PCN_CSR_MAR2 0x0A 80#define PCN_CSR_MAR3 0x0B 81#define PCN_CSR_PAR0 0x0C 82#define PCN_CSR_PAR1 0x0D 83#define PCN_CSR_PAR2 0x0E 84#define PCN_CSR_MODE 0x0F 85#define PCN_CSR_RXADDR0 0x18 86#define PCN_CSR_RXADDR1 0x19 87#define PCN_CSR_TXADDR0 0x1E 88#define PCN_CSR_TXADDR1 0x1F 89#define PCN_CSR_TXPOLL 0x2F 90#define PCN_CSR_RXPOLL 0x31 91#define PCN_CSR_RXRINGLEN 0x4C 92#define PCN_CSR_TXRINGLEN 0x4E 93#define PCN_CSR_DMACTL 0x50 94#define PCN_CSR_BUSTIMER 0x52 95#define PCN_CSR_MEMERRTIMEO 0x64 96#define PCN_CSR_ONNOWMISC 0x74 97#define PCN_CSR_ADVFEAT 0x7A 98#define PCN_CSR_MACCFG 0x7D 99#define PCN_CSR_CHIPID0 0x58 100#define PCN_CSR_CHIPID1 0x59 101 102/* 103 * Control and status register (CSR0) 104 */ 105#define PCN_CSR_INIT 0x0001 106#define PCN_CSR_START 0x0002 107#define PCN_CSR_STOP 0x0004 108#define PCN_CSR_TX 0x0008 109#define PCN_CSR_TXON 0x0010 110#define PCN_CSR_RXON 0x0020 111#define PCN_CSR_INTEN 0x0040 112#define PCN_CSR_INTR 0x0080 113#define PCN_CSR_IDONE 0x0100 114#define PCN_CSR_TINT 0x0200 115#define PCN_CSR_RINT 0x0400 116#define PCN_CSR_MERR 0x0800 117#define PCN_CSR_MISS 0x1000 118#define PCN_CSR_CERR 0x2000 119#define PCN_CSR_ERR 0x8000 120 121/* 122 * Interrupt masks and deferral control (CSR3) 123 */ 124#define PCN_IMR_BSWAP 0x0004 125#define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 126#define PCN_IMR_DXMT2PD 0x0010 127#define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 128#define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 129#define PCN_IMR_IDONE 0x0100 130#define PCN_IMR_TINT 0x0200 131#define PCN_IMR_RINT 0x0400 132#define PCN_IMR_MERR 0x0800 133#define PCN_IMR_MISS 0x1000 134 135/* 136 * Test and features control (CSR4) 137 */ 138#define PCN_TFEAT_TXSTRTMASK 0x0004 139#define PCN_TFEAT_TXSTRT 0x0008 140#define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 141#define PCN_TFEAT_RXCCOFLOW 0x0020 142#define PCN_TFEAT_UINT 0x0040 143#define PCN_TFEAT_UINTREQ 0x0080 144#define PCN_TFEAT_MISSOFLOWM 0x0100 145#define PCN_TFEAT_MISSOFLOW 0x0200 146#define PCN_TFEAT_STRIP_FCS 0x0400 147#define PCN_TFEAT_PAD_TX 0x0800 148#define PCN_TFEAT_TXDPOLL 0x1000 149#define PCN_TFEAT_DMAPLUS 0x4000 150 151/* 152 * Extended control and interrupt 1 (CSR5) 153 */ 154#define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 155#define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 156#define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 157#define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 158#define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 159#define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 160#define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 161#define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 162#define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 163#define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 164#define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 165#define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 166 167/* 168 * RX/TX descriptor len (CSR6) 169 */ 170#define PCN_DTBLLEN_RLEN 0x0F00 171#define PCN_DTBLLEN_TLEN 0xF000 172 173/* 174 * Extended control and interrupt 2 (CSR7) 175 */ 176#define PCN_EXTCTL2_MIIPDTINTE 0x0001 177#define PCN_EXTCTL2_MIIPDTINT 0x0002 178#define PCN_EXTCTL2_MCCIINTE 0x0004 179#define PCN_EXTCTL2_MCCIINT 0x0008 180#define PCN_EXTCTL2_MCCINTE 0x0010 181#define PCN_EXTCTL2_MCCINT 0x0020 182#define PCN_EXTCTL2_MAPINTE 0x0040 183#define PCN_EXTCTL2_MAPINT 0x0080 184#define PCN_EXTCTL2_MREINTE 0x0100 185#define PCN_EXTCTL2_MREINT 0x0200 186#define PCN_EXTCTL2_STINTE 0x0400 187#define PCN_EXTCTL2_STINT 0x0800 188#define PCN_EXTCTL2_RXDPOLL 0x1000 189#define PCN_EXTCTL2_RDMD 0x2000 190#define PCN_EXTCTL2_RXFRTG 0x4000 191#define PCN_EXTCTL2_FASTSPNDE 0x8000 192 193 194/* 195 * Mode (CSR15) 196 */ 197#define PCN_MODE_RXD 0x0001 /* RX disable */ 198#define PCN_MODE_TXD 0x0002 /* TX disable */ 199#define PCN_MODE_LOOP 0x0004 /* loopback enable */ 200#define PCN_MODE_TXCRCD 0x0008 201#define PCN_MODE_FORCECOLL 0x0010 202#define PCN_MODE_RETRYD 0x0020 203#define PCN_MODE_INTLOOP 0x0040 204#define PCN_MODE_PORTSEL 0x0180 205#define PCN_MODE_RXVPAD 0x2000 206#define PCN_MODE_RXNOBROAD 0x4000 207#define PCN_MODE_PROMISC 0x8000 208 209#define PCN_PORT_GPSI 0x0100 210#define PCN_PORT_MII 0x0180 211 212/* 213 * Chip ID values. 214 */ 215/* CSR88-89: Chip ID masks */ 216#define AMD_MASK 0x003 217#define PART_MASK 0xffff 218#define Am79C960 0x0003 219#define Am79C961 0x2260 220#define Am79C961A 0x2261 221#define Am79C965 0x2430 222#define Am79C970 0x0242 223#define Am79C970A 0x2621 224#define Am79C971 0x2623 225#define Am79C972 0x2624 226#define Am79C973 0x2625 227#define Am79C978 0x2626 228#define Am79C975 0x2627 229#define Am79C976 0x2628 230 231/* 232 * Advanced feature control (CSR122) 233 */ 234#define PCN_AFC_RXALIGN 0x0001 235 236/* 237 * BCR (bus control) registers 238 */ 239#define PCN_BCR_MISCCFG 0x02 240#define PCN_BCR_LED0 0x04 241#define PCN_BCR_LED1 0x05 242#define PCN_BCR_LED2 0x06 243#define PCN_BCR_LED3 0x07 244#define PCN_BCR_DUPLEX 0x09 245#define PCN_BCR_BUSCTL 0x12 246#define PCN_BCR_EECTL 0x13 247#define PCN_BCR_SSTYLE 0x14 248#define PCN_BCR_PCILAT 0x16 249#define PCN_BCR_PCISUBVENID 0x17 250#define PCN_BCR_PCISUBSYSID 0x18 251#define PCN_BCR_SRAMSIZE 0x19 252#define PCN_BCR_SRAMBOUND 0x1A 253#define PCN_BCR_SRAMCTL 0x1B 254#define PCN_BCR_MIICTL 0x20 255#define PCN_BCR_MIIADDR 0x21 256#define PCN_BCR_MIIDATA 0x22 257#define PCN_BCR_PCIVENID 0x23 258#define PCN_BCR_PCIPCAP 0x24 259#define PCN_BCR_DATA0 0x25 260#define PCN_BCR_DATA1 0x26 261#define PCN_BCR_DATA2 0x27 262#define PCN_BCR_DATA3 0x28 263#define PCN_BCR_DATA4 0x29 264#define PCN_BCR_DATA5 0x2A 265#define PCN_BCR_DATA6 0x2B 266#define PCN_BCR_DATA7 0x2C 267#define PCN_BCR_ONNOWPAT0 0x2D 268#define PCN_BCR_ONNOWPAT1 0x2E 269#define PCN_BCR_ONNOWPAT2 0x2F 270#define PCN_BCR_PHYSEL 0x31 271 272/* 273 * Full duplex control (BCR9) 274 */ 275#define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 276#define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 277 278/* 279 * Burst and bus control register (BCR18) 280 */ 281#define PCN_BUSCTL_BWRITE 0x0020 282#define PCN_BUSCTL_BREAD 0x0040 283#define PCN_BUSCTL_DWIO 0x0080 284#define PCN_BUSCTL_EXTREQ 0x0100 285#define PCN_BUSCTL_MEMCMD 0x0200 286#define PCN_BUSCTL_NOUFLOW 0x0800 287#define PCN_BUSCTL_ROMTMG 0xF000 288 289/* 290 * EEPROM control (BCR19) 291 */ 292#define PCN_EECTL_EDATA 0x0001 293#define PCN_EECTL_ECLK 0x0002 294#define PCN_EECTL_EECS 0x0004 295#define PCN_EECTL_EEN 0x0100 296#define PCN_EECTL_EEDET 0x2000 297#define PCN_EECTL_PREAD 0x4000 298#define PCN_EECTL_PVALID 0x8000 299 300/* 301 * Software style (BCR20) 302 */ 303#define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 304#define PCN_SSTYLE_SSIZE32 0x0100 305#define PCN_SSTYLE_SWSTYLE 0x00FF 306 307#define PCN_SWSTYLE_LANCE 0x0000 308#define PCN_SWSTYLE_PCNETPCI 0x0102 309#define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 310 311/* 312 * MII control and status (BCR32) 313 */ 314#define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 315#define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 316#define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 317#define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 318#define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 319#define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 320#define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 321#define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 322#define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 323#define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 324#define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 325 326/* 327 * MII address register (BCR33) 328 */ 329#define PCN_MIIADDR_REGAD 0x001F 330#define PCN_MIIADDR_PHYADD 0x03E0 331 332/* 333 * MII data register (BCR34) 334 */ 335#define PCN_MIIDATA_MIIMD 0xFFFF 336 337/* 338 * PHY selection (BCR49) (HomePNA NIC only) 339 */ 340#define PCN_PHYSEL_PHYSEL 0x0003 341#define PCN_PHYSEL_DEFAULT 0x0300 342#define PCN_PHYSEL_PCNET 0x8000 343 344#define PCN_PHY_10BT 0x0000 345#define PCN_PHY_HOMEPNA 0x0001 346#define PCN_PHY_EXTERNAL 0x0002 347 348struct pcn_rx_desc { 349 u_int16_t pcn_rxlen; 350 u_int16_t pcn_rsvd0; 351 u_int16_t pcn_bufsz; 352 u_int16_t pcn_rxstat; 353 u_int32_t pcn_rbaddr; 354 u_int32_t pcn_uspace; 355}; 356 357#define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 358#define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 359#define PCN_RXSTAT_STP 0x0200 /* start of packet */ 360#define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 361#define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 362#define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 363#define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 364#define PCN_RXSTAT_ERR 0x4000 /* error summary */ 365#define PCN_RXSTAT_OWN 0x8000 366 367#define PCN_RXLEN_MBO 0xF000 368#define PCN_RXLEN_BUFSZ 0x0FFF 369 370#define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 371 372struct pcn_tx_desc { 373 u_int32_t pcn_txstat; 374 u_int32_t pcn_txctl; 375 u_int32_t pcn_tbaddr; 376 u_int32_t pcn_uspace; 377}; 378 379#define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 380#define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 381#define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 382#define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 383#define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 384#define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 385#define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 386 387#define PCN_TXCTL_OWN 0x80000000 388#define PCN_TXCTL_ERR 0x40000000 /* error summary */ 389#define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 390#define PCN_TXCTL_MORE_LTINT 0x10000000 391#define PCN_TXCTL_ONE 0x08000000 392#define PCN_TXCTL_DEF 0x04000000 393#define PCN_TXCTL_STP 0x02000000 394#define PCN_TXCTL_ENP 0x01000000 395#define PCN_TXCTL_BPE 0x00800000 396#define PCN_TXCTL_MBO 0x0000F000 397#define PCN_TXCTL_BUFSZ 0x00000FFF 398 399#define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 400 401#define PCN_RX_LIST_CNT 64 402#define PCN_TX_LIST_CNT 256 403 404struct pcn_list_data { 405 struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 406 struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 407}; 408 409struct pcn_ring_data { 410 struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 411 struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 412 int pcn_rx_prod; 413 int pcn_tx_prod; 414 int pcn_tx_cons; 415 int pcn_tx_cnt; 416}; 417 418/* 419 * AMD PCI vendor ID. 420 */ 421#define PCN_VENDORID 0x1022 422 423/* 424 * AMD PCnet/PCI device IDs 425 */ 426#define PCN_DEVICEID_PCNET 0x2000 427#define PCN_DEVICEID_HOME 0x2001 428 429struct pcn_type { 430 u_int16_t pcn_vid; 431 u_int16_t pcn_did; 432 char *pcn_name; 433}; 434 435struct pcn_softc { 436 struct arpcom arpcom; /* interface info */ 437 bus_space_handle_t pcn_bhandle; 438 bus_space_tag_t pcn_btag; 439 struct resource *pcn_res; 440 struct resource *pcn_irq; 441 void *pcn_intrhand; 442 device_t pcn_miibus; 443 u_int8_t pcn_unit; 444 u_int8_t pcn_link; 445 u_int8_t pcn_phyaddr; 446 int pcn_if_flags; 447 int pcn_type; 448 struct pcn_list_data *pcn_ldata; 449 struct pcn_ring_data pcn_cdata; 450 struct callout_handle pcn_stat_ch; 451 struct mtx pcn_mtx; 452}; 453 454#define PCN_LOCK(_sc) mtx_enter(&(_sc)->pcn_mtx, MTX_DEF) 455#define PCN_UNLOCK(_sc) mtx_exit(&(_sc)->pcn_mtx, MTX_DEF) 456 457/* 458 * register space access macros 459 */ 460#define CSR_WRITE_4(sc, reg, val) \ 461 bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 462 463#define CSR_READ_4(sc, reg) \ 464 bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 465 466#define CSR_WRITE_2(sc, reg, val) \ 467 bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 468 469#define CSR_READ_2(sc, reg) \ 470 bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 471 472 473#define PCN_TIMEOUT 1000 474#define ETHER_ALIGN 2 475#define PCN_RXLEN 1536 476#define PCN_MIN_FRAMELEN 60 477#define PCN_INC(x, y) (x) = (x + 1) % y 478/* 479 * PCI low memory base and low I/O base register, and 480 * other PCI registers. 481 */ 482 483#define PCN_PCI_VENDOR_ID 0x00 484#define PCN_PCI_DEVICE_ID 0x02 485#define PCN_PCI_COMMAND 0x04 486#define PCN_PCI_STATUS 0x06 487#define PCN_PCI_REVID 0x08 488#define PCN_PCI_CLASSCODE 0x09 489#define PCN_PCI_CACHELEN 0x0C 490#define PCN_PCI_LATENCY_TIMER 0x0D 491#define PCN_PCI_HEADER_TYPE 0x0E 492#define PCN_PCI_LOIO 0x10 493#define PCN_PCI_LOMEM 0x14 494#define PCN_PCI_BIOSROM 0x30 495#define PCN_PCI_INTLINE 0x3C 496#define PCN_PCI_INTPIN 0x3D 497#define PCN_PCI_MINGNT 0x3E 498#define PCN_PCI_MINLAT 0x0F 499#define PCN_PCI_RESETOPT 0x48 500#define PCN_PCI_EEPROM_DATA 0x4C 501 502/* power management registers */ 503#define PCN_PCI_CAPID 0x50 /* 8 bits */ 504#define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 505#define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 506#define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 507 508#define PCN_PSTATE_MASK 0x0003 509#define PCN_PSTATE_D0 0x0000 510#define PCN_PSTATE_D1 0x0001 511#define PCN_PSTATE_D2 0x0002 512#define PCN_PSTATE_D3 0x0003 513#define PCN_PME_EN 0x0010 514#define PCN_PME_STATUS 0x8000 515 516#ifdef __alpha__ 517#undef vtophys 518#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 519#endif 520