if_pcnreg.h revision 148738
167754Smsmith/*- 267754Smsmith * Copyright (c) 2000 Berkeley Software Design, Inc. 367754Smsmith * Copyright (c) 1997, 1998, 1999, 2000 467754Smsmith * Bill Paul <wpaul@ee.columbia.edu>. All rights reserved. 585756Smsmith * 667754Smsmith * Redistribution and use in source and binary forms, with or without 767754Smsmith * modification, are permitted provided that the following conditions 867754Smsmith * are met: 967754Smsmith * 1. Redistributions of source code must retain the above copyright 1067754Smsmith * notice, this list of conditions and the following disclaimer. 1167754Smsmith * 2. Redistributions in binary form must reproduce the above copyright 1267754Smsmith * notice, this list of conditions and the following disclaimer in the 1371867Smsmith * documentation and/or other materials provided with the distribution. 1470243Smsmith * 3. All advertising materials mentioning features or use of this software 1567754Smsmith * must display the following acknowledgement: 1667754Smsmith * This product includes software developed by Bill Paul. 1767754Smsmith * 4. Neither the name of the author nor the names of any co-contributors 1867754Smsmith * may be used to endorse or promote products derived from this software 1967754Smsmith * without specific prior written permission. 2067754Smsmith * 2167754Smsmith * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 2267754Smsmith * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2367754Smsmith * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2467754Smsmith * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 2567754Smsmith * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2667754Smsmith * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2767754Smsmith * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2867754Smsmith * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2967754Smsmith * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 3067754Smsmith * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 3167754Smsmith * THE POSSIBILITY OF SUCH DAMAGE. 3267754Smsmith * 3367754Smsmith * $FreeBSD: head/sys/pci/if_pcnreg.h 148738 2005-08-05 16:03:16Z jhb $ 3467754Smsmith */ 3567754Smsmith 3667754Smsmith/* 3767754Smsmith * I/O map in 16-bit mode. To switch to 32-bit mode, 3867754Smsmith * you need to perform a 32-bit write to the RDP register 3967754Smsmith * (writing a 0 is recommended). 4067754Smsmith */ 4167754Smsmith#define PCN_IO16_APROM00 0x00 4267754Smsmith#define PCN_IO16_APROM01 0x02 4367754Smsmith#define PCN_IO16_APROM02 0x04 4467754Smsmith#define PCN_IO16_APROM03 0x06 4567754Smsmith#define PCN_IO16_APROM04 0x08 4667754Smsmith#define PCN_IO16_APROM05 0x0A 4767754Smsmith#define PCN_IO16_APROM06 0x0C 4867754Smsmith#define PCN_IO16_APROM07 0x0E 4967754Smsmith#define PCN_IO16_RDP 0x10 5067754Smsmith#define PCN_IO16_RAP 0x12 5167754Smsmith#define PCN_IO16_RESET 0x14 5267754Smsmith#define PCN_IO16_BDP 0x16 5367754Smsmith 5467754Smsmith/* 5567754Smsmith * I/O map in 32-bit mode. 5667754Smsmith */ 5767754Smsmith#define PCN_IO32_APROM00 0x00 5867754Smsmith#define PCN_IO32_APROM01 0x04 5967754Smsmith#define PCN_IO32_APROM02 0x08 6067754Smsmith#define PCN_IO32_APROM03 0x0C 6167754Smsmith#define PCN_IO32_RDP 0x10 6267754Smsmith#define PCN_IO32_RAP 0x14 6367754Smsmith#define PCN_IO32_RESET 0x18 6467754Smsmith#define PCN_IO32_BDP 0x1C 6567754Smsmith 6667754Smsmith/* 6767754Smsmith * CSR registers 6867754Smsmith */ 6967754Smsmith#define PCN_CSR_CSR 0x00 7067754Smsmith#define PCN_CSR_IAB0 0x01 7167754Smsmith#define PCN_CSR_IAB1 0x02 7267754Smsmith#define PCN_CSR_IMR 0x03 7367754Smsmith#define PCN_CSR_TFEAT 0x04 7467754Smsmith#define PCN_CSR_EXTCTL1 0x05 7567754Smsmith#define PCN_CSR_DTBLLEN 0x06 7667754Smsmith#define PCN_CSR_EXTCTL2 0x07 7767754Smsmith#define PCN_CSR_MAR0 0x08 7867754Smsmith#define PCN_CSR_MAR1 0x09 7967754Smsmith#define PCN_CSR_MAR2 0x0A 8067754Smsmith#define PCN_CSR_MAR3 0x0B 8167754Smsmith#define PCN_CSR_PAR0 0x0C 8267754Smsmith#define PCN_CSR_PAR1 0x0D 8367754Smsmith#define PCN_CSR_PAR2 0x0E 8467754Smsmith#define PCN_CSR_MODE 0x0F 8567754Smsmith#define PCN_CSR_RXADDR0 0x18 8667754Smsmith#define PCN_CSR_RXADDR1 0x19 8767754Smsmith#define PCN_CSR_TXADDR0 0x1E 8867754Smsmith#define PCN_CSR_TXADDR1 0x1F 8967754Smsmith#define PCN_CSR_TXPOLL 0x2F 9067754Smsmith#define PCN_CSR_RXPOLL 0x31 9167754Smsmith#define PCN_CSR_RXRINGLEN 0x4C 9267754Smsmith#define PCN_CSR_TXRINGLEN 0x4E 9367754Smsmith#define PCN_CSR_DMACTL 0x50 9467754Smsmith#define PCN_CSR_BUSTIMER 0x52 9567754Smsmith#define PCN_CSR_MEMERRTIMEO 0x64 9667754Smsmith#define PCN_CSR_ONNOWMISC 0x74 9767754Smsmith#define PCN_CSR_ADVFEAT 0x7A 9867754Smsmith#define PCN_CSR_MACCFG 0x7D 9967754Smsmith#define PCN_CSR_CHIPID0 0x58 10067754Smsmith#define PCN_CSR_CHIPID1 0x59 10167754Smsmith 10267754Smsmith/* 10367754Smsmith * Control and status register (CSR0) 10467754Smsmith */ 10567754Smsmith#define PCN_CSR_INIT 0x0001 10667754Smsmith#define PCN_CSR_START 0x0002 10767754Smsmith#define PCN_CSR_STOP 0x0004 10867754Smsmith#define PCN_CSR_TX 0x0008 10967754Smsmith#define PCN_CSR_TXON 0x0010 11067754Smsmith#define PCN_CSR_RXON 0x0020 11167754Smsmith#define PCN_CSR_INTEN 0x0040 11267754Smsmith#define PCN_CSR_INTR 0x0080 11367754Smsmith#define PCN_CSR_IDONE 0x0100 11467754Smsmith#define PCN_CSR_TINT 0x0200 11567754Smsmith#define PCN_CSR_RINT 0x0400 11667754Smsmith#define PCN_CSR_MERR 0x0800 11767754Smsmith#define PCN_CSR_MISS 0x1000 11867754Smsmith#define PCN_CSR_CERR 0x2000 11967754Smsmith#define PCN_CSR_ERR 0x8000 12067754Smsmith 12167754Smsmith/* 12267754Smsmith * Interrupt masks and deferral control (CSR3) 12367754Smsmith */ 12467754Smsmith#define PCN_IMR_BSWAP 0x0004 12567754Smsmith#define PCN_IMR_ENMBA 0x0008 /* enable modified backoff alg */ 12677424Smsmith#define PCN_IMR_DXMT2PD 0x0010 12767754Smsmith#define PCN_IMR_LAPPEN 0x0020 /* lookahead packet processing enb */ 12867754Smsmith#define PCN_IMR_DXSUFLO 0x0040 /* disable TX stop on underflow */ 12967754Smsmith#define PCN_IMR_IDONE 0x0100 13077424Smsmith#define PCN_IMR_TINT 0x0200 13167754Smsmith#define PCN_IMR_RINT 0x0400 13267754Smsmith#define PCN_IMR_MERR 0x0800 13367754Smsmith#define PCN_IMR_MISS 0x1000 13467754Smsmith 13567754Smsmith/* 13667754Smsmith * Test and features control (CSR4) 13767754Smsmith */ 13867754Smsmith#define PCN_TFEAT_TXSTRTMASK 0x0004 13967754Smsmith#define PCN_TFEAT_TXSTRT 0x0008 14077424Smsmith#define PCN_TFEAT_RXCCOFLOWM 0x0010 /* Rx collision counter oflow */ 14167754Smsmith#define PCN_TFEAT_RXCCOFLOW 0x0020 14267754Smsmith#define PCN_TFEAT_UINT 0x0040 14367754Smsmith#define PCN_TFEAT_UINTREQ 0x0080 14467754Smsmith#define PCN_TFEAT_MISSOFLOWM 0x0100 14567754Smsmith#define PCN_TFEAT_MISSOFLOW 0x0200 14667754Smsmith#define PCN_TFEAT_STRIP_FCS 0x0400 14767754Smsmith#define PCN_TFEAT_PAD_TX 0x0800 14867754Smsmith#define PCN_TFEAT_TXDPOLL 0x1000 14967754Smsmith#define PCN_TFEAT_DMAPLUS 0x4000 15067754Smsmith 15177424Smsmith/* 15267754Smsmith * Extended control and interrupt 1 (CSR5) 15367754Smsmith */ 15467754Smsmith#define PCN_EXTCTL1_SPND 0x0001 /* suspend */ 15567754Smsmith#define PCN_EXTCTL1_MPMODE 0x0002 /* magic packet mode */ 15667754Smsmith#define PCN_EXTCTL1_MPENB 0x0004 /* magic packet enable */ 15767754Smsmith#define PCN_EXTCTL1_MPINTEN 0x0008 /* magic packet interrupt enable */ 15867754Smsmith#define PCN_EXTCTL1_MPINT 0x0010 /* magic packet interrupt */ 15967754Smsmith#define PCN_EXTCTL1_MPPLBA 0x0020 /* magic packet phys. logical bcast */ 16067754Smsmith#define PCN_EXTCTL1_EXDEFEN 0x0040 /* excessive deferral interrupt enb. */ 16177424Smsmith#define PCN_EXTCTL1_EXDEF 0x0080 /* excessive deferral interrupt */ 16267754Smsmith#define PCN_EXTCTL1_SINTEN 0x0400 /* system interrupt enable */ 16367754Smsmith#define PCN_EXTCTL1_SINT 0x0800 /* system interrupt */ 16467754Smsmith#define PCN_EXTCTL1_LTINTEN 0x4000 /* last TX interrupt enb */ 16567754Smsmith#define PCN_EXTCTL1_TXOKINTD 0x8000 /* TX OK interrupt disable */ 16667754Smsmith 16767754Smsmith/* 16867754Smsmith * RX/TX descriptor len (CSR6) 16967754Smsmith */ 17067754Smsmith#define PCN_DTBLLEN_RLEN 0x0F00 17167754Smsmith#define PCN_DTBLLEN_TLEN 0xF000 17277424Smsmith 17367754Smsmith/* 17467754Smsmith * Extended control and interrupt 2 (CSR7) 17567754Smsmith */ 17667754Smsmith#define PCN_EXTCTL2_MIIPDTINTE 0x0001 17767754Smsmith#define PCN_EXTCTL2_MIIPDTINT 0x0002 17867754Smsmith#define PCN_EXTCTL2_MCCIINTE 0x0004 17967754Smsmith#define PCN_EXTCTL2_MCCIINT 0x0008 18077424Smsmith#define PCN_EXTCTL2_MCCINTE 0x0010 18167754Smsmith#define PCN_EXTCTL2_MCCINT 0x0020 18277424Smsmith#define PCN_EXTCTL2_MAPINTE 0x0040 18367754Smsmith#define PCN_EXTCTL2_MAPINT 0x0080 18477424Smsmith#define PCN_EXTCTL2_MREINTE 0x0100 18567754Smsmith#define PCN_EXTCTL2_MREINT 0x0200 18667754Smsmith#define PCN_EXTCTL2_STINTE 0x0400 18767754Smsmith#define PCN_EXTCTL2_STINT 0x0800 18867754Smsmith#define PCN_EXTCTL2_RXDPOLL 0x1000 18977424Smsmith#define PCN_EXTCTL2_RDMD 0x2000 19067754Smsmith#define PCN_EXTCTL2_RXFRTG 0x4000 19177424Smsmith#define PCN_EXTCTL2_FASTSPNDE 0x8000 19267754Smsmith 19367754Smsmith 19467754Smsmith/* 19577424Smsmith * Mode (CSR15) 19667754Smsmith */ 19767754Smsmith#define PCN_MODE_RXD 0x0001 /* RX disable */ 19867754Smsmith#define PCN_MODE_TXD 0x0002 /* TX disable */ 19977424Smsmith#define PCN_MODE_LOOP 0x0004 /* loopback enable */ 20067754Smsmith#define PCN_MODE_TXCRCD 0x0008 20167754Smsmith#define PCN_MODE_FORCECOLL 0x0010 20267754Smsmith#define PCN_MODE_RETRYD 0x0020 20367754Smsmith#define PCN_MODE_INTLOOP 0x0040 20467754Smsmith#define PCN_MODE_PORTSEL 0x0180 20567754Smsmith#define PCN_MODE_RXVPAD 0x2000 20667754Smsmith#define PCN_MODE_RXNOBROAD 0x4000 20767754Smsmith#define PCN_MODE_PROMISC 0x8000 20877424Smsmith 20967754Smsmith/* Settings for PCN_MODE_PORTSEL when ASEL (BCR2[1] is 0 */ 21067754Smsmith#define PCN_PORT_AUI 0x0000 21167754Smsmith#define PCN_PORT_10BASET 0x0080 21277424Smsmith#define PCN_PORT_GPSI 0x0100 21367754Smsmith#define PCN_PORT_MII 0x0180 21467754Smsmith 21567754Smsmith/* 21667754Smsmith * Chip ID values. 21777424Smsmith */ 21867754Smsmith/* CSR88-89: Chip ID masks */ 21967754Smsmith#define AMD_MASK 0x003 22067754Smsmith#define PART_MASK 0xffff 22167754Smsmith#define Am79C960 0x0003 22267754Smsmith#define Am79C961 0x2260 22367754Smsmith#define Am79C961A 0x2261 22467754Smsmith#define Am79C965 0x2430 22567754Smsmith#define Am79C970 0x0242 22667754Smsmith#define Am79C970A 0x2621 22767754Smsmith#define Am79C971 0x2623 22867754Smsmith#define Am79C972 0x2624 22977424Smsmith#define Am79C973 0x2625 23067754Smsmith#define Am79C978 0x2626 23177424Smsmith#define Am79C975 0x2627 23267754Smsmith#define Am79C976 0x2628 23383174Smsmith 23477424Smsmith/* 23567754Smsmith * Advanced feature control (CSR122) 23667754Smsmith */ 23767754Smsmith#define PCN_AFC_RXALIGN 0x0001 23883174Smsmith 23977424Smsmith/* 24067754Smsmith * BCR (bus control) registers 24177424Smsmith */ 24267754Smsmith#define PCN_BCR_MMRA 0x00 /* Master Mode Read Active */ 24367754Smsmith#define PCN_BCR_MMW 0x01 /* Master Mode Write Active */ 24477424Smsmith#define PCN_BCR_MISCCFG 0x02 24577424Smsmith#define PCN_BCR_LED0 0x04 24667754Smsmith#define PCN_BCR_LED1 0x05 24777424Smsmith#define PCN_BCR_LED2 0x06 24867754Smsmith#define PCN_BCR_LED3 0x07 24967754Smsmith#define PCN_BCR_DUPLEX 0x09 25067754Smsmith#define PCN_BCR_BUSCTL 0x12 25183174Smsmith#define PCN_BCR_EECTL 0x13 25283174Smsmith#define PCN_BCR_SSTYLE 0x14 25383174Smsmith#define PCN_BCR_PCILAT 0x16 25477424Smsmith#define PCN_BCR_PCISUBVENID 0x17 25577424Smsmith#define PCN_BCR_PCISUBSYSID 0x18 25677424Smsmith#define PCN_BCR_SRAMSIZE 0x19 25777424Smsmith#define PCN_BCR_SRAMBOUND 0x1A 25883174Smsmith#define PCN_BCR_SRAMCTL 0x1B 25967754Smsmith#define PCN_BCR_MIICTL 0x20 26067754Smsmith#define PCN_BCR_MIIADDR 0x21 26167754Smsmith#define PCN_BCR_MIIDATA 0x22 26267754Smsmith#define PCN_BCR_PCIVENID 0x23 26367754Smsmith#define PCN_BCR_PCIPCAP 0x24 26467754Smsmith#define PCN_BCR_DATA0 0x25 26567754Smsmith#define PCN_BCR_DATA1 0x26 26667754Smsmith#define PCN_BCR_DATA2 0x27 26767754Smsmith#define PCN_BCR_DATA3 0x28 26877424Smsmith#define PCN_BCR_DATA4 0x29 26967754Smsmith#define PCN_BCR_DATA5 0x2A 27077424Smsmith#define PCN_BCR_DATA6 0x2B 27177424Smsmith#define PCN_BCR_DATA7 0x2C 27267754Smsmith#define PCN_BCR_ONNOWPAT0 0x2D 27367754Smsmith#define PCN_BCR_ONNOWPAT1 0x2E 27469450Smsmith#define PCN_BCR_ONNOWPAT2 0x2F 27569450Smsmith#define PCN_BCR_PHYSEL 0x31 27669450Smsmith 27769450Smsmith/* 27869450Smsmith * Miscellaneous Configuration (BCR2) 27977424Smsmith */ 28069450Smsmith#define PCN_MISC_TMAULOOP 1<<14 /* T-MAU Loopback packet enable. */ 28177424Smsmith#define PCN_MISC_LEDPE 1<<12 /* LED Program Enable */ 28277424Smsmith#define PCN_MISC_APROMWE 1<<8 /* Address PROM Write Enable */ 28369450Smsmith#define PCN_MISC_INTLEVEL 1<<7 /* Interrupt level */ 28469450Smsmith#define PCN_MISC_EADISEL 1<<3 /* EADI Select */ 28569450Smsmith#define PCN_MISC_AWAKE 1<<2 /* Power saving mode select */ 28667754Smsmith#define PCN_MISC_ASEL 1<<1 /* Auto Select */ 28767754Smsmith#define PCN_MISC_XMAUSEL 1<<0 /* Reserved. */ 28867754Smsmith 28967754Smsmith/* 29067754Smsmith * Full duplex control (BCR9) 29167754Smsmith */ 29277424Smsmith#define PCN_DUPLEX_FDEN 0x0001 /* Full-duplex enable */ 29367754Smsmith#define PCN_DUPLEX_AUI 0x0002 /* AUI full-duplex */ 29477424Smsmith#define PCN_DUPLEX_FDRPAD 0x0004 /* Full-duplex runt pkt accept dis. */ 29577424Smsmith 29667754Smsmith/* 29777424Smsmith * Burst and bus control register (BCR18) 29869450Smsmith */ 29977424Smsmith#define PCN_BUSCTL_BWRITE 0x0020 30069450Smsmith#define PCN_BUSCTL_BREAD 0x0040 30167754Smsmith#define PCN_BUSCTL_DWIO 0x0080 30267754Smsmith#define PCN_BUSCTL_EXTREQ 0x0100 30367754Smsmith#define PCN_BUSCTL_MEMCMD 0x0200 30483174Smsmith#define PCN_BUSCTL_NOUFLOW 0x0800 30577424Smsmith#define PCN_BUSCTL_ROMTMG 0xF000 30667754Smsmith 30777424Smsmith/* 30867754Smsmith * EEPROM control (BCR19) 30977424Smsmith */ 31077424Smsmith#define PCN_EECTL_EDATA 0x0001 31167754Smsmith#define PCN_EECTL_ECLK 0x0002 31267754Smsmith#define PCN_EECTL_EECS 0x0004 31377424Smsmith#define PCN_EECTL_EEN 0x0100 31477424Smsmith#define PCN_EECTL_EEDET 0x2000 31577424Smsmith#define PCN_EECTL_PREAD 0x4000 31677424Smsmith#define PCN_EECTL_PVALID 0x8000 31777424Smsmith 31877424Smsmith/* 31977424Smsmith * Software style (BCR20) 32077424Smsmith */ 32183174Smsmith#define PCN_SSTYLE_APERREN 0x0400 /* advanced parity error checking */ 32277424Smsmith#define PCN_SSTYLE_SSIZE32 0x0100 32377424Smsmith#define PCN_SSTYLE_SWSTYLE 0x00FF 32477424Smsmith 32577424Smsmith#define PCN_SWSTYLE_LANCE 0x0000 32677424Smsmith#define PCN_SWSTYLE_PCNETPCI 0x0102 32777424Smsmith#define PCN_SWSTYLE_PCNETPCI_BURST 0x0103 32877424Smsmith 32977424Smsmith/* 33077424Smsmith * MII control and status (BCR32) 33177424Smsmith */ 33277424Smsmith#define PCN_MIICTL_MIILP 0x0002 /* MII internal loopback */ 33377424Smsmith#define PCN_MIICTL_XPHYSP 0x0008 /* external PHY speed */ 33477424Smsmith#define PCN_MIICTL_XPHYFD 0x0010 /* external PHY full duplex */ 33577424Smsmith#define PCN_MIICTL_XPHYANE 0x0020 /* external phy auto-neg enable */ 33677424Smsmith#define PCN_MIICTL_XPHYRST 0x0040 /* external PHY reset */ 33783174Smsmith#define PCN_MIICTL_DANAS 0x0080 /* disable auto-neg auto-setup */ 33877424Smsmith#define PCN_MIICTL_APDW 0x0700 /* auto-poll dwell time */ 33983174Smsmith#define PCN_MIICTL_APEP 0x0100 /* auto-poll external PHY */ 34067754Smsmith#define PCN_MIICTL_FMDC 0x3000 /* data clock speed */ 34167754Smsmith#define PCN_MIICTL_MIIPD 0x4000 /* PHY detect */ 34277424Smsmith#define PCN_MIICTL_ANTST 0x8000 /* Manufacturing test */ 34367754Smsmith 34467754Smsmith/* 34569450Smsmith * MII address register (BCR33) 34669450Smsmith */ 34769450Smsmith#define PCN_MIIADDR_REGAD 0x001F 34869450Smsmith#define PCN_MIIADDR_PHYADD 0x03E0 34969450Smsmith 35069450Smsmith/* 35169450Smsmith * MII data register (BCR34) 35269450Smsmith */ 35369450Smsmith#define PCN_MIIDATA_MIIMD 0xFFFF 35469450Smsmith 35569450Smsmith/* 35669450Smsmith * PHY selection (BCR49) (HomePNA NIC only) 35769450Smsmith */ 35869450Smsmith#define PCN_PHYSEL_PHYSEL 0x0003 35969450Smsmith#define PCN_PHYSEL_DEFAULT 0x0300 36069450Smsmith#define PCN_PHYSEL_PCNET 0x8000 36167754Smsmith 36269450Smsmith#define PCN_PHY_10BT 0x0000 36367754Smsmith#define PCN_PHY_HOMEPNA 0x0001 36467754Smsmith#define PCN_PHY_EXTERNAL 0x0002 36569450Smsmith 36669450Smsmithstruct pcn_rx_desc { 36769450Smsmith u_int16_t pcn_rxlen; 36869450Smsmith u_int16_t pcn_rsvd0; 36969450Smsmith u_int16_t pcn_bufsz; 37077424Smsmith u_int16_t pcn_rxstat; 37169450Smsmith u_int32_t pcn_rbaddr; 37277424Smsmith u_int32_t pcn_uspace; 37369450Smsmith}; 37469450Smsmith 37569450Smsmith#define PCN_RXSTAT_BPE 0x0080 /* bus parity error */ 37669450Smsmith#define PCN_RXSTAT_ENP 0x0100 /* end of packet */ 37769450Smsmith#define PCN_RXSTAT_STP 0x0200 /* start of packet */ 37869450Smsmith#define PCN_RXSTAT_BUFF 0x0400 /* buffer error */ 37969450Smsmith#define PCN_RXSTAT_CRC 0x0800 /* CRC error */ 38069450Smsmith#define PCN_RXSTAT_OFLOW 0x1000 /* rx overrun */ 38169450Smsmith#define PCN_RXSTAT_FRAM 0x2000 /* framing error */ 38269450Smsmith#define PCN_RXSTAT_ERR 0x4000 /* error summary */ 38369450Smsmith#define PCN_RXSTAT_OWN 0x8000 38469450Smsmith 38569450Smsmith#define PCN_RXLEN_MBO 0xF000 38669450Smsmith#define PCN_RXLEN_BUFSZ 0x0FFF 38769450Smsmith 38869450Smsmith#define PCN_OWN_RXDESC(x) (((x)->pcn_rxstat & PCN_RXSTAT_OWN) == 0) 38969450Smsmith 39069450Smsmithstruct pcn_tx_desc { 39169450Smsmith u_int32_t pcn_txstat; 39269450Smsmith u_int32_t pcn_txctl; 39369450Smsmith u_int32_t pcn_tbaddr; 39469450Smsmith u_int32_t pcn_uspace; 39567754Smsmith}; 39667754Smsmith 39767754Smsmith#define PCN_TXSTAT_TRC 0x0000000F /* transmit retries */ 39867754Smsmith#define PCN_TXSTAT_RTRY 0x04000000 /* retry */ 39967754Smsmith#define PCN_TXSTAT_LCAR 0x08000000 /* lost carrier */ 40067754Smsmith#define PCN_TXSTAT_LCOL 0x10000000 /* late collision */ 40167754Smsmith#define PCN_TXSTAT_EXDEF 0x20000000 /* excessive deferrals */ 40267754Smsmith#define PCN_TXSTAT_UFLOW 0x40000000 /* transmit underrun */ 40367754Smsmith#define PCN_TXSTAT_BUFF 0x80000000 /* buffer error */ 40467754Smsmith 40567754Smsmith#define PCN_TXCTL_OWN 0x80000000 40667754Smsmith#define PCN_TXCTL_ERR 0x40000000 /* error summary */ 40777424Smsmith#define PCN_TXCTL_ADD_FCS 0x20000000 /* add FCS to pkt */ 40867754Smsmith#define PCN_TXCTL_MORE_LTINT 0x10000000 40967754Smsmith#define PCN_TXCTL_ONE 0x08000000 41067754Smsmith#define PCN_TXCTL_DEF 0x04000000 41167754Smsmith#define PCN_TXCTL_STP 0x02000000 41267754Smsmith#define PCN_TXCTL_ENP 0x01000000 41367754Smsmith#define PCN_TXCTL_BPE 0x00800000 41477424Smsmith#define PCN_TXCTL_MBO 0x0000F000 41567754Smsmith#define PCN_TXCTL_BUFSZ 0x00000FFF 41667754Smsmith 41767754Smsmith#define PCN_OWN_TXDESC(x) (((x)->pcn_txctl & PCN_TXCTL_OWN) == 0) 41867754Smsmith 41967754Smsmith#define PCN_RX_LIST_CNT 64 42067754Smsmith#define PCN_TX_LIST_CNT 256 42167754Smsmith 42267754Smsmithstruct pcn_list_data { 42367754Smsmith struct pcn_rx_desc pcn_rx_list[PCN_RX_LIST_CNT]; 42467754Smsmith struct pcn_tx_desc pcn_tx_list[PCN_TX_LIST_CNT]; 42567754Smsmith}; 42667754Smsmith 42767754Smsmithstruct pcn_ring_data { 42867754Smsmith struct mbuf *pcn_rx_chain[PCN_RX_LIST_CNT]; 42967754Smsmith struct mbuf *pcn_tx_chain[PCN_TX_LIST_CNT]; 43067754Smsmith int pcn_rx_prod; 43167754Smsmith int pcn_tx_prod; 43267754Smsmith int pcn_tx_cons; 43367754Smsmith int pcn_tx_cnt; 43467754Smsmith}; 43567754Smsmith 43677424Smsmith/* 43767754Smsmith * AMD PCI vendor ID. 43867754Smsmith */ 43967754Smsmith#define PCN_VENDORID 0x1022 44077424Smsmith 44167754Smsmith/* 44282367Smsmith * AMD PCnet/PCI device IDs 44369450Smsmith */ 44467754Smsmith#define PCN_DEVICEID_PCNET 0x2000 44567754Smsmith#define PCN_DEVICEID_HOME 0x2001 44667754Smsmith 44782367Smsmithstruct pcn_type { 44867754Smsmith u_int16_t pcn_vid; 44967754Smsmith u_int16_t pcn_did; 45067754Smsmith char *pcn_name; 45167754Smsmith}; 45267754Smsmith 45367754Smsmithstruct pcn_softc { 45467754Smsmith struct ifnet *pcn_ifp; 45577424Smsmith bus_space_handle_t pcn_bhandle; 45667754Smsmith bus_space_tag_t pcn_btag; 45777424Smsmith struct resource *pcn_res; 45877424Smsmith struct resource *pcn_irq; 45977424Smsmith void *pcn_intrhand; 46077424Smsmith device_t pcn_miibus; 46177424Smsmith u_int8_t pcn_unit; 46277424Smsmith u_int8_t pcn_link; 46377424Smsmith u_int8_t pcn_phyaddr; 46477424Smsmith int pcn_if_flags; 46577424Smsmith int pcn_type; 46677424Smsmith struct pcn_list_data *pcn_ldata; 46777424Smsmith struct pcn_ring_data pcn_cdata; 46877424Smsmith struct callout pcn_stat_callout; 46977424Smsmith struct mtx pcn_mtx; 47077424Smsmith}; 47177424Smsmith 47277424Smsmith#define PCN_LOCK(_sc) mtx_lock(&(_sc)->pcn_mtx) 47377424Smsmith#define PCN_UNLOCK(_sc) mtx_unlock(&(_sc)->pcn_mtx) 47477424Smsmith#define PCN_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->pcn_mtx, MA_OWNED) 47577424Smsmith 47677424Smsmith/* 47777424Smsmith * register space access macros 47877424Smsmith */ 47977424Smsmith#define CSR_WRITE_4(sc, reg, val) \ 48077424Smsmith bus_space_write_4(sc->pcn_btag, sc->pcn_bhandle, reg, val) 48177424Smsmith 48277424Smsmith#define CSR_READ_4(sc, reg) \ 48377424Smsmith bus_space_read_4(sc->pcn_btag, sc->pcn_bhandle, reg) 48477424Smsmith 48577424Smsmith#define CSR_WRITE_2(sc, reg, val) \ 48677424Smsmith bus_space_write_2(sc->pcn_btag, sc->pcn_bhandle, reg, val) 48777424Smsmith 48877424Smsmith#define CSR_READ_2(sc, reg) \ 48977424Smsmith bus_space_read_2(sc->pcn_btag, sc->pcn_bhandle, reg) 49077424Smsmith 49177424Smsmith 49277424Smsmith#define PCN_TIMEOUT 1000 49377424Smsmith#define ETHER_ALIGN 2 49477424Smsmith#define PCN_RXLEN 1536 49577424Smsmith#define PCN_MIN_FRAMELEN 60 49677424Smsmith#define PCN_INC(x, y) (x) = (x + 1) % y 49777424Smsmith/* 49880062Smsmith * PCI low memory base and low I/O base register, and 49977424Smsmith * other PCI registers. 50077424Smsmith */ 50177424Smsmith 50277424Smsmith#define PCN_PCI_VENDOR_ID 0x00 50377424Smsmith#define PCN_PCI_DEVICE_ID 0x02 50477424Smsmith#define PCN_PCI_COMMAND 0x04 50577424Smsmith#define PCN_PCI_STATUS 0x06 50677424Smsmith#define PCN_PCI_REVID 0x08 50777424Smsmith#define PCN_PCI_CLASSCODE 0x09 50877424Smsmith#define PCN_PCI_CACHELEN 0x0C 50977424Smsmith#define PCN_PCI_LATENCY_TIMER 0x0D 51080062Smsmith#define PCN_PCI_HEADER_TYPE 0x0E 51177424Smsmith#define PCN_PCI_LOIO 0x10 51277424Smsmith#define PCN_PCI_LOMEM 0x14 51377424Smsmith#define PCN_PCI_BIOSROM 0x30 51477424Smsmith#define PCN_PCI_INTLINE 0x3C 51577424Smsmith#define PCN_PCI_INTPIN 0x3D 51677424Smsmith#define PCN_PCI_MINGNT 0x3E 51777424Smsmith#define PCN_PCI_MINLAT 0x3F 51877424Smsmith#define PCN_PCI_RESETOPT 0x48 51977424Smsmith#define PCN_PCI_EEPROM_DATA 0x4C 52077424Smsmith 52167754Smsmith/* power management registers */ 52267754Smsmith#define PCN_PCI_CAPID 0x50 /* 8 bits */ 52367754Smsmith#define PCN_PCI_NEXTPTR 0x51 /* 8 bits */ 52467754Smsmith#define PCN_PCI_PWRMGMTCAP 0x52 /* 16 bits */ 52577424Smsmith#define PCN_PCI_PWRMGMTCTRL 0x54 /* 16 bits */ 52667754Smsmith 52767754Smsmith#define PCN_PSTATE_MASK 0x0003 52867754Smsmith#define PCN_PSTATE_D0 0x0000 52967754Smsmith#define PCN_PSTATE_D1 0x0001 53067754Smsmith#define PCN_PSTATE_D2 0x0002 53167754Smsmith#define PCN_PSTATE_D3 0x0003 53277424Smsmith#define PCN_PME_EN 0x0010 53367754Smsmith#define PCN_PME_STATUS 0x8000 53467754Smsmith 53567754Smsmith#ifdef __alpha__ 53667754Smsmith#undef vtophys 53767754Smsmith#define vtophys(va) alpha_XXX_dmamap((vm_offset_t)va) 53867754Smsmith#endif 53967754Smsmith