if_pcn.c revision 164712
1/*- 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 164712 2006-11-28 01:33:17Z marius $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69#include <net/if_types.h> 70 71#include <net/bpf.h> 72 73#include <vm/vm.h> /* for vtophys */ 74#include <vm/pmap.h> /* for vtophys */ 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <dev/pci/pcireg.h> 84#include <dev/pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "device miibus" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static const struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static const struct pcn_chipid { 107 u_int32_t id; 108 const char *name; 109} pcn_chipid[] = { 110 { Am79C971, "Am79C971" }, 111 { Am79C972, "Am79C972" }, 112 { Am79C973, "Am79C973" }, 113 { Am79C978, "Am79C978" }, 114 { Am79C975, "Am79C975" }, 115 { Am79C976, "Am79C976" }, 116 { 0, NULL }, 117}; 118 119static const char *pcn_chipid_name(u_int32_t); 120static u_int32_t pcn_chip_id(device_t); 121static const struct pcn_type *pcn_match(u_int16_t, u_int16_t); 122 123static u_int32_t pcn_csr_read(struct pcn_softc *, int); 124static u_int16_t pcn_csr_read16(struct pcn_softc *, int); 125static u_int16_t pcn_bcr_read16(struct pcn_softc *, int); 126static void pcn_csr_write(struct pcn_softc *, int, int); 127static u_int32_t pcn_bcr_read(struct pcn_softc *, int); 128static void pcn_bcr_write(struct pcn_softc *, int, int); 129 130static int pcn_probe(device_t); 131static int pcn_attach(device_t); 132static int pcn_detach(device_t); 133 134static int pcn_newbuf(struct pcn_softc *, int, struct mbuf *); 135static int pcn_encap(struct pcn_softc *, struct mbuf *, u_int32_t *); 136static void pcn_rxeof(struct pcn_softc *); 137static void pcn_txeof(struct pcn_softc *); 138static void pcn_intr(void *); 139static void pcn_tick(void *); 140static void pcn_start(struct ifnet *); 141static void pcn_start_locked(struct ifnet *); 142static int pcn_ioctl(struct ifnet *, u_long, caddr_t); 143static void pcn_init(void *); 144static void pcn_init_locked(struct pcn_softc *); 145static void pcn_stop(struct pcn_softc *); 146static void pcn_watchdog(struct ifnet *); 147static void pcn_shutdown(device_t); 148static int pcn_ifmedia_upd(struct ifnet *); 149static void pcn_ifmedia_sts(struct ifnet *, struct ifmediareq *); 150 151static int pcn_miibus_readreg(device_t, int, int); 152static int pcn_miibus_writereg(device_t, int, int, int); 153static void pcn_miibus_statchg(device_t); 154 155static void pcn_setfilt(struct ifnet *); 156static void pcn_setmulti(struct pcn_softc *); 157static void pcn_reset(struct pcn_softc *); 158static int pcn_list_rx_init(struct pcn_softc *); 159static int pcn_list_tx_init(struct pcn_softc *); 160 161#ifdef PCN_USEIOSPACE 162#define PCN_RES SYS_RES_IOPORT 163#define PCN_RID PCN_PCI_LOIO 164#else 165#define PCN_RES SYS_RES_MEMORY 166#define PCN_RID PCN_PCI_LOMEM 167#endif 168 169static device_method_t pcn_methods[] = { 170 /* Device interface */ 171 DEVMETHOD(device_probe, pcn_probe), 172 DEVMETHOD(device_attach, pcn_attach), 173 DEVMETHOD(device_detach, pcn_detach), 174 DEVMETHOD(device_shutdown, pcn_shutdown), 175 176 /* bus interface */ 177 DEVMETHOD(bus_print_child, bus_generic_print_child), 178 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 179 180 /* MII interface */ 181 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 182 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 183 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 184 185 { 0, 0 } 186}; 187 188static driver_t pcn_driver = { 189 "pcn", 190 pcn_methods, 191 sizeof(struct pcn_softc) 192}; 193 194static devclass_t pcn_devclass; 195 196DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 197DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 198 199#define PCN_CSR_SETBIT(sc, reg, x) \ 200 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 201 202#define PCN_CSR_CLRBIT(sc, reg, x) \ 203 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 204 205#define PCN_BCR_SETBIT(sc, reg, x) \ 206 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 207 208#define PCN_BCR_CLRBIT(sc, reg, x) \ 209 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 210 211static u_int32_t 212pcn_csr_read(sc, reg) 213 struct pcn_softc *sc; 214 int reg; 215{ 216 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 217 return(CSR_READ_4(sc, PCN_IO32_RDP)); 218} 219 220static u_int16_t 221pcn_csr_read16(sc, reg) 222 struct pcn_softc *sc; 223 int reg; 224{ 225 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 226 return(CSR_READ_2(sc, PCN_IO16_RDP)); 227} 228 229static void 230pcn_csr_write(sc, reg, val) 231 struct pcn_softc *sc; 232 int reg; 233 int val; 234{ 235 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 236 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 237 return; 238} 239 240static u_int32_t 241pcn_bcr_read(sc, reg) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 return(CSR_READ_4(sc, PCN_IO32_BDP)); 247} 248 249static u_int16_t 250pcn_bcr_read16(sc, reg) 251 struct pcn_softc *sc; 252 int reg; 253{ 254 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 255 return(CSR_READ_2(sc, PCN_IO16_BDP)); 256} 257 258static void 259pcn_bcr_write(sc, reg, val) 260 struct pcn_softc *sc; 261 int reg; 262 int val; 263{ 264 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 265 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 266 return; 267} 268 269static int 270pcn_miibus_readreg(dev, phy, reg) 271 device_t dev; 272 int phy, reg; 273{ 274 struct pcn_softc *sc; 275 int val; 276 277 sc = device_get_softc(dev); 278 279 /* 280 * At least Am79C971 with DP83840A wedge when isolating the 281 * external PHY so we can't allow multiple external PHYs. 282 * This needs refinement as there are some Allied Telesyn 283 * card models which use multiple external PHYs. 284 * For internal PHYs it doesn't really matter whether we can 285 * isolate the remaining internal and the external ones in 286 * the PHY drivers as the internal PHYs have to be enabled 287 * individually in PCN_BCR_PHYSEL, PCN_CSR_MODE, etc. 288 */ 289 if (phy != PCN_PHYAD_10BT && sc->pcn_extphyaddr != -1 && 290 phy != sc->pcn_extphyaddr) 291 return(0); 292 293 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 294 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 295 if (val == 0xFFFF) 296 return(0); 297 298 if (phy != PCN_PHYAD_10BT && sc->pcn_extphyaddr != -1) 299 sc->pcn_extphyaddr = phy; 300 301 return(val); 302} 303 304static int 305pcn_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct pcn_softc *sc; 310 311 sc = device_get_softc(dev); 312 313 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 314 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 315 316 return(0); 317} 318 319static void 320pcn_miibus_statchg(dev) 321 device_t dev; 322{ 323 struct pcn_softc *sc; 324 struct mii_data *mii; 325 326 sc = device_get_softc(dev); 327 mii = device_get_softc(sc->pcn_miibus); 328 329 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 330 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 331 } else { 332 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 333 } 334 335 return; 336} 337 338static void 339pcn_setmulti(sc) 340 struct pcn_softc *sc; 341{ 342 struct ifnet *ifp; 343 struct ifmultiaddr *ifma; 344 u_int32_t h, i; 345 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 346 347 ifp = sc->pcn_ifp; 348 349 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 350 351 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 352 for (i = 0; i < 4; i++) 353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 354 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 355 return; 356 } 357 358 /* first, zot all the existing hash bits */ 359 for (i = 0; i < 4; i++) 360 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 361 362 /* now program new ones */ 363 IF_ADDR_LOCK(ifp); 364 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 365 if (ifma->ifma_addr->sa_family != AF_LINK) 366 continue; 367 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 368 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 369 hashes[h >> 4] |= 1 << (h & 0xF); 370 } 371 IF_ADDR_UNLOCK(ifp); 372 373 for (i = 0; i < 4; i++) 374 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 375 376 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 377 378 return; 379} 380 381static void 382pcn_reset(sc) 383 struct pcn_softc *sc; 384{ 385 /* 386 * Issue a reset by reading from the RESET register. 387 * Note that we don't know if the chip is operating in 388 * 16-bit or 32-bit mode at this point, so we attempt 389 * to reset the chip both ways. If one fails, the other 390 * will succeed. 391 */ 392 CSR_READ_2(sc, PCN_IO16_RESET); 393 CSR_READ_4(sc, PCN_IO32_RESET); 394 395 /* Wait a little while for the chip to get its brains in order. */ 396 DELAY(1000); 397 398 /* Select 32-bit (DWIO) mode */ 399 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 400 401 /* Select software style 3. */ 402 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 403 404 return; 405} 406 407static const char * 408pcn_chipid_name(u_int32_t id) 409{ 410 const struct pcn_chipid *p; 411 412 p = pcn_chipid; 413 while (p->name) { 414 if (id == p->id) 415 return (p->name); 416 p++; 417 } 418 return ("Unknown"); 419} 420 421static u_int32_t 422pcn_chip_id(device_t dev) 423{ 424 struct pcn_softc *sc; 425 u_int32_t chip_id; 426 427 sc = device_get_softc(dev); 428 /* 429 * Note: we can *NOT* put the chip into 430 * 32-bit mode yet. The le(4) driver will only 431 * work in 16-bit mode, and once the chip 432 * goes into 32-bit mode, the only way to 433 * get it out again is with a hardware reset. 434 * So if pcn_probe() is called before the 435 * le(4) driver's probe routine, the chip will 436 * be locked into 32-bit operation and the 437 * le(4) driver will be unable to attach to it. 438 * Note II: if the chip happens to already 439 * be in 32-bit mode, we still need to check 440 * the chip ID, but first we have to detect 441 * 32-bit mode using only 16-bit operations. 442 * The safest way to do this is to read the 443 * PCI subsystem ID from BCR23/24 and compare 444 * that with the value read from PCI config 445 * space. 446 */ 447 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 448 chip_id <<= 16; 449 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 450 /* 451 * Note III: the test for 0x10001000 is a hack to 452 * pacify VMware, who's pseudo-PCnet interface is 453 * broken. Reading the subsystem register from PCI 454 * config space yields 0x00000000 while reading the 455 * same value from I/O space yields 0x10001000. It's 456 * not supposed to be that way. 457 */ 458 if (chip_id == pci_read_config(dev, 459 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 460 /* We're in 16-bit mode. */ 461 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 462 chip_id <<= 16; 463 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 464 } else { 465 /* We're in 32-bit mode. */ 466 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 467 chip_id <<= 16; 468 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 469 } 470 471 return (chip_id); 472} 473 474static const struct pcn_type * 475pcn_match(u_int16_t vid, u_int16_t did) 476{ 477 const struct pcn_type *t; 478 479 t = pcn_devs; 480 while (t->pcn_name != NULL) { 481 if ((vid == t->pcn_vid) && (did == t->pcn_did)) 482 return (t); 483 t++; 484 } 485 return (NULL); 486} 487 488/* 489 * Probe for an AMD chip. Check the PCI vendor and device 490 * IDs against our list and return a device name if we find a match. 491 */ 492static int 493pcn_probe(dev) 494 device_t dev; 495{ 496 const struct pcn_type *t; 497 struct pcn_softc *sc; 498 int rid; 499 u_int32_t chip_id; 500 501 t = pcn_match(pci_get_vendor(dev), pci_get_device(dev)); 502 if (t == NULL) 503 return (ENXIO); 504 sc = device_get_softc(dev); 505 506 /* 507 * Temporarily map the I/O space so we can read the chip ID register. 508 */ 509 rid = PCN_RID; 510 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 511 if (sc->pcn_res == NULL) { 512 device_printf(dev, "couldn't map ports/memory\n"); 513 return(ENXIO); 514 } 515 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 516 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 517 518 chip_id = pcn_chip_id(dev); 519 520 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 521 522 switch((chip_id >> 12) & PART_MASK) { 523 case Am79C971: 524 case Am79C972: 525 case Am79C973: 526 case Am79C975: 527 case Am79C976: 528 case Am79C978: 529 break; 530 default: 531 return(ENXIO); 532 } 533 device_set_desc(dev, t->pcn_name); 534 return(BUS_PROBE_DEFAULT); 535} 536 537/* 538 * Attach the interface. Allocate softc structures, do ifmedia 539 * setup and ethernet/BPF attach. 540 */ 541static int 542pcn_attach(dev) 543 device_t dev; 544{ 545 u_int32_t eaddr[2]; 546 struct pcn_softc *sc; 547 struct mii_data *mii; 548 struct mii_softc *miisc; 549 struct ifnet *ifp; 550 int error = 0, rid; 551 552 sc = device_get_softc(dev); 553 554 /* Initialize our mutex. */ 555 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 556 MTX_DEF); 557 /* 558 * Map control/status registers. 559 */ 560 pci_enable_busmaster(dev); 561 562 /* Retrieve the chip ID */ 563 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 564 device_printf(dev, "Chip ID %04x (%s)\n", 565 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 566 567 rid = PCN_RID; 568 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 569 570 if (sc->pcn_res == NULL) { 571 device_printf(dev, "couldn't map ports/memory\n"); 572 error = ENXIO; 573 goto fail; 574 } 575 576 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 577 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 578 579 /* Allocate interrupt */ 580 rid = 0; 581 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 582 RF_SHAREABLE | RF_ACTIVE); 583 584 if (sc->pcn_irq == NULL) { 585 device_printf(dev, "couldn't map interrupt\n"); 586 error = ENXIO; 587 goto fail; 588 } 589 590 /* Reset the adapter. */ 591 pcn_reset(sc); 592 593 /* 594 * Get station address from the EEPROM. 595 */ 596 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 597 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 598 599 callout_init_mtx(&sc->pcn_stat_callout, &sc->pcn_mtx, 0); 600 601 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 602 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 603 604 if (sc->pcn_ldata == NULL) { 605 device_printf(dev, "no memory for list buffers!\n"); 606 error = ENXIO; 607 goto fail; 608 } 609 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 610 611 ifp = sc->pcn_ifp = if_alloc(IFT_ETHER); 612 if (ifp == NULL) { 613 device_printf(dev, "can not if_alloc()\n"); 614 error = ENOSPC; 615 goto fail; 616 } 617 ifp->if_softc = sc; 618 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 619 ifp->if_mtu = ETHERMTU; 620 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 621 ifp->if_ioctl = pcn_ioctl; 622 ifp->if_start = pcn_start; 623 ifp->if_watchdog = pcn_watchdog; 624 ifp->if_init = pcn_init; 625 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 626 627 /* 628 * Do MII setup. 629 */ 630 sc->pcn_extphyaddr = -1; 631 if (mii_phy_probe(dev, &sc->pcn_miibus, 632 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 633 device_printf(dev, "MII without any PHY!\n"); 634 error = ENXIO; 635 goto fail; 636 } 637 /* 638 * Record the media instances of internal PHYs, which map the 639 * built-in interfaces to the MII, so we can set the active 640 * PHY/port based on the currently selected media. 641 */ 642 sc->pcn_inst_10bt = -1; 643 mii = device_get_softc(sc->pcn_miibus); 644 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) { 645 switch (miisc->mii_phy) { 646 case PCN_PHYAD_10BT: 647 sc->pcn_inst_10bt = miisc->mii_inst; 648 break; 649 /* 650 * XXX deal with the Am79C97{3,5} internal 100baseT 651 * and the Am79C978 internal HomePNA PHYs. 652 */ 653 } 654 } 655 656 /* 657 * Call MI attach routine. 658 */ 659 ether_ifattach(ifp, (u_int8_t *) eaddr); 660 661 /* Hook interrupt last to avoid having to lock softc */ 662 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET | INTR_MPSAFE, 663 pcn_intr, sc, &sc->pcn_intrhand); 664 665 if (error) { 666 device_printf(dev, "couldn't set up irq\n"); 667 ether_ifdetach(ifp); 668 goto fail; 669 } 670 671fail: 672 if (error) 673 pcn_detach(dev); 674 675 return(error); 676} 677 678/* 679 * Shutdown hardware and free up resources. This can be called any 680 * time after the mutex has been initialized. It is called in both 681 * the error case in attach and the normal detach case so it needs 682 * to be careful about only freeing resources that have actually been 683 * allocated. 684 */ 685static int 686pcn_detach(dev) 687 device_t dev; 688{ 689 struct pcn_softc *sc; 690 struct ifnet *ifp; 691 692 sc = device_get_softc(dev); 693 ifp = sc->pcn_ifp; 694 695 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 696 697 /* These should only be active if attach succeeded */ 698 if (device_is_attached(dev)) { 699 PCN_LOCK(sc); 700 pcn_reset(sc); 701 pcn_stop(sc); 702 PCN_UNLOCK(sc); 703 callout_drain(&sc->pcn_stat_callout); 704 ether_ifdetach(ifp); 705 } 706 if (sc->pcn_miibus) 707 device_delete_child(dev, sc->pcn_miibus); 708 bus_generic_detach(dev); 709 710 if (sc->pcn_intrhand) 711 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 712 if (sc->pcn_irq) 713 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 714 if (sc->pcn_res) 715 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 716 717 if (ifp) 718 if_free(ifp); 719 720 if (sc->pcn_ldata) { 721 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 722 M_DEVBUF); 723 } 724 725 mtx_destroy(&sc->pcn_mtx); 726 727 return(0); 728} 729 730/* 731 * Initialize the transmit descriptors. 732 */ 733static int 734pcn_list_tx_init(sc) 735 struct pcn_softc *sc; 736{ 737 struct pcn_list_data *ld; 738 struct pcn_ring_data *cd; 739 int i; 740 741 cd = &sc->pcn_cdata; 742 ld = sc->pcn_ldata; 743 744 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 745 cd->pcn_tx_chain[i] = NULL; 746 ld->pcn_tx_list[i].pcn_tbaddr = 0; 747 ld->pcn_tx_list[i].pcn_txctl = 0; 748 ld->pcn_tx_list[i].pcn_txstat = 0; 749 } 750 751 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 752 753 return(0); 754} 755 756 757/* 758 * Initialize the RX descriptors and allocate mbufs for them. 759 */ 760static int 761pcn_list_rx_init(sc) 762 struct pcn_softc *sc; 763{ 764 struct pcn_ring_data *cd; 765 int i; 766 767 cd = &sc->pcn_cdata; 768 769 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 770 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 771 return(ENOBUFS); 772 } 773 774 cd->pcn_rx_prod = 0; 775 776 return(0); 777} 778 779/* 780 * Initialize an RX descriptor and attach an MBUF cluster. 781 */ 782static int 783pcn_newbuf(sc, idx, m) 784 struct pcn_softc *sc; 785 int idx; 786 struct mbuf *m; 787{ 788 struct mbuf *m_new = NULL; 789 struct pcn_rx_desc *c; 790 791 c = &sc->pcn_ldata->pcn_rx_list[idx]; 792 793 if (m == NULL) { 794 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 795 if (m_new == NULL) 796 return(ENOBUFS); 797 798 MCLGET(m_new, M_DONTWAIT); 799 if (!(m_new->m_flags & M_EXT)) { 800 m_freem(m_new); 801 return(ENOBUFS); 802 } 803 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 804 } else { 805 m_new = m; 806 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 807 m_new->m_data = m_new->m_ext.ext_buf; 808 } 809 810 m_adj(m_new, ETHER_ALIGN); 811 812 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 813 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 814 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 815 c->pcn_bufsz |= PCN_RXLEN_MBO; 816 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 817 818 return(0); 819} 820 821/* 822 * A frame has been uploaded: pass the resulting mbuf chain up to 823 * the higher level protocols. 824 */ 825static void 826pcn_rxeof(sc) 827 struct pcn_softc *sc; 828{ 829 struct mbuf *m; 830 struct ifnet *ifp; 831 struct pcn_rx_desc *cur_rx; 832 int i; 833 834 PCN_LOCK_ASSERT(sc); 835 836 ifp = sc->pcn_ifp; 837 i = sc->pcn_cdata.pcn_rx_prod; 838 839 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 840 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 841 m = sc->pcn_cdata.pcn_rx_chain[i]; 842 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 843 844 /* 845 * If an error occurs, update stats, clear the 846 * status word and leave the mbuf cluster in place: 847 * it should simply get re-used next time this descriptor 848 * comes up in the ring. 849 */ 850 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 851 ifp->if_ierrors++; 852 pcn_newbuf(sc, i, m); 853 PCN_INC(i, PCN_RX_LIST_CNT); 854 continue; 855 } 856 857 if (pcn_newbuf(sc, i, NULL)) { 858 /* Ran out of mbufs; recycle this one. */ 859 pcn_newbuf(sc, i, m); 860 ifp->if_ierrors++; 861 PCN_INC(i, PCN_RX_LIST_CNT); 862 continue; 863 } 864 865 PCN_INC(i, PCN_RX_LIST_CNT); 866 867 /* No errors; receive the packet. */ 868 ifp->if_ipackets++; 869 m->m_len = m->m_pkthdr.len = 870 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 871 m->m_pkthdr.rcvif = ifp; 872 873 PCN_UNLOCK(sc); 874 (*ifp->if_input)(ifp, m); 875 PCN_LOCK(sc); 876 } 877 878 sc->pcn_cdata.pcn_rx_prod = i; 879 880 return; 881} 882 883/* 884 * A frame was downloaded to the chip. It's safe for us to clean up 885 * the list buffers. 886 */ 887 888static void 889pcn_txeof(sc) 890 struct pcn_softc *sc; 891{ 892 struct pcn_tx_desc *cur_tx = NULL; 893 struct ifnet *ifp; 894 u_int32_t idx; 895 896 ifp = sc->pcn_ifp; 897 898 /* 899 * Go through our tx list and free mbufs for those 900 * frames that have been transmitted. 901 */ 902 idx = sc->pcn_cdata.pcn_tx_cons; 903 while (idx != sc->pcn_cdata.pcn_tx_prod) { 904 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 905 906 if (!PCN_OWN_TXDESC(cur_tx)) 907 break; 908 909 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 910 sc->pcn_cdata.pcn_tx_cnt--; 911 PCN_INC(idx, PCN_TX_LIST_CNT); 912 continue; 913 } 914 915 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 916 ifp->if_oerrors++; 917 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 918 ifp->if_collisions++; 919 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 920 ifp->if_collisions++; 921 } 922 923 ifp->if_collisions += 924 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 925 926 ifp->if_opackets++; 927 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 928 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 929 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 930 } 931 932 sc->pcn_cdata.pcn_tx_cnt--; 933 PCN_INC(idx, PCN_TX_LIST_CNT); 934 } 935 936 if (idx != sc->pcn_cdata.pcn_tx_cons) { 937 /* Some buffers have been freed. */ 938 sc->pcn_cdata.pcn_tx_cons = idx; 939 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 940 } 941 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 942 943 return; 944} 945 946static void 947pcn_tick(xsc) 948 void *xsc; 949{ 950 struct pcn_softc *sc; 951 struct mii_data *mii; 952 struct ifnet *ifp; 953 954 sc = xsc; 955 ifp = sc->pcn_ifp; 956 PCN_LOCK_ASSERT(sc); 957 958 mii = device_get_softc(sc->pcn_miibus); 959 mii_tick(mii); 960 961 /* link just died */ 962 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 963 sc->pcn_link = 0; 964 965 /* link just came up, restart */ 966 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 967 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 968 sc->pcn_link++; 969 if (ifp->if_snd.ifq_head != NULL) 970 pcn_start_locked(ifp); 971 } 972 973 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 974 975 return; 976} 977 978static void 979pcn_intr(arg) 980 void *arg; 981{ 982 struct pcn_softc *sc; 983 struct ifnet *ifp; 984 u_int32_t status; 985 986 sc = arg; 987 ifp = sc->pcn_ifp; 988 989 PCN_LOCK(sc); 990 991 /* Suppress unwanted interrupts */ 992 if (!(ifp->if_flags & IFF_UP)) { 993 pcn_stop(sc); 994 PCN_UNLOCK(sc); 995 return; 996 } 997 998 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 999 1000 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 1001 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 1002 1003 if (status & PCN_CSR_RINT) 1004 pcn_rxeof(sc); 1005 1006 if (status & PCN_CSR_TINT) 1007 pcn_txeof(sc); 1008 1009 if (status & PCN_CSR_ERR) { 1010 pcn_init_locked(sc); 1011 break; 1012 } 1013 } 1014 1015 if (ifp->if_snd.ifq_head != NULL) 1016 pcn_start_locked(ifp); 1017 1018 PCN_UNLOCK(sc); 1019 return; 1020} 1021 1022/* 1023 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1024 * pointers to the fragment pointers. 1025 */ 1026static int 1027pcn_encap(sc, m_head, txidx) 1028 struct pcn_softc *sc; 1029 struct mbuf *m_head; 1030 u_int32_t *txidx; 1031{ 1032 struct pcn_tx_desc *f = NULL; 1033 struct mbuf *m; 1034 int frag, cur, cnt = 0; 1035 1036 /* 1037 * Start packing the mbufs in this chain into 1038 * the fragment pointers. Stop when we run out 1039 * of fragments or hit the end of the mbuf chain. 1040 */ 1041 m = m_head; 1042 cur = frag = *txidx; 1043 1044 for (m = m_head; m != NULL; m = m->m_next) { 1045 if (m->m_len == 0) 1046 continue; 1047 1048 if ((PCN_TX_LIST_CNT - (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1049 return(ENOBUFS); 1050 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1051 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1052 f->pcn_txctl |= PCN_TXCTL_MBO; 1053 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1054 if (cnt == 0) 1055 f->pcn_txctl |= PCN_TXCTL_STP; 1056 else 1057 f->pcn_txctl |= PCN_TXCTL_OWN; 1058 cur = frag; 1059 PCN_INC(frag, PCN_TX_LIST_CNT); 1060 cnt++; 1061 } 1062 1063 if (m != NULL) 1064 return(ENOBUFS); 1065 1066 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1067 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1068 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1069 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1070 sc->pcn_cdata.pcn_tx_cnt += cnt; 1071 *txidx = frag; 1072 1073 return(0); 1074} 1075 1076/* 1077 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1078 * to the mbuf data regions directly in the transmit lists. We also save a 1079 * copy of the pointers since the transmit list fragment pointers are 1080 * physical addresses. 1081 */ 1082static void 1083pcn_start(ifp) 1084 struct ifnet *ifp; 1085{ 1086 struct pcn_softc *sc; 1087 1088 sc = ifp->if_softc; 1089 PCN_LOCK(sc); 1090 pcn_start_locked(ifp); 1091 PCN_UNLOCK(sc); 1092} 1093 1094static void 1095pcn_start_locked(ifp) 1096 struct ifnet *ifp; 1097{ 1098 struct pcn_softc *sc; 1099 struct mbuf *m_head = NULL; 1100 u_int32_t idx; 1101 1102 sc = ifp->if_softc; 1103 1104 PCN_LOCK_ASSERT(sc); 1105 1106 if (!sc->pcn_link) 1107 return; 1108 1109 idx = sc->pcn_cdata.pcn_tx_prod; 1110 1111 if (ifp->if_drv_flags & IFF_DRV_OACTIVE) 1112 return; 1113 1114 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1115 IF_DEQUEUE(&ifp->if_snd, m_head); 1116 if (m_head == NULL) 1117 break; 1118 1119 if (pcn_encap(sc, m_head, &idx)) { 1120 IF_PREPEND(&ifp->if_snd, m_head); 1121 ifp->if_drv_flags |= IFF_DRV_OACTIVE; 1122 break; 1123 } 1124 1125 /* 1126 * If there's a BPF listener, bounce a copy of this frame 1127 * to him. 1128 */ 1129 BPF_MTAP(ifp, m_head); 1130 1131 } 1132 1133 /* Transmit */ 1134 sc->pcn_cdata.pcn_tx_prod = idx; 1135 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1136 1137 /* 1138 * Set a timeout in case the chip goes out to lunch. 1139 */ 1140 ifp->if_timer = 5; 1141 1142 return; 1143} 1144 1145static void 1146pcn_setfilt(ifp) 1147 struct ifnet *ifp; 1148{ 1149 struct pcn_softc *sc; 1150 1151 sc = ifp->if_softc; 1152 1153 /* If we want promiscuous mode, set the allframes bit. */ 1154 if (ifp->if_flags & IFF_PROMISC) { 1155 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1156 } else { 1157 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1158 } 1159 1160 /* Set the capture broadcast bit to capture broadcast frames. */ 1161 if (ifp->if_flags & IFF_BROADCAST) { 1162 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1163 } else { 1164 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1165 } 1166 1167 return; 1168} 1169 1170static void 1171pcn_init(xsc) 1172 void *xsc; 1173{ 1174 struct pcn_softc *sc = xsc; 1175 1176 PCN_LOCK(sc); 1177 pcn_init_locked(sc); 1178 PCN_UNLOCK(sc); 1179} 1180 1181static void 1182pcn_init_locked(sc) 1183 struct pcn_softc *sc; 1184{ 1185 struct ifnet *ifp = sc->pcn_ifp; 1186 struct mii_data *mii = NULL; 1187 struct ifmedia_entry *ife; 1188 1189 PCN_LOCK_ASSERT(sc); 1190 1191 /* 1192 * Cancel pending I/O and free all RX/TX buffers. 1193 */ 1194 pcn_stop(sc); 1195 pcn_reset(sc); 1196 1197 mii = device_get_softc(sc->pcn_miibus); 1198 ife = mii->mii_media.ifm_cur; 1199 1200 /* Set MAC address */ 1201 pcn_csr_write(sc, PCN_CSR_PAR0, 1202 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[0]); 1203 pcn_csr_write(sc, PCN_CSR_PAR1, 1204 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[1]); 1205 pcn_csr_write(sc, PCN_CSR_PAR2, 1206 ((u_int16_t *)IF_LLADDR(sc->pcn_ifp))[2]); 1207 1208 /* Init circular RX list. */ 1209 if (pcn_list_rx_init(sc) == ENOBUFS) { 1210 if_printf(ifp, "initialization failed: no " 1211 "memory for rx buffers\n"); 1212 pcn_stop(sc); 1213 return; 1214 } 1215 1216 /* 1217 * Init tx descriptors. 1218 */ 1219 pcn_list_tx_init(sc); 1220 1221 /* Clear PCN_MISC_ASEL so we can set the port via PCN_CSR_MODE. */ 1222 PCN_BCR_CLRBIT(sc, PCN_BCR_MISCCFG, PCN_MISC_ASEL); 1223 1224 /* 1225 * Set up the port based on the currently selected media. 1226 * For Am79C978 we've to unconditionally set PCN_PORT_MII and 1227 * set the PHY in PCN_BCR_PHYSEL instead. 1228 */ 1229 if (sc->pcn_type != Am79C978 && 1230 IFM_INST(ife->ifm_media) == sc->pcn_inst_10bt) 1231 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_10BASET); 1232 else 1233 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1234 1235 /* Set up RX filter. */ 1236 pcn_setfilt(ifp); 1237 1238 /* 1239 * Load the multicast filter. 1240 */ 1241 pcn_setmulti(sc); 1242 1243 /* 1244 * Load the addresses of the RX and TX lists. 1245 */ 1246 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1247 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1248 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1249 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1250 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1251 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1252 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1253 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1254 1255 /* Set the RX and TX ring sizes. */ 1256 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1257 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1258 1259 /* We're not using the initialization block. */ 1260 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1261 1262 /* Enable fast suspend mode. */ 1263 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1264 1265 /* 1266 * Enable burst read and write. Also set the no underflow 1267 * bit. This will avoid transmit underruns in certain 1268 * conditions while still providing decent performance. 1269 */ 1270 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1271 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1272 1273 /* Enable graceful recovery from underflow. */ 1274 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1275 1276 /* Enable auto-padding of short TX frames. */ 1277 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1278 1279 /* Disable MII autoneg (we handle this ourselves). */ 1280 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1281 1282 if (sc->pcn_type == Am79C978) 1283 /* XXX support other PHYs? */ 1284 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1285 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1286 1287 /* Enable interrupts and start the controller running. */ 1288 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1289 1290 mii_mediachg(mii); 1291 1292 ifp->if_drv_flags |= IFF_DRV_RUNNING; 1293 ifp->if_drv_flags &= ~IFF_DRV_OACTIVE; 1294 1295 callout_reset(&sc->pcn_stat_callout, hz, pcn_tick, sc); 1296 1297 return; 1298} 1299 1300/* 1301 * Set media options. 1302 */ 1303static int 1304pcn_ifmedia_upd(ifp) 1305 struct ifnet *ifp; 1306{ 1307 struct pcn_softc *sc; 1308 1309 sc = ifp->if_softc; 1310 1311 PCN_LOCK(sc); 1312 1313 /* 1314 * At least Am79C971 with DP83840A can wedge when switching 1315 * from the internal 10baseT PHY to the external PHY without 1316 * issuing pcn_reset(). For setting the port in PCN_CSR_MODE 1317 * the PCnet chip has to be powered down or stopped anyway 1318 * and although documented otherwise it doesn't take effect 1319 * until the next initialization. 1320 */ 1321 sc->pcn_link = 0; 1322 pcn_stop(sc); 1323 pcn_reset(sc); 1324 pcn_init_locked(sc); 1325 if (ifp->if_snd.ifq_head != NULL) 1326 pcn_start_locked(ifp); 1327 1328 PCN_UNLOCK(sc); 1329 1330 return(0); 1331} 1332 1333/* 1334 * Report current media status. 1335 */ 1336static void 1337pcn_ifmedia_sts(ifp, ifmr) 1338 struct ifnet *ifp; 1339 struct ifmediareq *ifmr; 1340{ 1341 struct pcn_softc *sc; 1342 struct mii_data *mii; 1343 1344 sc = ifp->if_softc; 1345 1346 mii = device_get_softc(sc->pcn_miibus); 1347 PCN_LOCK(sc); 1348 mii_pollstat(mii); 1349 ifmr->ifm_active = mii->mii_media_active; 1350 ifmr->ifm_status = mii->mii_media_status; 1351 PCN_UNLOCK(sc); 1352 1353 return; 1354} 1355 1356static int 1357pcn_ioctl(ifp, command, data) 1358 struct ifnet *ifp; 1359 u_long command; 1360 caddr_t data; 1361{ 1362 struct pcn_softc *sc = ifp->if_softc; 1363 struct ifreq *ifr = (struct ifreq *) data; 1364 struct mii_data *mii = NULL; 1365 int error = 0; 1366 1367 switch(command) { 1368 case SIOCSIFFLAGS: 1369 PCN_LOCK(sc); 1370 if (ifp->if_flags & IFF_UP) { 1371 if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1372 ifp->if_flags & IFF_PROMISC && 1373 !(sc->pcn_if_flags & IFF_PROMISC)) { 1374 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1375 PCN_EXTCTL1_SPND); 1376 pcn_setfilt(ifp); 1377 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1378 PCN_EXTCTL1_SPND); 1379 pcn_csr_write(sc, PCN_CSR_CSR, 1380 PCN_CSR_INTEN|PCN_CSR_START); 1381 } else if (ifp->if_drv_flags & IFF_DRV_RUNNING && 1382 !(ifp->if_flags & IFF_PROMISC) && 1383 sc->pcn_if_flags & IFF_PROMISC) { 1384 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1385 PCN_EXTCTL1_SPND); 1386 pcn_setfilt(ifp); 1387 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1388 PCN_EXTCTL1_SPND); 1389 pcn_csr_write(sc, PCN_CSR_CSR, 1390 PCN_CSR_INTEN|PCN_CSR_START); 1391 } else if (!(ifp->if_drv_flags & IFF_DRV_RUNNING)) 1392 pcn_init_locked(sc); 1393 } else { 1394 if (ifp->if_drv_flags & IFF_DRV_RUNNING) 1395 pcn_stop(sc); 1396 } 1397 sc->pcn_if_flags = ifp->if_flags; 1398 PCN_UNLOCK(sc); 1399 error = 0; 1400 break; 1401 case SIOCADDMULTI: 1402 case SIOCDELMULTI: 1403 PCN_LOCK(sc); 1404 pcn_setmulti(sc); 1405 PCN_UNLOCK(sc); 1406 error = 0; 1407 break; 1408 case SIOCGIFMEDIA: 1409 case SIOCSIFMEDIA: 1410 mii = device_get_softc(sc->pcn_miibus); 1411 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1412 break; 1413 default: 1414 error = ether_ioctl(ifp, command, data); 1415 break; 1416 } 1417 1418 return(error); 1419} 1420 1421static void 1422pcn_watchdog(ifp) 1423 struct ifnet *ifp; 1424{ 1425 struct pcn_softc *sc; 1426 1427 sc = ifp->if_softc; 1428 1429 PCN_LOCK(sc); 1430 1431 ifp->if_oerrors++; 1432 if_printf(ifp, "watchdog timeout\n"); 1433 1434 pcn_stop(sc); 1435 pcn_reset(sc); 1436 pcn_init_locked(sc); 1437 1438 if (ifp->if_snd.ifq_head != NULL) 1439 pcn_start(ifp); 1440 1441 PCN_UNLOCK(sc); 1442 1443 return; 1444} 1445 1446/* 1447 * Stop the adapter and free any mbufs allocated to the 1448 * RX and TX lists. 1449 */ 1450static void 1451pcn_stop(sc) 1452 struct pcn_softc *sc; 1453{ 1454 register int i; 1455 struct ifnet *ifp; 1456 1457 PCN_LOCK_ASSERT(sc); 1458 ifp = sc->pcn_ifp; 1459 ifp->if_timer = 0; 1460 1461 callout_stop(&sc->pcn_stat_callout); 1462 1463 /* Turn off interrupts */ 1464 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1465 /* Stop adapter */ 1466 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1467 sc->pcn_link = 0; 1468 1469 /* 1470 * Free data in the RX lists. 1471 */ 1472 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1473 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1474 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1475 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1476 } 1477 } 1478 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1479 sizeof(sc->pcn_ldata->pcn_rx_list)); 1480 1481 /* 1482 * Free the TX list buffers. 1483 */ 1484 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1485 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1486 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1487 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1488 } 1489 } 1490 1491 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1492 sizeof(sc->pcn_ldata->pcn_tx_list)); 1493 1494 ifp->if_drv_flags &= ~(IFF_DRV_RUNNING | IFF_DRV_OACTIVE); 1495 1496 return; 1497} 1498 1499/* 1500 * Stop all chip I/O so that the kernel's probe routines don't 1501 * get confused by errant DMAs when rebooting. 1502 */ 1503static void 1504pcn_shutdown(dev) 1505 device_t dev; 1506{ 1507 struct pcn_softc *sc; 1508 1509 sc = device_get_softc(dev); 1510 1511 PCN_LOCK(sc); 1512 pcn_reset(sc); 1513 pcn_stop(sc); 1514 PCN_UNLOCK(sc); 1515 1516 return; 1517} 1518