if_pcn.c revision 138354
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 138354 2004-12-03 18:21:30Z mdodd $"); 36 37/* 38 * AMD Am79c972 fast ethernet PCI NIC driver. Datasheets are available 39 * from http://www.amd.com. 40 * 41 * The AMD PCnet/PCI controllers are more advanced and functional 42 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 43 * backwards compatibility with the LANCE and thus can be made 44 * to work with older LANCE drivers. This is in fact how the 45 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 46 * is that the PCnet/PCI devices offer several performance enhancements 47 * which can't be exploited in LANCE compatibility mode. Chief among 48 * these enhancements is the ability to perform PCI DMA operations 49 * using 32-bit addressing (which eliminates the need for ISA 50 * bounce-buffering), and special receive buffer alignment (which 51 * allows the receive handler to pass packets to the upper protocol 52 * layers without copying on both the x86 and alpha platforms). 53 */ 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/module.h> 62#include <sys/socket.h> 63 64#include <net/if.h> 65#include <net/if_arp.h> 66#include <net/ethernet.h> 67#include <net/if_dl.h> 68#include <net/if_media.h> 69 70#include <net/bpf.h> 71 72#include <vm/vm.h> /* for vtophys */ 73#include <vm/pmap.h> /* for vtophys */ 74#include <machine/bus_pio.h> 75#include <machine/bus_memio.h> 76#include <machine/bus.h> 77#include <machine/resource.h> 78#include <sys/bus.h> 79#include <sys/rman.h> 80 81#include <dev/mii/mii.h> 82#include <dev/mii/miivar.h> 83 84#include <dev/pci/pcireg.h> 85#include <dev/pci/pcivar.h> 86 87#define PCN_USEIOSPACE 88 89#include <pci/if_pcnreg.h> 90 91MODULE_DEPEND(pcn, pci, 1, 1, 1); 92MODULE_DEPEND(pcn, ether, 1, 1, 1); 93MODULE_DEPEND(pcn, miibus, 1, 1, 1); 94 95/* "controller miibus0" required. See GENERIC if you get errors here. */ 96#include "miibus_if.h" 97 98/* 99 * Various supported device vendors/types and their names. 100 */ 101static struct pcn_type pcn_devs[] = { 102 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 103 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 104 { 0, 0, NULL } 105}; 106 107static struct pcn_chipid { 108 u_int32_t id; 109 char * name; 110} pcn_chipid[] = { 111 { Am79C960, "Am79C960" }, 112 { Am79C961, "Am79C961" }, 113 { Am79C961A, "Am79C961A" }, 114 { Am79C965, "Am79C965" }, 115 { Am79C970, "Am79C970" }, 116 { Am79C970A, "Am79C970A" }, 117 { Am79C971, "Am79C971" }, 118 { Am79C972, "Am79C972" }, 119 { Am79C973, "Am79C973" }, 120 { Am79C978, "Am79C978" }, 121 { Am79C975, "Am79C975" }, 122 { Am79C976, "Am79C976" }, 123 { 0, NULL }, 124}; 125 126static char * pcn_chipid_name(u_int32_t); 127static u_int32_t pcn_chip_id (device_t); 128 129static u_int32_t pcn_csr_read (struct pcn_softc *, int); 130static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 131static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 132static void pcn_csr_write (struct pcn_softc *, int, int); 133static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 134static void pcn_bcr_write (struct pcn_softc *, int, int); 135 136static int pcn_probe (device_t); 137static int pcn_attach (device_t); 138static int pcn_detach (device_t); 139 140static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 141static int pcn_encap (struct pcn_softc *, 142 struct mbuf *, u_int32_t *); 143static void pcn_rxeof (struct pcn_softc *); 144static void pcn_txeof (struct pcn_softc *); 145static void pcn_intr (void *); 146static void pcn_tick (void *); 147static void pcn_start (struct ifnet *); 148static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 149static void pcn_init (void *); 150static void pcn_stop (struct pcn_softc *); 151static void pcn_watchdog (struct ifnet *); 152static void pcn_shutdown (device_t); 153static int pcn_ifmedia_upd (struct ifnet *); 154static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 155 156static int pcn_miibus_readreg (device_t, int, int); 157static int pcn_miibus_writereg (device_t, int, int, int); 158static void pcn_miibus_statchg (device_t); 159 160static void pcn_setfilt (struct ifnet *); 161static void pcn_setmulti (struct pcn_softc *); 162static void pcn_reset (struct pcn_softc *); 163static int pcn_list_rx_init (struct pcn_softc *); 164static int pcn_list_tx_init (struct pcn_softc *); 165 166#ifdef PCN_USEIOSPACE 167#define PCN_RES SYS_RES_IOPORT 168#define PCN_RID PCN_PCI_LOIO 169#else 170#define PCN_RES SYS_RES_MEMORY 171#define PCN_RID PCN_PCI_LOMEM 172#endif 173 174static device_method_t pcn_methods[] = { 175 /* Device interface */ 176 DEVMETHOD(device_probe, pcn_probe), 177 DEVMETHOD(device_attach, pcn_attach), 178 DEVMETHOD(device_detach, pcn_detach), 179 DEVMETHOD(device_shutdown, pcn_shutdown), 180 181 /* bus interface */ 182 DEVMETHOD(bus_print_child, bus_generic_print_child), 183 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 184 185 /* MII interface */ 186 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 187 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 188 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 189 190 { 0, 0 } 191}; 192 193static driver_t pcn_driver = { 194 "pcn", 195 pcn_methods, 196 sizeof(struct pcn_softc) 197}; 198 199static devclass_t pcn_devclass; 200 201DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 202DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 203 204#define PCN_CSR_SETBIT(sc, reg, x) \ 205 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 206 207#define PCN_CSR_CLRBIT(sc, reg, x) \ 208 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 209 210#define PCN_BCR_SETBIT(sc, reg, x) \ 211 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 212 213#define PCN_BCR_CLRBIT(sc, reg, x) \ 214 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 215 216static u_int32_t 217pcn_csr_read(sc, reg) 218 struct pcn_softc *sc; 219 int reg; 220{ 221 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 222 return(CSR_READ_4(sc, PCN_IO32_RDP)); 223} 224 225static u_int16_t 226pcn_csr_read16(sc, reg) 227 struct pcn_softc *sc; 228 int reg; 229{ 230 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 231 return(CSR_READ_2(sc, PCN_IO16_RDP)); 232} 233 234static void 235pcn_csr_write(sc, reg, val) 236 struct pcn_softc *sc; 237 int reg; 238 int val; 239{ 240 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 241 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 242 return; 243} 244 245static u_int32_t 246pcn_bcr_read(sc, reg) 247 struct pcn_softc *sc; 248 int reg; 249{ 250 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 251 return(CSR_READ_4(sc, PCN_IO32_BDP)); 252} 253 254static u_int16_t 255pcn_bcr_read16(sc, reg) 256 struct pcn_softc *sc; 257 int reg; 258{ 259 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 260 return(CSR_READ_2(sc, PCN_IO16_BDP)); 261} 262 263static void 264pcn_bcr_write(sc, reg, val) 265 struct pcn_softc *sc; 266 int reg; 267 int val; 268{ 269 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 270 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 271 return; 272} 273 274static int 275pcn_miibus_readreg(dev, phy, reg) 276 device_t dev; 277 int phy, reg; 278{ 279 struct pcn_softc *sc; 280 int val; 281 282 sc = device_get_softc(dev); 283 284 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 285 return(0); 286 287 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 288 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 289 if (val == 0xFFFF) 290 return(0); 291 292 sc->pcn_phyaddr = phy; 293 294 return(val); 295} 296 297static int 298pcn_miibus_writereg(dev, phy, reg, data) 299 device_t dev; 300 int phy, reg, data; 301{ 302 struct pcn_softc *sc; 303 304 sc = device_get_softc(dev); 305 306 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 307 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 308 309 return(0); 310} 311 312static void 313pcn_miibus_statchg(dev) 314 device_t dev; 315{ 316 struct pcn_softc *sc; 317 struct mii_data *mii; 318 319 sc = device_get_softc(dev); 320 mii = device_get_softc(sc->pcn_miibus); 321 322 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 323 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 324 } else { 325 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 326 } 327 328 return; 329} 330 331static void 332pcn_setmulti(sc) 333 struct pcn_softc *sc; 334{ 335 struct ifnet *ifp; 336 struct ifmultiaddr *ifma; 337 u_int32_t h, i; 338 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 339 340 ifp = &sc->arpcom.ac_if; 341 342 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 343 344 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 345 for (i = 0; i < 4; i++) 346 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 347 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 348 return; 349 } 350 351 /* first, zot all the existing hash bits */ 352 for (i = 0; i < 4; i++) 353 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 354 355 /* now program new ones */ 356 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 357 if (ifma->ifma_addr->sa_family != AF_LINK) 358 continue; 359 h = ether_crc32_le(LLADDR((struct sockaddr_dl *) 360 ifma->ifma_addr), ETHER_ADDR_LEN) >> 26; 361 hashes[h >> 4] |= 1 << (h & 0xF); 362 } 363 364 for (i = 0; i < 4; i++) 365 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 366 367 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 368 369 return; 370} 371 372static void 373pcn_reset(sc) 374 struct pcn_softc *sc; 375{ 376 /* 377 * Issue a reset by reading from the RESET register. 378 * Note that we don't know if the chip is operating in 379 * 16-bit or 32-bit mode at this point, so we attempt 380 * to reset the chip both ways. If one fails, the other 381 * will succeed. 382 */ 383 CSR_READ_2(sc, PCN_IO16_RESET); 384 CSR_READ_4(sc, PCN_IO32_RESET); 385 386 /* Wait a little while for the chip to get its brains in order. */ 387 DELAY(1000); 388 389 /* Select 32-bit (DWIO) mode */ 390 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 391 392 /* Select software style 3. */ 393 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 394 395 return; 396} 397 398static char * 399pcn_chipid_name (u_int32_t id) 400{ 401 struct pcn_chipid *p = pcn_chipid; 402 403 while (p->name) { 404 if (id == p->id) 405 return (p->name); 406 p++; 407 } 408 return ("Unknown"); 409} 410 411static u_int32_t 412pcn_chip_id (device_t dev) 413{ 414 struct pcn_softc *sc; 415 u_int32_t chip_id; 416 417 sc = device_get_softc(dev); 418 /* 419 * Note: we can *NOT* put the chip into 420 * 32-bit mode yet. The lnc driver will only 421 * work in 16-bit mode, and once the chip 422 * goes into 32-bit mode, the only way to 423 * get it out again is with a hardware reset. 424 * So if pcn_probe() is called before the 425 * lnc driver's probe routine, the chip will 426 * be locked into 32-bit operation and the lnc 427 * driver will be unable to attach to it. 428 * Note II: if the chip happens to already 429 * be in 32-bit mode, we still need to check 430 * the chip ID, but first we have to detect 431 * 32-bit mode using only 16-bit operations. 432 * The safest way to do this is to read the 433 * PCI subsystem ID from BCR23/24 and compare 434 * that with the value read from PCI config 435 * space. 436 */ 437 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 438 chip_id <<= 16; 439 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 440 /* 441 * Note III: the test for 0x10001000 is a hack to 442 * pacify VMware, who's pseudo-PCnet interface is 443 * broken. Reading the subsystem register from PCI 444 * config space yields 0x00000000 while reading the 445 * same value from I/O space yields 0x10001000. It's 446 * not supposed to be that way. 447 */ 448 if (chip_id == pci_read_config(dev, 449 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 450 /* We're in 16-bit mode. */ 451 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 452 chip_id <<= 16; 453 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 454 } else { 455 /* We're in 32-bit mode. */ 456 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 457 chip_id <<= 16; 458 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 459 } 460 461 return (chip_id); 462} 463 464/* 465 * Probe for an AMD chip. Check the PCI vendor and device 466 * IDs against our list and return a device name if we find a match. 467 */ 468static int 469pcn_probe(dev) 470 device_t dev; 471{ 472 struct pcn_type *t; 473 struct pcn_softc *sc; 474 int rid; 475 u_int32_t chip_id; 476 477 t = pcn_devs; 478 sc = device_get_softc(dev); 479 480 while(t->pcn_name != NULL) { 481 if ((pci_get_vendor(dev) == t->pcn_vid) && 482 (pci_get_device(dev) == t->pcn_did)) { 483 /* 484 * Temporarily map the I/O space 485 * so we can read the chip ID register. 486 */ 487 rid = PCN_RID; 488 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, 489 RF_ACTIVE); 490 if (sc->pcn_res == NULL) { 491 device_printf(dev, 492 "couldn't map ports/memory\n"); 493 return(ENXIO); 494 } 495 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 496 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 497 mtx_init(&sc->pcn_mtx, 498 device_get_nameunit(dev), MTX_NETWORK_LOCK, 499 MTX_DEF); 500 PCN_LOCK(sc); 501 chip_id = pcn_chip_id(dev); 502 bus_release_resource(dev, PCN_RES, 503 PCN_RID, sc->pcn_res); 504 PCN_UNLOCK(sc); 505 mtx_destroy(&sc->pcn_mtx); 506 chip_id >>= 12; 507 sc->pcn_type = chip_id & PART_MASK; 508 switch(sc->pcn_type) { 509 case Am79C971: 510 case Am79C972: 511 case Am79C973: 512 case Am79C975: 513 case Am79C976: 514 case Am79C978: 515 break; 516 default: 517 return(ENXIO); 518 } 519 device_set_desc(dev, t->pcn_name); 520 return(0); 521 } 522 t++; 523 } 524 525 return(ENXIO); 526} 527 528/* 529 * Attach the interface. Allocate softc structures, do ifmedia 530 * setup and ethernet/BPF attach. 531 */ 532static int 533pcn_attach(dev) 534 device_t dev; 535{ 536 u_int32_t eaddr[2]; 537 struct pcn_softc *sc; 538 struct ifnet *ifp; 539 int unit, error = 0, rid; 540 541 sc = device_get_softc(dev); 542 unit = device_get_unit(dev); 543 544 /* Initialize our mutex. */ 545 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 546 MTX_DEF | MTX_RECURSE); 547 /* 548 * Map control/status registers. 549 */ 550 pci_enable_busmaster(dev); 551 552 /* Retrieve the chip ID */ 553 sc->pcn_type = (pcn_chip_id(dev) >> 12) & PART_MASK; 554 device_printf(dev, "Chip ID %04x (%s)\n", 555 sc->pcn_type, pcn_chipid_name(sc->pcn_type)); 556 557 rid = PCN_RID; 558 sc->pcn_res = bus_alloc_resource_any(dev, PCN_RES, &rid, RF_ACTIVE); 559 560 if (sc->pcn_res == NULL) { 561 printf("pcn%d: couldn't map ports/memory\n", unit); 562 error = ENXIO; 563 goto fail; 564 } 565 566 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 567 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 568 569 /* Allocate interrupt */ 570 rid = 0; 571 sc->pcn_irq = bus_alloc_resource_any(dev, SYS_RES_IRQ, &rid, 572 RF_SHAREABLE | RF_ACTIVE); 573 574 if (sc->pcn_irq == NULL) { 575 printf("pcn%d: couldn't map interrupt\n", unit); 576 error = ENXIO; 577 goto fail; 578 } 579 580 /* Reset the adapter. */ 581 pcn_reset(sc); 582 583 /* 584 * Get station address from the EEPROM. 585 */ 586 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 587 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 588 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 589 590 sc->pcn_unit = unit; 591 callout_handle_init(&sc->pcn_stat_ch); 592 593 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 594 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 595 596 if (sc->pcn_ldata == NULL) { 597 printf("pcn%d: no memory for list buffers!\n", unit); 598 error = ENXIO; 599 goto fail; 600 } 601 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 602 603 ifp = &sc->arpcom.ac_if; 604 ifp->if_softc = sc; 605 if_initname(ifp, device_get_name(dev), device_get_unit(dev)); 606 ifp->if_mtu = ETHERMTU; 607 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST | 608 IFF_NEEDSGIANT; 609 ifp->if_ioctl = pcn_ioctl; 610 ifp->if_start = pcn_start; 611 ifp->if_watchdog = pcn_watchdog; 612 ifp->if_init = pcn_init; 613 ifp->if_baudrate = 10000000; 614 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 615 616 /* 617 * Do MII setup. 618 */ 619 if (mii_phy_probe(dev, &sc->pcn_miibus, 620 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 621 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 622 error = ENXIO; 623 goto fail; 624 } 625 626 /* 627 * Call MI attach routine. 628 */ 629 ether_ifattach(ifp, (u_int8_t *) eaddr); 630 631 /* Hook interrupt last to avoid having to lock softc */ 632 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 633 pcn_intr, sc, &sc->pcn_intrhand); 634 635 if (error) { 636 printf("pcn%d: couldn't set up irq\n", unit); 637 ether_ifdetach(ifp); 638 goto fail; 639 } 640 641fail: 642 if (error) 643 pcn_detach(dev); 644 645 return(error); 646} 647 648/* 649 * Shutdown hardware and free up resources. This can be called any 650 * time after the mutex has been initialized. It is called in both 651 * the error case in attach and the normal detach case so it needs 652 * to be careful about only freeing resources that have actually been 653 * allocated. 654 */ 655static int 656pcn_detach(dev) 657 device_t dev; 658{ 659 struct pcn_softc *sc; 660 struct ifnet *ifp; 661 662 sc = device_get_softc(dev); 663 ifp = &sc->arpcom.ac_if; 664 665 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 666 PCN_LOCK(sc); 667 668 /* These should only be active if attach succeeded */ 669 if (device_is_attached(dev)) { 670 pcn_reset(sc); 671 pcn_stop(sc); 672 ether_ifdetach(ifp); 673 } 674 if (sc->pcn_miibus) 675 device_delete_child(dev, sc->pcn_miibus); 676 bus_generic_detach(dev); 677 678 if (sc->pcn_intrhand) 679 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 680 if (sc->pcn_irq) 681 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 682 if (sc->pcn_res) 683 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 684 685 if (sc->pcn_ldata) { 686 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 687 M_DEVBUF); 688 } 689 PCN_UNLOCK(sc); 690 691 mtx_destroy(&sc->pcn_mtx); 692 693 return(0); 694} 695 696/* 697 * Initialize the transmit descriptors. 698 */ 699static int 700pcn_list_tx_init(sc) 701 struct pcn_softc *sc; 702{ 703 struct pcn_list_data *ld; 704 struct pcn_ring_data *cd; 705 int i; 706 707 cd = &sc->pcn_cdata; 708 ld = sc->pcn_ldata; 709 710 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 711 cd->pcn_tx_chain[i] = NULL; 712 ld->pcn_tx_list[i].pcn_tbaddr = 0; 713 ld->pcn_tx_list[i].pcn_txctl = 0; 714 ld->pcn_tx_list[i].pcn_txstat = 0; 715 } 716 717 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 718 719 return(0); 720} 721 722 723/* 724 * Initialize the RX descriptors and allocate mbufs for them. 725 */ 726static int 727pcn_list_rx_init(sc) 728 struct pcn_softc *sc; 729{ 730 struct pcn_ring_data *cd; 731 int i; 732 733 cd = &sc->pcn_cdata; 734 735 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 736 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 737 return(ENOBUFS); 738 } 739 740 cd->pcn_rx_prod = 0; 741 742 return(0); 743} 744 745/* 746 * Initialize an RX descriptor and attach an MBUF cluster. 747 */ 748static int 749pcn_newbuf(sc, idx, m) 750 struct pcn_softc *sc; 751 int idx; 752 struct mbuf *m; 753{ 754 struct mbuf *m_new = NULL; 755 struct pcn_rx_desc *c; 756 757 c = &sc->pcn_ldata->pcn_rx_list[idx]; 758 759 if (m == NULL) { 760 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 761 if (m_new == NULL) 762 return(ENOBUFS); 763 764 MCLGET(m_new, M_DONTWAIT); 765 if (!(m_new->m_flags & M_EXT)) { 766 m_freem(m_new); 767 return(ENOBUFS); 768 } 769 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 770 } else { 771 m_new = m; 772 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 773 m_new->m_data = m_new->m_ext.ext_buf; 774 } 775 776 m_adj(m_new, ETHER_ALIGN); 777 778 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 779 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 780 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 781 c->pcn_bufsz |= PCN_RXLEN_MBO; 782 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 783 784 return(0); 785} 786 787/* 788 * A frame has been uploaded: pass the resulting mbuf chain up to 789 * the higher level protocols. 790 */ 791static void 792pcn_rxeof(sc) 793 struct pcn_softc *sc; 794{ 795 struct mbuf *m; 796 struct ifnet *ifp; 797 struct pcn_rx_desc *cur_rx; 798 int i; 799 800 PCN_LOCK_ASSERT(sc); 801 802 ifp = &sc->arpcom.ac_if; 803 i = sc->pcn_cdata.pcn_rx_prod; 804 805 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 806 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 807 m = sc->pcn_cdata.pcn_rx_chain[i]; 808 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 809 810 /* 811 * If an error occurs, update stats, clear the 812 * status word and leave the mbuf cluster in place: 813 * it should simply get re-used next time this descriptor 814 * comes up in the ring. 815 */ 816 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 817 ifp->if_ierrors++; 818 pcn_newbuf(sc, i, m); 819 PCN_INC(i, PCN_RX_LIST_CNT); 820 continue; 821 } 822 823 if (pcn_newbuf(sc, i, NULL)) { 824 /* Ran out of mbufs; recycle this one. */ 825 pcn_newbuf(sc, i, m); 826 ifp->if_ierrors++; 827 PCN_INC(i, PCN_RX_LIST_CNT); 828 continue; 829 } 830 831 PCN_INC(i, PCN_RX_LIST_CNT); 832 833 /* No errors; receive the packet. */ 834 ifp->if_ipackets++; 835 m->m_len = m->m_pkthdr.len = 836 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 837 m->m_pkthdr.rcvif = ifp; 838 839 PCN_UNLOCK(sc); 840 (*ifp->if_input)(ifp, m); 841 PCN_LOCK(sc); 842 } 843 844 sc->pcn_cdata.pcn_rx_prod = i; 845 846 return; 847} 848 849/* 850 * A frame was downloaded to the chip. It's safe for us to clean up 851 * the list buffers. 852 */ 853 854static void 855pcn_txeof(sc) 856 struct pcn_softc *sc; 857{ 858 struct pcn_tx_desc *cur_tx = NULL; 859 struct ifnet *ifp; 860 u_int32_t idx; 861 862 ifp = &sc->arpcom.ac_if; 863 864 /* 865 * Go through our tx list and free mbufs for those 866 * frames that have been transmitted. 867 */ 868 idx = sc->pcn_cdata.pcn_tx_cons; 869 while (idx != sc->pcn_cdata.pcn_tx_prod) { 870 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 871 872 if (!PCN_OWN_TXDESC(cur_tx)) 873 break; 874 875 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 876 sc->pcn_cdata.pcn_tx_cnt--; 877 PCN_INC(idx, PCN_TX_LIST_CNT); 878 continue; 879 } 880 881 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 882 ifp->if_oerrors++; 883 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 884 ifp->if_collisions++; 885 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 886 ifp->if_collisions++; 887 } 888 889 ifp->if_collisions += 890 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 891 892 ifp->if_opackets++; 893 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 894 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 895 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 896 } 897 898 sc->pcn_cdata.pcn_tx_cnt--; 899 PCN_INC(idx, PCN_TX_LIST_CNT); 900 } 901 902 if (idx != sc->pcn_cdata.pcn_tx_cons) { 903 /* Some buffers have been freed. */ 904 sc->pcn_cdata.pcn_tx_cons = idx; 905 ifp->if_flags &= ~IFF_OACTIVE; 906 } 907 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 908 909 return; 910} 911 912static void 913pcn_tick(xsc) 914 void *xsc; 915{ 916 struct pcn_softc *sc; 917 struct mii_data *mii; 918 struct ifnet *ifp; 919 920 sc = xsc; 921 ifp = &sc->arpcom.ac_if; 922 PCN_LOCK(sc); 923 924 mii = device_get_softc(sc->pcn_miibus); 925 mii_tick(mii); 926 927 /* link just died */ 928 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 929 sc->pcn_link = 0; 930 931 /* link just came up, restart */ 932 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 933 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 934 sc->pcn_link++; 935 if (ifp->if_snd.ifq_head != NULL) 936 pcn_start(ifp); 937 } 938 939 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 940 941 PCN_UNLOCK(sc); 942 943 return; 944} 945 946static void 947pcn_intr(arg) 948 void *arg; 949{ 950 struct pcn_softc *sc; 951 struct ifnet *ifp; 952 u_int32_t status; 953 954 sc = arg; 955 ifp = &sc->arpcom.ac_if; 956 957 /* Suppress unwanted interrupts */ 958 if (!(ifp->if_flags & IFF_UP)) { 959 pcn_stop(sc); 960 return; 961 } 962 963 PCN_LOCK(sc); 964 965 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 966 967 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 968 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 969 970 if (status & PCN_CSR_RINT) 971 pcn_rxeof(sc); 972 973 if (status & PCN_CSR_TINT) 974 pcn_txeof(sc); 975 976 if (status & PCN_CSR_ERR) { 977 pcn_init(sc); 978 break; 979 } 980 } 981 982 if (ifp->if_snd.ifq_head != NULL) 983 pcn_start(ifp); 984 985 PCN_UNLOCK(sc); 986 return; 987} 988 989/* 990 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 991 * pointers to the fragment pointers. 992 */ 993static int 994pcn_encap(sc, m_head, txidx) 995 struct pcn_softc *sc; 996 struct mbuf *m_head; 997 u_int32_t *txidx; 998{ 999 struct pcn_tx_desc *f = NULL; 1000 struct mbuf *m; 1001 int frag, cur, cnt = 0; 1002 1003 /* 1004 * Start packing the mbufs in this chain into 1005 * the fragment pointers. Stop when we run out 1006 * of fragments or hit the end of the mbuf chain. 1007 */ 1008 m = m_head; 1009 cur = frag = *txidx; 1010 1011 for (m = m_head; m != NULL; m = m->m_next) { 1012 if (m->m_len != 0) { 1013 if ((PCN_TX_LIST_CNT - 1014 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1015 return(ENOBUFS); 1016 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1017 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1018 f->pcn_txctl |= PCN_TXCTL_MBO; 1019 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1020 if (cnt == 0) 1021 f->pcn_txctl |= PCN_TXCTL_STP; 1022 else 1023 f->pcn_txctl |= PCN_TXCTL_OWN; 1024 cur = frag; 1025 PCN_INC(frag, PCN_TX_LIST_CNT); 1026 cnt++; 1027 } 1028 } 1029 1030 if (m != NULL) 1031 return(ENOBUFS); 1032 1033 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1034 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1035 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1036 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1037 sc->pcn_cdata.pcn_tx_cnt += cnt; 1038 *txidx = frag; 1039 1040 return(0); 1041} 1042 1043/* 1044 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1045 * to the mbuf data regions directly in the transmit lists. We also save a 1046 * copy of the pointers since the transmit list fragment pointers are 1047 * physical addresses. 1048 */ 1049static void 1050pcn_start(ifp) 1051 struct ifnet *ifp; 1052{ 1053 struct pcn_softc *sc; 1054 struct mbuf *m_head = NULL; 1055 u_int32_t idx; 1056 1057 sc = ifp->if_softc; 1058 1059 PCN_LOCK(sc); 1060 1061 if (!sc->pcn_link) { 1062 PCN_UNLOCK(sc); 1063 return; 1064 } 1065 1066 idx = sc->pcn_cdata.pcn_tx_prod; 1067 1068 if (ifp->if_flags & IFF_OACTIVE) { 1069 PCN_UNLOCK(sc); 1070 return; 1071 } 1072 1073 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1074 IF_DEQUEUE(&ifp->if_snd, m_head); 1075 if (m_head == NULL) 1076 break; 1077 1078 if (pcn_encap(sc, m_head, &idx)) { 1079 IF_PREPEND(&ifp->if_snd, m_head); 1080 ifp->if_flags |= IFF_OACTIVE; 1081 break; 1082 } 1083 1084 /* 1085 * If there's a BPF listener, bounce a copy of this frame 1086 * to him. 1087 */ 1088 BPF_MTAP(ifp, m_head); 1089 1090 } 1091 1092 /* Transmit */ 1093 sc->pcn_cdata.pcn_tx_prod = idx; 1094 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1095 1096 /* 1097 * Set a timeout in case the chip goes out to lunch. 1098 */ 1099 ifp->if_timer = 5; 1100 1101 PCN_UNLOCK(sc); 1102 1103 return; 1104} 1105 1106static void 1107pcn_setfilt(ifp) 1108 struct ifnet *ifp; 1109{ 1110 struct pcn_softc *sc; 1111 1112 sc = ifp->if_softc; 1113 1114 /* If we want promiscuous mode, set the allframes bit. */ 1115 if (ifp->if_flags & IFF_PROMISC) { 1116 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1117 } else { 1118 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1119 } 1120 1121 /* Set the capture broadcast bit to capture broadcast frames. */ 1122 if (ifp->if_flags & IFF_BROADCAST) { 1123 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1124 } else { 1125 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1126 } 1127 1128 return; 1129} 1130 1131static void 1132pcn_init(xsc) 1133 void *xsc; 1134{ 1135 struct pcn_softc *sc = xsc; 1136 struct ifnet *ifp = &sc->arpcom.ac_if; 1137 struct mii_data *mii = NULL; 1138 1139 PCN_LOCK(sc); 1140 1141 /* 1142 * Cancel pending I/O and free all RX/TX buffers. 1143 */ 1144 pcn_stop(sc); 1145 pcn_reset(sc); 1146 1147 mii = device_get_softc(sc->pcn_miibus); 1148 1149 /* Set MAC address */ 1150 pcn_csr_write(sc, PCN_CSR_PAR0, 1151 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1152 pcn_csr_write(sc, PCN_CSR_PAR1, 1153 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1154 pcn_csr_write(sc, PCN_CSR_PAR2, 1155 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1156 1157 /* Init circular RX list. */ 1158 if (pcn_list_rx_init(sc) == ENOBUFS) { 1159 printf("pcn%d: initialization failed: no " 1160 "memory for rx buffers\n", sc->pcn_unit); 1161 pcn_stop(sc); 1162 PCN_UNLOCK(sc); 1163 return; 1164 } 1165 1166 /* 1167 * Init tx descriptors. 1168 */ 1169 pcn_list_tx_init(sc); 1170 1171 /* Set up the mode register. */ 1172 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1173 1174 /* Set up RX filter. */ 1175 pcn_setfilt(ifp); 1176 1177 /* 1178 * Load the multicast filter. 1179 */ 1180 pcn_setmulti(sc); 1181 1182 /* 1183 * Load the addresses of the RX and TX lists. 1184 */ 1185 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1186 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1187 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1188 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1189 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1190 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1191 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1192 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1193 1194 /* Set the RX and TX ring sizes. */ 1195 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1196 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1197 1198 /* We're not using the initialization block. */ 1199 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1200 1201 /* Enable fast suspend mode. */ 1202 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1203 1204 /* 1205 * Enable burst read and write. Also set the no underflow 1206 * bit. This will avoid transmit underruns in certain 1207 * conditions while still providing decent performance. 1208 */ 1209 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1210 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1211 1212 /* Enable graceful recovery from underflow. */ 1213 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1214 1215 /* Enable auto-padding of short TX frames. */ 1216 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1217 1218 /* Disable MII autoneg (we handle this ourselves). */ 1219 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1220 1221 if (sc->pcn_type == Am79C978) 1222 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1223 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1224 1225 /* Enable interrupts and start the controller running. */ 1226 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1227 1228 mii_mediachg(mii); 1229 1230 ifp->if_flags |= IFF_RUNNING; 1231 ifp->if_flags &= ~IFF_OACTIVE; 1232 1233 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1234 PCN_UNLOCK(sc); 1235 1236 return; 1237} 1238 1239/* 1240 * Set media options. 1241 */ 1242static int 1243pcn_ifmedia_upd(ifp) 1244 struct ifnet *ifp; 1245{ 1246 struct pcn_softc *sc; 1247 struct mii_data *mii; 1248 1249 sc = ifp->if_softc; 1250 mii = device_get_softc(sc->pcn_miibus); 1251 1252 sc->pcn_link = 0; 1253 if (mii->mii_instance) { 1254 struct mii_softc *miisc; 1255 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1256 mii_phy_reset(miisc); 1257 } 1258 mii_mediachg(mii); 1259 1260 return(0); 1261} 1262 1263/* 1264 * Report current media status. 1265 */ 1266static void 1267pcn_ifmedia_sts(ifp, ifmr) 1268 struct ifnet *ifp; 1269 struct ifmediareq *ifmr; 1270{ 1271 struct pcn_softc *sc; 1272 struct mii_data *mii; 1273 1274 sc = ifp->if_softc; 1275 1276 mii = device_get_softc(sc->pcn_miibus); 1277 mii_pollstat(mii); 1278 ifmr->ifm_active = mii->mii_media_active; 1279 ifmr->ifm_status = mii->mii_media_status; 1280 1281 return; 1282} 1283 1284static int 1285pcn_ioctl(ifp, command, data) 1286 struct ifnet *ifp; 1287 u_long command; 1288 caddr_t data; 1289{ 1290 struct pcn_softc *sc = ifp->if_softc; 1291 struct ifreq *ifr = (struct ifreq *) data; 1292 struct mii_data *mii = NULL; 1293 int error = 0; 1294 1295 PCN_LOCK(sc); 1296 1297 switch(command) { 1298 case SIOCSIFFLAGS: 1299 if (ifp->if_flags & IFF_UP) { 1300 if (ifp->if_flags & IFF_RUNNING && 1301 ifp->if_flags & IFF_PROMISC && 1302 !(sc->pcn_if_flags & IFF_PROMISC)) { 1303 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1304 PCN_EXTCTL1_SPND); 1305 pcn_setfilt(ifp); 1306 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1307 PCN_EXTCTL1_SPND); 1308 pcn_csr_write(sc, PCN_CSR_CSR, 1309 PCN_CSR_INTEN|PCN_CSR_START); 1310 } else if (ifp->if_flags & IFF_RUNNING && 1311 !(ifp->if_flags & IFF_PROMISC) && 1312 sc->pcn_if_flags & IFF_PROMISC) { 1313 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1314 PCN_EXTCTL1_SPND); 1315 pcn_setfilt(ifp); 1316 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1317 PCN_EXTCTL1_SPND); 1318 pcn_csr_write(sc, PCN_CSR_CSR, 1319 PCN_CSR_INTEN|PCN_CSR_START); 1320 } else if (!(ifp->if_flags & IFF_RUNNING)) 1321 pcn_init(sc); 1322 } else { 1323 if (ifp->if_flags & IFF_RUNNING) 1324 pcn_stop(sc); 1325 } 1326 sc->pcn_if_flags = ifp->if_flags; 1327 error = 0; 1328 break; 1329 case SIOCADDMULTI: 1330 case SIOCDELMULTI: 1331 pcn_setmulti(sc); 1332 error = 0; 1333 break; 1334 case SIOCGIFMEDIA: 1335 case SIOCSIFMEDIA: 1336 mii = device_get_softc(sc->pcn_miibus); 1337 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1338 break; 1339 default: 1340 error = ether_ioctl(ifp, command, data); 1341 break; 1342 } 1343 1344 PCN_UNLOCK(sc); 1345 1346 return(error); 1347} 1348 1349static void 1350pcn_watchdog(ifp) 1351 struct ifnet *ifp; 1352{ 1353 struct pcn_softc *sc; 1354 1355 sc = ifp->if_softc; 1356 1357 PCN_LOCK(sc); 1358 1359 ifp->if_oerrors++; 1360 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1361 1362 pcn_stop(sc); 1363 pcn_reset(sc); 1364 pcn_init(sc); 1365 1366 if (ifp->if_snd.ifq_head != NULL) 1367 pcn_start(ifp); 1368 1369 PCN_UNLOCK(sc); 1370 1371 return; 1372} 1373 1374/* 1375 * Stop the adapter and free any mbufs allocated to the 1376 * RX and TX lists. 1377 */ 1378static void 1379pcn_stop(sc) 1380 struct pcn_softc *sc; 1381{ 1382 register int i; 1383 struct ifnet *ifp; 1384 1385 ifp = &sc->arpcom.ac_if; 1386 PCN_LOCK(sc); 1387 ifp->if_timer = 0; 1388 1389 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1390 1391 /* Turn off interrupts */ 1392 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1393 /* Stop adapter */ 1394 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1395 sc->pcn_link = 0; 1396 1397 /* 1398 * Free data in the RX lists. 1399 */ 1400 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1401 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1402 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1403 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1404 } 1405 } 1406 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1407 sizeof(sc->pcn_ldata->pcn_rx_list)); 1408 1409 /* 1410 * Free the TX list buffers. 1411 */ 1412 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1413 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1414 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1415 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1416 } 1417 } 1418 1419 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1420 sizeof(sc->pcn_ldata->pcn_tx_list)); 1421 1422 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1423 PCN_UNLOCK(sc); 1424 1425 return; 1426} 1427 1428/* 1429 * Stop all chip I/O so that the kernel's probe routines don't 1430 * get confused by errant DMAs when rebooting. 1431 */ 1432static void 1433pcn_shutdown(dev) 1434 device_t dev; 1435{ 1436 struct pcn_softc *sc; 1437 1438 sc = device_get_softc(dev); 1439 1440 PCN_LOCK(sc); 1441 pcn_reset(sc); 1442 pcn_stop(sc); 1443 PCN_UNLOCK(sc); 1444 1445 return; 1446} 1447