if_pcn.c revision 113561
1/* 2 * Copyright (c) 2000 Berkeley Software Design, Inc. 3 * Copyright (c) 1997, 1998, 1999, 2000 4 * Bill Paul <wpaul@osd.bsdi.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * AMD Am79c972 fast ethernet PCI NIC driver. Datatheets are available 36 * from http://www.amd.com. 37 * 38 * The AMD PCnet/PCI controllers are more advanced and functional 39 * versions of the venerable 7990 LANCE. The PCnet/PCI chips retain 40 * backwards compatibility with the LANCE and thus can be made 41 * to work with older LANCE drivers. This is in fact how the 42 * PCnet/PCI chips were supported in FreeBSD originally. The trouble 43 * is that the PCnet/PCI devices offer several performance enhancements 44 * which can't be exploited in LANCE compatibility mode. Chief among 45 * these enhancements is the ability to perform PCI DMA operations 46 * using 32-bit addressing (which eliminates the need for ISA 47 * bounce-buffering), and special receive buffer alignment (which 48 * allows the receive handler to pass packets to the upper protocol 49 * layers without copying on both the x86 and alpha platforms). 50 */ 51 52#include <sys/cdefs.h> 53__FBSDID("$FreeBSD: head/sys/pci/if_pcn.c 113561 2003-04-16 13:18:27Z mdodd $"); 54 55#include <sys/param.h> 56#include <sys/systm.h> 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/malloc.h> 60#include <sys/kernel.h> 61#include <sys/socket.h> 62 63#include <net/if.h> 64#include <net/if_arp.h> 65#include <net/ethernet.h> 66#include <net/if_dl.h> 67#include <net/if_media.h> 68 69#include <net/bpf.h> 70 71#include <vm/vm.h> /* for vtophys */ 72#include <vm/pmap.h> /* for vtophys */ 73#include <machine/bus_pio.h> 74#include <machine/bus_memio.h> 75#include <machine/bus.h> 76#include <machine/resource.h> 77#include <sys/bus.h> 78#include <sys/rman.h> 79 80#include <dev/mii/mii.h> 81#include <dev/mii/miivar.h> 82 83#include <pci/pcireg.h> 84#include <pci/pcivar.h> 85 86#define PCN_USEIOSPACE 87 88#include <pci/if_pcnreg.h> 89 90MODULE_DEPEND(pcn, pci, 1, 1, 1); 91MODULE_DEPEND(pcn, ether, 1, 1, 1); 92MODULE_DEPEND(pcn, miibus, 1, 1, 1); 93 94/* "controller miibus0" required. See GENERIC if you get errors here. */ 95#include "miibus_if.h" 96 97/* 98 * Various supported device vendors/types and their names. 99 */ 100static struct pcn_type pcn_devs[] = { 101 { PCN_VENDORID, PCN_DEVICEID_PCNET, "AMD PCnet/PCI 10/100BaseTX" }, 102 { PCN_VENDORID, PCN_DEVICEID_HOME, "AMD PCnet/Home HomePNA" }, 103 { 0, 0, NULL } 104}; 105 106static u_int32_t pcn_csr_read (struct pcn_softc *, int); 107static u_int16_t pcn_csr_read16 (struct pcn_softc *, int); 108static u_int16_t pcn_bcr_read16 (struct pcn_softc *, int); 109static void pcn_csr_write (struct pcn_softc *, int, int); 110static u_int32_t pcn_bcr_read (struct pcn_softc *, int); 111static void pcn_bcr_write (struct pcn_softc *, int, int); 112 113static int pcn_probe (device_t); 114static int pcn_attach (device_t); 115static int pcn_detach (device_t); 116 117static int pcn_newbuf (struct pcn_softc *, int, struct mbuf *); 118static int pcn_encap (struct pcn_softc *, 119 struct mbuf *, u_int32_t *); 120static void pcn_rxeof (struct pcn_softc *); 121static void pcn_txeof (struct pcn_softc *); 122static void pcn_intr (void *); 123static void pcn_tick (void *); 124static void pcn_start (struct ifnet *); 125static int pcn_ioctl (struct ifnet *, u_long, caddr_t); 126static void pcn_init (void *); 127static void pcn_stop (struct pcn_softc *); 128static void pcn_watchdog (struct ifnet *); 129static void pcn_shutdown (device_t); 130static int pcn_ifmedia_upd (struct ifnet *); 131static void pcn_ifmedia_sts (struct ifnet *, struct ifmediareq *); 132 133static int pcn_miibus_readreg (device_t, int, int); 134static int pcn_miibus_writereg (device_t, int, int, int); 135static void pcn_miibus_statchg (device_t); 136 137static void pcn_setfilt (struct ifnet *); 138static void pcn_setmulti (struct pcn_softc *); 139static u_int32_t pcn_crc (caddr_t); 140static void pcn_reset (struct pcn_softc *); 141static int pcn_list_rx_init (struct pcn_softc *); 142static int pcn_list_tx_init (struct pcn_softc *); 143 144#ifdef PCN_USEIOSPACE 145#define PCN_RES SYS_RES_IOPORT 146#define PCN_RID PCN_PCI_LOIO 147#else 148#define PCN_RES SYS_RES_MEMORY 149#define PCN_RID PCN_PCI_LOMEM 150#endif 151 152static device_method_t pcn_methods[] = { 153 /* Device interface */ 154 DEVMETHOD(device_probe, pcn_probe), 155 DEVMETHOD(device_attach, pcn_attach), 156 DEVMETHOD(device_detach, pcn_detach), 157 DEVMETHOD(device_shutdown, pcn_shutdown), 158 159 /* bus interface */ 160 DEVMETHOD(bus_print_child, bus_generic_print_child), 161 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 162 163 /* MII interface */ 164 DEVMETHOD(miibus_readreg, pcn_miibus_readreg), 165 DEVMETHOD(miibus_writereg, pcn_miibus_writereg), 166 DEVMETHOD(miibus_statchg, pcn_miibus_statchg), 167 168 { 0, 0 } 169}; 170 171static driver_t pcn_driver = { 172 "pcn", 173 pcn_methods, 174 sizeof(struct pcn_softc) 175}; 176 177static devclass_t pcn_devclass; 178 179DRIVER_MODULE(pcn, pci, pcn_driver, pcn_devclass, 0, 0); 180DRIVER_MODULE(miibus, pcn, miibus_driver, miibus_devclass, 0, 0); 181 182#define PCN_CSR_SETBIT(sc, reg, x) \ 183 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) | (x)) 184 185#define PCN_CSR_CLRBIT(sc, reg, x) \ 186 pcn_csr_write(sc, reg, pcn_csr_read(sc, reg) & ~(x)) 187 188#define PCN_BCR_SETBIT(sc, reg, x) \ 189 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) | (x)) 190 191#define PCN_BCR_CLRBIT(sc, reg, x) \ 192 pcn_bcr_write(sc, reg, pcn_bcr_read(sc, reg) & ~(x)) 193 194static u_int32_t 195pcn_csr_read(sc, reg) 196 struct pcn_softc *sc; 197 int reg; 198{ 199 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 200 return(CSR_READ_4(sc, PCN_IO32_RDP)); 201} 202 203static u_int16_t 204pcn_csr_read16(sc, reg) 205 struct pcn_softc *sc; 206 int reg; 207{ 208 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 209 return(CSR_READ_2(sc, PCN_IO16_RDP)); 210} 211 212static void 213pcn_csr_write(sc, reg, val) 214 struct pcn_softc *sc; 215 int reg; 216{ 217 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 218 CSR_WRITE_4(sc, PCN_IO32_RDP, val); 219 return; 220} 221 222static u_int32_t 223pcn_bcr_read(sc, reg) 224 struct pcn_softc *sc; 225 int reg; 226{ 227 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 228 return(CSR_READ_4(sc, PCN_IO32_BDP)); 229} 230 231static u_int16_t 232pcn_bcr_read16(sc, reg) 233 struct pcn_softc *sc; 234 int reg; 235{ 236 CSR_WRITE_2(sc, PCN_IO16_RAP, reg); 237 return(CSR_READ_2(sc, PCN_IO16_BDP)); 238} 239 240static void 241pcn_bcr_write(sc, reg, val) 242 struct pcn_softc *sc; 243 int reg; 244{ 245 CSR_WRITE_4(sc, PCN_IO32_RAP, reg); 246 CSR_WRITE_4(sc, PCN_IO32_BDP, val); 247 return; 248} 249 250static int 251pcn_miibus_readreg(dev, phy, reg) 252 device_t dev; 253 int phy, reg; 254{ 255 struct pcn_softc *sc; 256 int val; 257 258 sc = device_get_softc(dev); 259 260 if (sc->pcn_phyaddr && phy > sc->pcn_phyaddr) 261 return(0); 262 263 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 264 val = pcn_bcr_read(sc, PCN_BCR_MIIDATA) & 0xFFFF; 265 if (val == 0xFFFF) 266 return(0); 267 268 sc->pcn_phyaddr = phy; 269 270 return(val); 271} 272 273static int 274pcn_miibus_writereg(dev, phy, reg, data) 275 device_t dev; 276 int phy, reg, data; 277{ 278 struct pcn_softc *sc; 279 280 sc = device_get_softc(dev); 281 282 pcn_bcr_write(sc, PCN_BCR_MIIADDR, reg | (phy << 5)); 283 pcn_bcr_write(sc, PCN_BCR_MIIDATA, data); 284 285 return(0); 286} 287 288static void 289pcn_miibus_statchg(dev) 290 device_t dev; 291{ 292 struct pcn_softc *sc; 293 struct mii_data *mii; 294 295 sc = device_get_softc(dev); 296 mii = device_get_softc(sc->pcn_miibus); 297 298 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 299 PCN_BCR_SETBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 300 } else { 301 PCN_BCR_CLRBIT(sc, PCN_BCR_DUPLEX, PCN_DUPLEX_FDEN); 302 } 303 304 return; 305} 306 307#define DC_POLY 0xEDB88320 308 309static u_int32_t 310pcn_crc(addr) 311 caddr_t addr; 312{ 313 u_int32_t idx, bit, data, crc; 314 315 /* Compute CRC for the address value. */ 316 crc = 0xFFFFFFFF; /* initial value */ 317 318 for (idx = 0; idx < 6; idx++) { 319 for (data = *addr++, bit = 0; bit < 8; bit++, data >>= 1) 320 crc = (crc >> 1) ^ (((crc ^ data) & 1) ? DC_POLY : 0); 321 } 322 323 return ((crc >> 26) & 0x3F); 324} 325 326static void 327pcn_setmulti(sc) 328 struct pcn_softc *sc; 329{ 330 struct ifnet *ifp; 331 struct ifmultiaddr *ifma; 332 u_int32_t h, i; 333 u_int16_t hashes[4] = { 0, 0, 0, 0 }; 334 335 ifp = &sc->arpcom.ac_if; 336 337 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 338 339 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 340 for (i = 0; i < 4; i++) 341 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0xFFFF); 342 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 343 return; 344 } 345 346 /* first, zot all the existing hash bits */ 347 for (i = 0; i < 4; i++) 348 pcn_csr_write(sc, PCN_CSR_MAR0 + i, 0); 349 350 /* now program new ones */ 351 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 352 if (ifma->ifma_addr->sa_family != AF_LINK) 353 continue; 354 h = pcn_crc(LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 355 hashes[h >> 4] |= 1 << (h & 0xF); 356 } 357 358 for (i = 0; i < 4; i++) 359 pcn_csr_write(sc, PCN_CSR_MAR0 + i, hashes[i]); 360 361 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, PCN_EXTCTL1_SPND); 362 363 return; 364} 365 366static void 367pcn_reset(sc) 368 struct pcn_softc *sc; 369{ 370 /* 371 * Issue a reset by reading from the RESET register. 372 * Note that we don't know if the chip is operating in 373 * 16-bit or 32-bit mode at this point, so we attempt 374 * to reset the chip both ways. If one fails, the other 375 * will succeed. 376 */ 377 CSR_READ_2(sc, PCN_IO16_RESET); 378 CSR_READ_4(sc, PCN_IO32_RESET); 379 380 /* Wait a little while for the chip to get its brains in order. */ 381 DELAY(1000); 382 383 /* Select 32-bit (DWIO) mode */ 384 CSR_WRITE_4(sc, PCN_IO32_RDP, 0); 385 386 /* Select software style 3. */ 387 pcn_bcr_write(sc, PCN_BCR_SSTYLE, PCN_SWSTYLE_PCNETPCI_BURST); 388 389 return; 390} 391 392/* 393 * Probe for an AMD chip. Check the PCI vendor and device 394 * IDs against our list and return a device name if we find a match. 395 */ 396static int 397pcn_probe(dev) 398 device_t dev; 399{ 400 struct pcn_type *t; 401 struct pcn_softc *sc; 402 int rid; 403 u_int32_t chip_id; 404 405 t = pcn_devs; 406 sc = device_get_softc(dev); 407 408 while(t->pcn_name != NULL) { 409 if ((pci_get_vendor(dev) == t->pcn_vid) && 410 (pci_get_device(dev) == t->pcn_did)) { 411 /* 412 * Temporarily map the I/O space 413 * so we can read the chip ID register. 414 */ 415 rid = PCN_RID; 416 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 417 0, ~0, 1, RF_ACTIVE); 418 if (sc->pcn_res == NULL) { 419 device_printf(dev, 420 "couldn't map ports/memory\n"); 421 return(ENXIO); 422 } 423 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 424 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 425 mtx_init(&sc->pcn_mtx, 426 device_get_nameunit(dev), MTX_NETWORK_LOCK, 427 MTX_DEF); 428 PCN_LOCK(sc); 429 /* 430 * Note: we can *NOT* put the chip into 431 * 32-bit mode yet. The lnc driver will only 432 * work in 16-bit mode, and once the chip 433 * goes into 32-bit mode, the only way to 434 * get it out again is with a hardware reset. 435 * So if pcn_probe() is called before the 436 * lnc driver's probe routine, the chip will 437 * be locked into 32-bit operation and the lnc 438 * driver will be unable to attach to it. 439 * Note II: if the chip happens to already 440 * be in 32-bit mode, we still need to check 441 * the chip ID, but first we have to detect 442 * 32-bit mode using only 16-bit operations. 443 * The safest way to do this is to read the 444 * PCI subsystem ID from BCR23/24 and compare 445 * that with the value read from PCI config 446 * space. 447 */ 448 chip_id = pcn_bcr_read16(sc, PCN_BCR_PCISUBSYSID); 449 chip_id <<= 16; 450 chip_id |= pcn_bcr_read16(sc, PCN_BCR_PCISUBVENID); 451 /* 452 * Note III: the test for 0x10001000 is a hack to 453 * pacify VMware, who's pseudo-PCnet interface is 454 * broken. Reading the subsystem register from PCI 455 * config space yeilds 0x00000000 while reading the 456 * same value from I/O space yeilds 0x10001000. It's 457 * not supposed to be that way. 458 */ 459 if (chip_id == pci_read_config(dev, 460 PCIR_SUBVEND_0, 4) || chip_id == 0x10001000) { 461 /* We're in 16-bit mode. */ 462 chip_id = pcn_csr_read16(sc, PCN_CSR_CHIPID1); 463 chip_id <<= 16; 464 chip_id |= pcn_csr_read16(sc, PCN_CSR_CHIPID0); 465 } else { 466 /* We're in 32-bit mode. */ 467 chip_id = pcn_csr_read(sc, PCN_CSR_CHIPID1); 468 chip_id <<= 16; 469 chip_id |= pcn_csr_read(sc, PCN_CSR_CHIPID0); 470 } 471 bus_release_resource(dev, PCN_RES, 472 PCN_RID, sc->pcn_res); 473 PCN_UNLOCK(sc); 474 mtx_destroy(&sc->pcn_mtx); 475 chip_id >>= 12; 476 sc->pcn_type = chip_id & PART_MASK; 477 switch(sc->pcn_type) { 478 case Am79C971: 479 case Am79C972: 480 case Am79C973: 481 case Am79C975: 482 case Am79C976: 483 case Am79C978: 484 break; 485 default: 486 return(ENXIO); 487 break; 488 } 489 device_set_desc(dev, t->pcn_name); 490 return(0); 491 } 492 t++; 493 } 494 495 return(ENXIO); 496} 497 498/* 499 * Attach the interface. Allocate softc structures, do ifmedia 500 * setup and ethernet/BPF attach. 501 */ 502static int 503pcn_attach(dev) 504 device_t dev; 505{ 506 u_int32_t eaddr[2]; 507 u_int32_t command; 508 struct pcn_softc *sc; 509 struct ifnet *ifp; 510 int unit, error = 0, rid; 511 512 sc = device_get_softc(dev); 513 unit = device_get_unit(dev); 514 515 /* Initialize our mutex. */ 516 mtx_init(&sc->pcn_mtx, device_get_nameunit(dev), MTX_NETWORK_LOCK, 517 MTX_DEF | MTX_RECURSE); 518 519 /* 520 * Handle power management nonsense. 521 */ 522 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 523 u_int32_t iobase, membase, irq; 524 525 /* Save important PCI config data. */ 526 iobase = pci_read_config(dev, PCN_PCI_LOIO, 4); 527 membase = pci_read_config(dev, PCN_PCI_LOMEM, 4); 528 irq = pci_read_config(dev, PCN_PCI_INTLINE, 4); 529 530 /* Reset the power state. */ 531 printf("pcn%d: chip is in D%d power mode " 532 "-- setting to D0\n", unit, 533 pci_get_powerstate(dev)); 534 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 535 536 /* Restore PCI config data. */ 537 pci_write_config(dev, PCN_PCI_LOIO, iobase, 4); 538 pci_write_config(dev, PCN_PCI_LOMEM, membase, 4); 539 pci_write_config(dev, PCN_PCI_INTLINE, irq, 4); 540 } 541 542 /* 543 * Map control/status registers. 544 */ 545 pci_enable_busmaster(dev); 546 547 rid = PCN_RID; 548 sc->pcn_res = bus_alloc_resource(dev, PCN_RES, &rid, 549 0, ~0, 1, RF_ACTIVE); 550 551 if (sc->pcn_res == NULL) { 552 printf("pcn%d: couldn't map ports/memory\n", unit); 553 error = ENXIO; 554 goto fail; 555 } 556 557 sc->pcn_btag = rman_get_bustag(sc->pcn_res); 558 sc->pcn_bhandle = rman_get_bushandle(sc->pcn_res); 559 560 /* Allocate interrupt */ 561 rid = 0; 562 sc->pcn_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 563 RF_SHAREABLE | RF_ACTIVE); 564 565 if (sc->pcn_irq == NULL) { 566 printf("pcn%d: couldn't map interrupt\n", unit); 567 error = ENXIO; 568 goto fail; 569 } 570 571 /* Reset the adapter. */ 572 pcn_reset(sc); 573 574 /* 575 * Get station address from the EEPROM. 576 */ 577 eaddr[0] = CSR_READ_4(sc, PCN_IO32_APROM00); 578 eaddr[1] = CSR_READ_4(sc, PCN_IO32_APROM01); 579 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 580 581 /* 582 * An AMD chip was detected. Inform the world. 583 */ 584 printf("pcn%d: Ethernet address: %6D\n", unit, 585 sc->arpcom.ac_enaddr, ":"); 586 587 sc->pcn_unit = unit; 588 callout_handle_init(&sc->pcn_stat_ch); 589 590 sc->pcn_ldata = contigmalloc(sizeof(struct pcn_list_data), M_DEVBUF, 591 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 592 593 if (sc->pcn_ldata == NULL) { 594 printf("pcn%d: no memory for list buffers!\n", unit); 595 error = ENXIO; 596 goto fail; 597 } 598 bzero(sc->pcn_ldata, sizeof(struct pcn_list_data)); 599 600 ifp = &sc->arpcom.ac_if; 601 ifp->if_softc = sc; 602 ifp->if_unit = unit; 603 ifp->if_name = "pcn"; 604 ifp->if_mtu = ETHERMTU; 605 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 606 ifp->if_ioctl = pcn_ioctl; 607 ifp->if_output = ether_output; 608 ifp->if_start = pcn_start; 609 ifp->if_watchdog = pcn_watchdog; 610 ifp->if_init = pcn_init; 611 ifp->if_baudrate = 10000000; 612 ifp->if_snd.ifq_maxlen = PCN_TX_LIST_CNT - 1; 613 614 /* 615 * Do MII setup. 616 */ 617 if (mii_phy_probe(dev, &sc->pcn_miibus, 618 pcn_ifmedia_upd, pcn_ifmedia_sts)) { 619 printf("pcn%d: MII without any PHY!\n", sc->pcn_unit); 620 error = ENXIO; 621 goto fail; 622 } 623 624 /* 625 * Call MI attach routine. 626 */ 627 ether_ifattach(ifp, (u_int8_t *) eaddr); 628 629 error = bus_setup_intr(dev, sc->pcn_irq, INTR_TYPE_NET, 630 pcn_intr, sc, &sc->pcn_intrhand); 631 632 if (error) { 633 printf("pcn%d: couldn't set up irq\n", unit); 634 goto fail; 635 } 636 637fail: 638 if (error) 639 pcn_detach(dev); 640 641 return(error); 642} 643 644static int 645pcn_detach(dev) 646 device_t dev; 647{ 648 struct pcn_softc *sc; 649 struct ifnet *ifp; 650 651 sc = device_get_softc(dev); 652 ifp = &sc->arpcom.ac_if; 653 654 KASSERT(mtx_initialized(&sc->pcn_mtx), ("pcn mutex not initialized")); 655 PCN_LOCK(sc); 656 657 if (device_is_alive(dev)) { 658 if (bus_child_present(dev)) { 659 pcn_reset(sc); 660 pcn_stop(sc); 661 } 662 ether_ifdetach(ifp); 663 device_delete_child(dev, sc->pcn_miibus); 664 bus_generic_detach(dev); 665 } 666 667 if (sc->pcn_intrhand) 668 bus_teardown_intr(dev, sc->pcn_irq, sc->pcn_intrhand); 669 if (sc->pcn_irq) 670 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->pcn_irq); 671 if (sc->pcn_res) 672 bus_release_resource(dev, PCN_RES, PCN_RID, sc->pcn_res); 673 674 if (sc->pcn_ldata) { 675 contigfree(sc->pcn_ldata, sizeof(struct pcn_list_data), 676 M_DEVBUF); 677 } 678 PCN_UNLOCK(sc); 679 680 mtx_destroy(&sc->pcn_mtx); 681 682 return(0); 683} 684 685/* 686 * Initialize the transmit descriptors. 687 */ 688static int 689pcn_list_tx_init(sc) 690 struct pcn_softc *sc; 691{ 692 struct pcn_list_data *ld; 693 struct pcn_ring_data *cd; 694 int i; 695 696 cd = &sc->pcn_cdata; 697 ld = sc->pcn_ldata; 698 699 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 700 cd->pcn_tx_chain[i] = NULL; 701 ld->pcn_tx_list[i].pcn_tbaddr = 0; 702 ld->pcn_tx_list[i].pcn_txctl = 0; 703 ld->pcn_tx_list[i].pcn_txstat = 0; 704 } 705 706 cd->pcn_tx_prod = cd->pcn_tx_cons = cd->pcn_tx_cnt = 0; 707 708 return(0); 709} 710 711 712/* 713 * Initialize the RX descriptors and allocate mbufs for them. 714 */ 715static int 716pcn_list_rx_init(sc) 717 struct pcn_softc *sc; 718{ 719 struct pcn_list_data *ld; 720 struct pcn_ring_data *cd; 721 int i; 722 723 ld = sc->pcn_ldata; 724 cd = &sc->pcn_cdata; 725 726 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 727 if (pcn_newbuf(sc, i, NULL) == ENOBUFS) 728 return(ENOBUFS); 729 } 730 731 cd->pcn_rx_prod = 0; 732 733 return(0); 734} 735 736/* 737 * Initialize an RX descriptor and attach an MBUF cluster. 738 */ 739static int 740pcn_newbuf(sc, idx, m) 741 struct pcn_softc *sc; 742 int idx; 743 struct mbuf *m; 744{ 745 struct mbuf *m_new = NULL; 746 struct pcn_rx_desc *c; 747 748 c = &sc->pcn_ldata->pcn_rx_list[idx]; 749 750 if (m == NULL) { 751 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 752 if (m_new == NULL) 753 return(ENOBUFS); 754 755 MCLGET(m_new, M_DONTWAIT); 756 if (!(m_new->m_flags & M_EXT)) { 757 m_freem(m_new); 758 return(ENOBUFS); 759 } 760 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 761 } else { 762 m_new = m; 763 m_new->m_len = m_new->m_pkthdr.len = MCLBYTES; 764 m_new->m_data = m_new->m_ext.ext_buf; 765 } 766 767 m_adj(m_new, ETHER_ALIGN); 768 769 sc->pcn_cdata.pcn_rx_chain[idx] = m_new; 770 c->pcn_rbaddr = vtophys(mtod(m_new, caddr_t)); 771 c->pcn_bufsz = (~(PCN_RXLEN) + 1) & PCN_RXLEN_BUFSZ; 772 c->pcn_bufsz |= PCN_RXLEN_MBO; 773 c->pcn_rxstat = PCN_RXSTAT_STP|PCN_RXSTAT_ENP|PCN_RXSTAT_OWN; 774 775 return(0); 776} 777 778/* 779 * A frame has been uploaded: pass the resulting mbuf chain up to 780 * the higher level protocols. 781 */ 782static void 783pcn_rxeof(sc) 784 struct pcn_softc *sc; 785{ 786 struct ether_header *eh; 787 struct mbuf *m; 788 struct ifnet *ifp; 789 struct pcn_rx_desc *cur_rx; 790 int i; 791 792 ifp = &sc->arpcom.ac_if; 793 i = sc->pcn_cdata.pcn_rx_prod; 794 795 while(PCN_OWN_RXDESC(&sc->pcn_ldata->pcn_rx_list[i])) { 796 cur_rx = &sc->pcn_ldata->pcn_rx_list[i]; 797 m = sc->pcn_cdata.pcn_rx_chain[i]; 798 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 799 800 /* 801 * If an error occurs, update stats, clear the 802 * status word and leave the mbuf cluster in place: 803 * it should simply get re-used next time this descriptor 804 * comes up in the ring. 805 */ 806 if (cur_rx->pcn_rxstat & PCN_RXSTAT_ERR) { 807 ifp->if_ierrors++; 808 pcn_newbuf(sc, i, m); 809 PCN_INC(i, PCN_RX_LIST_CNT); 810 continue; 811 } 812 813 if (pcn_newbuf(sc, i, NULL)) { 814 /* Ran out of mbufs; recycle this one. */ 815 pcn_newbuf(sc, i, m); 816 ifp->if_ierrors++; 817 PCN_INC(i, PCN_RX_LIST_CNT); 818 continue; 819 } 820 821 PCN_INC(i, PCN_RX_LIST_CNT); 822 823 /* No errors; receive the packet. */ 824 ifp->if_ipackets++; 825 eh = mtod(m, struct ether_header *); 826 m->m_len = m->m_pkthdr.len = 827 cur_rx->pcn_rxlen - ETHER_CRC_LEN; 828 m->m_pkthdr.rcvif = ifp; 829 830 (*ifp->if_input)(ifp, m); 831 } 832 833 sc->pcn_cdata.pcn_rx_prod = i; 834 835 return; 836} 837 838/* 839 * A frame was downloaded to the chip. It's safe for us to clean up 840 * the list buffers. 841 */ 842 843static void 844pcn_txeof(sc) 845 struct pcn_softc *sc; 846{ 847 struct pcn_tx_desc *cur_tx = NULL; 848 struct ifnet *ifp; 849 u_int32_t idx; 850 851 ifp = &sc->arpcom.ac_if; 852 853 /* 854 * Go through our tx list and free mbufs for those 855 * frames that have been transmitted. 856 */ 857 idx = sc->pcn_cdata.pcn_tx_cons; 858 while (idx != sc->pcn_cdata.pcn_tx_prod) { 859 cur_tx = &sc->pcn_ldata->pcn_tx_list[idx]; 860 861 if (!PCN_OWN_TXDESC(cur_tx)) 862 break; 863 864 if (!(cur_tx->pcn_txctl & PCN_TXCTL_ENP)) { 865 sc->pcn_cdata.pcn_tx_cnt--; 866 PCN_INC(idx, PCN_TX_LIST_CNT); 867 continue; 868 } 869 870 if (cur_tx->pcn_txctl & PCN_TXCTL_ERR) { 871 ifp->if_oerrors++; 872 if (cur_tx->pcn_txstat & PCN_TXSTAT_EXDEF) 873 ifp->if_collisions++; 874 if (cur_tx->pcn_txstat & PCN_TXSTAT_RTRY) 875 ifp->if_collisions++; 876 } 877 878 ifp->if_collisions += 879 cur_tx->pcn_txstat & PCN_TXSTAT_TRC; 880 881 ifp->if_opackets++; 882 if (sc->pcn_cdata.pcn_tx_chain[idx] != NULL) { 883 m_freem(sc->pcn_cdata.pcn_tx_chain[idx]); 884 sc->pcn_cdata.pcn_tx_chain[idx] = NULL; 885 } 886 887 sc->pcn_cdata.pcn_tx_cnt--; 888 PCN_INC(idx, PCN_TX_LIST_CNT); 889 } 890 891 if (idx != sc->pcn_cdata.pcn_tx_cons) { 892 /* Some buffers have been freed. */ 893 sc->pcn_cdata.pcn_tx_cons = idx; 894 ifp->if_flags &= ~IFF_OACTIVE; 895 } 896 ifp->if_timer = (sc->pcn_cdata.pcn_tx_cnt == 0) ? 0 : 5; 897 898 return; 899} 900 901static void 902pcn_tick(xsc) 903 void *xsc; 904{ 905 struct pcn_softc *sc; 906 struct mii_data *mii; 907 struct ifnet *ifp; 908 909 sc = xsc; 910 ifp = &sc->arpcom.ac_if; 911 PCN_LOCK(sc); 912 913 mii = device_get_softc(sc->pcn_miibus); 914 mii_tick(mii); 915 916 /* link just died */ 917 if (sc->pcn_link & !(mii->mii_media_status & IFM_ACTIVE)) 918 sc->pcn_link = 0; 919 920 /* link just came up, restart */ 921 if (!sc->pcn_link && mii->mii_media_status & IFM_ACTIVE && 922 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 923 sc->pcn_link++; 924 if (ifp->if_snd.ifq_head != NULL) 925 pcn_start(ifp); 926 } 927 928 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 929 930 PCN_UNLOCK(sc); 931 932 return; 933} 934 935static void 936pcn_intr(arg) 937 void *arg; 938{ 939 struct pcn_softc *sc; 940 struct ifnet *ifp; 941 u_int32_t status; 942 943 sc = arg; 944 ifp = &sc->arpcom.ac_if; 945 946 /* Supress unwanted interrupts */ 947 if (!(ifp->if_flags & IFF_UP)) { 948 pcn_stop(sc); 949 return; 950 } 951 952 PCN_LOCK(sc); 953 954 CSR_WRITE_4(sc, PCN_IO32_RAP, PCN_CSR_CSR); 955 956 while ((status = CSR_READ_4(sc, PCN_IO32_RDP)) & PCN_CSR_INTR) { 957 CSR_WRITE_4(sc, PCN_IO32_RDP, status); 958 959 if (status & PCN_CSR_RINT) 960 pcn_rxeof(sc); 961 962 if (status & PCN_CSR_TINT) 963 pcn_txeof(sc); 964 965 if (status & PCN_CSR_ERR) { 966 pcn_init(sc); 967 break; 968 } 969 } 970 971 if (ifp->if_snd.ifq_head != NULL) 972 pcn_start(ifp); 973 974 PCN_UNLOCK(sc); 975 return; 976} 977 978/* 979 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 980 * pointers to the fragment pointers. 981 */ 982static int 983pcn_encap(sc, m_head, txidx) 984 struct pcn_softc *sc; 985 struct mbuf *m_head; 986 u_int32_t *txidx; 987{ 988 struct pcn_tx_desc *f = NULL; 989 struct mbuf *m; 990 int frag, cur, cnt = 0; 991 992 /* 993 * Start packing the mbufs in this chain into 994 * the fragment pointers. Stop when we run out 995 * of fragments or hit the end of the mbuf chain. 996 */ 997 m = m_head; 998 cur = frag = *txidx; 999 1000 for (m = m_head; m != NULL; m = m->m_next) { 1001 if (m->m_len != 0) { 1002 if ((PCN_TX_LIST_CNT - 1003 (sc->pcn_cdata.pcn_tx_cnt + cnt)) < 2) 1004 return(ENOBUFS); 1005 f = &sc->pcn_ldata->pcn_tx_list[frag]; 1006 f->pcn_txctl = (~(m->m_len) + 1) & PCN_TXCTL_BUFSZ; 1007 f->pcn_txctl |= PCN_TXCTL_MBO; 1008 f->pcn_tbaddr = vtophys(mtod(m, vm_offset_t)); 1009 if (cnt == 0) 1010 f->pcn_txctl |= PCN_TXCTL_STP; 1011 else 1012 f->pcn_txctl |= PCN_TXCTL_OWN; 1013 cur = frag; 1014 PCN_INC(frag, PCN_TX_LIST_CNT); 1015 cnt++; 1016 } 1017 } 1018 1019 if (m != NULL) 1020 return(ENOBUFS); 1021 1022 sc->pcn_cdata.pcn_tx_chain[cur] = m_head; 1023 sc->pcn_ldata->pcn_tx_list[cur].pcn_txctl |= 1024 PCN_TXCTL_ENP|PCN_TXCTL_ADD_FCS|PCN_TXCTL_MORE_LTINT; 1025 sc->pcn_ldata->pcn_tx_list[*txidx].pcn_txctl |= PCN_TXCTL_OWN; 1026 sc->pcn_cdata.pcn_tx_cnt += cnt; 1027 *txidx = frag; 1028 1029 return(0); 1030} 1031 1032/* 1033 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1034 * to the mbuf data regions directly in the transmit lists. We also save a 1035 * copy of the pointers since the transmit list fragment pointers are 1036 * physical addresses. 1037 */ 1038static void 1039pcn_start(ifp) 1040 struct ifnet *ifp; 1041{ 1042 struct pcn_softc *sc; 1043 struct mbuf *m_head = NULL; 1044 u_int32_t idx; 1045 1046 sc = ifp->if_softc; 1047 1048 PCN_LOCK(sc); 1049 1050 if (!sc->pcn_link) { 1051 PCN_UNLOCK(sc); 1052 return; 1053 } 1054 1055 idx = sc->pcn_cdata.pcn_tx_prod; 1056 1057 if (ifp->if_flags & IFF_OACTIVE) { 1058 PCN_UNLOCK(sc); 1059 return; 1060 } 1061 1062 while(sc->pcn_cdata.pcn_tx_chain[idx] == NULL) { 1063 IF_DEQUEUE(&ifp->if_snd, m_head); 1064 if (m_head == NULL) 1065 break; 1066 1067 if (pcn_encap(sc, m_head, &idx)) { 1068 IF_PREPEND(&ifp->if_snd, m_head); 1069 ifp->if_flags |= IFF_OACTIVE; 1070 break; 1071 } 1072 1073 /* 1074 * If there's a BPF listener, bounce a copy of this frame 1075 * to him. 1076 */ 1077 BPF_MTAP(ifp, m_head); 1078 1079 } 1080 1081 /* Transmit */ 1082 sc->pcn_cdata.pcn_tx_prod = idx; 1083 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_TX|PCN_CSR_INTEN); 1084 1085 /* 1086 * Set a timeout in case the chip goes out to lunch. 1087 */ 1088 ifp->if_timer = 5; 1089 1090 PCN_UNLOCK(sc); 1091 1092 return; 1093} 1094 1095static void 1096pcn_setfilt(ifp) 1097 struct ifnet *ifp; 1098{ 1099 struct pcn_softc *sc; 1100 1101 sc = ifp->if_softc; 1102 1103 /* If we want promiscuous mode, set the allframes bit. */ 1104 if (ifp->if_flags & IFF_PROMISC) { 1105 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1106 } else { 1107 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_PROMISC); 1108 } 1109 1110 /* Set the capture broadcast bit to capture broadcast frames. */ 1111 if (ifp->if_flags & IFF_BROADCAST) { 1112 PCN_CSR_CLRBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1113 } else { 1114 PCN_CSR_SETBIT(sc, PCN_CSR_MODE, PCN_MODE_RXNOBROAD); 1115 } 1116 1117 return; 1118} 1119 1120static void 1121pcn_init(xsc) 1122 void *xsc; 1123{ 1124 struct pcn_softc *sc = xsc; 1125 struct ifnet *ifp = &sc->arpcom.ac_if; 1126 struct mii_data *mii = NULL; 1127 1128 PCN_LOCK(sc); 1129 1130 /* 1131 * Cancel pending I/O and free all RX/TX buffers. 1132 */ 1133 pcn_stop(sc); 1134 pcn_reset(sc); 1135 1136 mii = device_get_softc(sc->pcn_miibus); 1137 1138 /* Set MAC address */ 1139 pcn_csr_write(sc, PCN_CSR_PAR0, 1140 ((u_int16_t *)sc->arpcom.ac_enaddr)[0]); 1141 pcn_csr_write(sc, PCN_CSR_PAR1, 1142 ((u_int16_t *)sc->arpcom.ac_enaddr)[1]); 1143 pcn_csr_write(sc, PCN_CSR_PAR2, 1144 ((u_int16_t *)sc->arpcom.ac_enaddr)[2]); 1145 1146 /* Init circular RX list. */ 1147 if (pcn_list_rx_init(sc) == ENOBUFS) { 1148 printf("pcn%d: initialization failed: no " 1149 "memory for rx buffers\n", sc->pcn_unit); 1150 pcn_stop(sc); 1151 PCN_UNLOCK(sc); 1152 return; 1153 } 1154 1155 /* 1156 * Init tx descriptors. 1157 */ 1158 pcn_list_tx_init(sc); 1159 1160 /* Set up the mode register. */ 1161 pcn_csr_write(sc, PCN_CSR_MODE, PCN_PORT_MII); 1162 1163 /* Set up RX filter. */ 1164 pcn_setfilt(ifp); 1165 1166 /* 1167 * Load the multicast filter. 1168 */ 1169 pcn_setmulti(sc); 1170 1171 /* 1172 * Load the addresses of the RX and TX lists. 1173 */ 1174 pcn_csr_write(sc, PCN_CSR_RXADDR0, 1175 vtophys(&sc->pcn_ldata->pcn_rx_list[0]) & 0xFFFF); 1176 pcn_csr_write(sc, PCN_CSR_RXADDR1, 1177 (vtophys(&sc->pcn_ldata->pcn_rx_list[0]) >> 16) & 0xFFFF); 1178 pcn_csr_write(sc, PCN_CSR_TXADDR0, 1179 vtophys(&sc->pcn_ldata->pcn_tx_list[0]) & 0xFFFF); 1180 pcn_csr_write(sc, PCN_CSR_TXADDR1, 1181 (vtophys(&sc->pcn_ldata->pcn_tx_list[0]) >> 16) & 0xFFFF); 1182 1183 /* Set the RX and TX ring sizes. */ 1184 pcn_csr_write(sc, PCN_CSR_RXRINGLEN, (~PCN_RX_LIST_CNT) + 1); 1185 pcn_csr_write(sc, PCN_CSR_TXRINGLEN, (~PCN_TX_LIST_CNT) + 1); 1186 1187 /* We're not using the initialization block. */ 1188 pcn_csr_write(sc, PCN_CSR_IAB1, 0); 1189 1190 /* Enable fast suspend mode. */ 1191 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL2, PCN_EXTCTL2_FASTSPNDE); 1192 1193 /* 1194 * Enable burst read and write. Also set the no underflow 1195 * bit. This will avoid transmit underruns in certain 1196 * conditions while still providing decent performance. 1197 */ 1198 PCN_BCR_SETBIT(sc, PCN_BCR_BUSCTL, PCN_BUSCTL_NOUFLOW| 1199 PCN_BUSCTL_BREAD|PCN_BUSCTL_BWRITE); 1200 1201 /* Enable graceful recovery from underflow. */ 1202 PCN_CSR_SETBIT(sc, PCN_CSR_IMR, PCN_IMR_DXSUFLO); 1203 1204 /* Enable auto-padding of short TX frames. */ 1205 PCN_CSR_SETBIT(sc, PCN_CSR_TFEAT, PCN_TFEAT_PAD_TX); 1206 1207 /* Disable MII autoneg (we handle this ourselves). */ 1208 PCN_BCR_SETBIT(sc, PCN_BCR_MIICTL, PCN_MIICTL_DANAS); 1209 1210 if (sc->pcn_type == Am79C978) 1211 pcn_bcr_write(sc, PCN_BCR_PHYSEL, 1212 PCN_PHYSEL_PCNET|PCN_PHY_HOMEPNA); 1213 1214 /* Enable interrupts and start the controller running. */ 1215 pcn_csr_write(sc, PCN_CSR_CSR, PCN_CSR_INTEN|PCN_CSR_START); 1216 1217 mii_mediachg(mii); 1218 1219 ifp->if_flags |= IFF_RUNNING; 1220 ifp->if_flags &= ~IFF_OACTIVE; 1221 1222 sc->pcn_stat_ch = timeout(pcn_tick, sc, hz); 1223 PCN_UNLOCK(sc); 1224 1225 return; 1226} 1227 1228/* 1229 * Set media options. 1230 */ 1231static int 1232pcn_ifmedia_upd(ifp) 1233 struct ifnet *ifp; 1234{ 1235 struct pcn_softc *sc; 1236 struct mii_data *mii; 1237 1238 sc = ifp->if_softc; 1239 mii = device_get_softc(sc->pcn_miibus); 1240 1241 sc->pcn_link = 0; 1242 if (mii->mii_instance) { 1243 struct mii_softc *miisc; 1244 LIST_FOREACH(miisc, &mii->mii_phys, mii_list) 1245 mii_phy_reset(miisc); 1246 } 1247 mii_mediachg(mii); 1248 1249 return(0); 1250} 1251 1252/* 1253 * Report current media status. 1254 */ 1255static void 1256pcn_ifmedia_sts(ifp, ifmr) 1257 struct ifnet *ifp; 1258 struct ifmediareq *ifmr; 1259{ 1260 struct pcn_softc *sc; 1261 struct mii_data *mii; 1262 1263 sc = ifp->if_softc; 1264 1265 mii = device_get_softc(sc->pcn_miibus); 1266 mii_pollstat(mii); 1267 ifmr->ifm_active = mii->mii_media_active; 1268 ifmr->ifm_status = mii->mii_media_status; 1269 1270 return; 1271} 1272 1273static int 1274pcn_ioctl(ifp, command, data) 1275 struct ifnet *ifp; 1276 u_long command; 1277 caddr_t data; 1278{ 1279 struct pcn_softc *sc = ifp->if_softc; 1280 struct ifreq *ifr = (struct ifreq *) data; 1281 struct mii_data *mii = NULL; 1282 int error = 0; 1283 1284 PCN_LOCK(sc); 1285 1286 switch(command) { 1287 case SIOCSIFFLAGS: 1288 if (ifp->if_flags & IFF_UP) { 1289 if (ifp->if_flags & IFF_RUNNING && 1290 ifp->if_flags & IFF_PROMISC && 1291 !(sc->pcn_if_flags & IFF_PROMISC)) { 1292 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1293 PCN_EXTCTL1_SPND); 1294 pcn_setfilt(ifp); 1295 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1296 PCN_EXTCTL1_SPND); 1297 pcn_csr_write(sc, PCN_CSR_CSR, 1298 PCN_CSR_INTEN|PCN_CSR_START); 1299 } else if (ifp->if_flags & IFF_RUNNING && 1300 !(ifp->if_flags & IFF_PROMISC) && 1301 sc->pcn_if_flags & IFF_PROMISC) { 1302 PCN_CSR_SETBIT(sc, PCN_CSR_EXTCTL1, 1303 PCN_EXTCTL1_SPND); 1304 pcn_setfilt(ifp); 1305 PCN_CSR_CLRBIT(sc, PCN_CSR_EXTCTL1, 1306 PCN_EXTCTL1_SPND); 1307 pcn_csr_write(sc, PCN_CSR_CSR, 1308 PCN_CSR_INTEN|PCN_CSR_START); 1309 } else if (!(ifp->if_flags & IFF_RUNNING)) 1310 pcn_init(sc); 1311 } else { 1312 if (ifp->if_flags & IFF_RUNNING) 1313 pcn_stop(sc); 1314 } 1315 sc->pcn_if_flags = ifp->if_flags; 1316 error = 0; 1317 break; 1318 case SIOCADDMULTI: 1319 case SIOCDELMULTI: 1320 pcn_setmulti(sc); 1321 error = 0; 1322 break; 1323 case SIOCGIFMEDIA: 1324 case SIOCSIFMEDIA: 1325 mii = device_get_softc(sc->pcn_miibus); 1326 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1327 break; 1328 default: 1329 error = ether_ioctl(ifp, command, data); 1330 break; 1331 } 1332 1333 PCN_UNLOCK(sc); 1334 1335 return(error); 1336} 1337 1338static void 1339pcn_watchdog(ifp) 1340 struct ifnet *ifp; 1341{ 1342 struct pcn_softc *sc; 1343 1344 sc = ifp->if_softc; 1345 1346 PCN_LOCK(sc); 1347 1348 ifp->if_oerrors++; 1349 printf("pcn%d: watchdog timeout\n", sc->pcn_unit); 1350 1351 pcn_stop(sc); 1352 pcn_reset(sc); 1353 pcn_init(sc); 1354 1355 if (ifp->if_snd.ifq_head != NULL) 1356 pcn_start(ifp); 1357 1358 PCN_UNLOCK(sc); 1359 1360 return; 1361} 1362 1363/* 1364 * Stop the adapter and free any mbufs allocated to the 1365 * RX and TX lists. 1366 */ 1367static void 1368pcn_stop(sc) 1369 struct pcn_softc *sc; 1370{ 1371 register int i; 1372 struct ifnet *ifp; 1373 1374 ifp = &sc->arpcom.ac_if; 1375 PCN_LOCK(sc); 1376 ifp->if_timer = 0; 1377 1378 untimeout(pcn_tick, sc, sc->pcn_stat_ch); 1379 1380 /* Turn off interrupts */ 1381 PCN_CSR_CLRBIT(sc, PCN_CSR_CSR, PCN_CSR_INTEN); 1382 /* Stop adapter */ 1383 PCN_CSR_SETBIT(sc, PCN_CSR_CSR, PCN_CSR_STOP); 1384 sc->pcn_link = 0; 1385 1386 /* 1387 * Free data in the RX lists. 1388 */ 1389 for (i = 0; i < PCN_RX_LIST_CNT; i++) { 1390 if (sc->pcn_cdata.pcn_rx_chain[i] != NULL) { 1391 m_freem(sc->pcn_cdata.pcn_rx_chain[i]); 1392 sc->pcn_cdata.pcn_rx_chain[i] = NULL; 1393 } 1394 } 1395 bzero((char *)&sc->pcn_ldata->pcn_rx_list, 1396 sizeof(sc->pcn_ldata->pcn_rx_list)); 1397 1398 /* 1399 * Free the TX list buffers. 1400 */ 1401 for (i = 0; i < PCN_TX_LIST_CNT; i++) { 1402 if (sc->pcn_cdata.pcn_tx_chain[i] != NULL) { 1403 m_freem(sc->pcn_cdata.pcn_tx_chain[i]); 1404 sc->pcn_cdata.pcn_tx_chain[i] = NULL; 1405 } 1406 } 1407 1408 bzero((char *)&sc->pcn_ldata->pcn_tx_list, 1409 sizeof(sc->pcn_ldata->pcn_tx_list)); 1410 1411 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1412 PCN_UNLOCK(sc); 1413 1414 return; 1415} 1416 1417/* 1418 * Stop all chip I/O so that the kernel's probe routines don't 1419 * get confused by errant DMAs when rebooting. 1420 */ 1421static void 1422pcn_shutdown(dev) 1423 device_t dev; 1424{ 1425 struct pcn_softc *sc; 1426 1427 sc = device_get_softc(dev); 1428 1429 PCN_LOCK(sc); 1430 pcn_reset(sc); 1431 pcn_stop(sc); 1432 PCN_UNLOCK(sc); 1433 1434 return; 1435} 1436