pcivar.h revision 279470
1/*- 2 * Copyright (c) 1997, Stefan Esser <se@freebsd.org> 3 * All rights reserved. 4 * 5 * Redistribution and use in source and binary forms, with or without 6 * modification, are permitted provided that the following conditions 7 * are met: 8 * 1. Redistributions of source code must retain the above copyright 9 * notice unmodified, this list of conditions, and the following 10 * disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 16 * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 17 * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 18 * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 19 * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 20 * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 21 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 22 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 23 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 24 * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 25 * 26 * $FreeBSD: stable/10/sys/dev/pci/pcivar.h 279470 2015-03-01 04:22:06Z rstone $ 27 * 28 */ 29 30#ifndef _PCIVAR_H_ 31#define _PCIVAR_H_ 32 33#include <sys/queue.h> 34 35/* some PCI bus constants */ 36#define PCI_MAXMAPS_0 6 /* max. no. of memory/port maps */ 37#define PCI_MAXMAPS_1 2 /* max. no. of maps for PCI to PCI bridge */ 38#define PCI_MAXMAPS_2 1 /* max. no. of maps for CardBus bridge */ 39 40typedef uint64_t pci_addr_t; 41 42/* Interesting values for PCI power management */ 43struct pcicfg_pp { 44 uint16_t pp_cap; /* PCI power management capabilities */ 45 uint8_t pp_status; /* conf. space addr. of PM control/status reg */ 46 uint8_t pp_bse; /* conf. space addr. of PM BSE reg */ 47 uint8_t pp_data; /* conf. space addr. of PM data reg */ 48}; 49 50struct pci_map { 51 pci_addr_t pm_value; /* Raw BAR value */ 52 pci_addr_t pm_size; 53 uint8_t pm_reg; 54 STAILQ_ENTRY(pci_map) pm_link; 55}; 56 57struct vpd_readonly { 58 char keyword[2]; 59 char *value; 60 int len; 61}; 62 63struct vpd_write { 64 char keyword[2]; 65 char *value; 66 int start; 67 int len; 68}; 69 70struct pcicfg_vpd { 71 uint8_t vpd_reg; /* base register, + 2 for addr, + 4 data */ 72 char vpd_cached; 73 char *vpd_ident; /* string identifier */ 74 int vpd_rocnt; 75 struct vpd_readonly *vpd_ros; 76 int vpd_wcnt; 77 struct vpd_write *vpd_w; 78}; 79 80/* Interesting values for PCI MSI */ 81struct pcicfg_msi { 82 uint16_t msi_ctrl; /* Message Control */ 83 uint8_t msi_location; /* Offset of MSI capability registers. */ 84 uint8_t msi_msgnum; /* Number of messages */ 85 int msi_alloc; /* Number of allocated messages. */ 86 uint64_t msi_addr; /* Contents of address register. */ 87 uint16_t msi_data; /* Contents of data register. */ 88 u_int msi_handlers; 89}; 90 91/* Interesting values for PCI MSI-X */ 92struct msix_vector { 93 uint64_t mv_address; /* Contents of address register. */ 94 uint32_t mv_data; /* Contents of data register. */ 95 int mv_irq; 96}; 97 98struct msix_table_entry { 99 u_int mte_vector; /* 1-based index into msix_vectors array. */ 100 u_int mte_handlers; 101}; 102 103struct pcicfg_msix { 104 uint16_t msix_ctrl; /* Message Control */ 105 uint16_t msix_msgnum; /* Number of messages */ 106 uint8_t msix_location; /* Offset of MSI-X capability registers. */ 107 uint8_t msix_table_bar; /* BAR containing vector table. */ 108 uint8_t msix_pba_bar; /* BAR containing PBA. */ 109 uint32_t msix_table_offset; 110 uint32_t msix_pba_offset; 111 int msix_alloc; /* Number of allocated vectors. */ 112 int msix_table_len; /* Length of virtual table. */ 113 struct msix_table_entry *msix_table; /* Virtual table. */ 114 struct msix_vector *msix_vectors; /* Array of allocated vectors. */ 115 struct resource *msix_table_res; /* Resource containing vector table. */ 116 struct resource *msix_pba_res; /* Resource containing PBA. */ 117}; 118 119/* Interesting values for HyperTransport */ 120struct pcicfg_ht { 121 uint8_t ht_slave; /* Non-zero if device is an HT slave. */ 122 uint8_t ht_msimap; /* Offset of MSI mapping cap registers. */ 123 uint16_t ht_msictrl; /* MSI mapping control */ 124 uint64_t ht_msiaddr; /* MSI mapping base address */ 125}; 126 127/* Interesting values for PCI-express */ 128struct pcicfg_pcie { 129 uint8_t pcie_location; /* Offset of PCI-e capability registers. */ 130 uint8_t pcie_type; /* Device type. */ 131 uint16_t pcie_flags; /* Device capabilities register. */ 132 uint16_t pcie_device_ctl; /* Device control register. */ 133 uint16_t pcie_link_ctl; /* Link control register. */ 134 uint16_t pcie_slot_ctl; /* Slot control register. */ 135 uint16_t pcie_root_ctl; /* Root control register. */ 136 uint16_t pcie_device_ctl2; /* Second device control register. */ 137 uint16_t pcie_link_ctl2; /* Second link control register. */ 138 uint16_t pcie_slot_ctl2; /* Second slot control register. */ 139}; 140 141struct pcicfg_pcix { 142 uint16_t pcix_command; 143 uint8_t pcix_location; /* Offset of PCI-X capability registers. */ 144}; 145 146/* config header information common to all header types */ 147typedef struct pcicfg { 148 struct device *dev; /* device which owns this */ 149 150 STAILQ_HEAD(, pci_map) maps; /* BARs */ 151 152 uint16_t subvendor; /* card vendor ID */ 153 uint16_t subdevice; /* card device ID, assigned by card vendor */ 154 uint16_t vendor; /* chip vendor ID */ 155 uint16_t device; /* chip device ID, assigned by chip vendor */ 156 157 uint16_t cmdreg; /* disable/enable chip and PCI options */ 158 uint16_t statreg; /* supported PCI features and error state */ 159 160 uint8_t baseclass; /* chip PCI class */ 161 uint8_t subclass; /* chip PCI subclass */ 162 uint8_t progif; /* chip PCI programming interface */ 163 uint8_t revid; /* chip revision ID */ 164 165 uint8_t hdrtype; /* chip config header type */ 166 uint8_t cachelnsz; /* cache line size in 4byte units */ 167 uint8_t intpin; /* PCI interrupt pin */ 168 uint8_t intline; /* interrupt line (IRQ for PC arch) */ 169 170 uint8_t mingnt; /* min. useful bus grant time in 250ns units */ 171 uint8_t maxlat; /* max. tolerated bus grant latency in 250ns */ 172 uint8_t lattimer; /* latency timer in units of 30ns bus cycles */ 173 174 uint8_t mfdev; /* multi-function device (from hdrtype reg) */ 175 uint8_t nummaps; /* actual number of PCI maps used */ 176 177 uint32_t domain; /* PCI domain */ 178 uint8_t bus; /* config space bus address */ 179 uint8_t slot; /* config space slot address */ 180 uint8_t func; /* config space function number */ 181 182 struct pcicfg_pp pp; /* Power management */ 183 struct pcicfg_vpd vpd; /* Vital product data */ 184 struct pcicfg_msi msi; /* PCI MSI */ 185 struct pcicfg_msix msix; /* PCI MSI-X */ 186 struct pcicfg_ht ht; /* HyperTransport */ 187 struct pcicfg_pcie pcie; /* PCI Express */ 188 struct pcicfg_pcix pcix; /* PCI-X */ 189} pcicfgregs; 190 191/* additional type 1 device config header information (PCI to PCI bridge) */ 192 193#define PCI_PPBMEMBASE(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) & ~0xfffff) 194#define PCI_PPBMEMLIMIT(h,l) ((((pci_addr_t)(h) << 32) + ((l)<<16)) | 0xfffff) 195#define PCI_PPBIOBASE(h,l) ((((h)<<16) + ((l)<<8)) & ~0xfff) 196#define PCI_PPBIOLIMIT(h,l) ((((h)<<16) + ((l)<<8)) | 0xfff) 197 198typedef struct { 199 pci_addr_t pmembase; /* base address of prefetchable memory */ 200 pci_addr_t pmemlimit; /* topmost address of prefetchable memory */ 201 uint32_t membase; /* base address of memory window */ 202 uint32_t memlimit; /* topmost address of memory window */ 203 uint32_t iobase; /* base address of port window */ 204 uint32_t iolimit; /* topmost address of port window */ 205 uint16_t secstat; /* secondary bus status register */ 206 uint16_t bridgectl; /* bridge control register */ 207 uint8_t seclat; /* CardBus latency timer */ 208} pcih1cfgregs; 209 210/* additional type 2 device config header information (CardBus bridge) */ 211 212typedef struct { 213 uint32_t membase0; /* base address of memory window */ 214 uint32_t memlimit0; /* topmost address of memory window */ 215 uint32_t membase1; /* base address of memory window */ 216 uint32_t memlimit1; /* topmost address of memory window */ 217 uint32_t iobase0; /* base address of port window */ 218 uint32_t iolimit0; /* topmost address of port window */ 219 uint32_t iobase1; /* base address of port window */ 220 uint32_t iolimit1; /* topmost address of port window */ 221 uint32_t pccardif; /* PC Card 16bit IF legacy more base addr. */ 222 uint16_t secstat; /* secondary bus status register */ 223 uint16_t bridgectl; /* bridge control register */ 224 uint8_t seclat; /* CardBus latency timer */ 225} pcih2cfgregs; 226 227extern uint32_t pci_numdevs; 228 229/* Only if the prerequisites are present */ 230#if defined(_SYS_BUS_H_) && defined(_SYS_PCIIO_H_) 231struct pci_devinfo { 232 STAILQ_ENTRY(pci_devinfo) pci_links; 233 struct resource_list resources; 234 pcicfgregs cfg; 235 struct pci_conf conf; 236}; 237#endif 238 239#ifdef _SYS_BUS_H_ 240 241#include "pci_if.h" 242 243enum pci_device_ivars { 244 PCI_IVAR_SUBVENDOR, 245 PCI_IVAR_SUBDEVICE, 246 PCI_IVAR_VENDOR, 247 PCI_IVAR_DEVICE, 248 PCI_IVAR_DEVID, 249 PCI_IVAR_CLASS, 250 PCI_IVAR_SUBCLASS, 251 PCI_IVAR_PROGIF, 252 PCI_IVAR_REVID, 253 PCI_IVAR_INTPIN, 254 PCI_IVAR_IRQ, 255 PCI_IVAR_DOMAIN, 256 PCI_IVAR_BUS, 257 PCI_IVAR_SLOT, 258 PCI_IVAR_FUNCTION, 259 PCI_IVAR_ETHADDR, 260 PCI_IVAR_CMDREG, 261 PCI_IVAR_CACHELNSZ, 262 PCI_IVAR_MINGNT, 263 PCI_IVAR_MAXLAT, 264 PCI_IVAR_LATTIMER 265}; 266 267/* 268 * Simplified accessors for pci devices 269 */ 270#define PCI_ACCESSOR(var, ivar, type) \ 271 __BUS_ACCESSOR(pci, var, PCI, ivar, type) 272 273PCI_ACCESSOR(subvendor, SUBVENDOR, uint16_t) 274PCI_ACCESSOR(subdevice, SUBDEVICE, uint16_t) 275PCI_ACCESSOR(vendor, VENDOR, uint16_t) 276PCI_ACCESSOR(device, DEVICE, uint16_t) 277PCI_ACCESSOR(devid, DEVID, uint32_t) 278PCI_ACCESSOR(class, CLASS, uint8_t) 279PCI_ACCESSOR(subclass, SUBCLASS, uint8_t) 280PCI_ACCESSOR(progif, PROGIF, uint8_t) 281PCI_ACCESSOR(revid, REVID, uint8_t) 282PCI_ACCESSOR(intpin, INTPIN, uint8_t) 283PCI_ACCESSOR(irq, IRQ, uint8_t) 284PCI_ACCESSOR(domain, DOMAIN, uint32_t) 285PCI_ACCESSOR(bus, BUS, uint8_t) 286PCI_ACCESSOR(slot, SLOT, uint8_t) 287PCI_ACCESSOR(function, FUNCTION, uint8_t) 288PCI_ACCESSOR(ether, ETHADDR, uint8_t *) 289PCI_ACCESSOR(cmdreg, CMDREG, uint8_t) 290PCI_ACCESSOR(cachelnsz, CACHELNSZ, uint8_t) 291PCI_ACCESSOR(mingnt, MINGNT, uint8_t) 292PCI_ACCESSOR(maxlat, MAXLAT, uint8_t) 293PCI_ACCESSOR(lattimer, LATTIMER, uint8_t) 294 295#undef PCI_ACCESSOR 296 297/* 298 * Operations on configuration space. 299 */ 300static __inline uint32_t 301pci_read_config(device_t dev, int reg, int width) 302{ 303 return PCI_READ_CONFIG(device_get_parent(dev), dev, reg, width); 304} 305 306static __inline void 307pci_write_config(device_t dev, int reg, uint32_t val, int width) 308{ 309 PCI_WRITE_CONFIG(device_get_parent(dev), dev, reg, val, width); 310} 311 312/* 313 * Ivars for pci bridges. 314 */ 315 316/*typedef enum pci_device_ivars pcib_device_ivars;*/ 317enum pcib_device_ivars { 318 PCIB_IVAR_DOMAIN, 319 PCIB_IVAR_BUS 320}; 321 322#define PCIB_ACCESSOR(var, ivar, type) \ 323 __BUS_ACCESSOR(pcib, var, PCIB, ivar, type) 324 325PCIB_ACCESSOR(domain, DOMAIN, uint32_t) 326PCIB_ACCESSOR(bus, BUS, uint32_t) 327 328#undef PCIB_ACCESSOR 329 330/* 331 * PCI interrupt validation. Invalid interrupt values such as 0 or 128 332 * on i386 or other platforms should be mapped out in the MD pcireadconf 333 * code and not here, since the only MI invalid IRQ is 255. 334 */ 335#define PCI_INVALID_IRQ 255 336#define PCI_INTERRUPT_VALID(x) ((x) != PCI_INVALID_IRQ) 337 338/* 339 * Convenience functions. 340 * 341 * These should be used in preference to manually manipulating 342 * configuration space. 343 */ 344static __inline int 345pci_enable_busmaster(device_t dev) 346{ 347 return(PCI_ENABLE_BUSMASTER(device_get_parent(dev), dev)); 348} 349 350static __inline int 351pci_disable_busmaster(device_t dev) 352{ 353 return(PCI_DISABLE_BUSMASTER(device_get_parent(dev), dev)); 354} 355 356static __inline int 357pci_enable_io(device_t dev, int space) 358{ 359 return(PCI_ENABLE_IO(device_get_parent(dev), dev, space)); 360} 361 362static __inline int 363pci_disable_io(device_t dev, int space) 364{ 365 return(PCI_DISABLE_IO(device_get_parent(dev), dev, space)); 366} 367 368static __inline int 369pci_get_vpd_ident(device_t dev, const char **identptr) 370{ 371 return(PCI_GET_VPD_IDENT(device_get_parent(dev), dev, identptr)); 372} 373 374static __inline int 375pci_get_vpd_readonly(device_t dev, const char *kw, const char **vptr) 376{ 377 return(PCI_GET_VPD_READONLY(device_get_parent(dev), dev, kw, vptr)); 378} 379 380/* 381 * Check if the address range falls within the VGA defined address range(s) 382 */ 383static __inline int 384pci_is_vga_ioport_range(u_long start, u_long end) 385{ 386 387 return (((start >= 0x3b0 && end <= 0x3bb) || 388 (start >= 0x3c0 && end <= 0x3df)) ? 1 : 0); 389} 390 391static __inline int 392pci_is_vga_memory_range(u_long start, u_long end) 393{ 394 395 return ((start >= 0xa0000 && end <= 0xbffff) ? 1 : 0); 396} 397 398/* 399 * PCI power states are as defined by ACPI: 400 * 401 * D0 State in which device is on and running. It is receiving full 402 * power from the system and delivering full functionality to the user. 403 * D1 Class-specific low-power state in which device context may or may not 404 * be lost. Buses in D1 cannot do anything to the bus that would force 405 * devices on that bus to lose context. 406 * D2 Class-specific low-power state in which device context may or may 407 * not be lost. Attains greater power savings than D1. Buses in D2 408 * can cause devices on that bus to lose some context. Devices in D2 409 * must be prepared for the bus to be in D2 or higher. 410 * D3 State in which the device is off and not running. Device context is 411 * lost. Power can be removed from the device. 412 */ 413#define PCI_POWERSTATE_D0 0 414#define PCI_POWERSTATE_D1 1 415#define PCI_POWERSTATE_D2 2 416#define PCI_POWERSTATE_D3 3 417#define PCI_POWERSTATE_UNKNOWN -1 418 419static __inline int 420pci_set_powerstate(device_t dev, int state) 421{ 422 return PCI_SET_POWERSTATE(device_get_parent(dev), dev, state); 423} 424 425static __inline int 426pci_get_powerstate(device_t dev) 427{ 428 return PCI_GET_POWERSTATE(device_get_parent(dev), dev); 429} 430 431static __inline int 432pci_find_cap(device_t dev, int capability, int *capreg) 433{ 434 return (PCI_FIND_CAP(device_get_parent(dev), dev, capability, capreg)); 435} 436 437static __inline int 438pci_find_extcap(device_t dev, int capability, int *capreg) 439{ 440 return (PCI_FIND_EXTCAP(device_get_parent(dev), dev, capability, capreg)); 441} 442 443static __inline int 444pci_find_htcap(device_t dev, int capability, int *capreg) 445{ 446 return (PCI_FIND_HTCAP(device_get_parent(dev), dev, capability, capreg)); 447} 448 449static __inline int 450pci_alloc_msi(device_t dev, int *count) 451{ 452 return (PCI_ALLOC_MSI(device_get_parent(dev), dev, count)); 453} 454 455static __inline int 456pci_alloc_msix(device_t dev, int *count) 457{ 458 return (PCI_ALLOC_MSIX(device_get_parent(dev), dev, count)); 459} 460 461static __inline int 462pci_remap_msix(device_t dev, int count, const u_int *vectors) 463{ 464 return (PCI_REMAP_MSIX(device_get_parent(dev), dev, count, vectors)); 465} 466 467static __inline int 468pci_release_msi(device_t dev) 469{ 470 return (PCI_RELEASE_MSI(device_get_parent(dev), dev)); 471} 472 473static __inline int 474pci_msi_count(device_t dev) 475{ 476 return (PCI_MSI_COUNT(device_get_parent(dev), dev)); 477} 478 479static __inline int 480pci_msix_count(device_t dev) 481{ 482 return (PCI_MSIX_COUNT(device_get_parent(dev), dev)); 483} 484 485static __inline uint16_t 486pci_get_rid(device_t dev) 487{ 488 return (PCI_GET_RID(device_get_parent(dev), dev)); 489} 490 491device_t pci_find_bsf(uint8_t, uint8_t, uint8_t); 492device_t pci_find_dbsf(uint32_t, uint8_t, uint8_t, uint8_t); 493device_t pci_find_device(uint16_t, uint16_t); 494device_t pci_find_class(uint8_t class, uint8_t subclass); 495 496/* Can be used by drivers to manage the MSI-X table. */ 497int pci_pending_msix(device_t dev, u_int index); 498 499int pci_msi_device_blacklisted(device_t dev); 500int pci_msix_device_blacklisted(device_t dev); 501 502void pci_ht_map_msi(device_t dev, uint64_t addr); 503 504int pci_get_max_read_req(device_t dev); 505void pci_restore_state(device_t dev); 506void pci_save_state(device_t dev); 507int pci_set_max_read_req(device_t dev, int size); 508 509 510#ifdef BUS_SPACE_MAXADDR 511#if (BUS_SPACE_MAXADDR > 0xFFFFFFFF) 512#define PCI_DMA_BOUNDARY 0x100000000 513#else 514#define PCI_DMA_BOUNDARY 0 515#endif 516#endif 517 518#endif /* _SYS_BUS_H_ */ 519 520/* 521 * cdev switch for control device, initialised in generic PCI code 522 */ 523extern struct cdevsw pcicdev; 524 525/* 526 * List of all PCI devices, generation count for the list. 527 */ 528STAILQ_HEAD(devlist, pci_devinfo); 529 530extern struct devlist pci_devq; 531extern uint32_t pci_generation; 532 533struct pci_map *pci_find_bar(device_t dev, int reg); 534int pci_bar_enabled(device_t dev, struct pci_map *pm); 535struct pcicfg_vpd *pci_fetch_vpd_list(device_t dev); 536 537#define VGA_PCI_BIOS_SHADOW_ADDR 0xC0000 538#define VGA_PCI_BIOS_SHADOW_SIZE 131072 539 540int vga_pci_is_boot_display(device_t dev); 541void * vga_pci_map_bios(device_t dev, size_t *size); 542void vga_pci_unmap_bios(device_t dev, void *bios); 543 544#endif /* _PCIVAR_H_ */ 545