1139749Simp/*- 267276Sjon * Copyright (c) 2000,2001 Jonathan Chen. 367276Sjon * All rights reserved. 467276Sjon * 567276Sjon * Redistribution and use in source and binary forms, with or without 667276Sjon * modification, are permitted provided that the following conditions 767276Sjon * are met: 867276Sjon * 1. Redistributions of source code must retain the above copyright 9140197Simp * notice, this list of conditions and the following disclaimer. 1067276Sjon * 2. Redistributions in binary form must reproduce the above copyright 11140197Simp * notice, this list of conditions and the following disclaimer in the 12140197Simp * documentation and/or other materials provided with the distribution. 1367276Sjon * 1467276Sjon * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1567276Sjon * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1667276Sjon * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 17140197Simp * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 18140197Simp * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1967276Sjon * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2067276Sjon * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2167276Sjon * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2267276Sjon * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2367276Sjon * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2467276Sjon * SUCH DAMAGE. 2567276Sjon * 2667276Sjon * $FreeBSD$ 2767276Sjon */ 2867276Sjon 2967276Sjon/* 3094570Simp * Copyright (c) 1998, 1999 and 2000 3194570Simp * HAYAKAWA Koichi. All rights reserved. 3294570Simp * 3394570Simp * Redistribution and use in source and binary forms, with or without 3494570Simp * modification, are permitted provided that the following conditions 3594570Simp * are met: 3694570Simp * 1. Redistributions of source code must retain the above copyright 3794570Simp * notice, this list of conditions and the following disclaimer. 3894570Simp * 2. Redistributions in binary form must reproduce the above copyright 3994570Simp * notice, this list of conditions and the following disclaimer in the 4094570Simp * documentation and/or other materials provided with the distribution. 4194570Simp * 3. All advertising materials mentioning features or use of this software 4294570Simp * must display the following acknowledgement: 4394570Simp * This product includes software developed by HAYAKAWA Koichi. 4494570Simp * 4. The name of the author may not be used to endorse or promote products 4594570Simp * derived from this software without specific prior written permission. 4694570Simp * 4794570Simp * THIS SOFTWARE IS PROVIDED BY THE AUTHOR ``AS IS'' AND ANY EXPRESS OR 4894570Simp * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES 4994570Simp * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. 5094570Simp * IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, 5194570Simp * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT 5294570Simp * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, 5394570Simp * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY 5494570Simp * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT 5594570Simp * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF 5694570Simp * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. 5794570Simp */ 5894570Simp 5994570Simp/* 6067276Sjon * Register definitions for PCI to Cardbus Bridge chips 6167276Sjon */ 6267276Sjon 6367276Sjon 6467276Sjon/* PCI header registers */ 6590751Simp#define CBBR_SOCKBASE 0x10 /* len=4 */ 6667276Sjon 6790751Simp#define CBBR_MEMBASE0 0x1c /* len=4 */ 6890751Simp#define CBBR_MEMLIMIT0 0x20 /* len=4 */ 6990751Simp#define CBBR_MEMBASE1 0x24 /* len=4 */ 7090751Simp#define CBBR_MEMLIMIT1 0x28 /* len=4 */ 7190751Simp#define CBBR_IOBASE0 0x2c /* len=4 */ 7290751Simp#define CBBR_IOLIMIT0 0x30 /* len=4 */ 7390751Simp#define CBBR_IOBASE1 0x34 /* len=4 */ 7490751Simp#define CBBR_IOLIMIT1 0x38 /* len=4 */ 7590751Simp#define CBB_MEMALIGN 4096 76118703Simp#define CBB_MEMALIGN_BITS 12 7790751Simp#define CBB_IOALIGN 4 78118703Simp#define CBB_IOALIGN_BITS 2 7967276Sjon 8090751Simp#define CBBR_INTRLINE 0x3c /* len=1 */ 8190751Simp#define CBBR_INTRPIN 0x3d /* len=1 */ 8290751Simp#define CBBR_BRIDGECTRL 0x3e /* len=2 */ 8390751Simp# define CBBM_BRIDGECTRL_MASTER_ABORT 0x0020 8490751Simp# define CBBM_BRIDGECTRL_RESET 0x0040 85148102Simp# define CBBM_BRIDGECTRL_INTR_IREQ_ISA_EN 0x0080 8690751Simp# define CBBM_BRIDGECTRL_PREFETCH_0 0x0100 8790751Simp# define CBBM_BRIDGECTRL_PREFETCH_1 0x0200 8890751Simp# define CBBM_BRIDGECTRL_WRITE_POST_EN 0x0400 8967276Sjon /* additional bit for RF5C46[567] */ 9090751Simp# define CBBM_BRIDGECTRL_RL_3E0_EN 0x0800 9190751Simp# define CBBM_BRIDGECTRL_RL_3E2_EN 0x1000 9267276Sjon 9390751Simp#define CBBR_LEGACY 0x44 /* len=4 */ 9467276Sjon 95153756Simp/* TI */ 96100704Simp#define CBBR_SYSCTRL 0x80 /* len=4 */ 97100704Simp# define CBBM_SYSCTRL_INTRTIE 0x20000000u 98100704Simp 99100704Simp/* TI [14][245]xx */ 100100704Simp#define CBBR_MMCTRL 0x84 /* len=4 */ 101100704Simp 102100704Simp/* TI 12xx/14xx/15xx (except 1250/1251/1251B/1450) */ 103100704Simp#define CBBR_MFUNC 0x8c /* len=4 */ 104100704Simp# define CBBM_MFUNC_PIN0 0x0000000f 105100704Simp# define CBBM_MFUNC_PIN0_INTA 0x02 106100704Simp# define CBBM_MFUNC_PIN1 0x000000f0 107100704Simp# define CBBM_MFUNC_PIN1_INTB 0x20 108100704Simp# define CBBM_MFUNC_PIN2 0x00000f00 109100704Simp# define CBBM_MFUNC_PIN3 0x0000f000 110100704Simp# define CBBM_MFUNC_PIN4 0x000f0000 111100704Simp# define CBBM_MFUNC_PIN5 0x00f00000 112100704Simp# define CBBM_MFUNC_PIN6 0x0f000000 113100704Simp 11490751Simp#define CBBR_CBCTRL 0x91 /* len=1 */ 11567276Sjon /* bits for TI 113X */ 11690751Simp# define CBBM_CBCTRL_113X_RI_EN 0x80 11790751Simp# define CBBM_CBCTRL_113X_ZV_EN 0x40 11890751Simp# define CBBM_CBCTRL_113X_PCI_IRQ_EN 0x20 11990751Simp# define CBBM_CBCTRL_113X_PCI_INTR 0x10 12090751Simp# define CBBM_CBCTRL_113X_PCI_CSC 0x08 12190751Simp# define CBBM_CBCTRL_113X_PCI_CSC_D 0x04 12290751Simp# define CBBM_CBCTRL_113X_SPEAKER_EN 0x02 12390751Simp# define CBBM_CBCTRL_113X_INTR_DET 0x01 124100704Simp /* TI [14][245]xx */ 12590751Simp# define CBBM_CBCTRL_12XX_RI_EN 0x80 12690751Simp# define CBBM_CBCTRL_12XX_ZV_EN 0x40 12790751Simp# define CBBM_CBCTRL_12XX_AUD2MUX 0x04 12890751Simp# define CBBM_CBCTRL_12XX_SPEAKER_EN 0x02 12990751Simp# define CBBM_CBCTRL_12XX_INTR_DET 0x01 13090751Simp#define CBBR_DEVCTRL 0x92 /* len=1 */ 13190751Simp# define CBBM_DEVCTRL_INT_SERIAL 0x04 13290751Simp# define CBBM_DEVCTRL_INT_PCI 0x02 13367276Sjon 13490751Simp/* ToPIC 95 ONLY */ 135161241Simp#define TOPIC95_SOCKETCTRL 0x90 136161241Simp# define TOPIC95_SOCKETCTRL_SCR_IRQSEL 0x00000001 /* PCI intr */ 13790751Simp/* ToPIC 97, 100 */ 138161241Simp#define TOPIC97_ZV_CONTROL 0x9c /* 1 byte */ 139161241Simp# define TOPIC97_ZVC_ENABLE 0x1 14067276Sjon 14190751Simp/* TOPIC 95+ */ 142161241Simp#define TOPIC_SLOTCTRL 0xa0 /* 1 byte */ 143161241Simp# define TOPIC_SLOTCTRL_SLOTON 0x80 144161241Simp# define TOPIC_SLOTCTRL_SLOTEN 0x40 145161241Simp# define TOPIC_SLOTCTRL_ID_LOCK 0x20 146161241Simp# define TOPIC_SLOTCTRL_ID_WP 0x10 147161241Simp# define TOPIC_SLOTCTRL_PORT_MASK 0x0c 148161241Simp# define TOPIC_SLOTCTRL_PORT_SHIFT 2 149161241Simp# define TOPIC_SLOTCTRL_OSF_MASK 0x03 150161241Simp# define TOPIC_SLOTCTRL_OSF_SHIFT 0 15167276Sjon 15290751Simp/* TOPIC 95+ */ 153161241Simp#define TOPIC_INTCTRL 0xa1 /* 1 byte */ 154161241Simp# define TOPIC_INTCTRL_INTB 0x20 155161241Simp# define TOPIC_INTCTRL_INTA 0x10 156161241Simp# define TOPIC_INTCTRL_INT_MASK 0x30 15790751Simp/* The following bits may be for ToPIC 95 only */ 158161241Simp# define TOPIC95_INTCTRL_CLOCK_MASK 0x0c 159161241Simp# define TOPIC95_INTCTRL_CLOCK_2 0x08 /* PCI Clk/2 */ 160161241Simp# define TOPIC95_INTCTRL_CLOCK_1 0x04 /* PCI Clk */ 161161241Simp# define TOPIC95_INTCTRL_CLOCK_0 0x00 /* no clock */ 16290751Simp/* ToPIC97, 100 defines the following bits */ 163161241Simp# define TOPIC97_INTCTRL_STSIRQNP 0x04 164161241Simp# define TOPIC97_INTCTRL_IRQNP 0x02 165161241Simp# define TOPIC97_INTCTRL_INTIRQSEL 0x01 16690751Simp 16790751Simp/* TOPIC 95+ */ 168161241Simp#define TOPIC_CDC 0xa3 /* 1 byte */ 169161241Simp# define TOPIC_CDC_CARDBUS 0x80 170161241Simp# define TOPIC_CDC_VS1 0x04 171161241Simp# define TOPIC_CDC_VS2 0x02 172161241Simp# define TOPIC_CDC_SWDETECT 0x01 17390751Simp 174161241Simp/* TOPIC97+? */ 175161241Simp#define TOPIC_REG_CTRL 0xa4 /* 4 bytes */ 176161241Simp# define TOPIC_REG_CTRL_RESUME_RESET 0x80000000 177161241Simp# define TOPIC_REG_CTRL_REMOVE_RESET 0x40000000 178161241Simp# define TOPIC97_REG_CTRL_CLKRUN_ENA 0x20000000 179161241Simp# define TOPIC97_REG_CTRL_TESTMODE 0x10000000 180161241Simp# define TOPIC97_REG_CTRL_IOPLUP 0x08000000 181161241Simp# define TOPIC_REG_CTRL_BUFOFF_PWROFF 0x02000000 182161241Simp# define TOPIC_REG_CTRL_BUFOFF_SIGOFF 0x01000000 183161241Simp# define TOPIC97_REG_CTRL_CB_DEV_MASK 0x0000f800 184161241Simp# define TOPIC97_REG_CTRL_CB_DEV_SHIFT 11 185161241Simp# define TOPIC97_REG_CTRL_RI_DISABLE 0x00000004 186161241Simp# define TOPIC97_REG_CTRL_CAUDIO_OFF 0x00000002 187161241Simp# define TOPIC_REG_CTRL_CAUDIO_INVERT 0x00000001 188161241Simp 189161241Simp 19067276Sjon/* Socket definitions */ 19190751Simp#define CBB_SOCKET_EVENT_CSTS 0x01 /* Card Status Change */ 19290751Simp#define CBB_SOCKET_EVENT_CD1 0x02 /* Card Detect 1 */ 19390751Simp#define CBB_SOCKET_EVENT_CD2 0x04 /* Card Detect 2 */ 19490751Simp#define CBB_SOCKET_EVENT_CD 0x06 /* Card Detect all */ 195107194Simp#define CBB_SOCKET_EVENT_POWER 0x08 /* Power Cycle */ 196157278Simp#define CBB_SOCKET_EVENT_VALID_MASK 0x0f /* All socket events */ 19767276Sjon 19890751Simp#define CBB_SOCKET_MASK_CSTS 0x01 /* Card Status Change */ 19990751Simp#define CBB_SOCKET_MASK_CD 0x06 /* Card Detect */ 20090751Simp#define CBB_SOCKET_MASK_POWER 0x08 /* Power Cycle */ 201107194Simp#define CBB_SOCKET_MASK_ALL 0x0F /* all of the above */ 20267276Sjon 203118705Simp#define CBB_STATE_CSTCHG (1UL << 0) /* Card Status Change */ 204118705Simp#define CBB_STATE_CD1_CHANGE (1UL << 1) /* Card Detect 1 */ 205118705Simp#define CBB_STATE_CD2_CHANGE (1UL << 2) /* Card Detect 2 */ 206118705Simp#define CBB_STATE_CD (3UL << 1) /* Card Detect all */ 207118705Simp#define CBB_STATE_POWER_CYCLE (1UL << 3) /* Power Cycle */ 208118705Simp#define CBB_STATE_R2_CARD (1UL << 4) /* 16-bit Card */ 209118705Simp#define CBB_STATE_CB_CARD (1UL << 5) /* Cardbus Card */ 210118705Simp#define CBB_STATE_IREQ (1UL << 6) /* Ready */ 211118705Simp#define CBB_STATE_NOT_A_CARD (1UL << 7) /* Unrecognized Card */ 212118705Simp#define CBB_STATE_DATA_LOST (1UL << 8) /* Data Lost */ 213118705Simp#define CBB_STATE_BAD_VCC_REQ (1UL << 9) /* Bad VccRequest */ 214118705Simp#define CBB_STATE_5VCARD (1UL << 10) /* 5 V Card */ 215118705Simp#define CBB_STATE_3VCARD (1UL << 11) /* 3.3 V Card */ 216118705Simp#define CBB_STATE_XVCARD (1UL << 12) /* X.X V Card */ 217118705Simp#define CBB_STATE_YVCARD (1UL << 13) /* Y.Y V Card */ 218118705Simp#define CBB_STATE_5VSOCK (1UL << 28) /* 5 V Socket */ 219118705Simp#define CBB_STATE_3VSOCK (1UL << 29) /* 3.3 V Socket */ 220118705Simp#define CBB_STATE_XVSOCK (1UL << 30) /* X.X V Socket */ 221118705Simp#define CBB_STATE_YVSOCK (1UL << 31) /* Y.Y V Socket */ 22267276Sjon 22390751Simp#define CBB_SOCKET_CTRL_VPPMASK 0x07 22490751Simp#define CBB_SOCKET_CTRL_VPP_OFF 0x00 22590751Simp#define CBB_SOCKET_CTRL_VPP_12V 0x01 22690751Simp#define CBB_SOCKET_CTRL_VPP_5V 0x02 22790751Simp#define CBB_SOCKET_CTRL_VPP_3V 0x03 22890751Simp#define CBB_SOCKET_CTRL_VPP_XV 0x04 22990751Simp#define CBB_SOCKET_CTRL_VPP_YV 0x05 23067276Sjon 23190751Simp#define CBB_SOCKET_CTRL_VCCMASK 0x70 23290751Simp#define CBB_SOCKET_CTRL_VCC_OFF 0x00 23390751Simp#define CBB_SOCKET_CTRL_VCC_5V 0x20 23490751Simp#define CBB_SOCKET_CTRL_VCC_3V 0x30 23590751Simp#define CBB_SOCKET_CTRL_VCC_XV 0x40 23690751Simp#define CBB_SOCKET_CTRL_VCC_YV 0x50 23767276Sjon 23890751Simp#define CBB_SOCKET_CTRL_STOPCLK 0x80 23967276Sjon 240157278Simp#define CBB_FORCE_CV_TEST (1UL << 14) 241157278Simp#define CBB_FORCE_3VCARD (1UL << 11) 242157278Simp#define CBB_FORCE_5VCARD (1UL << 10) 243157278Simp#define CBB_FORCE_BAD_VCC_REQ (1UL << 9) 244157278Simp#define CBB_FORCE_DATA_LOST (1UL << 8) 245157278Simp#define CBB_FORCE_NOT_A_CARD (1UL << 7) 246157278Simp#define CBB_FORCE_CB_CARD (1UL << 5) 247157278Simp#define CBB_FORCE_R2_CARD (1UL << 4) 248157278Simp#define CBB_FORCE_POWER_CYCLE (1UL << 3) 249157278Simp#define CBB_FORCE_CD2_CHANGE (1UL << 2) 250157278Simp#define CBB_FORCE_CD1_CHANGE (1UL << 1) 251157278Simp#define CBB_FORCE_CSTCHG (1UL << 0) 252118705Simp 25377195Simp#include <dev/pccbb/pccbbdevid.h> 25489326Simp 255157278Simp#define CBB_SOCKET_EVENT 0x00 256157278Simp#define CBB_SOCKET_MASK 0x04 257157278Simp#define CBB_SOCKET_STATE 0x08 258157278Simp#define CBB_SOCKET_FORCE 0x0c 259157278Simp#define CBB_SOCKET_CONTROL 0x10 260157278Simp#define CBB_SOCKET_POWER 0x14 261100704Simp 262157278Simp#define CBB_EXCA_OFFSET 0x800 /* offset for exca regs */ 263