if_patm.c revision 126396
1/* 2 * Copyright (c) 2003 3 * Fraunhofer Institute for Open Communication Systems (FhG Fokus). 4 * All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25 * SUCH DAMAGE. 26 * 27 * Author: Hartmut Brandt <harti@freebsd.org> 28 * 29 * Driver for IDT77252 based cards like ProSum's. 30 */ 31 32#include <sys/cdefs.h> 33__FBSDID("$FreeBSD: head/sys/dev/patm/if_patm.c 126396 2004-02-29 09:26:01Z scottl $"); 34#include <sys/cdefs.h> 35__FBSDID("$FreeBSD: head/sys/dev/patm/if_patm.c 126396 2004-02-29 09:26:01Z scottl $"); 36 37#include "opt_inet.h" 38#include "opt_natm.h" 39 40#include <sys/types.h> 41#include <sys/param.h> 42#include <sys/systm.h> 43#include <sys/malloc.h> 44#include <sys/kernel.h> 45#include <sys/bus.h> 46#include <sys/errno.h> 47#include <sys/conf.h> 48#include <sys/module.h> 49#include <sys/lock.h> 50#include <sys/mutex.h> 51#include <sys/sysctl.h> 52#include <sys/queue.h> 53#include <sys/condvar.h> 54#include <sys/endian.h> 55#include <vm/uma.h> 56 57#include <sys/sockio.h> 58#include <sys/mbuf.h> 59#include <sys/socket.h> 60 61#include <net/if.h> 62#include <net/if_media.h> 63#include <net/if_atm.h> 64#include <net/route.h> 65#include <netinet/in.h> 66#include <netinet/if_atm.h> 67 68#include <machine/bus.h> 69#include <machine/resource.h> 70#include <sys/bus.h> 71#include <sys/rman.h> 72#include <sys/mbpool.h> 73 74#include <dev/utopia/utopia.h> 75#include <dev/patm/idt77252reg.h> 76#include <dev/patm/if_patmvar.h> 77 78static void patm_tst_init(struct patm_softc *sc); 79static void patm_scd_init(struct patm_softc *sc); 80 81/* 82 * Start the card. This assumes the mutex to be held 83 */ 84void 85patm_initialize(struct patm_softc *sc) 86{ 87 uint32_t cfg; 88 u_int i; 89 90 patm_debug(sc, ATTACH, "configuring..."); 91 92 /* clear SRAM */ 93 for (i = 0; i < sc->mmap->sram * 1024; i += 4) 94 patm_sram_write4(sc, i, 0, 0, 0, 0); 95 patm_scd_init(sc); 96 97 /* configuration register. Setting NOIDLE makes the timing wrong! */ 98 cfg = IDT_CFG_TXFIFO9 | IDT_CFG_RXQ512 | PATM_CFG_VPI | 99 /* IDT_CFG_NOIDLE | */ sc->mmap->rxtab; 100 if (!(sc->flags & PATM_UNASS)) 101 cfg |= IDT_CFG_IDLECLP; 102 patm_nor_write(sc, IDT_NOR_CFG, cfg); 103 104 /* clean all the status queues and the Raw handle */ 105 memset(sc->tsq, 0, sc->sq_size); 106 107 /* initialize RSQ */ 108 patm_debug(sc, ATTACH, "RSQ %llx", (unsigned long long)sc->rsq_phy); 109 patm_nor_write(sc, IDT_NOR_RSQB, sc->rsq_phy); 110 patm_nor_write(sc, IDT_NOR_RSQT, sc->rsq_phy); 111 patm_nor_write(sc, IDT_NOR_RSQH, 0); 112 sc->rsq_last = PATM_RSQ_SIZE - 1; 113 114 /* initialize TSTB */ 115 patm_nor_write(sc, IDT_NOR_TSTB, sc->mmap->tst1base << 2); 116 patm_tst_init(sc); 117 118 /* initialize TSQ */ 119 for (i = 0; i < IDT_TSQ_SIZE; i++) 120 sc->tsq[i].stamp = htole32(IDT_TSQE_EMPTY); 121 patm_nor_write(sc, IDT_NOR_TSQB, sc->tsq_phy); 122 patm_nor_write(sc, IDT_NOR_TSQH, 0); 123 patm_nor_write(sc, IDT_NOR_TSQT, 0); 124 sc->tsq_next = sc->tsq; 125 126 /* GP */ 127#if BYTE_ORDER == BIG_ENDIAN && 0 128 patm_nor_write(sc, IDT_NOR_GP, IDT_GP_BIGE); 129#else 130 patm_nor_write(sc, IDT_NOR_GP, 0); 131#endif 132 133 /* VPM */ 134 patm_nor_write(sc, IDT_NOR_VPM, 0); 135 136 /* RxFIFO */ 137 patm_nor_write(sc, IDT_NOR_RXFD, 138 IDT_RXFD(sc->mmap->rxfifo_addr, sc->mmap->rxfifo_code)); 139 patm_nor_write(sc, IDT_NOR_RXFT, 0); 140 patm_nor_write(sc, IDT_NOR_RXFH, 0); 141 142 /* RAWHND */ 143 patm_debug(sc, ATTACH, "RWH %llx", 144 (unsigned long long)sc->rawhnd_phy); 145 patm_nor_write(sc, IDT_NOR_RAWHND, sc->rawhnd_phy); 146 147 /* ABRSTD */ 148 patm_nor_write(sc, IDT_NOR_ABRSTD, 149 IDT_ABRSTD(sc->mmap->abrstd_addr, sc->mmap->abrstd_code)); 150 for (i = 0; i < sc->mmap->abrstd_size; i++) 151 patm_sram_write(sc, sc->mmap->abrstd_addr + i, 0); 152 patm_nor_write(sc, IDT_NOR_ABRRQ, 0); 153 patm_nor_write(sc, IDT_NOR_VBRRQ, 0); 154 155 /* rate tables */ 156 if (sc->flags & PATM_25M) { 157 for (i = 0; i < patm_rtables_size; i++) 158 patm_sram_write(sc, sc->mmap->rtables + i, 159 patm_rtables25[i]); 160 } else { 161 for (i = 0; i < patm_rtables_size; i++) 162 patm_sram_write(sc, sc->mmap->rtables + i, 163 patm_rtables155[i]); 164 } 165 patm_nor_write(sc, IDT_NOR_RTBL, sc->mmap->rtables << 2); 166 167 /* Maximum deficit */ 168 patm_nor_write(sc, IDT_NOR_MXDFCT, 32 | IDT_MDFCT_LCI | IDT_MDFCT_LNI); 169 170 /* Free buffer queues */ 171 patm_nor_write(sc, IDT_NOR_FBQP0, 0); 172 patm_nor_write(sc, IDT_NOR_FBQP1, 0); 173 patm_nor_write(sc, IDT_NOR_FBQP2, 0); 174 patm_nor_write(sc, IDT_NOR_FBQP3, 0); 175 176 patm_nor_write(sc, IDT_NOR_FBQWP0, 0); 177 patm_nor_write(sc, IDT_NOR_FBQWP1, 0); 178 patm_nor_write(sc, IDT_NOR_FBQWP2, 0); 179 patm_nor_write(sc, IDT_NOR_FBQWP3, 0); 180 181 patm_nor_write(sc, IDT_NOR_FBQS0, 182 (SMBUF_THRESHOLD << 28) | 183 (SMBUF_NI_THRESH << 24) | 184 (SMBUF_CI_THRESH << 20) | 185 SMBUF_CELLS); 186 patm_nor_write(sc, IDT_NOR_FBQS1, 187 (LMBUF_THRESHOLD << 28) | 188 (LMBUF_NI_THRESH << 24) | 189 (LMBUF_CI_THRESH << 20) | 190 LMBUF_CELLS); 191 patm_nor_write(sc, IDT_NOR_FBQS2, 192 (VMBUF_THRESHOLD << 28) | VMBUF_CELLS); 193 patm_nor_write(sc, IDT_NOR_FBQS3, 0); 194 195 /* make SCD0 for UBR0 */ 196 if ((sc->scd0 = patm_scd_alloc(sc)) == NULL) { 197 patm_printf(sc, "cannot create UBR0 SCD\n"); 198 patm_reset(sc); 199 return; 200 } 201 sc->scd0->q.ifq_maxlen = PATM_DLFT_MAXQ; 202 203 patm_scd_setup(sc, sc->scd0); 204 patm_tct_setup(sc, sc->scd0, NULL); 205 206 patm_debug(sc, ATTACH, "go..."); 207 208 sc->utopia.flags &= ~UTP_FL_POLL_CARRIER; 209 sc->ifatm.ifnet.if_flags |= IFF_RUNNING; 210 211 /* enable interrupts, Tx and Rx paths */ 212 cfg |= IDT_CFG_RXPTH | IDT_CFG_RXIIMM | IDT_CFG_RAWIE | IDT_CFG_RQFIE | 213 IDT_CFG_TIMOIE | IDT_CFG_FBIE | IDT_CFG_TXENB | IDT_CFG_TXINT | 214 IDT_CFG_TXUIE | IDT_CFG_TXSFI | IDT_CFG_PHYIE; 215 patm_nor_write(sc, IDT_NOR_CFG, cfg); 216 217 for (i = 0; i < sc->mmap->max_conn; i++) 218 if (sc->vccs[i] != NULL) 219 patm_load_vc(sc, sc->vccs[i], 1); 220 221 ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm, 222 sc->utopia.carrier == UTP_CARR_OK); 223} 224 225/* 226 * External callable start function 227 */ 228void 229patm_init(void *p) 230{ 231 struct patm_softc *sc = p; 232 233 mtx_lock(&sc->mtx); 234 patm_stop(sc); 235 patm_initialize(sc); 236 mtx_unlock(&sc->mtx); 237} 238 239/* 240 * Stop the interface 241 */ 242void 243patm_stop(struct patm_softc *sc) 244{ 245 u_int i; 246 struct mbuf *m; 247 struct patm_txmap *map; 248 struct patm_scd *scd; 249 250 sc->ifatm.ifnet.if_flags &= ~IFF_RUNNING; 251 sc->utopia.flags |= UTP_FL_POLL_CARRIER; 252 253 patm_reset(sc); 254 255 mtx_lock(&sc->tst_lock); 256 i = sc->tst_state; 257 sc->tst_state = 0; 258 callout_stop(&sc->tst_callout); 259 mtx_unlock(&sc->tst_lock); 260 261 if (i != 0) { 262 /* this means we are just entering or leaving the timeout. 263 * wait a little bit. Doing this correctly would be more 264 * involved */ 265 DELAY(1000); 266 } 267 268 /* 269 * Give any waiters on closing a VCC a chance. They will stop 270 * to wait if they see that IFF_RUNNING disappeared. 271 */ 272 cv_broadcast(&sc->vcc_cv); 273 274 /* free large buffers */ 275 patm_debug(sc, ATTACH, "freeing large buffers..."); 276 for (i = 0; i < sc->lbuf_max; i++) 277 if (sc->lbufs[i].m != NULL) 278 patm_lbuf_free(sc, &sc->lbufs[i]); 279 280 /* free small buffers that are on the card */ 281 patm_debug(sc, ATTACH, "freeing small buffers..."); 282 mbp_card_free(sc->sbuf_pool); 283 284 /* free aal0 buffers that are on the card */ 285 patm_debug(sc, ATTACH, "freeing aal0 buffers..."); 286 mbp_card_free(sc->vbuf_pool); 287 288 /* freeing partial receive chains and reset vcc state */ 289 for (i = 0; i < sc->mmap->max_conn; i++) { 290 if (sc->vccs[i] != NULL) { 291 if (sc->vccs[i]->chain != NULL) { 292 m_freem(sc->vccs[i]->chain); 293 sc->vccs[i]->chain = NULL; 294 sc->vccs[i]->last = NULL; 295 } 296 297 if (sc->vccs[i]->vflags & (PATM_VCC_RX_CLOSING | 298 PATM_VCC_TX_CLOSING)) { 299 uma_zfree(sc->vcc_zone, sc->vccs[i]); 300 sc->vccs[i] = NULL; 301 } else { 302 /* keep */ 303 sc->vccs[i]->vflags &= ~PATM_VCC_OPEN; 304 sc->vccs[i]->cps = 0; 305 sc->vccs[i]->scd = NULL; 306 } 307 } 308 } 309 310 /* stop all active SCDs */ 311 while ((scd = LIST_FIRST(&sc->scd_list)) != NULL) { 312 /* free queue packets */ 313 for (;;) { 314 _IF_DEQUEUE(&scd->q, m); 315 if (m == NULL) 316 break; 317 m_freem(m); 318 } 319 320 /* free transmitting packets */ 321 for (i = 0; i < IDT_TSQE_TAG_SPACE; i++) { 322 if ((m = scd->on_card[i]) != NULL) { 323 scd->on_card[i] = 0; 324 map = m->m_pkthdr.header; 325 326 bus_dmamap_unload(sc->tx_tag, map->map); 327 SLIST_INSERT_HEAD(&sc->tx_maps_free, map, link); 328 m_freem(m); 329 } 330 } 331 patm_scd_free(sc, scd); 332 } 333 sc->scd0 = NULL; 334 335 sc->flags &= ~PATM_CLR; 336 337 /* reset raw cell queue */ 338 sc->rawh = NULL; 339 340 ATMEV_SEND_IFSTATE_CHANGED(&sc->ifatm, 341 sc->utopia.carrier == UTP_CARR_OK); 342} 343 344/* 345 * Stop the card and reset it 346 */ 347void 348patm_reset(struct patm_softc *sc) 349{ 350 351 patm_debug(sc, ATTACH, "resetting..."); 352 353 patm_nor_write(sc, IDT_NOR_CFG, IDT_CFG_SWRST); 354 DELAY(200); 355 patm_nor_write(sc, IDT_NOR_CFG, 0); 356 DELAY(200); 357 358 patm_nor_write(sc, IDT_NOR_RSQH, 0); 359 patm_nor_write(sc, IDT_NOR_TSQH, 0); 360 361 patm_nor_write(sc, IDT_NOR_GP, IDT_GP_PHY_RST); 362 DELAY(50); 363 patm_nor_write(sc, IDT_NOR_GP, IDT_GP_EEDO | IDT_GP_EECS); 364 DELAY(50); 365} 366 367/* 368 * Initialize the soft TST to contain only ABR scheduling and 369 * write it to SRAM 370 */ 371static void 372patm_tst_init(struct patm_softc *sc) 373{ 374 u_int i; 375 u_int base, idle; 376 377 base = sc->mmap->tst1base; 378 idle = sc->mmap->tst1base + sc->mmap->tst_size; 379 380 /* soft */ 381 for (i = 0; i < sc->mmap->tst_size - 1; i++) 382 sc->tst_soft[i] = IDT_TST_VBR; 383 384 sc->tst_state = 0; 385 sc->tst_jump[0] = base + sc->mmap->tst_size - 1; 386 sc->tst_jump[1] = idle + sc->mmap->tst_size - 1; 387 sc->tst_base[0] = base; 388 sc->tst_base[1] = idle; 389 390 /* TST1 */ 391 for (i = 0; i < sc->mmap->tst_size - 1; i++) 392 patm_sram_write(sc, base + i, IDT_TST_VBR); 393 patm_sram_write(sc, sc->tst_jump[0], IDT_TST_BR | (base << 2)); 394 395 /* TST2 */ 396 for (i = 0; i < sc->mmap->tst_size - 1; i++) 397 patm_sram_write(sc, idle + i, IDT_TST_VBR); 398 patm_sram_write(sc, sc->tst_jump[1], IDT_TST_BR | (idle << 2)); 399 400 sc->tst_free = sc->mmap->tst_size - 1; 401 sc->tst_reserve = sc->tst_free * PATM_TST_RESERVE / 100; 402 sc->bwrem = sc->ifatm.mib.pcr; 403} 404 405/* 406 * Initialize the SCDs. This is done by building a list of all free 407 * SCDs in SRAM. The first word of each potential SCD is used as a 408 * link to the next free SCD. The list is rooted in softc. 409 */ 410static void 411patm_scd_init(struct patm_softc *sc) 412{ 413 u_int s; /* SRAM address of current SCD */ 414 415 sc->scd_free = 0; 416 for (s = sc->mmap->scd_base; s + 12 <= sc->mmap->tst1base; s += 12) { 417 patm_sram_write(sc, s, sc->scd_free); 418 sc->scd_free = s; 419 } 420} 421 422/* 423 * allocate an SCQ 424 */ 425struct patm_scd * 426patm_scd_alloc(struct patm_softc *sc) 427{ 428 u_int sram, next; /* SRAM address of this and next SCD */ 429 int error; 430 void *p; 431 struct patm_scd *scd; 432 bus_dmamap_t map; 433 bus_addr_t phy; 434 435 /* get an SCD from the free list */ 436 if ((sram = sc->scd_free) == 0) 437 return (NULL); 438 next = patm_sram_read(sc, sram); 439 440 /* allocate memory for the queue and our host stuff */ 441 error = bus_dmamem_alloc(sc->scd_tag, &p, BUS_DMA_NOWAIT, &map); 442 if (error != 0) 443 return (NULL); 444 phy = 0x3ff; 445 error = bus_dmamap_load(sc->scd_tag, map, p, sizeof(scd->scq), 446 patm_load_callback, &phy, BUS_DMA_NOWAIT); 447 if (error != 0) { 448 bus_dmamem_free(sc->scd_tag, p, map); 449 return (NULL); 450 } 451 KASSERT((phy & 0x1ff) == 0, ("SCD not aligned %lx", (u_long)phy)); 452 453 scd = p; 454 bzero(scd, sizeof(*scd)); 455 456 scd->sram = sram; 457 scd->phy = phy; 458 scd->map = map; 459 scd->space = IDT_SCQ_SIZE; 460 scd->last_tag = IDT_TSQE_TAG_SPACE - 1; 461 scd->q.ifq_maxlen = PATM_TX_IFQLEN; 462 463 /* remove the scd from the free list */ 464 sc->scd_free = next; 465 LIST_INSERT_HEAD(&sc->scd_list, scd, link); 466 467 return (scd); 468} 469 470/* 471 * Free an SCD 472 */ 473void 474patm_scd_free(struct patm_softc *sc, struct patm_scd *scd) 475{ 476 477 LIST_REMOVE(scd, link); 478 479 /* clear SCD and insert link word */ 480 patm_sram_write4(sc, scd->sram, sc->scd_free, 0, 0, 0); 481 patm_sram_write4(sc, scd->sram, 0, 0, 0, 0); 482 patm_sram_write4(sc, scd->sram, 0, 0, 0, 0); 483 484 /* put on free list */ 485 sc->scd_free = scd->sram; 486 487 /* free memory */ 488 bus_dmamap_unload(sc->scd_tag, scd->map); 489 bus_dmamem_free(sc->scd_tag, scd, scd->map); 490} 491 492/* 493 * DMA loading helper function. This function handles the loading of 494 * all one segment DMA maps. The argument is a pointer to a bus_addr_t 495 * which must contain the desired alignment of the address as a bitmap. 496 */ 497void 498patm_load_callback(void *arg, bus_dma_segment_t *segs, int nsegs, int error) 499{ 500 bus_addr_t *phy = arg; 501 502 if (error) 503 return; 504 505 KASSERT(nsegs == 1, 506 ("too many segments for DMA: %d", nsegs)); 507 KASSERT(segs[0].ds_addr <= 0xffffffffUL, 508 ("phys addr too large %lx", (u_long)segs[0].ds_addr)); 509 KASSERT((segs[0].ds_addr & *phy) == 0, 510 ("bad alignment %lx:%lx", (u_long)segs[0].ds_addr, (u_long)*phy)); 511 512 *phy = segs[0].ds_addr; 513} 514