ntb_hw.c revision 304401
1/*- 2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (C) 2013 Intel Corporation 4 * Copyright (C) 2015 EMC Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * The Non-Transparent Bridge (NTB) is a device that allows you to connect 31 * two or more systems using a PCI-e links, providing remote memory access. 32 * 33 * This module contains a driver for NTB hardware in Intel Xeon/Atom CPUs. 34 * 35 * NOTE: Much of the code in this module is shared with Linux. Any patches may 36 * be picked up and redistributed in Linux with a dual GPL/BSD license. 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: stable/10/sys/dev/ntb/ntb_hw/ntb_hw.c 304401 2016-08-18 10:54:21Z mav $"); 41 42#include <sys/param.h> 43#include <sys/kernel.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/endian.h> 47#include <sys/interrupt.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/pciio.h> 52#include <sys/queue.h> 53#include <sys/rman.h> 54#include <sys/rmlock.h> 55#include <sys/sbuf.h> 56#include <sys/sysctl.h> 57#include <vm/vm.h> 58#include <vm/pmap.h> 59#include <machine/bus.h> 60#include <machine/intr_machdep.h> 61#include <machine/pmap.h> 62#include <machine/resource.h> 63#include <dev/pci/pcireg.h> 64#include <dev/pci/pcivar.h> 65 66#include "ntb_regs.h" 67#include "../ntb.h" 68 69#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 70 71#define NTB_HB_TIMEOUT 1 /* second */ 72#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 73#define BAR_HIGH_MASK (~((1ull << 12) - 1)) 74 75#define NTB_MSIX_VER_GUARD 0xaabbccdd 76#define NTB_MSIX_RECEIVED 0xe0f0e0f0 77 78/* 79 * PCI constants could be somewhere more generic, but aren't defined/used in 80 * pci.c. 81 */ 82#define PCI_MSIX_ENTRY_SIZE 16 83#define PCI_MSIX_ENTRY_LOWER_ADDR 0 84#define PCI_MSIX_ENTRY_UPPER_ADDR 4 85#define PCI_MSIX_ENTRY_DATA 8 86 87enum ntb_device_type { 88 NTB_XEON, 89 NTB_ATOM 90}; 91 92/* ntb_conn_type are hardware numbers, cannot change. */ 93enum ntb_conn_type { 94 NTB_CONN_TRANSPARENT = 0, 95 NTB_CONN_B2B = 1, 96 NTB_CONN_RP = 2, 97}; 98 99enum ntb_b2b_direction { 100 NTB_DEV_USD = 0, 101 NTB_DEV_DSD = 1, 102}; 103 104enum ntb_bar { 105 NTB_CONFIG_BAR = 0, 106 NTB_B2B_BAR_1, 107 NTB_B2B_BAR_2, 108 NTB_B2B_BAR_3, 109 NTB_MAX_BARS 110}; 111 112enum { 113 NTB_MSIX_GUARD = 0, 114 NTB_MSIX_DATA0, 115 NTB_MSIX_DATA1, 116 NTB_MSIX_DATA2, 117 NTB_MSIX_OFS0, 118 NTB_MSIX_OFS1, 119 NTB_MSIX_OFS2, 120 NTB_MSIX_DONE, 121 NTB_MAX_MSIX_SPAD 122}; 123 124/* Device features and workarounds */ 125#define HAS_FEATURE(ntb, feature) \ 126 (((ntb)->features & (feature)) != 0) 127 128struct ntb_hw_info { 129 uint32_t device_id; 130 const char *desc; 131 enum ntb_device_type type; 132 uint32_t features; 133}; 134 135struct ntb_pci_bar_info { 136 bus_space_tag_t pci_bus_tag; 137 bus_space_handle_t pci_bus_handle; 138 int pci_resource_id; 139 struct resource *pci_resource; 140 vm_paddr_t pbase; 141 caddr_t vbase; 142 vm_size_t size; 143 vm_memattr_t map_mode; 144 145 /* Configuration register offsets */ 146 uint32_t psz_off; 147 uint32_t ssz_off; 148 uint32_t pbarxlat_off; 149}; 150 151struct ntb_int_info { 152 struct resource *res; 153 int rid; 154 void *tag; 155}; 156 157struct ntb_vec { 158 struct ntb_softc *ntb; 159 uint32_t num; 160 unsigned masked; 161}; 162 163struct ntb_reg { 164 uint32_t ntb_ctl; 165 uint32_t lnk_sta; 166 uint8_t db_size; 167 unsigned mw_bar[NTB_MAX_BARS]; 168}; 169 170struct ntb_alt_reg { 171 uint32_t db_bell; 172 uint32_t db_mask; 173 uint32_t spad; 174}; 175 176struct ntb_xlat_reg { 177 uint32_t bar0_base; 178 uint32_t bar2_base; 179 uint32_t bar4_base; 180 uint32_t bar5_base; 181 182 uint32_t bar2_xlat; 183 uint32_t bar4_xlat; 184 uint32_t bar5_xlat; 185 186 uint32_t bar2_limit; 187 uint32_t bar4_limit; 188 uint32_t bar5_limit; 189}; 190 191struct ntb_b2b_addr { 192 uint64_t bar0_addr; 193 uint64_t bar2_addr64; 194 uint64_t bar4_addr64; 195 uint64_t bar4_addr32; 196 uint64_t bar5_addr32; 197}; 198 199struct ntb_msix_data { 200 uint32_t nmd_ofs; 201 uint32_t nmd_data; 202}; 203 204struct ntb_softc { 205 device_t device; 206 enum ntb_device_type type; 207 uint32_t features; 208 209 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 210 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 211 uint32_t allocated_interrupts; 212 213 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS]; 214 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS]; 215 bool peer_msix_good; 216 bool peer_msix_done; 217 struct ntb_pci_bar_info *peer_lapic_bar; 218 struct callout peer_msix_work; 219 220 struct callout heartbeat_timer; 221 struct callout lr_timer; 222 223 void *ntb_ctx; 224 const struct ntb_ctx_ops *ctx_ops; 225 struct ntb_vec *msix_vec; 226 struct rmlock ctx_lock; 227 228 uint32_t ppd; 229 enum ntb_conn_type conn_type; 230 enum ntb_b2b_direction dev_type; 231 232 /* Offset of peer bar0 in B2B BAR */ 233 uint64_t b2b_off; 234 /* Memory window used to access peer bar0 */ 235#define B2B_MW_DISABLED UINT8_MAX 236 uint8_t b2b_mw_idx; 237 uint32_t msix_xlat; 238 uint8_t msix_mw_idx; 239 240 uint8_t mw_count; 241 uint8_t spad_count; 242 uint8_t db_count; 243 uint8_t db_vec_count; 244 uint8_t db_vec_shift; 245 246 /* Protects local db_mask. */ 247#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 248#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 249#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 250 struct mtx db_mask_lock; 251 252 volatile uint32_t ntb_ctl; 253 volatile uint32_t lnk_sta; 254 255 uint64_t db_valid_mask; 256 uint64_t db_link_mask; 257 uint64_t db_mask; 258 uint64_t fake_db_bell; /* NTB_SB01BASE_LOCKUP*/ 259 260 int last_ts; /* ticks @ last irq */ 261 262 const struct ntb_reg *reg; 263 const struct ntb_alt_reg *self_reg; 264 const struct ntb_alt_reg *peer_reg; 265 const struct ntb_xlat_reg *xlat_reg; 266}; 267 268#ifdef __i386__ 269static __inline uint64_t 270bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 271 bus_size_t offset) 272{ 273 274 return (bus_space_read_4(tag, handle, offset) | 275 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 276} 277 278static __inline void 279bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 280 bus_size_t offset, uint64_t val) 281{ 282 283 bus_space_write_4(tag, handle, offset, val); 284 bus_space_write_4(tag, handle, offset + 4, val >> 32); 285} 286#endif 287 288#define ntb_bar_read(SIZE, bar, offset) \ 289 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 290 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 291#define ntb_bar_write(SIZE, bar, offset, val) \ 292 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 293 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 294#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 295#define ntb_reg_write(SIZE, offset, val) \ 296 ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 297#define ntb_mw_read(SIZE, offset) \ 298 ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 299#define ntb_mw_write(SIZE, offset, val) \ 300 ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 301 offset, val) 302 303static int ntb_probe(device_t device); 304static int ntb_attach(device_t device); 305static int ntb_detach(device_t device); 306static uint64_t ntb_db_valid_mask(device_t dev); 307static void ntb_spad_clear(device_t dev); 308static uint64_t ntb_db_vector_mask(device_t dev, uint32_t vector); 309static bool ntb_link_is_up(device_t dev, enum ntb_speed *speed, 310 enum ntb_width *width); 311static int ntb_link_enable(device_t dev, enum ntb_speed speed, 312 enum ntb_width width); 313static int ntb_link_disable(device_t dev); 314static int ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val); 315static int ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val); 316 317static unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 318static inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 319static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 320static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 321 uint32_t *base, uint32_t *xlat, uint32_t *lmt); 322static int ntb_map_pci_bars(struct ntb_softc *ntb); 323static int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 324 vm_memattr_t); 325static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 326 const char *); 327static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 328static int map_memory_window_bar(struct ntb_softc *ntb, 329 struct ntb_pci_bar_info *bar); 330static void ntb_unmap_pci_bar(struct ntb_softc *ntb); 331static int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 332static int ntb_init_isr(struct ntb_softc *ntb); 333static int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 334static int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 335static void ntb_teardown_interrupts(struct ntb_softc *ntb); 336static inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 337static void ntb_interrupt(struct ntb_softc *, uint32_t vec); 338static void ndev_vec_isr(void *arg); 339static void ndev_irq_isr(void *arg); 340static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 341static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 342static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 343static int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 344static void ntb_free_msix_vec(struct ntb_softc *ntb); 345static void ntb_get_msix_info(struct ntb_softc *ntb); 346static void ntb_exchange_msix(void *); 347static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 348static void ntb_detect_max_mw(struct ntb_softc *ntb); 349static int ntb_detect_xeon(struct ntb_softc *ntb); 350static int ntb_detect_atom(struct ntb_softc *ntb); 351static int ntb_xeon_init_dev(struct ntb_softc *ntb); 352static int ntb_atom_init_dev(struct ntb_softc *ntb); 353static void ntb_teardown_xeon(struct ntb_softc *ntb); 354static void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 355static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 356 enum ntb_bar regbar); 357static void xeon_set_sbar_base_and_limit(struct ntb_softc *, 358 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 359static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 360 enum ntb_bar idx); 361static int xeon_setup_b2b_mw(struct ntb_softc *, 362 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 363static inline bool link_is_up(struct ntb_softc *ntb); 364static inline bool _xeon_link_is_up(struct ntb_softc *ntb); 365static inline bool atom_link_is_err(struct ntb_softc *ntb); 366static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 367static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 368static void atom_link_hb(void *arg); 369static void ntb_link_event(device_t dev); 370static void ntb_db_event(device_t dev, uint32_t vec); 371static void recover_atom_link(void *arg); 372static bool ntb_poll_link(struct ntb_softc *ntb); 373static void save_bar_parameters(struct ntb_pci_bar_info *bar); 374static void ntb_sysctl_init(struct ntb_softc *); 375static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 376static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS); 377static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS); 378static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 379static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 380 381static unsigned g_ntb_hw_debug_level; 382TUNABLE_INT("hw.ntb.debug_level", &g_ntb_hw_debug_level); 383SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 384 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 385#define ntb_printf(lvl, ...) do { \ 386 if ((lvl) <= g_ntb_hw_debug_level) { \ 387 device_printf(ntb->device, __VA_ARGS__); \ 388 } \ 389} while (0) 390 391#define _NTB_PAT_UC 0 392#define _NTB_PAT_WC 1 393#define _NTB_PAT_WT 4 394#define _NTB_PAT_WP 5 395#define _NTB_PAT_WB 6 396#define _NTB_PAT_UCM 7 397static unsigned g_ntb_mw_pat = _NTB_PAT_UC; 398TUNABLE_INT("hw.ntb.default_mw_pat", &g_ntb_mw_pat); 399SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, 400 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " 401 "UC: " __XSTRING(_NTB_PAT_UC) ", " 402 "WC: " __XSTRING(_NTB_PAT_WC) ", " 403 "WT: " __XSTRING(_NTB_PAT_WT) ", " 404 "WP: " __XSTRING(_NTB_PAT_WP) ", " 405 "WB: " __XSTRING(_NTB_PAT_WB) ", " 406 "UC-: " __XSTRING(_NTB_PAT_UCM)); 407 408static inline vm_memattr_t 409ntb_pat_flags(void) 410{ 411 412 switch (g_ntb_mw_pat) { 413 case _NTB_PAT_WC: 414 return (VM_MEMATTR_WRITE_COMBINING); 415 case _NTB_PAT_WT: 416 return (VM_MEMATTR_WRITE_THROUGH); 417 case _NTB_PAT_WP: 418 return (VM_MEMATTR_WRITE_PROTECTED); 419 case _NTB_PAT_WB: 420 return (VM_MEMATTR_WRITE_BACK); 421 case _NTB_PAT_UCM: 422 return (VM_MEMATTR_WEAK_UNCACHEABLE); 423 case _NTB_PAT_UC: 424 /* FALLTHROUGH */ 425 default: 426 return (VM_MEMATTR_UNCACHEABLE); 427 } 428} 429 430/* 431 * Well, this obviously doesn't belong here, but it doesn't seem to exist 432 * anywhere better yet. 433 */ 434static inline const char * 435ntb_vm_memattr_to_str(vm_memattr_t pat) 436{ 437 438 switch (pat) { 439 case VM_MEMATTR_WRITE_COMBINING: 440 return ("WRITE_COMBINING"); 441 case VM_MEMATTR_WRITE_THROUGH: 442 return ("WRITE_THROUGH"); 443 case VM_MEMATTR_WRITE_PROTECTED: 444 return ("WRITE_PROTECTED"); 445 case VM_MEMATTR_WRITE_BACK: 446 return ("WRITE_BACK"); 447 case VM_MEMATTR_WEAK_UNCACHEABLE: 448 return ("UNCACHED"); 449 case VM_MEMATTR_UNCACHEABLE: 450 return ("UNCACHEABLE"); 451 default: 452 return ("UNKNOWN"); 453 } 454} 455 456static int g_ntb_msix_idx = 1; 457TUNABLE_INT("hw.ntb.msix_mw_idx", &g_ntb_msix_idx); 458SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx, 459 0, "Use this memory window to access the peer MSIX message complex on " 460 "certain Xeon-based NTB systems, as a workaround for a hardware errata. " 461 "Like b2b_mw_idx, negative values index from the last available memory " 462 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)"); 463 464static int g_ntb_mw_idx = -1; 465TUNABLE_INT("hw.ntb.b2b_mw_idx", &g_ntb_mw_idx); 466SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 467 0, "Use this memory window to access the peer NTB registers. A " 468 "non-negative value starts from the first MW index; a negative value " 469 "starts from the last MW index. The default is -1, i.e., the last " 470 "available memory window. Both sides of the NTB MUST set the same " 471 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 472 473/* Hardware owns the low 16 bits of features. */ 474#define NTB_BAR_SIZE_4K (1 << 0) 475#define NTB_SDOORBELL_LOCKUP (1 << 1) 476#define NTB_SB01BASE_LOCKUP (1 << 2) 477#define NTB_B2BDOORBELL_BIT14 (1 << 3) 478/* Software/configuration owns the top 16 bits. */ 479#define NTB_SPLIT_BAR (1ull << 16) 480 481#define NTB_FEATURES_STR \ 482 "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \ 483 "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K" 484 485static struct ntb_hw_info pci_ids[] = { 486 /* XXX: PS/SS IDs left out until they are supported. */ 487 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 488 NTB_ATOM, 0 }, 489 490 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 491 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 492 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 493 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 494 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 495 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 496 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 497 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 498 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 499 NTB_SB01BASE_LOCKUP }, 500 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 501 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 502 NTB_SB01BASE_LOCKUP }, 503 504 { 0x00000000, NULL, NTB_ATOM, 0 } 505}; 506 507static const struct ntb_reg atom_reg = { 508 .ntb_ctl = ATOM_NTBCNTL_OFFSET, 509 .lnk_sta = ATOM_LINK_STATUS_OFFSET, 510 .db_size = sizeof(uint64_t), 511 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 512}; 513 514static const struct ntb_alt_reg atom_pri_reg = { 515 .db_bell = ATOM_PDOORBELL_OFFSET, 516 .db_mask = ATOM_PDBMSK_OFFSET, 517 .spad = ATOM_SPAD_OFFSET, 518}; 519 520static const struct ntb_alt_reg atom_b2b_reg = { 521 .db_bell = ATOM_B2B_DOORBELL_OFFSET, 522 .spad = ATOM_B2B_SPAD_OFFSET, 523}; 524 525static const struct ntb_xlat_reg atom_sec_xlat = { 526#if 0 527 /* "FIXME" says the Linux driver. */ 528 .bar0_base = ATOM_SBAR0BASE_OFFSET, 529 .bar2_base = ATOM_SBAR2BASE_OFFSET, 530 .bar4_base = ATOM_SBAR4BASE_OFFSET, 531 532 .bar2_limit = ATOM_SBAR2LMT_OFFSET, 533 .bar4_limit = ATOM_SBAR4LMT_OFFSET, 534#endif 535 536 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 537 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 538}; 539 540static const struct ntb_reg xeon_reg = { 541 .ntb_ctl = XEON_NTBCNTL_OFFSET, 542 .lnk_sta = XEON_LINK_STATUS_OFFSET, 543 .db_size = sizeof(uint16_t), 544 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 545}; 546 547static const struct ntb_alt_reg xeon_pri_reg = { 548 .db_bell = XEON_PDOORBELL_OFFSET, 549 .db_mask = XEON_PDBMSK_OFFSET, 550 .spad = XEON_SPAD_OFFSET, 551}; 552 553static const struct ntb_alt_reg xeon_b2b_reg = { 554 .db_bell = XEON_B2B_DOORBELL_OFFSET, 555 .spad = XEON_B2B_SPAD_OFFSET, 556}; 557 558static const struct ntb_xlat_reg xeon_sec_xlat = { 559 .bar0_base = XEON_SBAR0BASE_OFFSET, 560 .bar2_base = XEON_SBAR2BASE_OFFSET, 561 .bar4_base = XEON_SBAR4BASE_OFFSET, 562 .bar5_base = XEON_SBAR5BASE_OFFSET, 563 564 .bar2_limit = XEON_SBAR2LMT_OFFSET, 565 .bar4_limit = XEON_SBAR4LMT_OFFSET, 566 .bar5_limit = XEON_SBAR5LMT_OFFSET, 567 568 .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 569 .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 570 .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 571}; 572 573static struct ntb_b2b_addr xeon_b2b_usd_addr = { 574 .bar0_addr = XEON_B2B_BAR0_ADDR, 575 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 576 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 577 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 578 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 579}; 580 581static struct ntb_b2b_addr xeon_b2b_dsd_addr = { 582 .bar0_addr = XEON_B2B_BAR0_ADDR, 583 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 584 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 585 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 586 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 587}; 588 589SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 590 "B2B MW segment overrides -- MUST be the same on both sides"); 591 592TUNABLE_QUAD("hw.ntb.usd_bar2_addr64", &xeon_b2b_usd_addr.bar2_addr64); 593SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 594 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 595 "hardware, use this 64-bit address on the bus between the NTB devices for " 596 "the window at BAR2, on the upstream side of the link. MUST be the same " 597 "address on both sides."); 598TUNABLE_QUAD("hw.ntb.usd_bar4_addr64", &xeon_b2b_usd_addr.bar4_addr64); 599SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 600 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 601TUNABLE_QUAD("hw.ntb.usd_bar4_addr32", &xeon_b2b_usd_addr.bar4_addr32); 602SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 603 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 604 "(split-BAR mode)."); 605TUNABLE_QUAD("hw.ntb.usd_bar5_addr32", &xeon_b2b_usd_addr.bar5_addr32); 606SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 607 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 608 "(split-BAR mode)."); 609 610TUNABLE_QUAD("hw.ntb.dsd_bar2_addr64", &xeon_b2b_dsd_addr.bar2_addr64); 611SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 612 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 613 "hardware, use this 64-bit address on the bus between the NTB devices for " 614 "the window at BAR2, on the downstream side of the link. MUST be the same" 615 " address on both sides."); 616TUNABLE_QUAD("hw.ntb.dsd_bar4_addr64", &xeon_b2b_dsd_addr.bar4_addr64); 617SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 618 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 619TUNABLE_QUAD("hw.ntb.dsd_bar4_addr32", &xeon_b2b_dsd_addr.bar4_addr32); 620SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 621 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 622 "(split-BAR mode)."); 623TUNABLE_QUAD("hw.ntb.dsd_bar5_addr32", &xeon_b2b_dsd_addr.bar5_addr32); 624SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 625 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 626 "(split-BAR mode)."); 627 628/* 629 * OS <-> Driver interface structures 630 */ 631MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 632 633/* 634 * OS <-> Driver linkage functions 635 */ 636static int 637ntb_probe(device_t device) 638{ 639 struct ntb_hw_info *p; 640 641 p = ntb_get_device_info(pci_get_devid(device)); 642 if (p == NULL) 643 return (ENXIO); 644 645 device_set_desc(device, p->desc); 646 return (0); 647} 648 649static int 650ntb_attach(device_t device) 651{ 652 struct ntb_softc *ntb; 653 struct ntb_hw_info *p; 654 int error; 655 656 ntb = device_get_softc(device); 657 p = ntb_get_device_info(pci_get_devid(device)); 658 659 ntb->device = device; 660 ntb->type = p->type; 661 ntb->features = p->features; 662 ntb->b2b_mw_idx = B2B_MW_DISABLED; 663 ntb->msix_mw_idx = B2B_MW_DISABLED; 664 665 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 666 callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE); 667 callout_init(&ntb->lr_timer, CALLOUT_MPSAFE); 668 callout_init(&ntb->peer_msix_work, 1); 669 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 670 rm_init(&ntb->ctx_lock, "ntb ctx"); 671 672 if (ntb->type == NTB_ATOM) 673 error = ntb_detect_atom(ntb); 674 else 675 error = ntb_detect_xeon(ntb); 676 if (error != 0) 677 goto out; 678 679 ntb_detect_max_mw(ntb); 680 681 pci_enable_busmaster(ntb->device); 682 683 error = ntb_map_pci_bars(ntb); 684 if (error != 0) 685 goto out; 686 if (ntb->type == NTB_ATOM) 687 error = ntb_atom_init_dev(ntb); 688 else 689 error = ntb_xeon_init_dev(ntb); 690 if (error != 0) 691 goto out; 692 693 ntb_spad_clear(device); 694 695 ntb_poll_link(ntb); 696 697 ntb_sysctl_init(ntb); 698 699 /* Attach children to this controller */ 700 device_add_child(device, NULL, -1); 701 bus_generic_attach(device); 702 703out: 704 if (error != 0) 705 ntb_detach(device); 706 return (error); 707} 708 709static int 710ntb_detach(device_t device) 711{ 712 struct ntb_softc *ntb; 713 714 ntb = device_get_softc(device); 715 716 /* Detach & delete all children */ 717 device_delete_children(device); 718 719 if (ntb->self_reg != NULL) { 720 DB_MASK_LOCK(ntb); 721 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask); 722 DB_MASK_UNLOCK(ntb); 723 } 724 callout_drain(&ntb->heartbeat_timer); 725 callout_drain(&ntb->lr_timer); 726 callout_drain(&ntb->peer_msix_work); 727 pci_disable_busmaster(ntb->device); 728 if (ntb->type == NTB_XEON) 729 ntb_teardown_xeon(ntb); 730 ntb_teardown_interrupts(ntb); 731 732 mtx_destroy(&ntb->db_mask_lock); 733 rm_destroy(&ntb->ctx_lock); 734 735 ntb_unmap_pci_bar(ntb); 736 737 return (0); 738} 739 740/* 741 * Driver internal routines 742 */ 743static inline enum ntb_bar 744ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 745{ 746 747 KASSERT(mw < ntb->mw_count, 748 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 749 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 750 751 return (ntb->reg->mw_bar[mw]); 752} 753 754static inline bool 755bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 756{ 757 /* XXX This assertion could be stronger. */ 758 KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 759 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR)); 760} 761 762static inline void 763bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 764 uint32_t *xlat, uint32_t *lmt) 765{ 766 uint32_t basev, lmtv, xlatv; 767 768 switch (bar) { 769 case NTB_B2B_BAR_1: 770 basev = ntb->xlat_reg->bar2_base; 771 lmtv = ntb->xlat_reg->bar2_limit; 772 xlatv = ntb->xlat_reg->bar2_xlat; 773 break; 774 case NTB_B2B_BAR_2: 775 basev = ntb->xlat_reg->bar4_base; 776 lmtv = ntb->xlat_reg->bar4_limit; 777 xlatv = ntb->xlat_reg->bar4_xlat; 778 break; 779 case NTB_B2B_BAR_3: 780 basev = ntb->xlat_reg->bar5_base; 781 lmtv = ntb->xlat_reg->bar5_limit; 782 xlatv = ntb->xlat_reg->bar5_xlat; 783 break; 784 default: 785 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 786 ("bad bar")); 787 basev = lmtv = xlatv = 0; 788 break; 789 } 790 791 if (base != NULL) 792 *base = basev; 793 if (xlat != NULL) 794 *xlat = xlatv; 795 if (lmt != NULL) 796 *lmt = lmtv; 797} 798 799static int 800ntb_map_pci_bars(struct ntb_softc *ntb) 801{ 802 int rc; 803 804 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 805 rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 806 if (rc != 0) 807 goto out; 808 809 ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 810 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 811 if (rc != 0) 812 goto out; 813 ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 814 ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 815 ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 816 817 ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 818 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 819 if (rc != 0) 820 goto out; 821 ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 822 ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 823 ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 824 825 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 826 goto out; 827 828 ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 829 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 830 ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 831 ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 832 ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 833 834out: 835 if (rc != 0) 836 device_printf(ntb->device, 837 "unable to allocate pci resource\n"); 838 return (rc); 839} 840 841static void 842print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 843 const char *kind) 844{ 845 846 device_printf(ntb->device, 847 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 848 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 849 (char *)bar->vbase + bar->size - 1, 850 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 851 (uintmax_t)bar->size, kind); 852} 853 854static int 855map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 856{ 857 858 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 859 &bar->pci_resource_id, RF_ACTIVE); 860 if (bar->pci_resource == NULL) 861 return (ENXIO); 862 863 save_bar_parameters(bar); 864 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 865 print_map_success(ntb, bar, "mmr"); 866 return (0); 867} 868 869static int 870map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 871{ 872 int rc; 873 vm_memattr_t mapmode; 874 uint8_t bar_size_bits = 0; 875 876 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 877 &bar->pci_resource_id, RF_ACTIVE); 878 879 if (bar->pci_resource == NULL) 880 return (ENXIO); 881 882 save_bar_parameters(bar); 883 /* 884 * Ivytown NTB BAR sizes are misreported by the hardware due to a 885 * hardware issue. To work around this, query the size it should be 886 * configured to by the device and modify the resource to correspond to 887 * this new size. The BIOS on systems with this problem is required to 888 * provide enough address space to allow the driver to make this change 889 * safely. 890 * 891 * Ideally I could have just specified the size when I allocated the 892 * resource like: 893 * bus_alloc_resource(ntb->device, 894 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 895 * 1ul << bar_size_bits, RF_ACTIVE); 896 * but the PCI driver does not honor the size in this call, so we have 897 * to modify it after the fact. 898 */ 899 if (HAS_FEATURE(ntb, NTB_BAR_SIZE_4K)) { 900 if (bar->pci_resource_id == PCIR_BAR(2)) 901 bar_size_bits = pci_read_config(ntb->device, 902 XEON_PBAR23SZ_OFFSET, 1); 903 else 904 bar_size_bits = pci_read_config(ntb->device, 905 XEON_PBAR45SZ_OFFSET, 1); 906 907 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 908 bar->pci_resource, bar->pbase, 909 bar->pbase + (1ul << bar_size_bits) - 1); 910 if (rc != 0) { 911 device_printf(ntb->device, 912 "unable to resize bar\n"); 913 return (rc); 914 } 915 916 save_bar_parameters(bar); 917 } 918 919 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 920 print_map_success(ntb, bar, "mw"); 921 922 /* 923 * Optionally, mark MW BARs as anything other than UC to improve 924 * performance. 925 */ 926 mapmode = ntb_pat_flags(); 927 if (mapmode == bar->map_mode) 928 return (0); 929 930 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 931 if (rc == 0) { 932 bar->map_mode = mapmode; 933 device_printf(ntb->device, 934 "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 935 "%s.\n", 936 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 937 (char *)bar->vbase + bar->size - 1, 938 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 939 ntb_vm_memattr_to_str(mapmode)); 940 } else 941 device_printf(ntb->device, 942 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 943 "%s: %d\n", 944 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 945 (char *)bar->vbase + bar->size - 1, 946 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 947 ntb_vm_memattr_to_str(mapmode), rc); 948 /* Proceed anyway */ 949 return (0); 950} 951 952static void 953ntb_unmap_pci_bar(struct ntb_softc *ntb) 954{ 955 struct ntb_pci_bar_info *current_bar; 956 int i; 957 958 for (i = 0; i < NTB_MAX_BARS; i++) { 959 current_bar = &ntb->bar_info[i]; 960 if (current_bar->pci_resource != NULL) 961 bus_release_resource(ntb->device, SYS_RES_MEMORY, 962 current_bar->pci_resource_id, 963 current_bar->pci_resource); 964 } 965} 966 967static int 968ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 969{ 970 uint32_t i; 971 int rc; 972 973 for (i = 0; i < num_vectors; i++) { 974 ntb->int_info[i].rid = i + 1; 975 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 976 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 977 if (ntb->int_info[i].res == NULL) { 978 device_printf(ntb->device, 979 "bus_alloc_resource failed\n"); 980 return (ENOMEM); 981 } 982 ntb->int_info[i].tag = NULL; 983 ntb->allocated_interrupts++; 984 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 985 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 986 &ntb->msix_vec[i], &ntb->int_info[i].tag); 987 if (rc != 0) { 988 device_printf(ntb->device, "bus_setup_intr failed\n"); 989 return (ENXIO); 990 } 991 } 992 return (0); 993} 994 995/* 996 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 997 * cannot be allocated for each MSI-X message. JHB seems to think remapping 998 * should be okay. This tunable should enable us to test that hypothesis 999 * when someone gets their hands on some Xeon hardware. 1000 */ 1001static int ntb_force_remap_mode; 1002TUNABLE_INT("hw.ntb.force_remap_mode", &ntb_force_remap_mode); 1003SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 1004 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 1005 " to a smaller number of ithreads, even if the desired number are " 1006 "available"); 1007 1008/* 1009 * In case it is NOT ok, give consumers an abort button. 1010 */ 1011static int ntb_prefer_intx; 1012TUNABLE_INT("hw.ntb.prefer_intx_to_remap", &ntb_prefer_intx); 1013SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 1014 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 1015 "than remapping MSI-X messages over available slots (match Linux driver " 1016 "behavior)"); 1017 1018/* 1019 * Remap the desired number of MSI-X messages to available ithreads in a simple 1020 * round-robin fashion. 1021 */ 1022static int 1023ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 1024{ 1025 u_int *vectors; 1026 uint32_t i; 1027 int rc; 1028 1029 if (ntb_prefer_intx != 0) 1030 return (ENXIO); 1031 1032 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 1033 1034 for (i = 0; i < desired; i++) 1035 vectors[i] = (i % avail) + 1; 1036 1037 rc = pci_remap_msix(dev, desired, vectors); 1038 free(vectors, M_NTB); 1039 return (rc); 1040} 1041 1042static int 1043ntb_init_isr(struct ntb_softc *ntb) 1044{ 1045 uint32_t desired_vectors, num_vectors; 1046 int rc; 1047 1048 ntb->allocated_interrupts = 0; 1049 ntb->last_ts = ticks; 1050 1051 /* 1052 * Mask all doorbell interrupts. (Except link events!) 1053 */ 1054 DB_MASK_LOCK(ntb); 1055 ntb->db_mask = ntb->db_valid_mask; 1056 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1057 DB_MASK_UNLOCK(ntb); 1058 1059 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 1060 ntb->db_count); 1061 if (desired_vectors >= 1) { 1062 rc = pci_alloc_msix(ntb->device, &num_vectors); 1063 1064 if (ntb_force_remap_mode != 0 && rc == 0 && 1065 num_vectors == desired_vectors) 1066 num_vectors--; 1067 1068 if (rc == 0 && num_vectors < desired_vectors) { 1069 rc = ntb_remap_msix(ntb->device, desired_vectors, 1070 num_vectors); 1071 if (rc == 0) 1072 num_vectors = desired_vectors; 1073 else 1074 pci_release_msi(ntb->device); 1075 } 1076 if (rc != 0) 1077 num_vectors = 1; 1078 } else 1079 num_vectors = 1; 1080 1081 if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 1082 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1083 device_printf(ntb->device, 1084 "Errata workaround does not support MSI or INTX\n"); 1085 return (EINVAL); 1086 } 1087 1088 ntb->db_vec_count = 1; 1089 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 1090 rc = ntb_setup_legacy_interrupt(ntb); 1091 } else { 1092 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS && 1093 HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1094 device_printf(ntb->device, 1095 "Errata workaround expects %d doorbell bits\n", 1096 XEON_NONLINK_DB_MSIX_BITS); 1097 return (EINVAL); 1098 } 1099 1100 ntb_create_msix_vec(ntb, num_vectors); 1101 rc = ntb_setup_msix(ntb, num_vectors); 1102 } 1103 if (rc != 0) { 1104 device_printf(ntb->device, 1105 "Error allocating interrupts: %d\n", rc); 1106 ntb_free_msix_vec(ntb); 1107 } 1108 1109 return (rc); 1110} 1111 1112static int 1113ntb_setup_legacy_interrupt(struct ntb_softc *ntb) 1114{ 1115 int rc; 1116 1117 ntb->int_info[0].rid = 0; 1118 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 1119 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 1120 if (ntb->int_info[0].res == NULL) { 1121 device_printf(ntb->device, "bus_alloc_resource failed\n"); 1122 return (ENOMEM); 1123 } 1124 1125 ntb->int_info[0].tag = NULL; 1126 ntb->allocated_interrupts = 1; 1127 1128 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 1129 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 1130 ntb, &ntb->int_info[0].tag); 1131 if (rc != 0) { 1132 device_printf(ntb->device, "bus_setup_intr failed\n"); 1133 return (ENXIO); 1134 } 1135 1136 return (0); 1137} 1138 1139static void 1140ntb_teardown_interrupts(struct ntb_softc *ntb) 1141{ 1142 struct ntb_int_info *current_int; 1143 int i; 1144 1145 for (i = 0; i < ntb->allocated_interrupts; i++) { 1146 current_int = &ntb->int_info[i]; 1147 if (current_int->tag != NULL) 1148 bus_teardown_intr(ntb->device, current_int->res, 1149 current_int->tag); 1150 1151 if (current_int->res != NULL) 1152 bus_release_resource(ntb->device, SYS_RES_IRQ, 1153 rman_get_rid(current_int->res), current_int->res); 1154 } 1155 1156 ntb_free_msix_vec(ntb); 1157 pci_release_msi(ntb->device); 1158} 1159 1160/* 1161 * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 1162 * out to make code clearer. 1163 */ 1164static inline uint64_t 1165db_ioread(struct ntb_softc *ntb, uint64_t regoff) 1166{ 1167 1168 if (ntb->type == NTB_ATOM) 1169 return (ntb_reg_read(8, regoff)); 1170 1171 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1172 1173 return (ntb_reg_read(2, regoff)); 1174} 1175 1176static inline void 1177db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1178{ 1179 1180 KASSERT((val & ~ntb->db_valid_mask) == 0, 1181 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1182 (uintmax_t)(val & ~ntb->db_valid_mask), 1183 (uintmax_t)ntb->db_valid_mask)); 1184 1185 if (regoff == ntb->self_reg->db_mask) 1186 DB_MASK_ASSERT(ntb, MA_OWNED); 1187 db_iowrite_raw(ntb, regoff, val); 1188} 1189 1190static inline void 1191db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1192{ 1193 1194 if (ntb->type == NTB_ATOM) { 1195 ntb_reg_write(8, regoff, val); 1196 return; 1197 } 1198 1199 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1200 ntb_reg_write(2, regoff, (uint16_t)val); 1201} 1202 1203static void 1204ntb_db_set_mask(device_t dev, uint64_t bits) 1205{ 1206 struct ntb_softc *ntb = device_get_softc(dev); 1207 1208 DB_MASK_LOCK(ntb); 1209 ntb->db_mask |= bits; 1210 if (!HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1211 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1212 DB_MASK_UNLOCK(ntb); 1213} 1214 1215static void 1216ntb_db_clear_mask(device_t dev, uint64_t bits) 1217{ 1218 struct ntb_softc *ntb = device_get_softc(dev); 1219 uint64_t ibits; 1220 int i; 1221 1222 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1223 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1224 (uintmax_t)(bits & ~ntb->db_valid_mask), 1225 (uintmax_t)ntb->db_valid_mask)); 1226 1227 DB_MASK_LOCK(ntb); 1228 ibits = ntb->fake_db_bell & ntb->db_mask & bits; 1229 ntb->db_mask &= ~bits; 1230 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1231 /* Simulate fake interrupts if unmasked DB bits are set. */ 1232 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1233 if ((ibits & ntb_db_vector_mask(dev, i)) != 0) 1234 swi_sched(ntb->int_info[i].tag, 0); 1235 } 1236 } else { 1237 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1238 } 1239 DB_MASK_UNLOCK(ntb); 1240} 1241 1242static uint64_t 1243ntb_db_read(device_t dev) 1244{ 1245 struct ntb_softc *ntb = device_get_softc(dev); 1246 1247 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1248 return (ntb->fake_db_bell); 1249 1250 return (db_ioread(ntb, ntb->self_reg->db_bell)); 1251} 1252 1253static void 1254ntb_db_clear(device_t dev, uint64_t bits) 1255{ 1256 struct ntb_softc *ntb = device_get_softc(dev); 1257 1258 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1259 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1260 (uintmax_t)(bits & ~ntb->db_valid_mask), 1261 (uintmax_t)ntb->db_valid_mask)); 1262 1263 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1264 DB_MASK_LOCK(ntb); 1265 ntb->fake_db_bell &= ~bits; 1266 DB_MASK_UNLOCK(ntb); 1267 return; 1268 } 1269 1270 db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1271} 1272 1273static inline uint64_t 1274ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1275{ 1276 uint64_t shift, mask; 1277 1278 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1279 /* 1280 * Remap vectors in custom way to make at least first 1281 * three doorbells to not generate stray events. 1282 * This breaks Linux compatibility (if one existed) 1283 * when more then one DB is used (not by if_ntb). 1284 */ 1285 if (db_vector < XEON_NONLINK_DB_MSIX_BITS - 1) 1286 return (1 << db_vector); 1287 if (db_vector == XEON_NONLINK_DB_MSIX_BITS - 1) 1288 return (0x7ffc); 1289 } 1290 1291 shift = ntb->db_vec_shift; 1292 mask = (1ull << shift) - 1; 1293 return (mask << (shift * db_vector)); 1294} 1295 1296static void 1297ntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1298{ 1299 uint64_t vec_mask; 1300 1301 ntb->last_ts = ticks; 1302 vec_mask = ntb_vec_mask(ntb, vec); 1303 1304 if ((vec_mask & ntb->db_link_mask) != 0) { 1305 if (ntb_poll_link(ntb)) 1306 ntb_link_event(ntb->device); 1307 } 1308 1309 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1310 (vec_mask & ntb->db_link_mask) == 0) { 1311 DB_MASK_LOCK(ntb); 1312 1313 /* Do not report same DB events again if not cleared yet. */ 1314 vec_mask &= ~ntb->fake_db_bell; 1315 1316 /* Update our internal doorbell register. */ 1317 ntb->fake_db_bell |= vec_mask; 1318 1319 /* Do not report masked DB events. */ 1320 vec_mask &= ~ntb->db_mask; 1321 1322 DB_MASK_UNLOCK(ntb); 1323 } 1324 1325 if ((vec_mask & ntb->db_valid_mask) != 0) 1326 ntb_db_event(ntb->device, vec); 1327} 1328 1329static void 1330ndev_vec_isr(void *arg) 1331{ 1332 struct ntb_vec *nvec = arg; 1333 1334 ntb_interrupt(nvec->ntb, nvec->num); 1335} 1336 1337static void 1338ndev_irq_isr(void *arg) 1339{ 1340 /* If we couldn't set up MSI-X, we only have the one vector. */ 1341 ntb_interrupt(arg, 0); 1342} 1343 1344static int 1345ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1346{ 1347 uint32_t i; 1348 1349 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1350 M_ZERO | M_WAITOK); 1351 for (i = 0; i < num_vectors; i++) { 1352 ntb->msix_vec[i].num = i; 1353 ntb->msix_vec[i].ntb = ntb; 1354 } 1355 1356 return (0); 1357} 1358 1359static void 1360ntb_free_msix_vec(struct ntb_softc *ntb) 1361{ 1362 1363 if (ntb->msix_vec == NULL) 1364 return; 1365 1366 free(ntb->msix_vec, M_NTB); 1367 ntb->msix_vec = NULL; 1368} 1369 1370static void 1371ntb_get_msix_info(struct ntb_softc *ntb) 1372{ 1373 struct pci_devinfo *dinfo; 1374 struct pcicfg_msix *msix; 1375 uint32_t laddr, data, i, offset; 1376 1377 dinfo = device_get_ivars(ntb->device); 1378 msix = &dinfo->cfg.msix; 1379 1380 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data)); 1381 1382 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1383 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE; 1384 1385 laddr = bus_read_4(msix->msix_table_res, offset + 1386 PCI_MSIX_ENTRY_LOWER_ADDR); 1387 ntb_printf(2, "local MSIX addr(%u): 0x%x\n", i, laddr); 1388 1389 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE, 1390 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr, 1391 MSI_INTEL_ADDR_BASE)); 1392 ntb->msix_data[i].nmd_ofs = laddr; 1393 1394 data = bus_read_4(msix->msix_table_res, offset + 1395 PCI_MSIX_ENTRY_DATA); 1396 ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data); 1397 1398 ntb->msix_data[i].nmd_data = data; 1399 } 1400} 1401 1402static struct ntb_hw_info * 1403ntb_get_device_info(uint32_t device_id) 1404{ 1405 struct ntb_hw_info *ep = pci_ids; 1406 1407 while (ep->device_id) { 1408 if (ep->device_id == device_id) 1409 return (ep); 1410 ++ep; 1411 } 1412 return (NULL); 1413} 1414 1415static void 1416ntb_teardown_xeon(struct ntb_softc *ntb) 1417{ 1418 1419 if (ntb->reg != NULL) 1420 ntb_link_disable(ntb->device); 1421} 1422 1423static void 1424ntb_detect_max_mw(struct ntb_softc *ntb) 1425{ 1426 1427 if (ntb->type == NTB_ATOM) { 1428 ntb->mw_count = ATOM_MW_COUNT; 1429 return; 1430 } 1431 1432 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1433 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1434 else 1435 ntb->mw_count = XEON_SNB_MW_COUNT; 1436} 1437 1438static int 1439ntb_detect_xeon(struct ntb_softc *ntb) 1440{ 1441 uint8_t ppd, conn_type; 1442 1443 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1444 ntb->ppd = ppd; 1445 1446 if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1447 ntb->dev_type = NTB_DEV_DSD; 1448 else 1449 ntb->dev_type = NTB_DEV_USD; 1450 1451 if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1452 ntb->features |= NTB_SPLIT_BAR; 1453 1454 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1455 !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1456 device_printf(ntb->device, 1457 "Can not apply SB01BASE_LOCKUP workaround " 1458 "with split BARs disabled!\n"); 1459 device_printf(ntb->device, 1460 "Expect system hangs under heavy NTB traffic!\n"); 1461 ntb->features &= ~NTB_SB01BASE_LOCKUP; 1462 } 1463 1464 /* 1465 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP 1466 * errata workaround; only do one at a time. 1467 */ 1468 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1469 ntb->features &= ~NTB_SDOORBELL_LOCKUP; 1470 1471 conn_type = ppd & XEON_PPD_CONN_TYPE; 1472 switch (conn_type) { 1473 case NTB_CONN_B2B: 1474 ntb->conn_type = conn_type; 1475 break; 1476 case NTB_CONN_RP: 1477 case NTB_CONN_TRANSPARENT: 1478 default: 1479 device_printf(ntb->device, "Unsupported connection type: %u\n", 1480 (unsigned)conn_type); 1481 return (ENXIO); 1482 } 1483 return (0); 1484} 1485 1486static int 1487ntb_detect_atom(struct ntb_softc *ntb) 1488{ 1489 uint32_t ppd, conn_type; 1490 1491 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1492 ntb->ppd = ppd; 1493 1494 if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1495 ntb->dev_type = NTB_DEV_DSD; 1496 else 1497 ntb->dev_type = NTB_DEV_USD; 1498 1499 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1500 switch (conn_type) { 1501 case NTB_CONN_B2B: 1502 ntb->conn_type = conn_type; 1503 break; 1504 default: 1505 device_printf(ntb->device, "Unsupported NTB configuration\n"); 1506 return (ENXIO); 1507 } 1508 return (0); 1509} 1510 1511static int 1512ntb_xeon_init_dev(struct ntb_softc *ntb) 1513{ 1514 int rc; 1515 1516 ntb->spad_count = XEON_SPAD_COUNT; 1517 ntb->db_count = XEON_DB_COUNT; 1518 ntb->db_link_mask = XEON_DB_LINK_BIT; 1519 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1520 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1521 1522 if (ntb->conn_type != NTB_CONN_B2B) { 1523 device_printf(ntb->device, "Connection type %d not supported\n", 1524 ntb->conn_type); 1525 return (ENXIO); 1526 } 1527 1528 ntb->reg = &xeon_reg; 1529 ntb->self_reg = &xeon_pri_reg; 1530 ntb->peer_reg = &xeon_b2b_reg; 1531 ntb->xlat_reg = &xeon_sec_xlat; 1532 1533 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1534 ntb->fake_db_bell = 0; 1535 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) % 1536 ntb->mw_count; 1537 ntb_printf(2, "Setting up MSIX mw idx %d means %u\n", 1538 g_ntb_msix_idx, ntb->msix_mw_idx); 1539 rc = ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx, 1540 VM_MEMATTR_UNCACHEABLE); 1541 KASSERT(rc == 0, ("shouldn't fail")); 1542 } else if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 1543 /* 1544 * There is a Xeon hardware errata related to writes to SDOORBELL or 1545 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1546 * which may hang the system. To workaround this, use a memory 1547 * window to access the interrupt and scratch pad registers on the 1548 * remote system. 1549 */ 1550 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1551 ntb->mw_count; 1552 ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1553 g_ntb_mw_idx, ntb->b2b_mw_idx); 1554 rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, 1555 VM_MEMATTR_UNCACHEABLE); 1556 KASSERT(rc == 0, ("shouldn't fail")); 1557 } else if (HAS_FEATURE(ntb, NTB_B2BDOORBELL_BIT14)) 1558 /* 1559 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1560 * mirrored to the remote system. Shrink the number of bits by one, 1561 * since bit 14 is the last bit. 1562 * 1563 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1564 * anyway. Nor for non-B2B connection types. 1565 */ 1566 ntb->db_count = XEON_DB_COUNT - 1; 1567 1568 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1569 1570 if (ntb->dev_type == NTB_DEV_USD) 1571 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1572 &xeon_b2b_usd_addr); 1573 else 1574 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1575 &xeon_b2b_dsd_addr); 1576 if (rc != 0) 1577 return (rc); 1578 1579 /* Enable Bus Master and Memory Space on the secondary side */ 1580 ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1581 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1582 1583 /* 1584 * Mask all doorbell interrupts. 1585 */ 1586 DB_MASK_LOCK(ntb); 1587 ntb->db_mask = ntb->db_valid_mask; 1588 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1589 DB_MASK_UNLOCK(ntb); 1590 1591 rc = ntb_init_isr(ntb); 1592 return (rc); 1593} 1594 1595static int 1596ntb_atom_init_dev(struct ntb_softc *ntb) 1597{ 1598 int error; 1599 1600 KASSERT(ntb->conn_type == NTB_CONN_B2B, 1601 ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1602 1603 ntb->spad_count = ATOM_SPAD_COUNT; 1604 ntb->db_count = ATOM_DB_COUNT; 1605 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1606 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1607 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1608 1609 ntb->reg = &atom_reg; 1610 ntb->self_reg = &atom_pri_reg; 1611 ntb->peer_reg = &atom_b2b_reg; 1612 ntb->xlat_reg = &atom_sec_xlat; 1613 1614 /* 1615 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1616 * resolved. Mask transaction layer internal parity errors. 1617 */ 1618 pci_write_config(ntb->device, 0xFC, 0x4, 4); 1619 1620 configure_atom_secondary_side_bars(ntb); 1621 1622 /* Enable Bus Master and Memory Space on the secondary side */ 1623 ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1624 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1625 1626 error = ntb_init_isr(ntb); 1627 if (error != 0) 1628 return (error); 1629 1630 /* Initiate PCI-E link training */ 1631 ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1632 1633 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1634 1635 return (0); 1636} 1637 1638/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1639static void 1640configure_atom_secondary_side_bars(struct ntb_softc *ntb) 1641{ 1642 1643 if (ntb->dev_type == NTB_DEV_USD) { 1644 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1645 XEON_B2B_BAR2_ADDR64); 1646 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1647 XEON_B2B_BAR4_ADDR64); 1648 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1649 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1650 } else { 1651 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1652 XEON_B2B_BAR2_ADDR64); 1653 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1654 XEON_B2B_BAR4_ADDR64); 1655 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1656 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1657 } 1658} 1659 1660 1661/* 1662 * When working around Xeon SDOORBELL errata by remapping remote registers in a 1663 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1664 * remains for use by a higher layer. 1665 * 1666 * Will only be used if working around SDOORBELL errata and the BIOS-configured 1667 * MW size is sufficiently large. 1668 */ 1669static unsigned int ntb_b2b_mw_share; 1670TUNABLE_INT("hw.ntb.b2b_mw_share", &ntb_b2b_mw_share); 1671SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1672 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1673 "MW with higher level consumers. Both sides of the NTB MUST set the same " 1674 "value here."); 1675 1676static void 1677xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1678 enum ntb_bar regbar) 1679{ 1680 struct ntb_pci_bar_info *bar; 1681 uint8_t bar_sz; 1682 1683 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1684 return; 1685 1686 bar = &ntb->bar_info[idx]; 1687 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1688 if (idx == regbar) { 1689 if (ntb->b2b_off != 0) 1690 bar_sz--; 1691 else 1692 bar_sz = 0; 1693 } 1694 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1695 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1696 (void)bar_sz; 1697} 1698 1699static void 1700xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1701 enum ntb_bar idx, enum ntb_bar regbar) 1702{ 1703 uint64_t reg_val; 1704 uint32_t base_reg, lmt_reg; 1705 1706 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1707 if (idx == regbar) { 1708 if (ntb->b2b_off) 1709 bar_addr += ntb->b2b_off; 1710 else 1711 bar_addr = 0; 1712 } 1713 1714 if (!bar_is_64bit(ntb, idx)) { 1715 ntb_reg_write(4, base_reg, bar_addr); 1716 reg_val = ntb_reg_read(4, base_reg); 1717 (void)reg_val; 1718 1719 ntb_reg_write(4, lmt_reg, bar_addr); 1720 reg_val = ntb_reg_read(4, lmt_reg); 1721 (void)reg_val; 1722 } else { 1723 ntb_reg_write(8, base_reg, bar_addr); 1724 reg_val = ntb_reg_read(8, base_reg); 1725 (void)reg_val; 1726 1727 ntb_reg_write(8, lmt_reg, bar_addr); 1728 reg_val = ntb_reg_read(8, lmt_reg); 1729 (void)reg_val; 1730 } 1731} 1732 1733static void 1734xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1735{ 1736 struct ntb_pci_bar_info *bar; 1737 1738 bar = &ntb->bar_info[idx]; 1739 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1740 ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1741 base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1742 } else { 1743 ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1744 base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1745 } 1746 (void)base_addr; 1747} 1748 1749static int 1750xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1751 const struct ntb_b2b_addr *peer_addr) 1752{ 1753 struct ntb_pci_bar_info *b2b_bar; 1754 vm_size_t bar_size; 1755 uint64_t bar_addr; 1756 enum ntb_bar b2b_bar_num, i; 1757 1758 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1759 b2b_bar = NULL; 1760 b2b_bar_num = NTB_CONFIG_BAR; 1761 ntb->b2b_off = 0; 1762 } else { 1763 b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1764 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1765 ("invalid b2b mw bar")); 1766 1767 b2b_bar = &ntb->bar_info[b2b_bar_num]; 1768 bar_size = b2b_bar->size; 1769 1770 if (ntb_b2b_mw_share != 0 && 1771 (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1772 ntb->b2b_off = bar_size >> 1; 1773 else if (bar_size >= XEON_B2B_MIN_SIZE) { 1774 ntb->b2b_off = 0; 1775 } else { 1776 device_printf(ntb->device, 1777 "B2B bar size is too small!\n"); 1778 return (EIO); 1779 } 1780 } 1781 1782 /* 1783 * Reset the secondary bar sizes to match the primary bar sizes. 1784 * (Except, disable or halve the size of the B2B secondary bar.) 1785 */ 1786 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1787 xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1788 1789 bar_addr = 0; 1790 if (b2b_bar_num == NTB_CONFIG_BAR) 1791 bar_addr = addr->bar0_addr; 1792 else if (b2b_bar_num == NTB_B2B_BAR_1) 1793 bar_addr = addr->bar2_addr64; 1794 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1795 bar_addr = addr->bar4_addr64; 1796 else if (b2b_bar_num == NTB_B2B_BAR_2) 1797 bar_addr = addr->bar4_addr32; 1798 else if (b2b_bar_num == NTB_B2B_BAR_3) 1799 bar_addr = addr->bar5_addr32; 1800 else 1801 KASSERT(false, ("invalid bar")); 1802 1803 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1804 1805 /* 1806 * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1807 * register BAR. The B2B BAR is either disabled above or configured 1808 * half-size. It starts at PBAR xlat + offset. 1809 * 1810 * Also set up incoming BAR limits == base (zero length window). 1811 */ 1812 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1813 b2b_bar_num); 1814 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1815 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1816 NTB_B2B_BAR_2, b2b_bar_num); 1817 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1818 NTB_B2B_BAR_3, b2b_bar_num); 1819 } else 1820 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1821 NTB_B2B_BAR_2, b2b_bar_num); 1822 1823 /* Zero incoming translation addrs */ 1824 ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1825 ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1826 1827 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1828 uint32_t xlat_reg, lmt_reg; 1829 enum ntb_bar bar_num; 1830 1831 /* 1832 * We point the chosen MSIX MW BAR xlat to remote LAPIC for 1833 * workaround 1834 */ 1835 bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); 1836 bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); 1837 if (bar_is_64bit(ntb, bar_num)) { 1838 ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); 1839 ntb->msix_xlat = ntb_reg_read(8, xlat_reg); 1840 ntb_reg_write(8, lmt_reg, 0); 1841 } else { 1842 ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); 1843 ntb->msix_xlat = ntb_reg_read(4, xlat_reg); 1844 ntb_reg_write(4, lmt_reg, 0); 1845 } 1846 1847 ntb->peer_lapic_bar = &ntb->bar_info[bar_num]; 1848 } 1849 (void)ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET); 1850 (void)ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET); 1851 1852 /* Zero outgoing translation limits (whole bar size windows) */ 1853 ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1854 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1855 1856 /* Set outgoing translation offsets */ 1857 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1858 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1859 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1860 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1861 } else 1862 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1863 1864 /* Set the translation offset for B2B registers */ 1865 bar_addr = 0; 1866 if (b2b_bar_num == NTB_CONFIG_BAR) 1867 bar_addr = peer_addr->bar0_addr; 1868 else if (b2b_bar_num == NTB_B2B_BAR_1) 1869 bar_addr = peer_addr->bar2_addr64; 1870 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1871 bar_addr = peer_addr->bar4_addr64; 1872 else if (b2b_bar_num == NTB_B2B_BAR_2) 1873 bar_addr = peer_addr->bar4_addr32; 1874 else if (b2b_bar_num == NTB_B2B_BAR_3) 1875 bar_addr = peer_addr->bar5_addr32; 1876 else 1877 KASSERT(false, ("invalid bar")); 1878 1879 /* 1880 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1881 * at a time. 1882 */ 1883 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1884 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1885 return (0); 1886} 1887 1888static inline bool 1889_xeon_link_is_up(struct ntb_softc *ntb) 1890{ 1891 1892 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1893 return (true); 1894 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1895} 1896 1897static inline bool 1898link_is_up(struct ntb_softc *ntb) 1899{ 1900 1901 if (ntb->type == NTB_XEON) 1902 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good || 1903 !HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))); 1904 1905 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1906 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1907} 1908 1909static inline bool 1910atom_link_is_err(struct ntb_softc *ntb) 1911{ 1912 uint32_t status; 1913 1914 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1915 1916 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1917 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1918 return (true); 1919 1920 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1921 return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1922} 1923 1924/* Atom does not have link status interrupt, poll on that platform */ 1925static void 1926atom_link_hb(void *arg) 1927{ 1928 struct ntb_softc *ntb = arg; 1929 sbintime_t timo, poll_ts; 1930 1931 timo = NTB_HB_TIMEOUT * hz; 1932 poll_ts = ntb->last_ts + timo; 1933 1934 /* 1935 * Delay polling the link status if an interrupt was received, unless 1936 * the cached link status says the link is down. 1937 */ 1938 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1939 timo = poll_ts - ticks; 1940 goto out; 1941 } 1942 1943 if (ntb_poll_link(ntb)) 1944 ntb_link_event(ntb->device); 1945 1946 if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1947 /* Link is down with error, proceed with recovery */ 1948 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1949 return; 1950 } 1951 1952out: 1953 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1954} 1955 1956static void 1957atom_perform_link_restart(struct ntb_softc *ntb) 1958{ 1959 uint32_t status; 1960 1961 /* Driver resets the NTB ModPhy lanes - magic! */ 1962 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1963 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1964 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1965 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1966 1967 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1968 pause("ModPhy", hz / 10); 1969 1970 /* Clear AER Errors, write to clear */ 1971 status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1972 status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1973 ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1974 1975 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1976 status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1977 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1978 ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1979 1980 /* Clear DeSkew Buffer error, write to clear */ 1981 status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1982 status |= ATOM_DESKEWSTS_DBERR; 1983 ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1984 1985 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1986 status &= ATOM_IBIST_ERR_OFLOW; 1987 ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1988 1989 /* Releases the NTB state machine to allow the link to retrain */ 1990 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1991 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1992 ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1993} 1994 1995static int 1996ntb_set_ctx(device_t dev, void *ctx, const struct ntb_ctx_ops *ops) 1997{ 1998 struct ntb_softc *ntb = device_get_softc(dev); 1999 2000 if (ctx == NULL || ops == NULL) 2001 return (EINVAL); 2002 2003 rm_wlock(&ntb->ctx_lock); 2004 if (ntb->ctx_ops != NULL) { 2005 rm_wunlock(&ntb->ctx_lock); 2006 return (EINVAL); 2007 } 2008 ntb->ntb_ctx = ctx; 2009 ntb->ctx_ops = ops; 2010 rm_wunlock(&ntb->ctx_lock); 2011 2012 return (0); 2013} 2014 2015/* 2016 * It is expected that this will only be used from contexts where the ctx_lock 2017 * is not needed to protect ntb_ctx lifetime. 2018 */ 2019static void * 2020ntb_get_ctx(device_t dev, const struct ntb_ctx_ops **ops) 2021{ 2022 struct ntb_softc *ntb = device_get_softc(dev); 2023 2024 KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 2025 if (ops != NULL) 2026 *ops = ntb->ctx_ops; 2027 return (ntb->ntb_ctx); 2028} 2029 2030static void 2031ntb_clear_ctx(device_t dev) 2032{ 2033 struct ntb_softc *ntb = device_get_softc(dev); 2034 2035 rm_wlock(&ntb->ctx_lock); 2036 ntb->ntb_ctx = NULL; 2037 ntb->ctx_ops = NULL; 2038 rm_wunlock(&ntb->ctx_lock); 2039} 2040 2041/* 2042 * ntb_link_event() - notify driver context of a change in link status 2043 * @ntb: NTB device context 2044 * 2045 * Notify the driver context that the link status may have changed. The driver 2046 * should call ntb_link_is_up() to get the current status. 2047 */ 2048static void 2049ntb_link_event(device_t dev) 2050{ 2051 struct ntb_softc *ntb = device_get_softc(dev); 2052 struct rm_priotracker ctx_tracker; 2053 2054 rm_rlock(&ntb->ctx_lock, &ctx_tracker); 2055 if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 2056 ntb->ctx_ops->link_event(ntb->ntb_ctx); 2057 rm_runlock(&ntb->ctx_lock, &ctx_tracker); 2058} 2059 2060/* 2061 * ntb_db_event() - notify driver context of a doorbell event 2062 * @ntb: NTB device context 2063 * @vector: Interrupt vector number 2064 * 2065 * Notify the driver context of a doorbell event. If hardware supports 2066 * multiple interrupt vectors for doorbells, the vector number indicates which 2067 * vector received the interrupt. The vector number is relative to the first 2068 * vector used for doorbells, starting at zero, and must be less than 2069 * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 2070 * doorbell bits need service, and ntb_db_vector_mask() to determine which of 2071 * those bits are associated with the vector number. 2072 */ 2073static void 2074ntb_db_event(device_t dev, uint32_t vec) 2075{ 2076 struct ntb_softc *ntb = device_get_softc(dev); 2077 struct rm_priotracker ctx_tracker; 2078 2079 rm_rlock(&ntb->ctx_lock, &ctx_tracker); 2080 if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 2081 ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 2082 rm_runlock(&ntb->ctx_lock, &ctx_tracker); 2083} 2084 2085static int 2086ntb_link_enable(device_t dev, enum ntb_speed speed __unused, 2087 enum ntb_width width __unused) 2088{ 2089 struct ntb_softc *ntb = device_get_softc(dev); 2090 uint32_t cntl; 2091 2092 ntb_printf(2, "%s\n", __func__); 2093 2094 if (ntb->type == NTB_ATOM) { 2095 pci_write_config(ntb->device, NTB_PPD_OFFSET, 2096 ntb->ppd | ATOM_PPD_INIT_LINK, 4); 2097 return (0); 2098 } 2099 2100 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2101 ntb_link_event(dev); 2102 return (0); 2103 } 2104 2105 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2106 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 2107 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 2108 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 2109 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2110 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 2111 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2112 return (0); 2113} 2114 2115static int 2116ntb_link_disable(device_t dev) 2117{ 2118 struct ntb_softc *ntb = device_get_softc(dev); 2119 uint32_t cntl; 2120 2121 ntb_printf(2, "%s\n", __func__); 2122 2123 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2124 ntb_link_event(dev); 2125 return (0); 2126 } 2127 2128 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2129 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 2130 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 2131 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2132 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 2133 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 2134 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2135 return (0); 2136} 2137 2138static bool 2139ntb_link_enabled(device_t dev) 2140{ 2141 struct ntb_softc *ntb = device_get_softc(dev); 2142 uint32_t cntl; 2143 2144 if (ntb->type == NTB_ATOM) { 2145 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 2146 return ((cntl & ATOM_PPD_INIT_LINK) != 0); 2147 } 2148 2149 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 2150 return (true); 2151 2152 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2153 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0); 2154} 2155 2156static void 2157recover_atom_link(void *arg) 2158{ 2159 struct ntb_softc *ntb = arg; 2160 unsigned speed, width, oldspeed, oldwidth; 2161 uint32_t status32; 2162 2163 atom_perform_link_restart(ntb); 2164 2165 /* 2166 * There is a potential race between the 2 NTB devices recovering at 2167 * the same time. If the times are the same, the link will not recover 2168 * and the driver will be stuck in this loop forever. Add a random 2169 * interval to the recovery time to prevent this race. 2170 */ 2171 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 2172 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 2173 2174 if (atom_link_is_err(ntb)) 2175 goto retry; 2176 2177 status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 2178 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 2179 goto out; 2180 2181 status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 2182 width = NTB_LNK_STA_WIDTH(status32); 2183 speed = status32 & NTB_LINK_SPEED_MASK; 2184 2185 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 2186 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 2187 if (oldwidth != width || oldspeed != speed) 2188 goto retry; 2189 2190out: 2191 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 2192 ntb); 2193 return; 2194 2195retry: 2196 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 2197 ntb); 2198} 2199 2200/* 2201 * Polls the HW link status register(s); returns true if something has changed. 2202 */ 2203static bool 2204ntb_poll_link(struct ntb_softc *ntb) 2205{ 2206 uint32_t ntb_cntl; 2207 uint16_t reg_val; 2208 2209 if (ntb->type == NTB_ATOM) { 2210 ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2211 if (ntb_cntl == ntb->ntb_ctl) 2212 return (false); 2213 2214 ntb->ntb_ctl = ntb_cntl; 2215 ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 2216 } else { 2217 db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 2218 2219 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2220 if (reg_val == ntb->lnk_sta) 2221 return (false); 2222 2223 ntb->lnk_sta = reg_val; 2224 2225 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 2226 if (_xeon_link_is_up(ntb)) { 2227 if (!ntb->peer_msix_good) { 2228 callout_reset(&ntb->peer_msix_work, 0, 2229 ntb_exchange_msix, ntb); 2230 return (false); 2231 } 2232 } else { 2233 ntb->peer_msix_good = false; 2234 ntb->peer_msix_done = false; 2235 } 2236 } 2237 } 2238 return (true); 2239} 2240 2241static inline enum ntb_speed 2242ntb_link_sta_speed(struct ntb_softc *ntb) 2243{ 2244 2245 if (!link_is_up(ntb)) 2246 return (NTB_SPEED_NONE); 2247 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 2248} 2249 2250static inline enum ntb_width 2251ntb_link_sta_width(struct ntb_softc *ntb) 2252{ 2253 2254 if (!link_is_up(ntb)) 2255 return (NTB_WIDTH_NONE); 2256 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 2257} 2258 2259SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 2260 "Driver state, statistics, and HW registers"); 2261 2262#define NTB_REGSZ_MASK (3ul << 30) 2263#define NTB_REG_64 (1ul << 30) 2264#define NTB_REG_32 (2ul << 30) 2265#define NTB_REG_16 (3ul << 30) 2266#define NTB_REG_8 (0ul << 30) 2267 2268#define NTB_DB_READ (1ul << 29) 2269#define NTB_PCI_REG (1ul << 28) 2270#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 2271 2272static void 2273ntb_sysctl_init(struct ntb_softc *ntb) 2274{ 2275 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar; 2276 struct sysctl_ctx_list *ctx; 2277 struct sysctl_oid *tree, *tmptree; 2278 2279 ctx = device_get_sysctl_ctx(ntb->device); 2280 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); 2281 2282 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status", 2283 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, 2284 sysctl_handle_link_status_human, "A", 2285 "Link status (human readable)"); 2286 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active", 2287 CTLFLAG_RD | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_status, 2288 "IU", "Link status (1=active, 0=inactive)"); 2289 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up", 2290 CTLFLAG_RW | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_admin, 2291 "IU", "Set/get interface status (1=UP, 0=DOWN)"); 2292 2293 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info", 2294 CTLFLAG_RD, NULL, "Driver state, statistics, and HW registers"); 2295 tree_par = SYSCTL_CHILDREN(tree); 2296 2297 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 2298 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 2299 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 2300 &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 2301 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 2302 &ntb->ppd, 0, "Raw PPD register (cached)"); 2303 2304 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 2305#ifdef notyet 2306 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 2307 &ntb->b2b_mw_idx, 0, 2308 "Index of the MW used for B2B remote register access"); 2309#endif 2310 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 2311 CTLFLAG_RD, &ntb->b2b_off, 2312 "If non-zero, offset of B2B register region in shared MW"); 2313 } 2314 2315 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 2316 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 2317 "Features/errata of this NTB device"); 2318 2319 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2320 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2321 "NTB CTL register (cached)"); 2322 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2323 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2324 "LNK STA register (cached)"); 2325 2326#ifdef notyet 2327 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2328 &ntb->mw_count, 0, "MW count"); 2329 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2330 &ntb->spad_count, 0, "Scratchpad count"); 2331 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2332 &ntb->db_count, 0, "Doorbell count"); 2333 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2334 &ntb->db_vec_count, 0, "Doorbell vector count"); 2335 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2336 &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2337#endif 2338 2339 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2340 &ntb->db_valid_mask, "Doorbell valid mask"); 2341 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2342 &ntb->db_link_mask, "Doorbell link mask"); 2343 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2344 &ntb->db_mask, "Doorbell mask (cached)"); 2345 2346 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2347 CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 2348 regpar = SYSCTL_CHILDREN(tmptree); 2349 2350 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2351 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2352 ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2353 "NTB Control register"); 2354 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2355 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2356 0x19c, sysctl_handle_register, "IU", 2357 "NTB Link Capabilities"); 2358 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2359 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2360 0x1a0, sysctl_handle_register, "IU", 2361 "NTB Link Control register"); 2362 2363 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2364 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2365 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2366 sysctl_handle_register, "QU", "Doorbell mask register"); 2367 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2368 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2369 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2370 sysctl_handle_register, "QU", "Doorbell register"); 2371 2372 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2373 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2374 NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2375 sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2376 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2377 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2378 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2379 NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2380 sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2381 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2382 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2383 NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2384 sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2385 } else { 2386 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2387 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2388 NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2389 sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2390 } 2391 2392 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2393 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2394 NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2395 sysctl_handle_register, "QU", "Incoming LMT23 register"); 2396 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2397 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2398 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2399 NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2400 sysctl_handle_register, "IU", "Incoming LMT4 register"); 2401 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2402 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2403 NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2404 sysctl_handle_register, "IU", "Incoming LMT5 register"); 2405 } else { 2406 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2407 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2408 NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2409 sysctl_handle_register, "QU", "Incoming LMT45 register"); 2410 } 2411 2412 if (ntb->type == NTB_ATOM) 2413 return; 2414 2415 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2416 CTLFLAG_RD, NULL, "Xeon HW statistics"); 2417 statpar = SYSCTL_CHILDREN(tmptree); 2418 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2419 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2420 NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2421 sysctl_handle_register, "SU", "Upstream Memory Miss"); 2422 2423 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2424 CTLFLAG_RD, NULL, "Xeon HW errors"); 2425 errpar = SYSCTL_CHILDREN(tmptree); 2426 2427 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2428 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2429 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2430 sysctl_handle_register, "CU", "PPD"); 2431 2432 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2433 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2434 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2435 sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2436 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2437 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2438 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2439 sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2440 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2441 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2442 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2443 sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2444 2445 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2446 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2447 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2448 sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2449 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2450 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2451 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2452 sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2453 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2454 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2455 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2456 sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2457 2458 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2459 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2460 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2461 sysctl_handle_register, "SU", "DEVSTS"); 2462 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2463 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2464 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2465 sysctl_handle_register, "SU", "LNKSTS"); 2466 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2467 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2468 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2469 sysctl_handle_register, "SU", "SLNKSTS"); 2470 2471 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2472 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2473 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2474 sysctl_handle_register, "IU", "UNCERRSTS"); 2475 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2476 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2477 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2478 sysctl_handle_register, "IU", "CORERRSTS"); 2479 2480 if (ntb->conn_type != NTB_CONN_B2B) 2481 return; 2482 2483 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2484 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2485 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2486 sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2487 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2488 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2489 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2490 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2491 sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2492 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2493 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2494 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2495 sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2496 } else { 2497 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2498 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2499 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2500 sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2501 } 2502 2503 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2504 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2505 NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2506 sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2507 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2508 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2509 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2510 NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2511 sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2512 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2513 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2514 NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2515 sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2516 } else { 2517 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2518 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2519 NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2520 sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2521 } 2522 2523 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2524 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2525 NTB_REG_64 | ntb->xlat_reg->bar0_base, 2526 sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2527 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2528 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2529 NTB_REG_64 | ntb->xlat_reg->bar2_base, 2530 sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2531 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2532 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2533 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2534 NTB_REG_32 | ntb->xlat_reg->bar4_base, 2535 sysctl_handle_register, "IU", 2536 "Secondary BAR4 base register"); 2537 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2538 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2539 NTB_REG_32 | ntb->xlat_reg->bar5_base, 2540 sysctl_handle_register, "IU", 2541 "Secondary BAR5 base register"); 2542 } else { 2543 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2544 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2545 NTB_REG_64 | ntb->xlat_reg->bar4_base, 2546 sysctl_handle_register, "QU", 2547 "Secondary BAR45 base register"); 2548 } 2549} 2550 2551static int 2552sysctl_handle_features(SYSCTL_HANDLER_ARGS) 2553{ 2554 struct ntb_softc *ntb = arg1; 2555 struct sbuf sb; 2556 int error; 2557 2558 sbuf_new_for_sysctl(&sb, NULL, 256, req); 2559 2560 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2561 error = sbuf_finish(&sb); 2562 sbuf_delete(&sb); 2563 2564 if (error || !req->newptr) 2565 return (error); 2566 return (EINVAL); 2567} 2568 2569static int 2570sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS) 2571{ 2572 struct ntb_softc *ntb = arg1; 2573 unsigned old, new; 2574 int error; 2575 2576 old = ntb_link_enabled(ntb->device); 2577 2578 error = SYSCTL_OUT(req, &old, sizeof(old)); 2579 if (error != 0 || req->newptr == NULL) 2580 return (error); 2581 2582 error = SYSCTL_IN(req, &new, sizeof(new)); 2583 if (error != 0) 2584 return (error); 2585 2586 ntb_printf(0, "Admin set interface state to '%sabled'\n", 2587 (new != 0)? "en" : "dis"); 2588 2589 if (new != 0) 2590 error = ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 2591 else 2592 error = ntb_link_disable(ntb->device); 2593 return (error); 2594} 2595 2596static int 2597sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS) 2598{ 2599 struct ntb_softc *ntb = arg1; 2600 struct sbuf sb; 2601 enum ntb_speed speed; 2602 enum ntb_width width; 2603 int error; 2604 2605 sbuf_new_for_sysctl(&sb, NULL, 32, req); 2606 2607 if (ntb_link_is_up(ntb->device, &speed, &width)) 2608 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2609 (unsigned)speed, (unsigned)width); 2610 else 2611 sbuf_printf(&sb, "down"); 2612 2613 error = sbuf_finish(&sb); 2614 sbuf_delete(&sb); 2615 2616 if (error || !req->newptr) 2617 return (error); 2618 return (EINVAL); 2619} 2620 2621static int 2622sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2623{ 2624 struct ntb_softc *ntb = arg1; 2625 unsigned res; 2626 int error; 2627 2628 res = ntb_link_is_up(ntb->device, NULL, NULL); 2629 2630 error = SYSCTL_OUT(req, &res, sizeof(res)); 2631 if (error || !req->newptr) 2632 return (error); 2633 return (EINVAL); 2634} 2635 2636static int 2637sysctl_handle_register(SYSCTL_HANDLER_ARGS) 2638{ 2639 struct ntb_softc *ntb; 2640 const void *outp; 2641 uintptr_t sz; 2642 uint64_t umv; 2643 char be[sizeof(umv)]; 2644 size_t outsz; 2645 uint32_t reg; 2646 bool db, pci; 2647 int error; 2648 2649 ntb = arg1; 2650 reg = arg2 & ~NTB_REGFLAGS_MASK; 2651 sz = arg2 & NTB_REGSZ_MASK; 2652 db = (arg2 & NTB_DB_READ) != 0; 2653 pci = (arg2 & NTB_PCI_REG) != 0; 2654 2655 KASSERT(!(db && pci), ("bogus")); 2656 2657 if (db) { 2658 KASSERT(sz == NTB_REG_64, ("bogus")); 2659 umv = db_ioread(ntb, reg); 2660 outsz = sizeof(uint64_t); 2661 } else { 2662 switch (sz) { 2663 case NTB_REG_64: 2664 if (pci) 2665 umv = pci_read_config(ntb->device, reg, 8); 2666 else 2667 umv = ntb_reg_read(8, reg); 2668 outsz = sizeof(uint64_t); 2669 break; 2670 case NTB_REG_32: 2671 if (pci) 2672 umv = pci_read_config(ntb->device, reg, 4); 2673 else 2674 umv = ntb_reg_read(4, reg); 2675 outsz = sizeof(uint32_t); 2676 break; 2677 case NTB_REG_16: 2678 if (pci) 2679 umv = pci_read_config(ntb->device, reg, 2); 2680 else 2681 umv = ntb_reg_read(2, reg); 2682 outsz = sizeof(uint16_t); 2683 break; 2684 case NTB_REG_8: 2685 if (pci) 2686 umv = pci_read_config(ntb->device, reg, 1); 2687 else 2688 umv = ntb_reg_read(1, reg); 2689 outsz = sizeof(uint8_t); 2690 break; 2691 default: 2692 panic("bogus"); 2693 break; 2694 } 2695 } 2696 2697 /* Encode bigendian so that sysctl -x is legible. */ 2698 be64enc(be, umv); 2699 outp = ((char *)be) + sizeof(umv) - outsz; 2700 2701 error = SYSCTL_OUT(req, outp, outsz); 2702 if (error || !req->newptr) 2703 return (error); 2704 return (EINVAL); 2705} 2706 2707static unsigned 2708ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2709{ 2710 2711 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2712 uidx >= ntb->b2b_mw_idx) || 2713 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2714 uidx++; 2715 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2716 uidx >= ntb->b2b_mw_idx) && 2717 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2718 uidx++; 2719 return (uidx); 2720} 2721 2722static void 2723ntb_exchange_msix(void *ctx) 2724{ 2725 struct ntb_softc *ntb; 2726 uint32_t val; 2727 unsigned i; 2728 2729 ntb = ctx; 2730 2731 if (ntb->peer_msix_good) 2732 goto msix_good; 2733 if (ntb->peer_msix_done) 2734 goto msix_done; 2735 2736 ntb_get_msix_info(ntb); 2737 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2738 ntb_peer_spad_write(ntb->device, NTB_MSIX_DATA0 + i, 2739 ntb->msix_data[i].nmd_data); 2740 ntb_peer_spad_write(ntb->device, NTB_MSIX_OFS0 + i, 2741 ntb->msix_data[i].nmd_ofs - ntb->msix_xlat); 2742 } 2743 ntb_peer_spad_write(ntb->device, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD); 2744 2745 ntb_spad_read(ntb->device, NTB_MSIX_GUARD, &val); 2746 if (val != NTB_MSIX_VER_GUARD) 2747 goto reschedule; 2748 2749 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2750 ntb_spad_read(ntb->device, NTB_MSIX_DATA0 + i, &val); 2751 ntb_printf(2, "remote MSIX data(%u): 0x%x\n", i, val); 2752 ntb->peer_msix_data[i].nmd_data = val; 2753 ntb_spad_read(ntb->device, NTB_MSIX_OFS0 + i, &val); 2754 ntb_printf(2, "remote MSIX addr(%u): 0x%x\n", i, val); 2755 ntb->peer_msix_data[i].nmd_ofs = val; 2756 } 2757 2758 ntb->peer_msix_done = true; 2759 2760msix_done: 2761 ntb_peer_spad_write(ntb->device, NTB_MSIX_DONE, NTB_MSIX_RECEIVED); 2762 ntb_spad_read(ntb->device, NTB_MSIX_DONE, &val); 2763 if (val != NTB_MSIX_RECEIVED) 2764 goto reschedule; 2765 2766 ntb->peer_msix_good = true; 2767 /* Give peer time to see our NTB_MSIX_RECEIVED. */ 2768 goto reschedule; 2769 2770msix_good: 2771 ntb_poll_link(ntb); 2772 ntb_link_event(ntb->device); 2773 return; 2774 2775reschedule: 2776 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2777 if (_xeon_link_is_up(ntb)) { 2778 callout_reset(&ntb->peer_msix_work, 2779 hz * (ntb->peer_msix_good ? 2 : 1) / 100, 2780 ntb_exchange_msix, ntb); 2781 } else 2782 ntb_spad_clear(ntb->device); 2783} 2784 2785/* 2786 * Public API to the rest of the OS 2787 */ 2788 2789static uint8_t 2790ntb_spad_count(device_t dev) 2791{ 2792 struct ntb_softc *ntb = device_get_softc(dev); 2793 2794 return (ntb->spad_count); 2795} 2796 2797static uint8_t 2798ntb_mw_count(device_t dev) 2799{ 2800 struct ntb_softc *ntb = device_get_softc(dev); 2801 uint8_t res; 2802 2803 res = ntb->mw_count; 2804 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 2805 res--; 2806 if (ntb->msix_mw_idx != B2B_MW_DISABLED) 2807 res--; 2808 return (res); 2809} 2810 2811static int 2812ntb_spad_write(device_t dev, unsigned int idx, uint32_t val) 2813{ 2814 struct ntb_softc *ntb = device_get_softc(dev); 2815 2816 if (idx >= ntb->spad_count) 2817 return (EINVAL); 2818 2819 ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2820 2821 return (0); 2822} 2823 2824/* 2825 * Zeros the local scratchpad. 2826 */ 2827static void 2828ntb_spad_clear(device_t dev) 2829{ 2830 struct ntb_softc *ntb = device_get_softc(dev); 2831 unsigned i; 2832 2833 for (i = 0; i < ntb->spad_count; i++) 2834 ntb_spad_write(dev, i, 0); 2835} 2836 2837static int 2838ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2839{ 2840 struct ntb_softc *ntb = device_get_softc(dev); 2841 2842 if (idx >= ntb->spad_count) 2843 return (EINVAL); 2844 2845 *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2846 2847 return (0); 2848} 2849 2850static int 2851ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val) 2852{ 2853 struct ntb_softc *ntb = device_get_softc(dev); 2854 2855 if (idx >= ntb->spad_count) 2856 return (EINVAL); 2857 2858 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2859 ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2860 else 2861 ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2862 2863 return (0); 2864} 2865 2866static int 2867ntb_peer_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2868{ 2869 struct ntb_softc *ntb = device_get_softc(dev); 2870 2871 if (idx >= ntb->spad_count) 2872 return (EINVAL); 2873 2874 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2875 *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2876 else 2877 *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2878 2879 return (0); 2880} 2881 2882static int 2883ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base, 2884 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 2885 bus_addr_t *plimit) 2886{ 2887 struct ntb_softc *ntb = device_get_softc(dev); 2888 struct ntb_pci_bar_info *bar; 2889 bus_addr_t limit; 2890 size_t bar_b2b_off; 2891 enum ntb_bar bar_num; 2892 2893 if (mw_idx >= ntb_mw_count(dev)) 2894 return (EINVAL); 2895 mw_idx = ntb_user_mw_to_idx(ntb, mw_idx); 2896 2897 bar_num = ntb_mw_to_bar(ntb, mw_idx); 2898 bar = &ntb->bar_info[bar_num]; 2899 bar_b2b_off = 0; 2900 if (mw_idx == ntb->b2b_mw_idx) { 2901 KASSERT(ntb->b2b_off != 0, 2902 ("user shouldn't get non-shared b2b mw")); 2903 bar_b2b_off = ntb->b2b_off; 2904 } 2905 2906 if (bar_is_64bit(ntb, bar_num)) 2907 limit = BUS_SPACE_MAXADDR; 2908 else 2909 limit = BUS_SPACE_MAXADDR_32BIT; 2910 2911 if (base != NULL) 2912 *base = bar->pbase + bar_b2b_off; 2913 if (vbase != NULL) 2914 *vbase = bar->vbase + bar_b2b_off; 2915 if (size != NULL) 2916 *size = bar->size - bar_b2b_off; 2917 if (align != NULL) 2918 *align = bar->size; 2919 if (align_size != NULL) 2920 *align_size = 1; 2921 if (plimit != NULL) 2922 *plimit = limit; 2923 return (0); 2924} 2925 2926static int 2927ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, size_t size) 2928{ 2929 struct ntb_softc *ntb = device_get_softc(dev); 2930 struct ntb_pci_bar_info *bar; 2931 uint64_t base, limit, reg_val; 2932 size_t bar_size, mw_size; 2933 uint32_t base_reg, xlat_reg, limit_reg; 2934 enum ntb_bar bar_num; 2935 2936 if (idx >= ntb_mw_count(dev)) 2937 return (EINVAL); 2938 idx = ntb_user_mw_to_idx(ntb, idx); 2939 2940 bar_num = ntb_mw_to_bar(ntb, idx); 2941 bar = &ntb->bar_info[bar_num]; 2942 2943 bar_size = bar->size; 2944 if (idx == ntb->b2b_mw_idx) 2945 mw_size = bar_size - ntb->b2b_off; 2946 else 2947 mw_size = bar_size; 2948 2949 /* Hardware requires that addr is aligned to bar size */ 2950 if ((addr & (bar_size - 1)) != 0) 2951 return (EINVAL); 2952 2953 if (size > mw_size) 2954 return (EINVAL); 2955 2956 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2957 2958 limit = 0; 2959 if (bar_is_64bit(ntb, bar_num)) { 2960 base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 2961 2962 if (limit_reg != 0 && size != mw_size) 2963 limit = base + size; 2964 2965 /* Set and verify translation address */ 2966 ntb_reg_write(8, xlat_reg, addr); 2967 reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 2968 if (reg_val != addr) { 2969 ntb_reg_write(8, xlat_reg, 0); 2970 return (EIO); 2971 } 2972 2973 /* Set and verify the limit */ 2974 ntb_reg_write(8, limit_reg, limit); 2975 reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 2976 if (reg_val != limit) { 2977 ntb_reg_write(8, limit_reg, base); 2978 ntb_reg_write(8, xlat_reg, 0); 2979 return (EIO); 2980 } 2981 } else { 2982 /* Configure 32-bit (split) BAR MW */ 2983 2984 if ((addr & UINT32_MAX) != addr) 2985 return (ERANGE); 2986 if (((addr + size) & UINT32_MAX) != (addr + size)) 2987 return (ERANGE); 2988 2989 base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 2990 2991 if (limit_reg != 0 && size != mw_size) 2992 limit = base + size; 2993 2994 /* Set and verify translation address */ 2995 ntb_reg_write(4, xlat_reg, addr); 2996 reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 2997 if (reg_val != addr) { 2998 ntb_reg_write(4, xlat_reg, 0); 2999 return (EIO); 3000 } 3001 3002 /* Set and verify the limit */ 3003 ntb_reg_write(4, limit_reg, limit); 3004 reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 3005 if (reg_val != limit) { 3006 ntb_reg_write(4, limit_reg, base); 3007 ntb_reg_write(4, xlat_reg, 0); 3008 return (EIO); 3009 } 3010 } 3011 return (0); 3012} 3013 3014static int 3015ntb_mw_clear_trans(device_t dev, unsigned mw_idx) 3016{ 3017 3018 return (ntb_mw_set_trans(dev, mw_idx, 0, 0)); 3019} 3020 3021static int 3022ntb_mw_get_wc(device_t dev, unsigned idx, vm_memattr_t *mode) 3023{ 3024 struct ntb_softc *ntb = device_get_softc(dev); 3025 struct ntb_pci_bar_info *bar; 3026 3027 if (idx >= ntb_mw_count(dev)) 3028 return (EINVAL); 3029 idx = ntb_user_mw_to_idx(ntb, idx); 3030 3031 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 3032 *mode = bar->map_mode; 3033 return (0); 3034} 3035 3036static int 3037ntb_mw_set_wc(device_t dev, unsigned idx, vm_memattr_t mode) 3038{ 3039 struct ntb_softc *ntb = device_get_softc(dev); 3040 3041 if (idx >= ntb_mw_count(dev)) 3042 return (EINVAL); 3043 3044 idx = ntb_user_mw_to_idx(ntb, idx); 3045 return (ntb_mw_set_wc_internal(ntb, idx, mode)); 3046} 3047 3048static int 3049ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 3050{ 3051 struct ntb_pci_bar_info *bar; 3052 int rc; 3053 3054 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 3055 if (bar->map_mode == mode) 3056 return (0); 3057 3058 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 3059 if (rc == 0) 3060 bar->map_mode = mode; 3061 3062 return (rc); 3063} 3064 3065static void 3066ntb_peer_db_set(device_t dev, uint64_t bit) 3067{ 3068 struct ntb_softc *ntb = device_get_softc(dev); 3069 3070 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 3071 struct ntb_pci_bar_info *lapic; 3072 unsigned i; 3073 3074 lapic = ntb->peer_lapic_bar; 3075 3076 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3077 if ((bit & ntb_db_vector_mask(dev, i)) != 0) 3078 bus_space_write_4(lapic->pci_bus_tag, 3079 lapic->pci_bus_handle, 3080 ntb->peer_msix_data[i].nmd_ofs, 3081 ntb->peer_msix_data[i].nmd_data); 3082 } 3083 return; 3084 } 3085 3086 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3087 ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 3088 return; 3089 } 3090 3091 db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 3092} 3093 3094static int 3095ntb_peer_db_addr(device_t dev, bus_addr_t *db_addr, vm_size_t *db_size) 3096{ 3097 struct ntb_softc *ntb = device_get_softc(dev); 3098 struct ntb_pci_bar_info *bar; 3099 uint64_t regoff; 3100 3101 KASSERT((db_addr != NULL && db_size != NULL), ("must be non-NULL")); 3102 3103 if (!HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3104 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 3105 regoff = ntb->peer_reg->db_bell; 3106 } else { 3107 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 3108 ("invalid b2b idx")); 3109 3110 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 3111 regoff = XEON_PDOORBELL_OFFSET; 3112 } 3113 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 3114 3115 /* HACK: Specific to current x86 bus implementation. */ 3116 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff); 3117 *db_size = ntb->reg->db_size; 3118 return (0); 3119} 3120 3121static uint64_t 3122ntb_db_valid_mask(device_t dev) 3123{ 3124 struct ntb_softc *ntb = device_get_softc(dev); 3125 3126 return (ntb->db_valid_mask); 3127} 3128 3129static int 3130ntb_db_vector_count(device_t dev) 3131{ 3132 struct ntb_softc *ntb = device_get_softc(dev); 3133 3134 return (ntb->db_vec_count); 3135} 3136 3137static uint64_t 3138ntb_db_vector_mask(device_t dev, uint32_t vector) 3139{ 3140 struct ntb_softc *ntb = device_get_softc(dev); 3141 3142 if (vector > ntb->db_vec_count) 3143 return (0); 3144 return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 3145} 3146 3147static bool 3148ntb_link_is_up(device_t dev, enum ntb_speed *speed, enum ntb_width *width) 3149{ 3150 struct ntb_softc *ntb = device_get_softc(dev); 3151 3152 if (speed != NULL) 3153 *speed = ntb_link_sta_speed(ntb); 3154 if (width != NULL) 3155 *width = ntb_link_sta_width(ntb); 3156 return (link_is_up(ntb)); 3157} 3158 3159static void 3160save_bar_parameters(struct ntb_pci_bar_info *bar) 3161{ 3162 3163 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 3164 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 3165 bar->pbase = rman_get_start(bar->pci_resource); 3166 bar->size = rman_get_size(bar->pci_resource); 3167 bar->vbase = rman_get_virtual(bar->pci_resource); 3168} 3169 3170static device_method_t ntb_intel_methods[] = { 3171 /* Device interface */ 3172 DEVMETHOD(device_probe, ntb_probe), 3173 DEVMETHOD(device_attach, ntb_attach), 3174 DEVMETHOD(device_detach, ntb_detach), 3175 /* NTB interface */ 3176 DEVMETHOD(ntb_link_is_up, ntb_link_is_up), 3177 DEVMETHOD(ntb_link_enable, ntb_link_enable), 3178 DEVMETHOD(ntb_link_disable, ntb_link_disable), 3179 DEVMETHOD(ntb_link_enabled, ntb_link_enabled), 3180 DEVMETHOD(ntb_set_ctx, ntb_set_ctx), 3181 DEVMETHOD(ntb_get_ctx, ntb_get_ctx), 3182 DEVMETHOD(ntb_clear_ctx, ntb_clear_ctx), 3183 DEVMETHOD(ntb_mw_count, ntb_mw_count), 3184 DEVMETHOD(ntb_mw_get_range, ntb_mw_get_range), 3185 DEVMETHOD(ntb_mw_set_trans, ntb_mw_set_trans), 3186 DEVMETHOD(ntb_mw_clear_trans, ntb_mw_clear_trans), 3187 DEVMETHOD(ntb_mw_get_wc, ntb_mw_get_wc), 3188 DEVMETHOD(ntb_mw_set_wc, ntb_mw_set_wc), 3189 DEVMETHOD(ntb_spad_count, ntb_spad_count), 3190 DEVMETHOD(ntb_spad_clear, ntb_spad_clear), 3191 DEVMETHOD(ntb_spad_write, ntb_spad_write), 3192 DEVMETHOD(ntb_spad_read, ntb_spad_read), 3193 DEVMETHOD(ntb_peer_spad_write, ntb_peer_spad_write), 3194 DEVMETHOD(ntb_peer_spad_read, ntb_peer_spad_read), 3195 DEVMETHOD(ntb_db_valid_mask, ntb_db_valid_mask), 3196 DEVMETHOD(ntb_db_vector_count, ntb_db_vector_count), 3197 DEVMETHOD(ntb_db_vector_mask, ntb_db_vector_mask), 3198 DEVMETHOD(ntb_db_clear, ntb_db_clear), 3199 DEVMETHOD(ntb_db_clear_mask, ntb_db_clear_mask), 3200 DEVMETHOD(ntb_db_read, ntb_db_read), 3201 DEVMETHOD(ntb_db_set_mask, ntb_db_set_mask), 3202 DEVMETHOD(ntb_peer_db_addr, ntb_peer_db_addr), 3203 DEVMETHOD(ntb_peer_db_set, ntb_peer_db_set), 3204 DEVMETHOD_END 3205}; 3206 3207static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods, 3208 sizeof(struct ntb_softc)); 3209DRIVER_MODULE(ntb_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL); 3210MODULE_DEPEND(ntb_intel, ntb, 1, 1, 1); 3211MODULE_VERSION(ntb_intel, 1); 3212