ntb_hw.c revision 304399
1/*- 2 * Copyright (c) 2016 Alexander Motin <mav@FreeBSD.org> 3 * Copyright (C) 2013 Intel Corporation 4 * Copyright (C) 2015 EMC Corporation 5 * All rights reserved. 6 * 7 * Redistribution and use in source and binary forms, with or without 8 * modification, are permitted provided that the following conditions 9 * are met: 10 * 1. Redistributions of source code must retain the above copyright 11 * notice, this list of conditions and the following disclaimer. 12 * 2. Redistributions in binary form must reproduce the above copyright 13 * notice, this list of conditions and the following disclaimer in the 14 * documentation and/or other materials provided with the distribution. 15 * 16 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 17 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 18 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 19 * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 20 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 21 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 22 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 23 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 24 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 25 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 26 * SUCH DAMAGE. 27 */ 28 29/* 30 * The Non-Transparent Bridge (NTB) is a device that allows you to connect 31 * two or more systems using a PCI-e links, providing remote memory access. 32 * 33 * This module contains a driver for NTB hardware in Intel Xeon/Atom CPUs. 34 * 35 * NOTE: Much of the code in this module is shared with Linux. Any patches may 36 * be picked up and redistributed in Linux with a dual GPL/BSD license. 37 */ 38 39#include <sys/cdefs.h> 40__FBSDID("$FreeBSD: stable/10/sys/dev/ntb/ntb_hw/ntb_hw.c 304399 2016-08-18 10:53:03Z mav $"); 41 42#include <sys/param.h> 43#include <sys/kernel.h> 44#include <sys/systm.h> 45#include <sys/bus.h> 46#include <sys/endian.h> 47#include <sys/interrupt.h> 48#include <sys/malloc.h> 49#include <sys/module.h> 50#include <sys/mutex.h> 51#include <sys/pciio.h> 52#include <sys/queue.h> 53#include <sys/rman.h> 54#include <sys/rmlock.h> 55#include <sys/sbuf.h> 56#include <sys/sysctl.h> 57#include <vm/vm.h> 58#include <vm/pmap.h> 59#include <machine/bus.h> 60#include <machine/intr_machdep.h> 61#include <machine/pmap.h> 62#include <machine/resource.h> 63#include <dev/pci/pcireg.h> 64#include <dev/pci/pcivar.h> 65 66#include "ntb_regs.h" 67#include "../ntb.h" 68 69#define MAX_MSIX_INTERRUPTS MAX(XEON_DB_COUNT, ATOM_DB_COUNT) 70 71#define NTB_HB_TIMEOUT 1 /* second */ 72#define ATOM_LINK_RECOVERY_TIME 500 /* ms */ 73#define BAR_HIGH_MASK (~((1ull << 12) - 1)) 74 75#define NTB_MSIX_VER_GUARD 0xaabbccdd 76#define NTB_MSIX_RECEIVED 0xe0f0e0f0 77 78/* 79 * PCI constants could be somewhere more generic, but aren't defined/used in 80 * pci.c. 81 */ 82#define PCI_MSIX_ENTRY_SIZE 16 83#define PCI_MSIX_ENTRY_LOWER_ADDR 0 84#define PCI_MSIX_ENTRY_UPPER_ADDR 4 85#define PCI_MSIX_ENTRY_DATA 8 86 87enum ntb_device_type { 88 NTB_XEON, 89 NTB_ATOM 90}; 91 92/* ntb_conn_type are hardware numbers, cannot change. */ 93enum ntb_conn_type { 94 NTB_CONN_TRANSPARENT = 0, 95 NTB_CONN_B2B = 1, 96 NTB_CONN_RP = 2, 97}; 98 99enum ntb_b2b_direction { 100 NTB_DEV_USD = 0, 101 NTB_DEV_DSD = 1, 102}; 103 104enum ntb_bar { 105 NTB_CONFIG_BAR = 0, 106 NTB_B2B_BAR_1, 107 NTB_B2B_BAR_2, 108 NTB_B2B_BAR_3, 109 NTB_MAX_BARS 110}; 111 112enum { 113 NTB_MSIX_GUARD = 0, 114 NTB_MSIX_DATA0, 115 NTB_MSIX_DATA1, 116 NTB_MSIX_DATA2, 117 NTB_MSIX_OFS0, 118 NTB_MSIX_OFS1, 119 NTB_MSIX_OFS2, 120 NTB_MSIX_DONE, 121 NTB_MAX_MSIX_SPAD 122}; 123 124/* Device features and workarounds */ 125#define HAS_FEATURE(ntb, feature) \ 126 (((ntb)->features & (feature)) != 0) 127 128struct ntb_hw_info { 129 uint32_t device_id; 130 const char *desc; 131 enum ntb_device_type type; 132 uint32_t features; 133}; 134 135struct ntb_pci_bar_info { 136 bus_space_tag_t pci_bus_tag; 137 bus_space_handle_t pci_bus_handle; 138 int pci_resource_id; 139 struct resource *pci_resource; 140 vm_paddr_t pbase; 141 caddr_t vbase; 142 vm_size_t size; 143 vm_memattr_t map_mode; 144 145 /* Configuration register offsets */ 146 uint32_t psz_off; 147 uint32_t ssz_off; 148 uint32_t pbarxlat_off; 149}; 150 151struct ntb_int_info { 152 struct resource *res; 153 int rid; 154 void *tag; 155}; 156 157struct ntb_vec { 158 struct ntb_softc *ntb; 159 uint32_t num; 160 unsigned masked; 161}; 162 163struct ntb_reg { 164 uint32_t ntb_ctl; 165 uint32_t lnk_sta; 166 uint8_t db_size; 167 unsigned mw_bar[NTB_MAX_BARS]; 168}; 169 170struct ntb_alt_reg { 171 uint32_t db_bell; 172 uint32_t db_mask; 173 uint32_t spad; 174}; 175 176struct ntb_xlat_reg { 177 uint32_t bar0_base; 178 uint32_t bar2_base; 179 uint32_t bar4_base; 180 uint32_t bar5_base; 181 182 uint32_t bar2_xlat; 183 uint32_t bar4_xlat; 184 uint32_t bar5_xlat; 185 186 uint32_t bar2_limit; 187 uint32_t bar4_limit; 188 uint32_t bar5_limit; 189}; 190 191struct ntb_b2b_addr { 192 uint64_t bar0_addr; 193 uint64_t bar2_addr64; 194 uint64_t bar4_addr64; 195 uint64_t bar4_addr32; 196 uint64_t bar5_addr32; 197}; 198 199struct ntb_msix_data { 200 uint32_t nmd_ofs; 201 uint32_t nmd_data; 202}; 203 204struct ntb_softc { 205 device_t device; 206 enum ntb_device_type type; 207 uint32_t features; 208 209 struct ntb_pci_bar_info bar_info[NTB_MAX_BARS]; 210 struct ntb_int_info int_info[MAX_MSIX_INTERRUPTS]; 211 uint32_t allocated_interrupts; 212 213 struct ntb_msix_data peer_msix_data[XEON_NONLINK_DB_MSIX_BITS]; 214 struct ntb_msix_data msix_data[XEON_NONLINK_DB_MSIX_BITS]; 215 bool peer_msix_good; 216 bool peer_msix_done; 217 struct ntb_pci_bar_info *peer_lapic_bar; 218 struct callout peer_msix_work; 219 220 struct callout heartbeat_timer; 221 struct callout lr_timer; 222 223 void *ntb_ctx; 224 const struct ntb_ctx_ops *ctx_ops; 225 struct ntb_vec *msix_vec; 226 struct rmlock ctx_lock; 227 228 uint32_t ppd; 229 enum ntb_conn_type conn_type; 230 enum ntb_b2b_direction dev_type; 231 232 /* Offset of peer bar0 in B2B BAR */ 233 uint64_t b2b_off; 234 /* Memory window used to access peer bar0 */ 235#define B2B_MW_DISABLED UINT8_MAX 236 uint8_t b2b_mw_idx; 237 uint32_t msix_xlat; 238 uint8_t msix_mw_idx; 239 240 uint8_t mw_count; 241 uint8_t spad_count; 242 uint8_t db_count; 243 uint8_t db_vec_count; 244 uint8_t db_vec_shift; 245 246 /* Protects local db_mask. */ 247#define DB_MASK_LOCK(sc) mtx_lock_spin(&(sc)->db_mask_lock) 248#define DB_MASK_UNLOCK(sc) mtx_unlock_spin(&(sc)->db_mask_lock) 249#define DB_MASK_ASSERT(sc,f) mtx_assert(&(sc)->db_mask_lock, (f)) 250 struct mtx db_mask_lock; 251 252 volatile uint32_t ntb_ctl; 253 volatile uint32_t lnk_sta; 254 255 uint64_t db_valid_mask; 256 uint64_t db_link_mask; 257 uint64_t db_mask; 258 uint64_t fake_db_bell; /* NTB_SB01BASE_LOCKUP*/ 259 260 int last_ts; /* ticks @ last irq */ 261 262 const struct ntb_reg *reg; 263 const struct ntb_alt_reg *self_reg; 264 const struct ntb_alt_reg *peer_reg; 265 const struct ntb_xlat_reg *xlat_reg; 266}; 267 268#ifdef __i386__ 269static __inline uint64_t 270bus_space_read_8(bus_space_tag_t tag, bus_space_handle_t handle, 271 bus_size_t offset) 272{ 273 274 return (bus_space_read_4(tag, handle, offset) | 275 ((uint64_t)bus_space_read_4(tag, handle, offset + 4)) << 32); 276} 277 278static __inline void 279bus_space_write_8(bus_space_tag_t tag, bus_space_handle_t handle, 280 bus_size_t offset, uint64_t val) 281{ 282 283 bus_space_write_4(tag, handle, offset, val); 284 bus_space_write_4(tag, handle, offset + 4, val >> 32); 285} 286#endif 287 288#define ntb_bar_read(SIZE, bar, offset) \ 289 bus_space_read_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 290 ntb->bar_info[(bar)].pci_bus_handle, (offset)) 291#define ntb_bar_write(SIZE, bar, offset, val) \ 292 bus_space_write_ ## SIZE (ntb->bar_info[(bar)].pci_bus_tag, \ 293 ntb->bar_info[(bar)].pci_bus_handle, (offset), (val)) 294#define ntb_reg_read(SIZE, offset) ntb_bar_read(SIZE, NTB_CONFIG_BAR, offset) 295#define ntb_reg_write(SIZE, offset, val) \ 296 ntb_bar_write(SIZE, NTB_CONFIG_BAR, offset, val) 297#define ntb_mw_read(SIZE, offset) \ 298 ntb_bar_read(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), offset) 299#define ntb_mw_write(SIZE, offset, val) \ 300 ntb_bar_write(SIZE, ntb_mw_to_bar(ntb, ntb->b2b_mw_idx), \ 301 offset, val) 302 303static int ntb_probe(device_t device); 304static int ntb_attach(device_t device); 305static int ntb_detach(device_t device); 306static uint64_t ntb_db_valid_mask(device_t dev); 307static void ntb_spad_clear(device_t dev); 308static uint64_t ntb_db_vector_mask(device_t dev, uint32_t vector); 309static bool ntb_link_is_up(device_t dev, enum ntb_speed *speed, 310 enum ntb_width *width); 311static int ntb_link_enable(device_t dev, enum ntb_speed speed, 312 enum ntb_width width); 313static int ntb_link_disable(device_t dev); 314static int ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val); 315static int ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val); 316 317static unsigned ntb_user_mw_to_idx(struct ntb_softc *, unsigned uidx); 318static inline enum ntb_bar ntb_mw_to_bar(struct ntb_softc *, unsigned mw); 319static inline bool bar_is_64bit(struct ntb_softc *, enum ntb_bar); 320static inline void bar_get_xlat_params(struct ntb_softc *, enum ntb_bar, 321 uint32_t *base, uint32_t *xlat, uint32_t *lmt); 322static int ntb_map_pci_bars(struct ntb_softc *ntb); 323static int ntb_mw_set_wc_internal(struct ntb_softc *, unsigned idx, 324 vm_memattr_t); 325static void print_map_success(struct ntb_softc *, struct ntb_pci_bar_info *, 326 const char *); 327static int map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar); 328static int map_memory_window_bar(struct ntb_softc *ntb, 329 struct ntb_pci_bar_info *bar); 330static void ntb_unmap_pci_bar(struct ntb_softc *ntb); 331static int ntb_remap_msix(device_t, uint32_t desired, uint32_t avail); 332static int ntb_init_isr(struct ntb_softc *ntb); 333static int ntb_setup_legacy_interrupt(struct ntb_softc *ntb); 334static int ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors); 335static void ntb_teardown_interrupts(struct ntb_softc *ntb); 336static inline uint64_t ntb_vec_mask(struct ntb_softc *, uint64_t db_vector); 337static void ntb_interrupt(struct ntb_softc *, uint32_t vec); 338static void ndev_vec_isr(void *arg); 339static void ndev_irq_isr(void *arg); 340static inline uint64_t db_ioread(struct ntb_softc *, uint64_t regoff); 341static inline void db_iowrite(struct ntb_softc *, uint64_t regoff, uint64_t); 342static inline void db_iowrite_raw(struct ntb_softc *, uint64_t regoff, uint64_t); 343static int ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors); 344static void ntb_free_msix_vec(struct ntb_softc *ntb); 345static void ntb_get_msix_info(struct ntb_softc *ntb); 346static void ntb_exchange_msix(void *); 347static struct ntb_hw_info *ntb_get_device_info(uint32_t device_id); 348static void ntb_detect_max_mw(struct ntb_softc *ntb); 349static int ntb_detect_xeon(struct ntb_softc *ntb); 350static int ntb_detect_atom(struct ntb_softc *ntb); 351static int ntb_xeon_init_dev(struct ntb_softc *ntb); 352static int ntb_atom_init_dev(struct ntb_softc *ntb); 353static void ntb_teardown_xeon(struct ntb_softc *ntb); 354static void configure_atom_secondary_side_bars(struct ntb_softc *ntb); 355static void xeon_reset_sbar_size(struct ntb_softc *, enum ntb_bar idx, 356 enum ntb_bar regbar); 357static void xeon_set_sbar_base_and_limit(struct ntb_softc *, 358 uint64_t base_addr, enum ntb_bar idx, enum ntb_bar regbar); 359static void xeon_set_pbar_xlat(struct ntb_softc *, uint64_t base_addr, 360 enum ntb_bar idx); 361static int xeon_setup_b2b_mw(struct ntb_softc *, 362 const struct ntb_b2b_addr *addr, const struct ntb_b2b_addr *peer_addr); 363static inline bool link_is_up(struct ntb_softc *ntb); 364static inline bool _xeon_link_is_up(struct ntb_softc *ntb); 365static inline bool atom_link_is_err(struct ntb_softc *ntb); 366static inline enum ntb_speed ntb_link_sta_speed(struct ntb_softc *); 367static inline enum ntb_width ntb_link_sta_width(struct ntb_softc *); 368static void atom_link_hb(void *arg); 369static void ntb_link_event(device_t dev); 370static void ntb_db_event(device_t dev, uint32_t vec); 371static void recover_atom_link(void *arg); 372static bool ntb_poll_link(struct ntb_softc *ntb); 373static void save_bar_parameters(struct ntb_pci_bar_info *bar); 374static void ntb_sysctl_init(struct ntb_softc *); 375static int sysctl_handle_features(SYSCTL_HANDLER_ARGS); 376static int sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS); 377static int sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS); 378static int sysctl_handle_link_status(SYSCTL_HANDLER_ARGS); 379static int sysctl_handle_register(SYSCTL_HANDLER_ARGS); 380 381static unsigned g_ntb_hw_debug_level; 382TUNABLE_INT("hw.ntb.debug_level", &g_ntb_hw_debug_level); 383SYSCTL_UINT(_hw_ntb, OID_AUTO, debug_level, CTLFLAG_RWTUN, 384 &g_ntb_hw_debug_level, 0, "ntb_hw log level -- higher is more verbose"); 385#define ntb_printf(lvl, ...) do { \ 386 if ((lvl) <= g_ntb_hw_debug_level) { \ 387 device_printf(ntb->device, __VA_ARGS__); \ 388 } \ 389} while (0) 390 391#define _NTB_PAT_UC 0 392#define _NTB_PAT_WC 1 393#define _NTB_PAT_WT 4 394#define _NTB_PAT_WP 5 395#define _NTB_PAT_WB 6 396#define _NTB_PAT_UCM 7 397static unsigned g_ntb_mw_pat = _NTB_PAT_UC; 398TUNABLE_INT("hw.ntb.default_mw_pat", &g_ntb_mw_pat); 399SYSCTL_UINT(_hw_ntb, OID_AUTO, default_mw_pat, CTLFLAG_RDTUN, 400 &g_ntb_mw_pat, 0, "Configure the default memory window cache flags (PAT): " 401 "UC: " __XSTRING(_NTB_PAT_UC) ", " 402 "WC: " __XSTRING(_NTB_PAT_WC) ", " 403 "WT: " __XSTRING(_NTB_PAT_WT) ", " 404 "WP: " __XSTRING(_NTB_PAT_WP) ", " 405 "WB: " __XSTRING(_NTB_PAT_WB) ", " 406 "UC-: " __XSTRING(_NTB_PAT_UCM)); 407 408static inline vm_memattr_t 409ntb_pat_flags(void) 410{ 411 412 switch (g_ntb_mw_pat) { 413 case _NTB_PAT_WC: 414 return (VM_MEMATTR_WRITE_COMBINING); 415 case _NTB_PAT_WT: 416 return (VM_MEMATTR_WRITE_THROUGH); 417 case _NTB_PAT_WP: 418 return (VM_MEMATTR_WRITE_PROTECTED); 419 case _NTB_PAT_WB: 420 return (VM_MEMATTR_WRITE_BACK); 421 case _NTB_PAT_UCM: 422 return (VM_MEMATTR_WEAK_UNCACHEABLE); 423 case _NTB_PAT_UC: 424 /* FALLTHROUGH */ 425 default: 426 return (VM_MEMATTR_UNCACHEABLE); 427 } 428} 429 430/* 431 * Well, this obviously doesn't belong here, but it doesn't seem to exist 432 * anywhere better yet. 433 */ 434static inline const char * 435ntb_vm_memattr_to_str(vm_memattr_t pat) 436{ 437 438 switch (pat) { 439 case VM_MEMATTR_WRITE_COMBINING: 440 return ("WRITE_COMBINING"); 441 case VM_MEMATTR_WRITE_THROUGH: 442 return ("WRITE_THROUGH"); 443 case VM_MEMATTR_WRITE_PROTECTED: 444 return ("WRITE_PROTECTED"); 445 case VM_MEMATTR_WRITE_BACK: 446 return ("WRITE_BACK"); 447 case VM_MEMATTR_WEAK_UNCACHEABLE: 448 return ("UNCACHED"); 449 case VM_MEMATTR_UNCACHEABLE: 450 return ("UNCACHEABLE"); 451 default: 452 return ("UNKNOWN"); 453 } 454} 455 456static int g_ntb_msix_idx = 1; 457TUNABLE_INT("hw.ntb.msix_mw_idx", &g_ntb_msix_idx); 458SYSCTL_INT(_hw_ntb, OID_AUTO, msix_mw_idx, CTLFLAG_RDTUN, &g_ntb_msix_idx, 459 0, "Use this memory window to access the peer MSIX message complex on " 460 "certain Xeon-based NTB systems, as a workaround for a hardware errata. " 461 "Like b2b_mw_idx, negative values index from the last available memory " 462 "window. (Applies on Xeon platforms with SB01BASE_LOCKUP errata.)"); 463 464static int g_ntb_mw_idx = -1; 465TUNABLE_INT("hw.ntb.b2b_mw_idx", &g_ntb_mw_idx); 466SYSCTL_INT(_hw_ntb, OID_AUTO, b2b_mw_idx, CTLFLAG_RDTUN, &g_ntb_mw_idx, 467 0, "Use this memory window to access the peer NTB registers. A " 468 "non-negative value starts from the first MW index; a negative value " 469 "starts from the last MW index. The default is -1, i.e., the last " 470 "available memory window. Both sides of the NTB MUST set the same " 471 "value here! (Applies on Xeon platforms with SDOORBELL_LOCKUP errata.)"); 472 473/* Hardware owns the low 16 bits of features. */ 474#define NTB_BAR_SIZE_4K (1 << 0) 475#define NTB_SDOORBELL_LOCKUP (1 << 1) 476#define NTB_SB01BASE_LOCKUP (1 << 2) 477#define NTB_B2BDOORBELL_BIT14 (1 << 3) 478/* Software/configuration owns the top 16 bits. */ 479#define NTB_SPLIT_BAR (1ull << 16) 480 481#define NTB_FEATURES_STR \ 482 "\20\21SPLIT_BAR4\04B2B_DOORBELL_BIT14\03SB01BASE_LOCKUP" \ 483 "\02SDOORBELL_LOCKUP\01BAR_SIZE_4K" 484 485static struct ntb_hw_info pci_ids[] = { 486 /* XXX: PS/SS IDs left out until they are supported. */ 487 { 0x0C4E8086, "BWD Atom Processor S1200 Non-Transparent Bridge B2B", 488 NTB_ATOM, 0 }, 489 490 { 0x37258086, "JSF Xeon C35xx/C55xx Non-Transparent Bridge B2B", 491 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 492 { 0x3C0D8086, "SNB Xeon E5/Core i7 Non-Transparent Bridge B2B", 493 NTB_XEON, NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 }, 494 { 0x0E0D8086, "IVT Xeon E5 V2 Non-Transparent Bridge B2B", NTB_XEON, 495 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 496 NTB_SB01BASE_LOCKUP | NTB_BAR_SIZE_4K }, 497 { 0x2F0D8086, "HSX Xeon E5 V3 Non-Transparent Bridge B2B", NTB_XEON, 498 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 499 NTB_SB01BASE_LOCKUP }, 500 { 0x6F0D8086, "BDX Xeon E5 V4 Non-Transparent Bridge B2B", NTB_XEON, 501 NTB_SDOORBELL_LOCKUP | NTB_B2BDOORBELL_BIT14 | 502 NTB_SB01BASE_LOCKUP }, 503 504 { 0x00000000, NULL, NTB_ATOM, 0 } 505}; 506 507static const struct ntb_reg atom_reg = { 508 .ntb_ctl = ATOM_NTBCNTL_OFFSET, 509 .lnk_sta = ATOM_LINK_STATUS_OFFSET, 510 .db_size = sizeof(uint64_t), 511 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2 }, 512}; 513 514static const struct ntb_alt_reg atom_pri_reg = { 515 .db_bell = ATOM_PDOORBELL_OFFSET, 516 .db_mask = ATOM_PDBMSK_OFFSET, 517 .spad = ATOM_SPAD_OFFSET, 518}; 519 520static const struct ntb_alt_reg atom_b2b_reg = { 521 .db_bell = ATOM_B2B_DOORBELL_OFFSET, 522 .spad = ATOM_B2B_SPAD_OFFSET, 523}; 524 525static const struct ntb_xlat_reg atom_sec_xlat = { 526#if 0 527 /* "FIXME" says the Linux driver. */ 528 .bar0_base = ATOM_SBAR0BASE_OFFSET, 529 .bar2_base = ATOM_SBAR2BASE_OFFSET, 530 .bar4_base = ATOM_SBAR4BASE_OFFSET, 531 532 .bar2_limit = ATOM_SBAR2LMT_OFFSET, 533 .bar4_limit = ATOM_SBAR4LMT_OFFSET, 534#endif 535 536 .bar2_xlat = ATOM_SBAR2XLAT_OFFSET, 537 .bar4_xlat = ATOM_SBAR4XLAT_OFFSET, 538}; 539 540static const struct ntb_reg xeon_reg = { 541 .ntb_ctl = XEON_NTBCNTL_OFFSET, 542 .lnk_sta = XEON_LINK_STATUS_OFFSET, 543 .db_size = sizeof(uint16_t), 544 .mw_bar = { NTB_B2B_BAR_1, NTB_B2B_BAR_2, NTB_B2B_BAR_3 }, 545}; 546 547static const struct ntb_alt_reg xeon_pri_reg = { 548 .db_bell = XEON_PDOORBELL_OFFSET, 549 .db_mask = XEON_PDBMSK_OFFSET, 550 .spad = XEON_SPAD_OFFSET, 551}; 552 553static const struct ntb_alt_reg xeon_b2b_reg = { 554 .db_bell = XEON_B2B_DOORBELL_OFFSET, 555 .spad = XEON_B2B_SPAD_OFFSET, 556}; 557 558static const struct ntb_xlat_reg xeon_sec_xlat = { 559 .bar0_base = XEON_SBAR0BASE_OFFSET, 560 .bar2_base = XEON_SBAR2BASE_OFFSET, 561 .bar4_base = XEON_SBAR4BASE_OFFSET, 562 .bar5_base = XEON_SBAR5BASE_OFFSET, 563 564 .bar2_limit = XEON_SBAR2LMT_OFFSET, 565 .bar4_limit = XEON_SBAR4LMT_OFFSET, 566 .bar5_limit = XEON_SBAR5LMT_OFFSET, 567 568 .bar2_xlat = XEON_SBAR2XLAT_OFFSET, 569 .bar4_xlat = XEON_SBAR4XLAT_OFFSET, 570 .bar5_xlat = XEON_SBAR5XLAT_OFFSET, 571}; 572 573static struct ntb_b2b_addr xeon_b2b_usd_addr = { 574 .bar0_addr = XEON_B2B_BAR0_ADDR, 575 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 576 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 577 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 578 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 579}; 580 581static struct ntb_b2b_addr xeon_b2b_dsd_addr = { 582 .bar0_addr = XEON_B2B_BAR0_ADDR, 583 .bar2_addr64 = XEON_B2B_BAR2_ADDR64, 584 .bar4_addr64 = XEON_B2B_BAR4_ADDR64, 585 .bar4_addr32 = XEON_B2B_BAR4_ADDR32, 586 .bar5_addr32 = XEON_B2B_BAR5_ADDR32, 587}; 588 589SYSCTL_NODE(_hw_ntb, OID_AUTO, xeon_b2b, CTLFLAG_RW, 0, 590 "B2B MW segment overrides -- MUST be the same on both sides"); 591 592TUNABLE_QUAD("hw.ntb.usd_bar2_addr64", &xeon_b2b_usd_addr.bar2_addr64); 593SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar2_addr64, CTLFLAG_RDTUN, 594 &xeon_b2b_usd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 595 "hardware, use this 64-bit address on the bus between the NTB devices for " 596 "the window at BAR2, on the upstream side of the link. MUST be the same " 597 "address on both sides."); 598TUNABLE_QUAD("hw.ntb.usd_bar4_addr64", &xeon_b2b_usd_addr.bar4_addr64); 599SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr64, CTLFLAG_RDTUN, 600 &xeon_b2b_usd_addr.bar4_addr64, 0, "See usd_bar2_addr64, but BAR4."); 601TUNABLE_QUAD("hw.ntb.usd_bar4_addr32", &xeon_b2b_usd_addr.bar4_addr32); 602SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar4_addr32, CTLFLAG_RDTUN, 603 &xeon_b2b_usd_addr.bar4_addr32, 0, "See usd_bar2_addr64, but BAR4 " 604 "(split-BAR mode)."); 605TUNABLE_QUAD("hw.ntb.usd_bar5_addr32", &xeon_b2b_usd_addr.bar5_addr32); 606SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, usd_bar5_addr32, CTLFLAG_RDTUN, 607 &xeon_b2b_usd_addr.bar5_addr32, 0, "See usd_bar2_addr64, but BAR5 " 608 "(split-BAR mode)."); 609 610TUNABLE_QUAD("hw.ntb.dsd_bar2_addr64", &xeon_b2b_dsd_addr.bar2_addr64); 611SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar2_addr64, CTLFLAG_RDTUN, 612 &xeon_b2b_dsd_addr.bar2_addr64, 0, "If using B2B topology on Xeon " 613 "hardware, use this 64-bit address on the bus between the NTB devices for " 614 "the window at BAR2, on the downstream side of the link. MUST be the same" 615 " address on both sides."); 616TUNABLE_QUAD("hw.ntb.dsd_bar4_addr64", &xeon_b2b_dsd_addr.bar4_addr64); 617SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr64, CTLFLAG_RDTUN, 618 &xeon_b2b_dsd_addr.bar4_addr64, 0, "See dsd_bar2_addr64, but BAR4."); 619TUNABLE_QUAD("hw.ntb.dsd_bar4_addr32", &xeon_b2b_dsd_addr.bar4_addr32); 620SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar4_addr32, CTLFLAG_RDTUN, 621 &xeon_b2b_dsd_addr.bar4_addr32, 0, "See dsd_bar2_addr64, but BAR4 " 622 "(split-BAR mode)."); 623TUNABLE_QUAD("hw.ntb.dsd_bar5_addr32", &xeon_b2b_dsd_addr.bar5_addr32); 624SYSCTL_UQUAD(_hw_ntb_xeon_b2b, OID_AUTO, dsd_bar5_addr32, CTLFLAG_RDTUN, 625 &xeon_b2b_dsd_addr.bar5_addr32, 0, "See dsd_bar2_addr64, but BAR5 " 626 "(split-BAR mode)."); 627 628/* 629 * OS <-> Driver interface structures 630 */ 631MALLOC_DEFINE(M_NTB, "ntb_hw", "ntb_hw driver memory allocations"); 632 633SYSCTL_NODE(_hw, OID_AUTO, ntb, CTLFLAG_RW, 0, "NTB sysctls"); 634 635/* 636 * OS <-> Driver linkage functions 637 */ 638static int 639ntb_probe(device_t device) 640{ 641 struct ntb_hw_info *p; 642 643 p = ntb_get_device_info(pci_get_devid(device)); 644 if (p == NULL) 645 return (ENXIO); 646 647 device_set_desc(device, p->desc); 648 return (0); 649} 650 651static int 652ntb_attach(device_t device) 653{ 654 struct ntb_softc *ntb; 655 struct ntb_hw_info *p; 656 int error; 657 658 ntb = device_get_softc(device); 659 p = ntb_get_device_info(pci_get_devid(device)); 660 661 ntb->device = device; 662 ntb->type = p->type; 663 ntb->features = p->features; 664 ntb->b2b_mw_idx = B2B_MW_DISABLED; 665 ntb->msix_mw_idx = B2B_MW_DISABLED; 666 667 /* Heartbeat timer for NTB_ATOM since there is no link interrupt */ 668 callout_init(&ntb->heartbeat_timer, CALLOUT_MPSAFE); 669 callout_init(&ntb->lr_timer, CALLOUT_MPSAFE); 670 callout_init(&ntb->peer_msix_work, 1); 671 mtx_init(&ntb->db_mask_lock, "ntb hw bits", NULL, MTX_SPIN); 672 rm_init(&ntb->ctx_lock, "ntb ctx"); 673 674 if (ntb->type == NTB_ATOM) 675 error = ntb_detect_atom(ntb); 676 else 677 error = ntb_detect_xeon(ntb); 678 if (error != 0) 679 goto out; 680 681 ntb_detect_max_mw(ntb); 682 683 pci_enable_busmaster(ntb->device); 684 685 error = ntb_map_pci_bars(ntb); 686 if (error != 0) 687 goto out; 688 if (ntb->type == NTB_ATOM) 689 error = ntb_atom_init_dev(ntb); 690 else 691 error = ntb_xeon_init_dev(ntb); 692 if (error != 0) 693 goto out; 694 695 ntb_spad_clear(device); 696 697 ntb_poll_link(ntb); 698 699 ntb_sysctl_init(ntb); 700 701 /* Attach children to this controller */ 702 device_add_child(device, NULL, -1); 703 bus_generic_attach(device); 704 705out: 706 if (error != 0) 707 ntb_detach(device); 708 return (error); 709} 710 711static int 712ntb_detach(device_t device) 713{ 714 struct ntb_softc *ntb; 715 716 ntb = device_get_softc(device); 717 718 /* Detach & delete all children */ 719 device_delete_children(device); 720 721 if (ntb->self_reg != NULL) { 722 DB_MASK_LOCK(ntb); 723 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_valid_mask); 724 DB_MASK_UNLOCK(ntb); 725 } 726 callout_drain(&ntb->heartbeat_timer); 727 callout_drain(&ntb->lr_timer); 728 callout_drain(&ntb->peer_msix_work); 729 pci_disable_busmaster(ntb->device); 730 if (ntb->type == NTB_XEON) 731 ntb_teardown_xeon(ntb); 732 ntb_teardown_interrupts(ntb); 733 734 mtx_destroy(&ntb->db_mask_lock); 735 rm_destroy(&ntb->ctx_lock); 736 737 ntb_unmap_pci_bar(ntb); 738 739 return (0); 740} 741 742/* 743 * Driver internal routines 744 */ 745static inline enum ntb_bar 746ntb_mw_to_bar(struct ntb_softc *ntb, unsigned mw) 747{ 748 749 KASSERT(mw < ntb->mw_count, 750 ("%s: mw:%u > count:%u", __func__, mw, (unsigned)ntb->mw_count)); 751 KASSERT(ntb->reg->mw_bar[mw] != 0, ("invalid mw")); 752 753 return (ntb->reg->mw_bar[mw]); 754} 755 756static inline bool 757bar_is_64bit(struct ntb_softc *ntb, enum ntb_bar bar) 758{ 759 /* XXX This assertion could be stronger. */ 760 KASSERT(bar < NTB_MAX_BARS, ("bogus bar")); 761 return (bar < NTB_B2B_BAR_2 || !HAS_FEATURE(ntb, NTB_SPLIT_BAR)); 762} 763 764static inline void 765bar_get_xlat_params(struct ntb_softc *ntb, enum ntb_bar bar, uint32_t *base, 766 uint32_t *xlat, uint32_t *lmt) 767{ 768 uint32_t basev, lmtv, xlatv; 769 770 switch (bar) { 771 case NTB_B2B_BAR_1: 772 basev = ntb->xlat_reg->bar2_base; 773 lmtv = ntb->xlat_reg->bar2_limit; 774 xlatv = ntb->xlat_reg->bar2_xlat; 775 break; 776 case NTB_B2B_BAR_2: 777 basev = ntb->xlat_reg->bar4_base; 778 lmtv = ntb->xlat_reg->bar4_limit; 779 xlatv = ntb->xlat_reg->bar4_xlat; 780 break; 781 case NTB_B2B_BAR_3: 782 basev = ntb->xlat_reg->bar5_base; 783 lmtv = ntb->xlat_reg->bar5_limit; 784 xlatv = ntb->xlat_reg->bar5_xlat; 785 break; 786 default: 787 KASSERT(bar >= NTB_B2B_BAR_1 && bar < NTB_MAX_BARS, 788 ("bad bar")); 789 basev = lmtv = xlatv = 0; 790 break; 791 } 792 793 if (base != NULL) 794 *base = basev; 795 if (xlat != NULL) 796 *xlat = xlatv; 797 if (lmt != NULL) 798 *lmt = lmtv; 799} 800 801static int 802ntb_map_pci_bars(struct ntb_softc *ntb) 803{ 804 int rc; 805 806 ntb->bar_info[NTB_CONFIG_BAR].pci_resource_id = PCIR_BAR(0); 807 rc = map_mmr_bar(ntb, &ntb->bar_info[NTB_CONFIG_BAR]); 808 if (rc != 0) 809 goto out; 810 811 ntb->bar_info[NTB_B2B_BAR_1].pci_resource_id = PCIR_BAR(2); 812 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_1]); 813 if (rc != 0) 814 goto out; 815 ntb->bar_info[NTB_B2B_BAR_1].psz_off = XEON_PBAR23SZ_OFFSET; 816 ntb->bar_info[NTB_B2B_BAR_1].ssz_off = XEON_SBAR23SZ_OFFSET; 817 ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off = XEON_PBAR2XLAT_OFFSET; 818 819 ntb->bar_info[NTB_B2B_BAR_2].pci_resource_id = PCIR_BAR(4); 820 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_2]); 821 if (rc != 0) 822 goto out; 823 ntb->bar_info[NTB_B2B_BAR_2].psz_off = XEON_PBAR4SZ_OFFSET; 824 ntb->bar_info[NTB_B2B_BAR_2].ssz_off = XEON_SBAR4SZ_OFFSET; 825 ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off = XEON_PBAR4XLAT_OFFSET; 826 827 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 828 goto out; 829 830 ntb->bar_info[NTB_B2B_BAR_3].pci_resource_id = PCIR_BAR(5); 831 rc = map_memory_window_bar(ntb, &ntb->bar_info[NTB_B2B_BAR_3]); 832 ntb->bar_info[NTB_B2B_BAR_3].psz_off = XEON_PBAR5SZ_OFFSET; 833 ntb->bar_info[NTB_B2B_BAR_3].ssz_off = XEON_SBAR5SZ_OFFSET; 834 ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off = XEON_PBAR5XLAT_OFFSET; 835 836out: 837 if (rc != 0) 838 device_printf(ntb->device, 839 "unable to allocate pci resource\n"); 840 return (rc); 841} 842 843static void 844print_map_success(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar, 845 const char *kind) 846{ 847 848 device_printf(ntb->device, 849 "Mapped BAR%d v:[%p-%p] p:[%p-%p] (0x%jx bytes) (%s)\n", 850 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 851 (char *)bar->vbase + bar->size - 1, 852 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 853 (uintmax_t)bar->size, kind); 854} 855 856static int 857map_mmr_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 858{ 859 860 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 861 &bar->pci_resource_id, RF_ACTIVE); 862 if (bar->pci_resource == NULL) 863 return (ENXIO); 864 865 save_bar_parameters(bar); 866 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 867 print_map_success(ntb, bar, "mmr"); 868 return (0); 869} 870 871static int 872map_memory_window_bar(struct ntb_softc *ntb, struct ntb_pci_bar_info *bar) 873{ 874 int rc; 875 vm_memattr_t mapmode; 876 uint8_t bar_size_bits = 0; 877 878 bar->pci_resource = bus_alloc_resource_any(ntb->device, SYS_RES_MEMORY, 879 &bar->pci_resource_id, RF_ACTIVE); 880 881 if (bar->pci_resource == NULL) 882 return (ENXIO); 883 884 save_bar_parameters(bar); 885 /* 886 * Ivytown NTB BAR sizes are misreported by the hardware due to a 887 * hardware issue. To work around this, query the size it should be 888 * configured to by the device and modify the resource to correspond to 889 * this new size. The BIOS on systems with this problem is required to 890 * provide enough address space to allow the driver to make this change 891 * safely. 892 * 893 * Ideally I could have just specified the size when I allocated the 894 * resource like: 895 * bus_alloc_resource(ntb->device, 896 * SYS_RES_MEMORY, &bar->pci_resource_id, 0ul, ~0ul, 897 * 1ul << bar_size_bits, RF_ACTIVE); 898 * but the PCI driver does not honor the size in this call, so we have 899 * to modify it after the fact. 900 */ 901 if (HAS_FEATURE(ntb, NTB_BAR_SIZE_4K)) { 902 if (bar->pci_resource_id == PCIR_BAR(2)) 903 bar_size_bits = pci_read_config(ntb->device, 904 XEON_PBAR23SZ_OFFSET, 1); 905 else 906 bar_size_bits = pci_read_config(ntb->device, 907 XEON_PBAR45SZ_OFFSET, 1); 908 909 rc = bus_adjust_resource(ntb->device, SYS_RES_MEMORY, 910 bar->pci_resource, bar->pbase, 911 bar->pbase + (1ul << bar_size_bits) - 1); 912 if (rc != 0) { 913 device_printf(ntb->device, 914 "unable to resize bar\n"); 915 return (rc); 916 } 917 918 save_bar_parameters(bar); 919 } 920 921 bar->map_mode = VM_MEMATTR_UNCACHEABLE; 922 print_map_success(ntb, bar, "mw"); 923 924 /* 925 * Optionally, mark MW BARs as anything other than UC to improve 926 * performance. 927 */ 928 mapmode = ntb_pat_flags(); 929 if (mapmode == bar->map_mode) 930 return (0); 931 932 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mapmode); 933 if (rc == 0) { 934 bar->map_mode = mapmode; 935 device_printf(ntb->device, 936 "Marked BAR%d v:[%p-%p] p:[%p-%p] as " 937 "%s.\n", 938 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 939 (char *)bar->vbase + bar->size - 1, 940 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 941 ntb_vm_memattr_to_str(mapmode)); 942 } else 943 device_printf(ntb->device, 944 "Unable to mark BAR%d v:[%p-%p] p:[%p-%p] as " 945 "%s: %d\n", 946 PCI_RID2BAR(bar->pci_resource_id), bar->vbase, 947 (char *)bar->vbase + bar->size - 1, 948 (void *)bar->pbase, (void *)(bar->pbase + bar->size - 1), 949 ntb_vm_memattr_to_str(mapmode), rc); 950 /* Proceed anyway */ 951 return (0); 952} 953 954static void 955ntb_unmap_pci_bar(struct ntb_softc *ntb) 956{ 957 struct ntb_pci_bar_info *current_bar; 958 int i; 959 960 for (i = 0; i < NTB_MAX_BARS; i++) { 961 current_bar = &ntb->bar_info[i]; 962 if (current_bar->pci_resource != NULL) 963 bus_release_resource(ntb->device, SYS_RES_MEMORY, 964 current_bar->pci_resource_id, 965 current_bar->pci_resource); 966 } 967} 968 969static int 970ntb_setup_msix(struct ntb_softc *ntb, uint32_t num_vectors) 971{ 972 uint32_t i; 973 int rc; 974 975 for (i = 0; i < num_vectors; i++) { 976 ntb->int_info[i].rid = i + 1; 977 ntb->int_info[i].res = bus_alloc_resource_any(ntb->device, 978 SYS_RES_IRQ, &ntb->int_info[i].rid, RF_ACTIVE); 979 if (ntb->int_info[i].res == NULL) { 980 device_printf(ntb->device, 981 "bus_alloc_resource failed\n"); 982 return (ENOMEM); 983 } 984 ntb->int_info[i].tag = NULL; 985 ntb->allocated_interrupts++; 986 rc = bus_setup_intr(ntb->device, ntb->int_info[i].res, 987 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_vec_isr, 988 &ntb->msix_vec[i], &ntb->int_info[i].tag); 989 if (rc != 0) { 990 device_printf(ntb->device, "bus_setup_intr failed\n"); 991 return (ENXIO); 992 } 993 } 994 return (0); 995} 996 997/* 998 * The Linux NTB driver drops from MSI-X to legacy INTx if a unique vector 999 * cannot be allocated for each MSI-X message. JHB seems to think remapping 1000 * should be okay. This tunable should enable us to test that hypothesis 1001 * when someone gets their hands on some Xeon hardware. 1002 */ 1003static int ntb_force_remap_mode; 1004TUNABLE_INT("hw.ntb.force_remap_mode", &ntb_force_remap_mode); 1005SYSCTL_INT(_hw_ntb, OID_AUTO, force_remap_mode, CTLFLAG_RDTUN, 1006 &ntb_force_remap_mode, 0, "If enabled, force MSI-X messages to be remapped" 1007 " to a smaller number of ithreads, even if the desired number are " 1008 "available"); 1009 1010/* 1011 * In case it is NOT ok, give consumers an abort button. 1012 */ 1013static int ntb_prefer_intx; 1014TUNABLE_INT("hw.ntb.prefer_intx_to_remap", &ntb_prefer_intx); 1015SYSCTL_INT(_hw_ntb, OID_AUTO, prefer_intx_to_remap, CTLFLAG_RDTUN, 1016 &ntb_prefer_intx, 0, "If enabled, prefer to use legacy INTx mode rather " 1017 "than remapping MSI-X messages over available slots (match Linux driver " 1018 "behavior)"); 1019 1020/* 1021 * Remap the desired number of MSI-X messages to available ithreads in a simple 1022 * round-robin fashion. 1023 */ 1024static int 1025ntb_remap_msix(device_t dev, uint32_t desired, uint32_t avail) 1026{ 1027 u_int *vectors; 1028 uint32_t i; 1029 int rc; 1030 1031 if (ntb_prefer_intx != 0) 1032 return (ENXIO); 1033 1034 vectors = malloc(desired * sizeof(*vectors), M_NTB, M_ZERO | M_WAITOK); 1035 1036 for (i = 0; i < desired; i++) 1037 vectors[i] = (i % avail) + 1; 1038 1039 rc = pci_remap_msix(dev, desired, vectors); 1040 free(vectors, M_NTB); 1041 return (rc); 1042} 1043 1044static int 1045ntb_init_isr(struct ntb_softc *ntb) 1046{ 1047 uint32_t desired_vectors, num_vectors; 1048 int rc; 1049 1050 ntb->allocated_interrupts = 0; 1051 ntb->last_ts = ticks; 1052 1053 /* 1054 * Mask all doorbell interrupts. (Except link events!) 1055 */ 1056 DB_MASK_LOCK(ntb); 1057 ntb->db_mask = ntb->db_valid_mask; 1058 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1059 DB_MASK_UNLOCK(ntb); 1060 1061 num_vectors = desired_vectors = MIN(pci_msix_count(ntb->device), 1062 ntb->db_count); 1063 if (desired_vectors >= 1) { 1064 rc = pci_alloc_msix(ntb->device, &num_vectors); 1065 1066 if (ntb_force_remap_mode != 0 && rc == 0 && 1067 num_vectors == desired_vectors) 1068 num_vectors--; 1069 1070 if (rc == 0 && num_vectors < desired_vectors) { 1071 rc = ntb_remap_msix(ntb->device, desired_vectors, 1072 num_vectors); 1073 if (rc == 0) 1074 num_vectors = desired_vectors; 1075 else 1076 pci_release_msi(ntb->device); 1077 } 1078 if (rc != 0) 1079 num_vectors = 1; 1080 } else 1081 num_vectors = 1; 1082 1083 if (ntb->type == NTB_XEON && num_vectors < ntb->db_vec_count) { 1084 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1085 device_printf(ntb->device, 1086 "Errata workaround does not support MSI or INTX\n"); 1087 return (EINVAL); 1088 } 1089 1090 ntb->db_vec_count = 1; 1091 ntb->db_vec_shift = XEON_DB_TOTAL_SHIFT; 1092 rc = ntb_setup_legacy_interrupt(ntb); 1093 } else { 1094 if (num_vectors - 1 != XEON_NONLINK_DB_MSIX_BITS && 1095 HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1096 device_printf(ntb->device, 1097 "Errata workaround expects %d doorbell bits\n", 1098 XEON_NONLINK_DB_MSIX_BITS); 1099 return (EINVAL); 1100 } 1101 1102 ntb_create_msix_vec(ntb, num_vectors); 1103 rc = ntb_setup_msix(ntb, num_vectors); 1104 if (rc == 0 && HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1105 ntb_get_msix_info(ntb); 1106 } 1107 if (rc != 0) { 1108 device_printf(ntb->device, 1109 "Error allocating interrupts: %d\n", rc); 1110 ntb_free_msix_vec(ntb); 1111 } 1112 1113 return (rc); 1114} 1115 1116static int 1117ntb_setup_legacy_interrupt(struct ntb_softc *ntb) 1118{ 1119 int rc; 1120 1121 ntb->int_info[0].rid = 0; 1122 ntb->int_info[0].res = bus_alloc_resource_any(ntb->device, SYS_RES_IRQ, 1123 &ntb->int_info[0].rid, RF_SHAREABLE|RF_ACTIVE); 1124 if (ntb->int_info[0].res == NULL) { 1125 device_printf(ntb->device, "bus_alloc_resource failed\n"); 1126 return (ENOMEM); 1127 } 1128 1129 ntb->int_info[0].tag = NULL; 1130 ntb->allocated_interrupts = 1; 1131 1132 rc = bus_setup_intr(ntb->device, ntb->int_info[0].res, 1133 INTR_MPSAFE | INTR_TYPE_MISC, NULL, ndev_irq_isr, 1134 ntb, &ntb->int_info[0].tag); 1135 if (rc != 0) { 1136 device_printf(ntb->device, "bus_setup_intr failed\n"); 1137 return (ENXIO); 1138 } 1139 1140 return (0); 1141} 1142 1143static void 1144ntb_teardown_interrupts(struct ntb_softc *ntb) 1145{ 1146 struct ntb_int_info *current_int; 1147 int i; 1148 1149 for (i = 0; i < ntb->allocated_interrupts; i++) { 1150 current_int = &ntb->int_info[i]; 1151 if (current_int->tag != NULL) 1152 bus_teardown_intr(ntb->device, current_int->res, 1153 current_int->tag); 1154 1155 if (current_int->res != NULL) 1156 bus_release_resource(ntb->device, SYS_RES_IRQ, 1157 rman_get_rid(current_int->res), current_int->res); 1158 } 1159 1160 ntb_free_msix_vec(ntb); 1161 pci_release_msi(ntb->device); 1162} 1163 1164/* 1165 * Doorbell register and mask are 64-bit on Atom, 16-bit on Xeon. Abstract it 1166 * out to make code clearer. 1167 */ 1168static inline uint64_t 1169db_ioread(struct ntb_softc *ntb, uint64_t regoff) 1170{ 1171 1172 if (ntb->type == NTB_ATOM) 1173 return (ntb_reg_read(8, regoff)); 1174 1175 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1176 1177 return (ntb_reg_read(2, regoff)); 1178} 1179 1180static inline void 1181db_iowrite(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1182{ 1183 1184 KASSERT((val & ~ntb->db_valid_mask) == 0, 1185 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1186 (uintmax_t)(val & ~ntb->db_valid_mask), 1187 (uintmax_t)ntb->db_valid_mask)); 1188 1189 if (regoff == ntb->self_reg->db_mask) 1190 DB_MASK_ASSERT(ntb, MA_OWNED); 1191 db_iowrite_raw(ntb, regoff, val); 1192} 1193 1194static inline void 1195db_iowrite_raw(struct ntb_softc *ntb, uint64_t regoff, uint64_t val) 1196{ 1197 1198 if (ntb->type == NTB_ATOM) { 1199 ntb_reg_write(8, regoff, val); 1200 return; 1201 } 1202 1203 KASSERT(ntb->type == NTB_XEON, ("bad ntb type")); 1204 ntb_reg_write(2, regoff, (uint16_t)val); 1205} 1206 1207static void 1208ntb_db_set_mask(device_t dev, uint64_t bits) 1209{ 1210 struct ntb_softc *ntb = device_get_softc(dev); 1211 1212 DB_MASK_LOCK(ntb); 1213 ntb->db_mask |= bits; 1214 if (!HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1215 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1216 DB_MASK_UNLOCK(ntb); 1217} 1218 1219static void 1220ntb_db_clear_mask(device_t dev, uint64_t bits) 1221{ 1222 struct ntb_softc *ntb = device_get_softc(dev); 1223 uint64_t ibits; 1224 int i; 1225 1226 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1227 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1228 (uintmax_t)(bits & ~ntb->db_valid_mask), 1229 (uintmax_t)ntb->db_valid_mask)); 1230 1231 DB_MASK_LOCK(ntb); 1232 ibits = ntb->fake_db_bell & ntb->db_mask & bits; 1233 ntb->db_mask &= ~bits; 1234 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1235 /* Simulate fake interrupts if unmasked DB bits are set. */ 1236 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1237 if ((ibits & ntb_db_vector_mask(dev, i)) != 0) 1238 swi_sched(ntb->int_info[i].tag, 0); 1239 } 1240 } else { 1241 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1242 } 1243 DB_MASK_UNLOCK(ntb); 1244} 1245 1246static uint64_t 1247ntb_db_read(device_t dev) 1248{ 1249 struct ntb_softc *ntb = device_get_softc(dev); 1250 1251 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1252 return (ntb->fake_db_bell); 1253 1254 return (db_ioread(ntb, ntb->self_reg->db_bell)); 1255} 1256 1257static void 1258ntb_db_clear(device_t dev, uint64_t bits) 1259{ 1260 struct ntb_softc *ntb = device_get_softc(dev); 1261 1262 KASSERT((bits & ~ntb->db_valid_mask) == 0, 1263 ("%s: Invalid bits 0x%jx (valid: 0x%jx)", __func__, 1264 (uintmax_t)(bits & ~ntb->db_valid_mask), 1265 (uintmax_t)ntb->db_valid_mask)); 1266 1267 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1268 DB_MASK_LOCK(ntb); 1269 ntb->fake_db_bell &= ~bits; 1270 DB_MASK_UNLOCK(ntb); 1271 return; 1272 } 1273 1274 db_iowrite(ntb, ntb->self_reg->db_bell, bits); 1275} 1276 1277static inline uint64_t 1278ntb_vec_mask(struct ntb_softc *ntb, uint64_t db_vector) 1279{ 1280 uint64_t shift, mask; 1281 1282 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1283 /* 1284 * Remap vectors in custom way to make at least first 1285 * three doorbells to not generate stray events. 1286 * This breaks Linux compatibility (if one existed) 1287 * when more then one DB is used (not by if_ntb). 1288 */ 1289 if (db_vector < XEON_NONLINK_DB_MSIX_BITS - 1) 1290 return (1 << db_vector); 1291 if (db_vector == XEON_NONLINK_DB_MSIX_BITS - 1) 1292 return (0x7ffc); 1293 } 1294 1295 shift = ntb->db_vec_shift; 1296 mask = (1ull << shift) - 1; 1297 return (mask << (shift * db_vector)); 1298} 1299 1300static void 1301ntb_interrupt(struct ntb_softc *ntb, uint32_t vec) 1302{ 1303 uint64_t vec_mask; 1304 1305 ntb->last_ts = ticks; 1306 vec_mask = ntb_vec_mask(ntb, vec); 1307 1308 if ((vec_mask & ntb->db_link_mask) != 0) { 1309 if (ntb_poll_link(ntb)) 1310 ntb_link_event(ntb->device); 1311 } 1312 1313 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1314 (vec_mask & ntb->db_link_mask) == 0) { 1315 DB_MASK_LOCK(ntb); 1316 1317 /* Do not report same DB events again if not cleared yet. */ 1318 vec_mask &= ~ntb->fake_db_bell; 1319 1320 /* Update our internal doorbell register. */ 1321 ntb->fake_db_bell |= vec_mask; 1322 1323 /* Do not report masked DB events. */ 1324 vec_mask &= ~ntb->db_mask; 1325 1326 DB_MASK_UNLOCK(ntb); 1327 } 1328 1329 if ((vec_mask & ntb->db_valid_mask) != 0) 1330 ntb_db_event(ntb->device, vec); 1331} 1332 1333static void 1334ndev_vec_isr(void *arg) 1335{ 1336 struct ntb_vec *nvec = arg; 1337 1338 ntb_interrupt(nvec->ntb, nvec->num); 1339} 1340 1341static void 1342ndev_irq_isr(void *arg) 1343{ 1344 /* If we couldn't set up MSI-X, we only have the one vector. */ 1345 ntb_interrupt(arg, 0); 1346} 1347 1348static int 1349ntb_create_msix_vec(struct ntb_softc *ntb, uint32_t num_vectors) 1350{ 1351 uint32_t i; 1352 1353 ntb->msix_vec = malloc(num_vectors * sizeof(*ntb->msix_vec), M_NTB, 1354 M_ZERO | M_WAITOK); 1355 for (i = 0; i < num_vectors; i++) { 1356 ntb->msix_vec[i].num = i; 1357 ntb->msix_vec[i].ntb = ntb; 1358 } 1359 1360 return (0); 1361} 1362 1363static void 1364ntb_free_msix_vec(struct ntb_softc *ntb) 1365{ 1366 1367 if (ntb->msix_vec == NULL) 1368 return; 1369 1370 free(ntb->msix_vec, M_NTB); 1371 ntb->msix_vec = NULL; 1372} 1373 1374static void 1375ntb_get_msix_info(struct ntb_softc *ntb) 1376{ 1377 struct pci_devinfo *dinfo; 1378 struct pcicfg_msix *msix; 1379 uint32_t laddr, data, i, offset; 1380 1381 dinfo = device_get_ivars(ntb->device); 1382 msix = &dinfo->cfg.msix; 1383 1384 CTASSERT(XEON_NONLINK_DB_MSIX_BITS == nitems(ntb->msix_data)); 1385 1386 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 1387 offset = msix->msix_table_offset + i * PCI_MSIX_ENTRY_SIZE; 1388 1389 laddr = bus_read_4(msix->msix_table_res, offset + 1390 PCI_MSIX_ENTRY_LOWER_ADDR); 1391 ntb_printf(2, "local MSIX addr(%u): 0x%x\n", i, laddr); 1392 1393 KASSERT((laddr & MSI_INTEL_ADDR_BASE) == MSI_INTEL_ADDR_BASE, 1394 ("local MSIX addr 0x%x not in MSI base 0x%x", laddr, 1395 MSI_INTEL_ADDR_BASE)); 1396 ntb->msix_data[i].nmd_ofs = laddr; 1397 1398 data = bus_read_4(msix->msix_table_res, offset + 1399 PCI_MSIX_ENTRY_DATA); 1400 ntb_printf(2, "local MSIX data(%u): 0x%x\n", i, data); 1401 1402 ntb->msix_data[i].nmd_data = data; 1403 } 1404} 1405 1406static struct ntb_hw_info * 1407ntb_get_device_info(uint32_t device_id) 1408{ 1409 struct ntb_hw_info *ep = pci_ids; 1410 1411 while (ep->device_id) { 1412 if (ep->device_id == device_id) 1413 return (ep); 1414 ++ep; 1415 } 1416 return (NULL); 1417} 1418 1419static void 1420ntb_teardown_xeon(struct ntb_softc *ntb) 1421{ 1422 1423 if (ntb->reg != NULL) 1424 ntb_link_disable(ntb->device); 1425} 1426 1427static void 1428ntb_detect_max_mw(struct ntb_softc *ntb) 1429{ 1430 1431 if (ntb->type == NTB_ATOM) { 1432 ntb->mw_count = ATOM_MW_COUNT; 1433 return; 1434 } 1435 1436 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1437 ntb->mw_count = XEON_HSX_SPLIT_MW_COUNT; 1438 else 1439 ntb->mw_count = XEON_SNB_MW_COUNT; 1440} 1441 1442static int 1443ntb_detect_xeon(struct ntb_softc *ntb) 1444{ 1445 uint8_t ppd, conn_type; 1446 1447 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 1); 1448 ntb->ppd = ppd; 1449 1450 if ((ppd & XEON_PPD_DEV_TYPE) != 0) 1451 ntb->dev_type = NTB_DEV_DSD; 1452 else 1453 ntb->dev_type = NTB_DEV_USD; 1454 1455 if ((ppd & XEON_PPD_SPLIT_BAR) != 0) 1456 ntb->features |= NTB_SPLIT_BAR; 1457 1458 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP) && 1459 !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1460 device_printf(ntb->device, 1461 "Can not apply SB01BASE_LOCKUP workaround " 1462 "with split BARs disabled!\n"); 1463 device_printf(ntb->device, 1464 "Expect system hangs under heavy NTB traffic!\n"); 1465 ntb->features &= ~NTB_SB01BASE_LOCKUP; 1466 } 1467 1468 /* 1469 * SDOORBELL errata workaround gets in the way of SB01BASE_LOCKUP 1470 * errata workaround; only do one at a time. 1471 */ 1472 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) 1473 ntb->features &= ~NTB_SDOORBELL_LOCKUP; 1474 1475 conn_type = ppd & XEON_PPD_CONN_TYPE; 1476 switch (conn_type) { 1477 case NTB_CONN_B2B: 1478 ntb->conn_type = conn_type; 1479 break; 1480 case NTB_CONN_RP: 1481 case NTB_CONN_TRANSPARENT: 1482 default: 1483 device_printf(ntb->device, "Unsupported connection type: %u\n", 1484 (unsigned)conn_type); 1485 return (ENXIO); 1486 } 1487 return (0); 1488} 1489 1490static int 1491ntb_detect_atom(struct ntb_softc *ntb) 1492{ 1493 uint32_t ppd, conn_type; 1494 1495 ppd = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 1496 ntb->ppd = ppd; 1497 1498 if ((ppd & ATOM_PPD_DEV_TYPE) != 0) 1499 ntb->dev_type = NTB_DEV_DSD; 1500 else 1501 ntb->dev_type = NTB_DEV_USD; 1502 1503 conn_type = (ppd & ATOM_PPD_CONN_TYPE) >> 8; 1504 switch (conn_type) { 1505 case NTB_CONN_B2B: 1506 ntb->conn_type = conn_type; 1507 break; 1508 default: 1509 device_printf(ntb->device, "Unsupported NTB configuration\n"); 1510 return (ENXIO); 1511 } 1512 return (0); 1513} 1514 1515static int 1516ntb_xeon_init_dev(struct ntb_softc *ntb) 1517{ 1518 int rc; 1519 1520 ntb->spad_count = XEON_SPAD_COUNT; 1521 ntb->db_count = XEON_DB_COUNT; 1522 ntb->db_link_mask = XEON_DB_LINK_BIT; 1523 ntb->db_vec_count = XEON_DB_MSIX_VECTOR_COUNT; 1524 ntb->db_vec_shift = XEON_DB_MSIX_VECTOR_SHIFT; 1525 1526 if (ntb->conn_type != NTB_CONN_B2B) { 1527 device_printf(ntb->device, "Connection type %d not supported\n", 1528 ntb->conn_type); 1529 return (ENXIO); 1530 } 1531 1532 ntb->reg = &xeon_reg; 1533 ntb->self_reg = &xeon_pri_reg; 1534 ntb->peer_reg = &xeon_b2b_reg; 1535 ntb->xlat_reg = &xeon_sec_xlat; 1536 1537 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1538 ntb->fake_db_bell = 0; 1539 ntb->msix_mw_idx = (ntb->mw_count + g_ntb_msix_idx) % 1540 ntb->mw_count; 1541 ntb_printf(2, "Setting up MSIX mw idx %d means %u\n", 1542 g_ntb_msix_idx, ntb->msix_mw_idx); 1543 rc = ntb_mw_set_wc_internal(ntb, ntb->msix_mw_idx, 1544 VM_MEMATTR_UNCACHEABLE); 1545 KASSERT(rc == 0, ("shouldn't fail")); 1546 } else if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 1547 /* 1548 * There is a Xeon hardware errata related to writes to SDOORBELL or 1549 * B2BDOORBELL in conjunction with inbound access to NTB MMIO space, 1550 * which may hang the system. To workaround this, use a memory 1551 * window to access the interrupt and scratch pad registers on the 1552 * remote system. 1553 */ 1554 ntb->b2b_mw_idx = (ntb->mw_count + g_ntb_mw_idx) % 1555 ntb->mw_count; 1556 ntb_printf(2, "Setting up b2b mw idx %d means %u\n", 1557 g_ntb_mw_idx, ntb->b2b_mw_idx); 1558 rc = ntb_mw_set_wc_internal(ntb, ntb->b2b_mw_idx, 1559 VM_MEMATTR_UNCACHEABLE); 1560 KASSERT(rc == 0, ("shouldn't fail")); 1561 } else if (HAS_FEATURE(ntb, NTB_B2BDOORBELL_BIT14)) 1562 /* 1563 * HW Errata on bit 14 of b2bdoorbell register. Writes will not be 1564 * mirrored to the remote system. Shrink the number of bits by one, 1565 * since bit 14 is the last bit. 1566 * 1567 * On REGS_THRU_MW errata mode, we don't use the b2bdoorbell register 1568 * anyway. Nor for non-B2B connection types. 1569 */ 1570 ntb->db_count = XEON_DB_COUNT - 1; 1571 1572 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1573 1574 if (ntb->dev_type == NTB_DEV_USD) 1575 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_dsd_addr, 1576 &xeon_b2b_usd_addr); 1577 else 1578 rc = xeon_setup_b2b_mw(ntb, &xeon_b2b_usd_addr, 1579 &xeon_b2b_dsd_addr); 1580 if (rc != 0) 1581 return (rc); 1582 1583 /* Enable Bus Master and Memory Space on the secondary side */ 1584 ntb_reg_write(2, XEON_SPCICMD_OFFSET, 1585 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1586 1587 /* 1588 * Mask all doorbell interrupts. 1589 */ 1590 DB_MASK_LOCK(ntb); 1591 ntb->db_mask = ntb->db_valid_mask; 1592 db_iowrite(ntb, ntb->self_reg->db_mask, ntb->db_mask); 1593 DB_MASK_UNLOCK(ntb); 1594 1595 rc = ntb_init_isr(ntb); 1596 return (rc); 1597} 1598 1599static int 1600ntb_atom_init_dev(struct ntb_softc *ntb) 1601{ 1602 int error; 1603 1604 KASSERT(ntb->conn_type == NTB_CONN_B2B, 1605 ("Unsupported NTB configuration (%d)\n", ntb->conn_type)); 1606 1607 ntb->spad_count = ATOM_SPAD_COUNT; 1608 ntb->db_count = ATOM_DB_COUNT; 1609 ntb->db_vec_count = ATOM_DB_MSIX_VECTOR_COUNT; 1610 ntb->db_vec_shift = ATOM_DB_MSIX_VECTOR_SHIFT; 1611 ntb->db_valid_mask = (1ull << ntb->db_count) - 1; 1612 1613 ntb->reg = &atom_reg; 1614 ntb->self_reg = &atom_pri_reg; 1615 ntb->peer_reg = &atom_b2b_reg; 1616 ntb->xlat_reg = &atom_sec_xlat; 1617 1618 /* 1619 * FIXME - MSI-X bug on early Atom HW, remove once internal issue is 1620 * resolved. Mask transaction layer internal parity errors. 1621 */ 1622 pci_write_config(ntb->device, 0xFC, 0x4, 4); 1623 1624 configure_atom_secondary_side_bars(ntb); 1625 1626 /* Enable Bus Master and Memory Space on the secondary side */ 1627 ntb_reg_write(2, ATOM_SPCICMD_OFFSET, 1628 PCIM_CMD_MEMEN | PCIM_CMD_BUSMASTEREN); 1629 1630 error = ntb_init_isr(ntb); 1631 if (error != 0) 1632 return (error); 1633 1634 /* Initiate PCI-E link training */ 1635 ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 1636 1637 callout_reset(&ntb->heartbeat_timer, 0, atom_link_hb, ntb); 1638 1639 return (0); 1640} 1641 1642/* XXX: Linux driver doesn't seem to do any of this for Atom. */ 1643static void 1644configure_atom_secondary_side_bars(struct ntb_softc *ntb) 1645{ 1646 1647 if (ntb->dev_type == NTB_DEV_USD) { 1648 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1649 XEON_B2B_BAR2_ADDR64); 1650 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1651 XEON_B2B_BAR4_ADDR64); 1652 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1653 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1654 } else { 1655 ntb_reg_write(8, ATOM_PBAR2XLAT_OFFSET, 1656 XEON_B2B_BAR2_ADDR64); 1657 ntb_reg_write(8, ATOM_PBAR4XLAT_OFFSET, 1658 XEON_B2B_BAR4_ADDR64); 1659 ntb_reg_write(8, ATOM_MBAR23_OFFSET, XEON_B2B_BAR2_ADDR64); 1660 ntb_reg_write(8, ATOM_MBAR45_OFFSET, XEON_B2B_BAR4_ADDR64); 1661 } 1662} 1663 1664 1665/* 1666 * When working around Xeon SDOORBELL errata by remapping remote registers in a 1667 * MW, limit the B2B MW to half a MW. By sharing a MW, half the shared MW 1668 * remains for use by a higher layer. 1669 * 1670 * Will only be used if working around SDOORBELL errata and the BIOS-configured 1671 * MW size is sufficiently large. 1672 */ 1673static unsigned int ntb_b2b_mw_share; 1674TUNABLE_INT("hw.ntb.b2b_mw_share", &ntb_b2b_mw_share); 1675SYSCTL_UINT(_hw_ntb, OID_AUTO, b2b_mw_share, CTLFLAG_RDTUN, &ntb_b2b_mw_share, 1676 0, "If enabled (non-zero), prefer to share half of the B2B peer register " 1677 "MW with higher level consumers. Both sides of the NTB MUST set the same " 1678 "value here."); 1679 1680static void 1681xeon_reset_sbar_size(struct ntb_softc *ntb, enum ntb_bar idx, 1682 enum ntb_bar regbar) 1683{ 1684 struct ntb_pci_bar_info *bar; 1685 uint8_t bar_sz; 1686 1687 if (!HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_3) 1688 return; 1689 1690 bar = &ntb->bar_info[idx]; 1691 bar_sz = pci_read_config(ntb->device, bar->psz_off, 1); 1692 if (idx == regbar) { 1693 if (ntb->b2b_off != 0) 1694 bar_sz--; 1695 else 1696 bar_sz = 0; 1697 } 1698 pci_write_config(ntb->device, bar->ssz_off, bar_sz, 1); 1699 bar_sz = pci_read_config(ntb->device, bar->ssz_off, 1); 1700 (void)bar_sz; 1701} 1702 1703static void 1704xeon_set_sbar_base_and_limit(struct ntb_softc *ntb, uint64_t bar_addr, 1705 enum ntb_bar idx, enum ntb_bar regbar) 1706{ 1707 uint64_t reg_val; 1708 uint32_t base_reg, lmt_reg; 1709 1710 bar_get_xlat_params(ntb, idx, &base_reg, NULL, &lmt_reg); 1711 if (idx == regbar) { 1712 if (ntb->b2b_off) 1713 bar_addr += ntb->b2b_off; 1714 else 1715 bar_addr = 0; 1716 } 1717 1718 if (!bar_is_64bit(ntb, idx)) { 1719 ntb_reg_write(4, base_reg, bar_addr); 1720 reg_val = ntb_reg_read(4, base_reg); 1721 (void)reg_val; 1722 1723 ntb_reg_write(4, lmt_reg, bar_addr); 1724 reg_val = ntb_reg_read(4, lmt_reg); 1725 (void)reg_val; 1726 } else { 1727 ntb_reg_write(8, base_reg, bar_addr); 1728 reg_val = ntb_reg_read(8, base_reg); 1729 (void)reg_val; 1730 1731 ntb_reg_write(8, lmt_reg, bar_addr); 1732 reg_val = ntb_reg_read(8, lmt_reg); 1733 (void)reg_val; 1734 } 1735} 1736 1737static void 1738xeon_set_pbar_xlat(struct ntb_softc *ntb, uint64_t base_addr, enum ntb_bar idx) 1739{ 1740 struct ntb_pci_bar_info *bar; 1741 1742 bar = &ntb->bar_info[idx]; 1743 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR) && idx >= NTB_B2B_BAR_2) { 1744 ntb_reg_write(4, bar->pbarxlat_off, base_addr); 1745 base_addr = ntb_reg_read(4, bar->pbarxlat_off); 1746 } else { 1747 ntb_reg_write(8, bar->pbarxlat_off, base_addr); 1748 base_addr = ntb_reg_read(8, bar->pbarxlat_off); 1749 } 1750 (void)base_addr; 1751} 1752 1753static int 1754xeon_setup_b2b_mw(struct ntb_softc *ntb, const struct ntb_b2b_addr *addr, 1755 const struct ntb_b2b_addr *peer_addr) 1756{ 1757 struct ntb_pci_bar_info *b2b_bar; 1758 vm_size_t bar_size; 1759 uint64_t bar_addr; 1760 enum ntb_bar b2b_bar_num, i; 1761 1762 if (ntb->b2b_mw_idx == B2B_MW_DISABLED) { 1763 b2b_bar = NULL; 1764 b2b_bar_num = NTB_CONFIG_BAR; 1765 ntb->b2b_off = 0; 1766 } else { 1767 b2b_bar_num = ntb_mw_to_bar(ntb, ntb->b2b_mw_idx); 1768 KASSERT(b2b_bar_num > 0 && b2b_bar_num < NTB_MAX_BARS, 1769 ("invalid b2b mw bar")); 1770 1771 b2b_bar = &ntb->bar_info[b2b_bar_num]; 1772 bar_size = b2b_bar->size; 1773 1774 if (ntb_b2b_mw_share != 0 && 1775 (bar_size >> 1) >= XEON_B2B_MIN_SIZE) 1776 ntb->b2b_off = bar_size >> 1; 1777 else if (bar_size >= XEON_B2B_MIN_SIZE) { 1778 ntb->b2b_off = 0; 1779 } else { 1780 device_printf(ntb->device, 1781 "B2B bar size is too small!\n"); 1782 return (EIO); 1783 } 1784 } 1785 1786 /* 1787 * Reset the secondary bar sizes to match the primary bar sizes. 1788 * (Except, disable or halve the size of the B2B secondary bar.) 1789 */ 1790 for (i = NTB_B2B_BAR_1; i < NTB_MAX_BARS; i++) 1791 xeon_reset_sbar_size(ntb, i, b2b_bar_num); 1792 1793 bar_addr = 0; 1794 if (b2b_bar_num == NTB_CONFIG_BAR) 1795 bar_addr = addr->bar0_addr; 1796 else if (b2b_bar_num == NTB_B2B_BAR_1) 1797 bar_addr = addr->bar2_addr64; 1798 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1799 bar_addr = addr->bar4_addr64; 1800 else if (b2b_bar_num == NTB_B2B_BAR_2) 1801 bar_addr = addr->bar4_addr32; 1802 else if (b2b_bar_num == NTB_B2B_BAR_3) 1803 bar_addr = addr->bar5_addr32; 1804 else 1805 KASSERT(false, ("invalid bar")); 1806 1807 ntb_reg_write(8, XEON_SBAR0BASE_OFFSET, bar_addr); 1808 1809 /* 1810 * Other SBARs are normally hit by the PBAR xlat, except for the b2b 1811 * register BAR. The B2B BAR is either disabled above or configured 1812 * half-size. It starts at PBAR xlat + offset. 1813 * 1814 * Also set up incoming BAR limits == base (zero length window). 1815 */ 1816 xeon_set_sbar_base_and_limit(ntb, addr->bar2_addr64, NTB_B2B_BAR_1, 1817 b2b_bar_num); 1818 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1819 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr32, 1820 NTB_B2B_BAR_2, b2b_bar_num); 1821 xeon_set_sbar_base_and_limit(ntb, addr->bar5_addr32, 1822 NTB_B2B_BAR_3, b2b_bar_num); 1823 } else 1824 xeon_set_sbar_base_and_limit(ntb, addr->bar4_addr64, 1825 NTB_B2B_BAR_2, b2b_bar_num); 1826 1827 /* Zero incoming translation addrs */ 1828 ntb_reg_write(8, XEON_SBAR2XLAT_OFFSET, 0); 1829 ntb_reg_write(8, XEON_SBAR4XLAT_OFFSET, 0); 1830 1831 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 1832 uint32_t xlat_reg, lmt_reg; 1833 enum ntb_bar bar_num; 1834 1835 /* 1836 * We point the chosen MSIX MW BAR xlat to remote LAPIC for 1837 * workaround 1838 */ 1839 bar_num = ntb_mw_to_bar(ntb, ntb->msix_mw_idx); 1840 bar_get_xlat_params(ntb, bar_num, NULL, &xlat_reg, &lmt_reg); 1841 if (bar_is_64bit(ntb, bar_num)) { 1842 ntb_reg_write(8, xlat_reg, MSI_INTEL_ADDR_BASE); 1843 ntb->msix_xlat = ntb_reg_read(8, xlat_reg); 1844 ntb_reg_write(8, lmt_reg, 0); 1845 } else { 1846 ntb_reg_write(4, xlat_reg, MSI_INTEL_ADDR_BASE); 1847 ntb->msix_xlat = ntb_reg_read(4, xlat_reg); 1848 ntb_reg_write(4, lmt_reg, 0); 1849 } 1850 1851 ntb->peer_lapic_bar = &ntb->bar_info[bar_num]; 1852 } 1853 (void)ntb_reg_read(8, XEON_SBAR2XLAT_OFFSET); 1854 (void)ntb_reg_read(8, XEON_SBAR4XLAT_OFFSET); 1855 1856 /* Zero outgoing translation limits (whole bar size windows) */ 1857 ntb_reg_write(8, XEON_PBAR2LMT_OFFSET, 0); 1858 ntb_reg_write(8, XEON_PBAR4LMT_OFFSET, 0); 1859 1860 /* Set outgoing translation offsets */ 1861 xeon_set_pbar_xlat(ntb, peer_addr->bar2_addr64, NTB_B2B_BAR_1); 1862 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 1863 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr32, NTB_B2B_BAR_2); 1864 xeon_set_pbar_xlat(ntb, peer_addr->bar5_addr32, NTB_B2B_BAR_3); 1865 } else 1866 xeon_set_pbar_xlat(ntb, peer_addr->bar4_addr64, NTB_B2B_BAR_2); 1867 1868 /* Set the translation offset for B2B registers */ 1869 bar_addr = 0; 1870 if (b2b_bar_num == NTB_CONFIG_BAR) 1871 bar_addr = peer_addr->bar0_addr; 1872 else if (b2b_bar_num == NTB_B2B_BAR_1) 1873 bar_addr = peer_addr->bar2_addr64; 1874 else if (b2b_bar_num == NTB_B2B_BAR_2 && !HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 1875 bar_addr = peer_addr->bar4_addr64; 1876 else if (b2b_bar_num == NTB_B2B_BAR_2) 1877 bar_addr = peer_addr->bar4_addr32; 1878 else if (b2b_bar_num == NTB_B2B_BAR_3) 1879 bar_addr = peer_addr->bar5_addr32; 1880 else 1881 KASSERT(false, ("invalid bar")); 1882 1883 /* 1884 * B2B_XLAT_OFFSET is a 64-bit register but can only be written 32 bits 1885 * at a time. 1886 */ 1887 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETL, bar_addr & 0xffffffff); 1888 ntb_reg_write(4, XEON_B2B_XLAT_OFFSETU, bar_addr >> 32); 1889 return (0); 1890} 1891 1892static inline bool 1893_xeon_link_is_up(struct ntb_softc *ntb) 1894{ 1895 1896 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 1897 return (true); 1898 return ((ntb->lnk_sta & NTB_LINK_STATUS_ACTIVE) != 0); 1899} 1900 1901static inline bool 1902link_is_up(struct ntb_softc *ntb) 1903{ 1904 1905 if (ntb->type == NTB_XEON) 1906 return (_xeon_link_is_up(ntb) && (ntb->peer_msix_good || 1907 !HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP))); 1908 1909 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1910 return ((ntb->ntb_ctl & ATOM_CNTL_LINK_DOWN) == 0); 1911} 1912 1913static inline bool 1914atom_link_is_err(struct ntb_softc *ntb) 1915{ 1916 uint32_t status; 1917 1918 KASSERT(ntb->type == NTB_ATOM, ("ntb type")); 1919 1920 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1921 if ((status & ATOM_LTSSMSTATEJMP_FORCEDETECT) != 0) 1922 return (true); 1923 1924 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1925 return ((status & ATOM_IBIST_ERR_OFLOW) != 0); 1926} 1927 1928/* Atom does not have link status interrupt, poll on that platform */ 1929static void 1930atom_link_hb(void *arg) 1931{ 1932 struct ntb_softc *ntb = arg; 1933 sbintime_t timo, poll_ts; 1934 1935 timo = NTB_HB_TIMEOUT * hz; 1936 poll_ts = ntb->last_ts + timo; 1937 1938 /* 1939 * Delay polling the link status if an interrupt was received, unless 1940 * the cached link status says the link is down. 1941 */ 1942 if ((sbintime_t)ticks - poll_ts < 0 && link_is_up(ntb)) { 1943 timo = poll_ts - ticks; 1944 goto out; 1945 } 1946 1947 if (ntb_poll_link(ntb)) 1948 ntb_link_event(ntb->device); 1949 1950 if (!link_is_up(ntb) && atom_link_is_err(ntb)) { 1951 /* Link is down with error, proceed with recovery */ 1952 callout_reset(&ntb->lr_timer, 0, recover_atom_link, ntb); 1953 return; 1954 } 1955 1956out: 1957 callout_reset(&ntb->heartbeat_timer, timo, atom_link_hb, ntb); 1958} 1959 1960static void 1961atom_perform_link_restart(struct ntb_softc *ntb) 1962{ 1963 uint32_t status; 1964 1965 /* Driver resets the NTB ModPhy lanes - magic! */ 1966 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0xe0); 1967 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x40); 1968 ntb_reg_write(1, ATOM_MODPHY_PCSREG4, 0x60); 1969 ntb_reg_write(1, ATOM_MODPHY_PCSREG6, 0x60); 1970 1971 /* Driver waits 100ms to allow the NTB ModPhy to settle */ 1972 pause("ModPhy", hz / 10); 1973 1974 /* Clear AER Errors, write to clear */ 1975 status = ntb_reg_read(4, ATOM_ERRCORSTS_OFFSET); 1976 status &= PCIM_AER_COR_REPLAY_ROLLOVER; 1977 ntb_reg_write(4, ATOM_ERRCORSTS_OFFSET, status); 1978 1979 /* Clear unexpected electrical idle event in LTSSM, write to clear */ 1980 status = ntb_reg_read(4, ATOM_LTSSMERRSTS0_OFFSET); 1981 status |= ATOM_LTSSMERRSTS0_UNEXPECTEDEI; 1982 ntb_reg_write(4, ATOM_LTSSMERRSTS0_OFFSET, status); 1983 1984 /* Clear DeSkew Buffer error, write to clear */ 1985 status = ntb_reg_read(4, ATOM_DESKEWSTS_OFFSET); 1986 status |= ATOM_DESKEWSTS_DBERR; 1987 ntb_reg_write(4, ATOM_DESKEWSTS_OFFSET, status); 1988 1989 status = ntb_reg_read(4, ATOM_IBSTERRRCRVSTS0_OFFSET); 1990 status &= ATOM_IBIST_ERR_OFLOW; 1991 ntb_reg_write(4, ATOM_IBSTERRRCRVSTS0_OFFSET, status); 1992 1993 /* Releases the NTB state machine to allow the link to retrain */ 1994 status = ntb_reg_read(4, ATOM_LTSSMSTATEJMP_OFFSET); 1995 status &= ~ATOM_LTSSMSTATEJMP_FORCEDETECT; 1996 ntb_reg_write(4, ATOM_LTSSMSTATEJMP_OFFSET, status); 1997} 1998 1999static int 2000ntb_set_ctx(device_t dev, void *ctx, const struct ntb_ctx_ops *ops) 2001{ 2002 struct ntb_softc *ntb = device_get_softc(dev); 2003 2004 if (ctx == NULL || ops == NULL) 2005 return (EINVAL); 2006 2007 rm_wlock(&ntb->ctx_lock); 2008 if (ntb->ctx_ops != NULL) { 2009 rm_wunlock(&ntb->ctx_lock); 2010 return (EINVAL); 2011 } 2012 ntb->ntb_ctx = ctx; 2013 ntb->ctx_ops = ops; 2014 rm_wunlock(&ntb->ctx_lock); 2015 2016 return (0); 2017} 2018 2019/* 2020 * It is expected that this will only be used from contexts where the ctx_lock 2021 * is not needed to protect ntb_ctx lifetime. 2022 */ 2023static void * 2024ntb_get_ctx(device_t dev, const struct ntb_ctx_ops **ops) 2025{ 2026 struct ntb_softc *ntb = device_get_softc(dev); 2027 2028 KASSERT(ntb->ntb_ctx != NULL && ntb->ctx_ops != NULL, ("bogus")); 2029 if (ops != NULL) 2030 *ops = ntb->ctx_ops; 2031 return (ntb->ntb_ctx); 2032} 2033 2034static void 2035ntb_clear_ctx(device_t dev) 2036{ 2037 struct ntb_softc *ntb = device_get_softc(dev); 2038 2039 rm_wlock(&ntb->ctx_lock); 2040 ntb->ntb_ctx = NULL; 2041 ntb->ctx_ops = NULL; 2042 rm_wunlock(&ntb->ctx_lock); 2043} 2044 2045/* 2046 * ntb_link_event() - notify driver context of a change in link status 2047 * @ntb: NTB device context 2048 * 2049 * Notify the driver context that the link status may have changed. The driver 2050 * should call ntb_link_is_up() to get the current status. 2051 */ 2052static void 2053ntb_link_event(device_t dev) 2054{ 2055 struct ntb_softc *ntb = device_get_softc(dev); 2056 struct rm_priotracker ctx_tracker; 2057 2058 rm_rlock(&ntb->ctx_lock, &ctx_tracker); 2059 if (ntb->ctx_ops != NULL && ntb->ctx_ops->link_event != NULL) 2060 ntb->ctx_ops->link_event(ntb->ntb_ctx); 2061 rm_runlock(&ntb->ctx_lock, &ctx_tracker); 2062} 2063 2064/* 2065 * ntb_db_event() - notify driver context of a doorbell event 2066 * @ntb: NTB device context 2067 * @vector: Interrupt vector number 2068 * 2069 * Notify the driver context of a doorbell event. If hardware supports 2070 * multiple interrupt vectors for doorbells, the vector number indicates which 2071 * vector received the interrupt. The vector number is relative to the first 2072 * vector used for doorbells, starting at zero, and must be less than 2073 * ntb_db_vector_count(). The driver may call ntb_db_read() to check which 2074 * doorbell bits need service, and ntb_db_vector_mask() to determine which of 2075 * those bits are associated with the vector number. 2076 */ 2077static void 2078ntb_db_event(device_t dev, uint32_t vec) 2079{ 2080 struct ntb_softc *ntb = device_get_softc(dev); 2081 struct rm_priotracker ctx_tracker; 2082 2083 rm_rlock(&ntb->ctx_lock, &ctx_tracker); 2084 if (ntb->ctx_ops != NULL && ntb->ctx_ops->db_event != NULL) 2085 ntb->ctx_ops->db_event(ntb->ntb_ctx, vec); 2086 rm_runlock(&ntb->ctx_lock, &ctx_tracker); 2087} 2088 2089static int 2090ntb_link_enable(device_t dev, enum ntb_speed speed __unused, 2091 enum ntb_width width __unused) 2092{ 2093 struct ntb_softc *ntb = device_get_softc(dev); 2094 uint32_t cntl; 2095 2096 ntb_printf(2, "%s\n", __func__); 2097 2098 if (ntb->type == NTB_ATOM) { 2099 pci_write_config(ntb->device, NTB_PPD_OFFSET, 2100 ntb->ppd | ATOM_PPD_INIT_LINK, 4); 2101 return (0); 2102 } 2103 2104 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2105 ntb_link_event(dev); 2106 return (0); 2107 } 2108 2109 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2110 cntl &= ~(NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK); 2111 cntl |= NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP; 2112 cntl |= NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP; 2113 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2114 cntl |= NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP; 2115 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2116 return (0); 2117} 2118 2119static int 2120ntb_link_disable(device_t dev) 2121{ 2122 struct ntb_softc *ntb = device_get_softc(dev); 2123 uint32_t cntl; 2124 2125 ntb_printf(2, "%s\n", __func__); 2126 2127 if (ntb->conn_type == NTB_CONN_TRANSPARENT) { 2128 ntb_link_event(dev); 2129 return (0); 2130 } 2131 2132 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2133 cntl &= ~(NTB_CNTL_P2S_BAR23_SNOOP | NTB_CNTL_S2P_BAR23_SNOOP); 2134 cntl &= ~(NTB_CNTL_P2S_BAR4_SNOOP | NTB_CNTL_S2P_BAR4_SNOOP); 2135 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) 2136 cntl &= ~(NTB_CNTL_P2S_BAR5_SNOOP | NTB_CNTL_S2P_BAR5_SNOOP); 2137 cntl |= NTB_CNTL_LINK_DISABLE | NTB_CNTL_CFG_LOCK; 2138 ntb_reg_write(4, ntb->reg->ntb_ctl, cntl); 2139 return (0); 2140} 2141 2142static bool 2143ntb_link_enabled(device_t dev) 2144{ 2145 struct ntb_softc *ntb = device_get_softc(dev); 2146 uint32_t cntl; 2147 2148 if (ntb->type == NTB_ATOM) { 2149 cntl = pci_read_config(ntb->device, NTB_PPD_OFFSET, 4); 2150 return ((cntl & ATOM_PPD_INIT_LINK) != 0); 2151 } 2152 2153 if (ntb->conn_type == NTB_CONN_TRANSPARENT) 2154 return (true); 2155 2156 cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2157 return ((cntl & NTB_CNTL_LINK_DISABLE) == 0); 2158} 2159 2160static void 2161recover_atom_link(void *arg) 2162{ 2163 struct ntb_softc *ntb = arg; 2164 unsigned speed, width, oldspeed, oldwidth; 2165 uint32_t status32; 2166 2167 atom_perform_link_restart(ntb); 2168 2169 /* 2170 * There is a potential race between the 2 NTB devices recovering at 2171 * the same time. If the times are the same, the link will not recover 2172 * and the driver will be stuck in this loop forever. Add a random 2173 * interval to the recovery time to prevent this race. 2174 */ 2175 status32 = arc4random() % ATOM_LINK_RECOVERY_TIME; 2176 pause("Link", (ATOM_LINK_RECOVERY_TIME + status32) * hz / 1000); 2177 2178 if (atom_link_is_err(ntb)) 2179 goto retry; 2180 2181 status32 = ntb_reg_read(4, ntb->reg->ntb_ctl); 2182 if ((status32 & ATOM_CNTL_LINK_DOWN) != 0) 2183 goto out; 2184 2185 status32 = ntb_reg_read(4, ntb->reg->lnk_sta); 2186 width = NTB_LNK_STA_WIDTH(status32); 2187 speed = status32 & NTB_LINK_SPEED_MASK; 2188 2189 oldwidth = NTB_LNK_STA_WIDTH(ntb->lnk_sta); 2190 oldspeed = ntb->lnk_sta & NTB_LINK_SPEED_MASK; 2191 if (oldwidth != width || oldspeed != speed) 2192 goto retry; 2193 2194out: 2195 callout_reset(&ntb->heartbeat_timer, NTB_HB_TIMEOUT * hz, atom_link_hb, 2196 ntb); 2197 return; 2198 2199retry: 2200 callout_reset(&ntb->lr_timer, NTB_HB_TIMEOUT * hz, recover_atom_link, 2201 ntb); 2202} 2203 2204/* 2205 * Polls the HW link status register(s); returns true if something has changed. 2206 */ 2207static bool 2208ntb_poll_link(struct ntb_softc *ntb) 2209{ 2210 uint32_t ntb_cntl; 2211 uint16_t reg_val; 2212 2213 if (ntb->type == NTB_ATOM) { 2214 ntb_cntl = ntb_reg_read(4, ntb->reg->ntb_ctl); 2215 if (ntb_cntl == ntb->ntb_ctl) 2216 return (false); 2217 2218 ntb->ntb_ctl = ntb_cntl; 2219 ntb->lnk_sta = ntb_reg_read(4, ntb->reg->lnk_sta); 2220 } else { 2221 db_iowrite_raw(ntb, ntb->self_reg->db_bell, ntb->db_link_mask); 2222 2223 reg_val = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2224 if (reg_val == ntb->lnk_sta) 2225 return (false); 2226 2227 ntb->lnk_sta = reg_val; 2228 2229 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 2230 if (_xeon_link_is_up(ntb)) { 2231 if (!ntb->peer_msix_good) { 2232 callout_reset(&ntb->peer_msix_work, 0, 2233 ntb_exchange_msix, ntb); 2234 return (false); 2235 } 2236 } else { 2237 ntb->peer_msix_good = false; 2238 ntb->peer_msix_done = false; 2239 } 2240 } 2241 } 2242 return (true); 2243} 2244 2245static inline enum ntb_speed 2246ntb_link_sta_speed(struct ntb_softc *ntb) 2247{ 2248 2249 if (!link_is_up(ntb)) 2250 return (NTB_SPEED_NONE); 2251 return (ntb->lnk_sta & NTB_LINK_SPEED_MASK); 2252} 2253 2254static inline enum ntb_width 2255ntb_link_sta_width(struct ntb_softc *ntb) 2256{ 2257 2258 if (!link_is_up(ntb)) 2259 return (NTB_WIDTH_NONE); 2260 return (NTB_LNK_STA_WIDTH(ntb->lnk_sta)); 2261} 2262 2263SYSCTL_NODE(_hw_ntb, OID_AUTO, debug_info, CTLFLAG_RW, 0, 2264 "Driver state, statistics, and HW registers"); 2265 2266#define NTB_REGSZ_MASK (3ul << 30) 2267#define NTB_REG_64 (1ul << 30) 2268#define NTB_REG_32 (2ul << 30) 2269#define NTB_REG_16 (3ul << 30) 2270#define NTB_REG_8 (0ul << 30) 2271 2272#define NTB_DB_READ (1ul << 29) 2273#define NTB_PCI_REG (1ul << 28) 2274#define NTB_REGFLAGS_MASK (NTB_REGSZ_MASK | NTB_DB_READ | NTB_PCI_REG) 2275 2276static void 2277ntb_sysctl_init(struct ntb_softc *ntb) 2278{ 2279 struct sysctl_oid_list *globals, *tree_par, *regpar, *statpar, *errpar; 2280 struct sysctl_ctx_list *ctx; 2281 struct sysctl_oid *tree, *tmptree; 2282 2283 ctx = device_get_sysctl_ctx(ntb->device); 2284 globals = SYSCTL_CHILDREN(device_get_sysctl_tree(ntb->device)); 2285 2286 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "link_status", 2287 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, 2288 sysctl_handle_link_status_human, "A", 2289 "Link status (human readable)"); 2290 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "active", 2291 CTLFLAG_RD | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_status, 2292 "IU", "Link status (1=active, 0=inactive)"); 2293 SYSCTL_ADD_PROC(ctx, globals, OID_AUTO, "admin_up", 2294 CTLFLAG_RW | CTLTYPE_UINT, ntb, 0, sysctl_handle_link_admin, 2295 "IU", "Set/get interface status (1=UP, 0=DOWN)"); 2296 2297 tree = SYSCTL_ADD_NODE(ctx, globals, OID_AUTO, "debug_info", 2298 CTLFLAG_RD, NULL, "Driver state, statistics, and HW registers"); 2299 tree_par = SYSCTL_CHILDREN(tree); 2300 2301 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "conn_type", CTLFLAG_RD, 2302 &ntb->conn_type, 0, "0 - Transparent; 1 - B2B; 2 - Root Port"); 2303 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "dev_type", CTLFLAG_RD, 2304 &ntb->dev_type, 0, "0 - USD; 1 - DSD"); 2305 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ppd", CTLFLAG_RD, 2306 &ntb->ppd, 0, "Raw PPD register (cached)"); 2307 2308 if (ntb->b2b_mw_idx != B2B_MW_DISABLED) { 2309#ifdef notyet 2310 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "b2b_idx", CTLFLAG_RD, 2311 &ntb->b2b_mw_idx, 0, 2312 "Index of the MW used for B2B remote register access"); 2313#endif 2314 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "b2b_off", 2315 CTLFLAG_RD, &ntb->b2b_off, 2316 "If non-zero, offset of B2B register region in shared MW"); 2317 } 2318 2319 SYSCTL_ADD_PROC(ctx, tree_par, OID_AUTO, "features", 2320 CTLFLAG_RD | CTLTYPE_STRING, ntb, 0, sysctl_handle_features, "A", 2321 "Features/errata of this NTB device"); 2322 2323 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "ntb_ctl", CTLFLAG_RD, 2324 __DEVOLATILE(uint32_t *, &ntb->ntb_ctl), 0, 2325 "NTB CTL register (cached)"); 2326 SYSCTL_ADD_UINT(ctx, tree_par, OID_AUTO, "lnk_sta", CTLFLAG_RD, 2327 __DEVOLATILE(uint32_t *, &ntb->lnk_sta), 0, 2328 "LNK STA register (cached)"); 2329 2330#ifdef notyet 2331 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "mw_count", CTLFLAG_RD, 2332 &ntb->mw_count, 0, "MW count"); 2333 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "spad_count", CTLFLAG_RD, 2334 &ntb->spad_count, 0, "Scratchpad count"); 2335 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_count", CTLFLAG_RD, 2336 &ntb->db_count, 0, "Doorbell count"); 2337 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_count", CTLFLAG_RD, 2338 &ntb->db_vec_count, 0, "Doorbell vector count"); 2339 SYSCTL_ADD_U8(ctx, tree_par, OID_AUTO, "db_vec_shift", CTLFLAG_RD, 2340 &ntb->db_vec_shift, 0, "Doorbell vector shift"); 2341#endif 2342 2343 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_valid_mask", CTLFLAG_RD, 2344 &ntb->db_valid_mask, "Doorbell valid mask"); 2345 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_link_mask", CTLFLAG_RD, 2346 &ntb->db_link_mask, "Doorbell link mask"); 2347 SYSCTL_ADD_UQUAD(ctx, tree_par, OID_AUTO, "db_mask", CTLFLAG_RD, 2348 &ntb->db_mask, "Doorbell mask (cached)"); 2349 2350 tmptree = SYSCTL_ADD_NODE(ctx, tree_par, OID_AUTO, "registers", 2351 CTLFLAG_RD, NULL, "Raw HW registers (big-endian)"); 2352 regpar = SYSCTL_CHILDREN(tmptree); 2353 2354 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ntbcntl", 2355 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2356 ntb->reg->ntb_ctl, sysctl_handle_register, "IU", 2357 "NTB Control register"); 2358 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcap", 2359 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2360 0x19c, sysctl_handle_register, "IU", 2361 "NTB Link Capabilities"); 2362 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnkcon", 2363 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, NTB_REG_32 | 2364 0x1a0, sysctl_handle_register, "IU", 2365 "NTB Link Control register"); 2366 2367 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_mask", 2368 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2369 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_mask, 2370 sysctl_handle_register, "QU", "Doorbell mask register"); 2371 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "db_bell", 2372 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2373 NTB_REG_64 | NTB_DB_READ | ntb->self_reg->db_bell, 2374 sysctl_handle_register, "QU", "Doorbell register"); 2375 2376 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat23", 2377 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2378 NTB_REG_64 | ntb->xlat_reg->bar2_xlat, 2379 sysctl_handle_register, "QU", "Incoming XLAT23 register"); 2380 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2381 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat4", 2382 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2383 NTB_REG_32 | ntb->xlat_reg->bar4_xlat, 2384 sysctl_handle_register, "IU", "Incoming XLAT4 register"); 2385 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat5", 2386 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2387 NTB_REG_32 | ntb->xlat_reg->bar5_xlat, 2388 sysctl_handle_register, "IU", "Incoming XLAT5 register"); 2389 } else { 2390 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_xlat45", 2391 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2392 NTB_REG_64 | ntb->xlat_reg->bar4_xlat, 2393 sysctl_handle_register, "QU", "Incoming XLAT45 register"); 2394 } 2395 2396 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt23", 2397 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2398 NTB_REG_64 | ntb->xlat_reg->bar2_limit, 2399 sysctl_handle_register, "QU", "Incoming LMT23 register"); 2400 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2401 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt4", 2402 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2403 NTB_REG_32 | ntb->xlat_reg->bar4_limit, 2404 sysctl_handle_register, "IU", "Incoming LMT4 register"); 2405 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt5", 2406 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2407 NTB_REG_32 | ntb->xlat_reg->bar5_limit, 2408 sysctl_handle_register, "IU", "Incoming LMT5 register"); 2409 } else { 2410 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "incoming_lmt45", 2411 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2412 NTB_REG_64 | ntb->xlat_reg->bar4_limit, 2413 sysctl_handle_register, "QU", "Incoming LMT45 register"); 2414 } 2415 2416 if (ntb->type == NTB_ATOM) 2417 return; 2418 2419 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_stats", 2420 CTLFLAG_RD, NULL, "Xeon HW statistics"); 2421 statpar = SYSCTL_CHILDREN(tmptree); 2422 SYSCTL_ADD_PROC(ctx, statpar, OID_AUTO, "upstream_mem_miss", 2423 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2424 NTB_REG_16 | XEON_USMEMMISS_OFFSET, 2425 sysctl_handle_register, "SU", "Upstream Memory Miss"); 2426 2427 tmptree = SYSCTL_ADD_NODE(ctx, regpar, OID_AUTO, "xeon_hw_err", 2428 CTLFLAG_RD, NULL, "Xeon HW errors"); 2429 errpar = SYSCTL_CHILDREN(tmptree); 2430 2431 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "ppd", 2432 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2433 NTB_REG_8 | NTB_PCI_REG | NTB_PPD_OFFSET, 2434 sysctl_handle_register, "CU", "PPD"); 2435 2436 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar23_sz", 2437 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2438 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR23SZ_OFFSET, 2439 sysctl_handle_register, "CU", "PBAR23 SZ (log2)"); 2440 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar4_sz", 2441 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2442 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR4SZ_OFFSET, 2443 sysctl_handle_register, "CU", "PBAR4 SZ (log2)"); 2444 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "pbar5_sz", 2445 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2446 NTB_REG_8 | NTB_PCI_REG | XEON_PBAR5SZ_OFFSET, 2447 sysctl_handle_register, "CU", "PBAR5 SZ (log2)"); 2448 2449 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_sz", 2450 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2451 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR23SZ_OFFSET, 2452 sysctl_handle_register, "CU", "SBAR23 SZ (log2)"); 2453 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_sz", 2454 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2455 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR4SZ_OFFSET, 2456 sysctl_handle_register, "CU", "SBAR4 SZ (log2)"); 2457 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_sz", 2458 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2459 NTB_REG_8 | NTB_PCI_REG | XEON_SBAR5SZ_OFFSET, 2460 sysctl_handle_register, "CU", "SBAR5 SZ (log2)"); 2461 2462 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "devsts", 2463 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2464 NTB_REG_16 | NTB_PCI_REG | XEON_DEVSTS_OFFSET, 2465 sysctl_handle_register, "SU", "DEVSTS"); 2466 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "lnksts", 2467 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2468 NTB_REG_16 | NTB_PCI_REG | XEON_LINK_STATUS_OFFSET, 2469 sysctl_handle_register, "SU", "LNKSTS"); 2470 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "slnksts", 2471 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2472 NTB_REG_16 | NTB_PCI_REG | XEON_SLINK_STATUS_OFFSET, 2473 sysctl_handle_register, "SU", "SLNKSTS"); 2474 2475 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "uncerrsts", 2476 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2477 NTB_REG_32 | NTB_PCI_REG | XEON_UNCERRSTS_OFFSET, 2478 sysctl_handle_register, "IU", "UNCERRSTS"); 2479 SYSCTL_ADD_PROC(ctx, errpar, OID_AUTO, "corerrsts", 2480 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2481 NTB_REG_32 | NTB_PCI_REG | XEON_CORERRSTS_OFFSET, 2482 sysctl_handle_register, "IU", "CORERRSTS"); 2483 2484 if (ntb->conn_type != NTB_CONN_B2B) 2485 return; 2486 2487 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat23", 2488 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2489 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_1].pbarxlat_off, 2490 sysctl_handle_register, "QU", "Outgoing XLAT23 register"); 2491 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2492 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat4", 2493 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2494 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2495 sysctl_handle_register, "IU", "Outgoing XLAT4 register"); 2496 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat5", 2497 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2498 NTB_REG_32 | ntb->bar_info[NTB_B2B_BAR_3].pbarxlat_off, 2499 sysctl_handle_register, "IU", "Outgoing XLAT5 register"); 2500 } else { 2501 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_xlat45", 2502 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2503 NTB_REG_64 | ntb->bar_info[NTB_B2B_BAR_2].pbarxlat_off, 2504 sysctl_handle_register, "QU", "Outgoing XLAT45 register"); 2505 } 2506 2507 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt23", 2508 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2509 NTB_REG_64 | XEON_PBAR2LMT_OFFSET, 2510 sysctl_handle_register, "QU", "Outgoing LMT23 register"); 2511 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2512 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt4", 2513 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2514 NTB_REG_32 | XEON_PBAR4LMT_OFFSET, 2515 sysctl_handle_register, "IU", "Outgoing LMT4 register"); 2516 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt5", 2517 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2518 NTB_REG_32 | XEON_PBAR5LMT_OFFSET, 2519 sysctl_handle_register, "IU", "Outgoing LMT5 register"); 2520 } else { 2521 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "outgoing_lmt45", 2522 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2523 NTB_REG_64 | XEON_PBAR4LMT_OFFSET, 2524 sysctl_handle_register, "QU", "Outgoing LMT45 register"); 2525 } 2526 2527 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar01_base", 2528 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2529 NTB_REG_64 | ntb->xlat_reg->bar0_base, 2530 sysctl_handle_register, "QU", "Secondary BAR01 base register"); 2531 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar23_base", 2532 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2533 NTB_REG_64 | ntb->xlat_reg->bar2_base, 2534 sysctl_handle_register, "QU", "Secondary BAR23 base register"); 2535 if (HAS_FEATURE(ntb, NTB_SPLIT_BAR)) { 2536 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar4_base", 2537 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2538 NTB_REG_32 | ntb->xlat_reg->bar4_base, 2539 sysctl_handle_register, "IU", 2540 "Secondary BAR4 base register"); 2541 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar5_base", 2542 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2543 NTB_REG_32 | ntb->xlat_reg->bar5_base, 2544 sysctl_handle_register, "IU", 2545 "Secondary BAR5 base register"); 2546 } else { 2547 SYSCTL_ADD_PROC(ctx, regpar, OID_AUTO, "sbar45_base", 2548 CTLFLAG_RD | CTLTYPE_OPAQUE, ntb, 2549 NTB_REG_64 | ntb->xlat_reg->bar4_base, 2550 sysctl_handle_register, "QU", 2551 "Secondary BAR45 base register"); 2552 } 2553} 2554 2555static int 2556sysctl_handle_features(SYSCTL_HANDLER_ARGS) 2557{ 2558 struct ntb_softc *ntb = arg1; 2559 struct sbuf sb; 2560 int error; 2561 2562 sbuf_new_for_sysctl(&sb, NULL, 256, req); 2563 2564 sbuf_printf(&sb, "%b", ntb->features, NTB_FEATURES_STR); 2565 error = sbuf_finish(&sb); 2566 sbuf_delete(&sb); 2567 2568 if (error || !req->newptr) 2569 return (error); 2570 return (EINVAL); 2571} 2572 2573static int 2574sysctl_handle_link_admin(SYSCTL_HANDLER_ARGS) 2575{ 2576 struct ntb_softc *ntb = arg1; 2577 unsigned old, new; 2578 int error; 2579 2580 old = ntb_link_enabled(ntb->device); 2581 2582 error = SYSCTL_OUT(req, &old, sizeof(old)); 2583 if (error != 0 || req->newptr == NULL) 2584 return (error); 2585 2586 error = SYSCTL_IN(req, &new, sizeof(new)); 2587 if (error != 0) 2588 return (error); 2589 2590 ntb_printf(0, "Admin set interface state to '%sabled'\n", 2591 (new != 0)? "en" : "dis"); 2592 2593 if (new != 0) 2594 error = ntb_link_enable(ntb->device, NTB_SPEED_AUTO, NTB_WIDTH_AUTO); 2595 else 2596 error = ntb_link_disable(ntb->device); 2597 return (error); 2598} 2599 2600static int 2601sysctl_handle_link_status_human(SYSCTL_HANDLER_ARGS) 2602{ 2603 struct ntb_softc *ntb = arg1; 2604 struct sbuf sb; 2605 enum ntb_speed speed; 2606 enum ntb_width width; 2607 int error; 2608 2609 sbuf_new_for_sysctl(&sb, NULL, 32, req); 2610 2611 if (ntb_link_is_up(ntb->device, &speed, &width)) 2612 sbuf_printf(&sb, "up / PCIe Gen %u / Width x%u", 2613 (unsigned)speed, (unsigned)width); 2614 else 2615 sbuf_printf(&sb, "down"); 2616 2617 error = sbuf_finish(&sb); 2618 sbuf_delete(&sb); 2619 2620 if (error || !req->newptr) 2621 return (error); 2622 return (EINVAL); 2623} 2624 2625static int 2626sysctl_handle_link_status(SYSCTL_HANDLER_ARGS) 2627{ 2628 struct ntb_softc *ntb = arg1; 2629 unsigned res; 2630 int error; 2631 2632 res = ntb_link_is_up(ntb->device, NULL, NULL); 2633 2634 error = SYSCTL_OUT(req, &res, sizeof(res)); 2635 if (error || !req->newptr) 2636 return (error); 2637 return (EINVAL); 2638} 2639 2640static int 2641sysctl_handle_register(SYSCTL_HANDLER_ARGS) 2642{ 2643 struct ntb_softc *ntb; 2644 const void *outp; 2645 uintptr_t sz; 2646 uint64_t umv; 2647 char be[sizeof(umv)]; 2648 size_t outsz; 2649 uint32_t reg; 2650 bool db, pci; 2651 int error; 2652 2653 ntb = arg1; 2654 reg = arg2 & ~NTB_REGFLAGS_MASK; 2655 sz = arg2 & NTB_REGSZ_MASK; 2656 db = (arg2 & NTB_DB_READ) != 0; 2657 pci = (arg2 & NTB_PCI_REG) != 0; 2658 2659 KASSERT(!(db && pci), ("bogus")); 2660 2661 if (db) { 2662 KASSERT(sz == NTB_REG_64, ("bogus")); 2663 umv = db_ioread(ntb, reg); 2664 outsz = sizeof(uint64_t); 2665 } else { 2666 switch (sz) { 2667 case NTB_REG_64: 2668 if (pci) 2669 umv = pci_read_config(ntb->device, reg, 8); 2670 else 2671 umv = ntb_reg_read(8, reg); 2672 outsz = sizeof(uint64_t); 2673 break; 2674 case NTB_REG_32: 2675 if (pci) 2676 umv = pci_read_config(ntb->device, reg, 4); 2677 else 2678 umv = ntb_reg_read(4, reg); 2679 outsz = sizeof(uint32_t); 2680 break; 2681 case NTB_REG_16: 2682 if (pci) 2683 umv = pci_read_config(ntb->device, reg, 2); 2684 else 2685 umv = ntb_reg_read(2, reg); 2686 outsz = sizeof(uint16_t); 2687 break; 2688 case NTB_REG_8: 2689 if (pci) 2690 umv = pci_read_config(ntb->device, reg, 1); 2691 else 2692 umv = ntb_reg_read(1, reg); 2693 outsz = sizeof(uint8_t); 2694 break; 2695 default: 2696 panic("bogus"); 2697 break; 2698 } 2699 } 2700 2701 /* Encode bigendian so that sysctl -x is legible. */ 2702 be64enc(be, umv); 2703 outp = ((char *)be) + sizeof(umv) - outsz; 2704 2705 error = SYSCTL_OUT(req, outp, outsz); 2706 if (error || !req->newptr) 2707 return (error); 2708 return (EINVAL); 2709} 2710 2711static unsigned 2712ntb_user_mw_to_idx(struct ntb_softc *ntb, unsigned uidx) 2713{ 2714 2715 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2716 uidx >= ntb->b2b_mw_idx) || 2717 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2718 uidx++; 2719 if ((ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0 && 2720 uidx >= ntb->b2b_mw_idx) && 2721 (ntb->msix_mw_idx != B2B_MW_DISABLED && uidx >= ntb->msix_mw_idx)) 2722 uidx++; 2723 return (uidx); 2724} 2725 2726static void 2727ntb_exchange_msix(void *ctx) 2728{ 2729 struct ntb_softc *ntb; 2730 uint32_t val; 2731 unsigned i; 2732 2733 ntb = ctx; 2734 2735 if (ntb->peer_msix_good) 2736 goto msix_good; 2737 if (ntb->peer_msix_done) 2738 goto msix_done; 2739 2740 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2741 ntb_peer_spad_write(ntb->device, NTB_MSIX_DATA0 + i, 2742 ntb->msix_data[i].nmd_data); 2743 ntb_peer_spad_write(ntb->device, NTB_MSIX_OFS0 + i, 2744 ntb->msix_data[i].nmd_ofs - ntb->msix_xlat); 2745 } 2746 ntb_peer_spad_write(ntb->device, NTB_MSIX_GUARD, NTB_MSIX_VER_GUARD); 2747 2748 ntb_spad_read(ntb->device, NTB_MSIX_GUARD, &val); 2749 if (val != NTB_MSIX_VER_GUARD) 2750 goto reschedule; 2751 2752 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 2753 ntb_spad_read(ntb->device, NTB_MSIX_DATA0 + i, &val); 2754 ntb_printf(2, "remote MSIX data(%u): 0x%x\n", i, val); 2755 ntb->peer_msix_data[i].nmd_data = val; 2756 ntb_spad_read(ntb->device, NTB_MSIX_OFS0 + i, &val); 2757 ntb_printf(2, "remote MSIX addr(%u): 0x%x\n", i, val); 2758 ntb->peer_msix_data[i].nmd_ofs = val; 2759 } 2760 2761 ntb->peer_msix_done = true; 2762 2763msix_done: 2764 ntb_peer_spad_write(ntb->device, NTB_MSIX_DONE, NTB_MSIX_RECEIVED); 2765 ntb_spad_read(ntb->device, NTB_MSIX_DONE, &val); 2766 if (val != NTB_MSIX_RECEIVED) 2767 goto reschedule; 2768 2769 ntb->peer_msix_good = true; 2770 /* Give peer time to see our NTB_MSIX_RECEIVED. */ 2771 goto reschedule; 2772 2773msix_good: 2774 ntb_poll_link(ntb); 2775 ntb_link_event(ntb->device); 2776 return; 2777 2778reschedule: 2779 ntb->lnk_sta = pci_read_config(ntb->device, ntb->reg->lnk_sta, 2); 2780 if (_xeon_link_is_up(ntb)) { 2781 callout_reset(&ntb->peer_msix_work, 2782 hz * (ntb->peer_msix_good ? 2 : 1) / 100, 2783 ntb_exchange_msix, ntb); 2784 } else 2785 ntb_spad_clear(ntb->device); 2786} 2787 2788/* 2789 * Public API to the rest of the OS 2790 */ 2791 2792static uint8_t 2793ntb_spad_count(device_t dev) 2794{ 2795 struct ntb_softc *ntb = device_get_softc(dev); 2796 2797 return (ntb->spad_count); 2798} 2799 2800static uint8_t 2801ntb_mw_count(device_t dev) 2802{ 2803 struct ntb_softc *ntb = device_get_softc(dev); 2804 uint8_t res; 2805 2806 res = ntb->mw_count; 2807 if (ntb->b2b_mw_idx != B2B_MW_DISABLED && ntb->b2b_off == 0) 2808 res--; 2809 if (ntb->msix_mw_idx != B2B_MW_DISABLED) 2810 res--; 2811 return (res); 2812} 2813 2814static int 2815ntb_spad_write(device_t dev, unsigned int idx, uint32_t val) 2816{ 2817 struct ntb_softc *ntb = device_get_softc(dev); 2818 2819 if (idx >= ntb->spad_count) 2820 return (EINVAL); 2821 2822 ntb_reg_write(4, ntb->self_reg->spad + idx * 4, val); 2823 2824 return (0); 2825} 2826 2827/* 2828 * Zeros the local scratchpad. 2829 */ 2830static void 2831ntb_spad_clear(device_t dev) 2832{ 2833 struct ntb_softc *ntb = device_get_softc(dev); 2834 unsigned i; 2835 2836 for (i = 0; i < ntb->spad_count; i++) 2837 ntb_spad_write(dev, i, 0); 2838} 2839 2840static int 2841ntb_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2842{ 2843 struct ntb_softc *ntb = device_get_softc(dev); 2844 2845 if (idx >= ntb->spad_count) 2846 return (EINVAL); 2847 2848 *val = ntb_reg_read(4, ntb->self_reg->spad + idx * 4); 2849 2850 return (0); 2851} 2852 2853static int 2854ntb_peer_spad_write(device_t dev, unsigned int idx, uint32_t val) 2855{ 2856 struct ntb_softc *ntb = device_get_softc(dev); 2857 2858 if (idx >= ntb->spad_count) 2859 return (EINVAL); 2860 2861 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2862 ntb_mw_write(4, XEON_SPAD_OFFSET + idx * 4, val); 2863 else 2864 ntb_reg_write(4, ntb->peer_reg->spad + idx * 4, val); 2865 2866 return (0); 2867} 2868 2869static int 2870ntb_peer_spad_read(device_t dev, unsigned int idx, uint32_t *val) 2871{ 2872 struct ntb_softc *ntb = device_get_softc(dev); 2873 2874 if (idx >= ntb->spad_count) 2875 return (EINVAL); 2876 2877 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) 2878 *val = ntb_mw_read(4, XEON_SPAD_OFFSET + idx * 4); 2879 else 2880 *val = ntb_reg_read(4, ntb->peer_reg->spad + idx * 4); 2881 2882 return (0); 2883} 2884 2885static int 2886ntb_mw_get_range(device_t dev, unsigned mw_idx, vm_paddr_t *base, 2887 caddr_t *vbase, size_t *size, size_t *align, size_t *align_size, 2888 bus_addr_t *plimit) 2889{ 2890 struct ntb_softc *ntb = device_get_softc(dev); 2891 struct ntb_pci_bar_info *bar; 2892 bus_addr_t limit; 2893 size_t bar_b2b_off; 2894 enum ntb_bar bar_num; 2895 2896 if (mw_idx >= ntb_mw_count(dev)) 2897 return (EINVAL); 2898 mw_idx = ntb_user_mw_to_idx(ntb, mw_idx); 2899 2900 bar_num = ntb_mw_to_bar(ntb, mw_idx); 2901 bar = &ntb->bar_info[bar_num]; 2902 bar_b2b_off = 0; 2903 if (mw_idx == ntb->b2b_mw_idx) { 2904 KASSERT(ntb->b2b_off != 0, 2905 ("user shouldn't get non-shared b2b mw")); 2906 bar_b2b_off = ntb->b2b_off; 2907 } 2908 2909 if (bar_is_64bit(ntb, bar_num)) 2910 limit = BUS_SPACE_MAXADDR; 2911 else 2912 limit = BUS_SPACE_MAXADDR_32BIT; 2913 2914 if (base != NULL) 2915 *base = bar->pbase + bar_b2b_off; 2916 if (vbase != NULL) 2917 *vbase = bar->vbase + bar_b2b_off; 2918 if (size != NULL) 2919 *size = bar->size - bar_b2b_off; 2920 if (align != NULL) 2921 *align = bar->size; 2922 if (align_size != NULL) 2923 *align_size = 1; 2924 if (plimit != NULL) 2925 *plimit = limit; 2926 return (0); 2927} 2928 2929static int 2930ntb_mw_set_trans(device_t dev, unsigned idx, bus_addr_t addr, size_t size) 2931{ 2932 struct ntb_softc *ntb = device_get_softc(dev); 2933 struct ntb_pci_bar_info *bar; 2934 uint64_t base, limit, reg_val; 2935 size_t bar_size, mw_size; 2936 uint32_t base_reg, xlat_reg, limit_reg; 2937 enum ntb_bar bar_num; 2938 2939 if (idx >= ntb_mw_count(dev)) 2940 return (EINVAL); 2941 idx = ntb_user_mw_to_idx(ntb, idx); 2942 2943 bar_num = ntb_mw_to_bar(ntb, idx); 2944 bar = &ntb->bar_info[bar_num]; 2945 2946 bar_size = bar->size; 2947 if (idx == ntb->b2b_mw_idx) 2948 mw_size = bar_size - ntb->b2b_off; 2949 else 2950 mw_size = bar_size; 2951 2952 /* Hardware requires that addr is aligned to bar size */ 2953 if ((addr & (bar_size - 1)) != 0) 2954 return (EINVAL); 2955 2956 if (size > mw_size) 2957 return (EINVAL); 2958 2959 bar_get_xlat_params(ntb, bar_num, &base_reg, &xlat_reg, &limit_reg); 2960 2961 limit = 0; 2962 if (bar_is_64bit(ntb, bar_num)) { 2963 base = ntb_reg_read(8, base_reg) & BAR_HIGH_MASK; 2964 2965 if (limit_reg != 0 && size != mw_size) 2966 limit = base + size; 2967 2968 /* Set and verify translation address */ 2969 ntb_reg_write(8, xlat_reg, addr); 2970 reg_val = ntb_reg_read(8, xlat_reg) & BAR_HIGH_MASK; 2971 if (reg_val != addr) { 2972 ntb_reg_write(8, xlat_reg, 0); 2973 return (EIO); 2974 } 2975 2976 /* Set and verify the limit */ 2977 ntb_reg_write(8, limit_reg, limit); 2978 reg_val = ntb_reg_read(8, limit_reg) & BAR_HIGH_MASK; 2979 if (reg_val != limit) { 2980 ntb_reg_write(8, limit_reg, base); 2981 ntb_reg_write(8, xlat_reg, 0); 2982 return (EIO); 2983 } 2984 } else { 2985 /* Configure 32-bit (split) BAR MW */ 2986 2987 if ((addr & UINT32_MAX) != addr) 2988 return (ERANGE); 2989 if (((addr + size) & UINT32_MAX) != (addr + size)) 2990 return (ERANGE); 2991 2992 base = ntb_reg_read(4, base_reg) & BAR_HIGH_MASK; 2993 2994 if (limit_reg != 0 && size != mw_size) 2995 limit = base + size; 2996 2997 /* Set and verify translation address */ 2998 ntb_reg_write(4, xlat_reg, addr); 2999 reg_val = ntb_reg_read(4, xlat_reg) & BAR_HIGH_MASK; 3000 if (reg_val != addr) { 3001 ntb_reg_write(4, xlat_reg, 0); 3002 return (EIO); 3003 } 3004 3005 /* Set and verify the limit */ 3006 ntb_reg_write(4, limit_reg, limit); 3007 reg_val = ntb_reg_read(4, limit_reg) & BAR_HIGH_MASK; 3008 if (reg_val != limit) { 3009 ntb_reg_write(4, limit_reg, base); 3010 ntb_reg_write(4, xlat_reg, 0); 3011 return (EIO); 3012 } 3013 } 3014 return (0); 3015} 3016 3017static int 3018ntb_mw_clear_trans(device_t dev, unsigned mw_idx) 3019{ 3020 3021 return (ntb_mw_set_trans(dev, mw_idx, 0, 0)); 3022} 3023 3024static int 3025ntb_mw_get_wc(device_t dev, unsigned idx, vm_memattr_t *mode) 3026{ 3027 struct ntb_softc *ntb = device_get_softc(dev); 3028 struct ntb_pci_bar_info *bar; 3029 3030 if (idx >= ntb_mw_count(dev)) 3031 return (EINVAL); 3032 idx = ntb_user_mw_to_idx(ntb, idx); 3033 3034 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 3035 *mode = bar->map_mode; 3036 return (0); 3037} 3038 3039static int 3040ntb_mw_set_wc(device_t dev, unsigned idx, vm_memattr_t mode) 3041{ 3042 struct ntb_softc *ntb = device_get_softc(dev); 3043 3044 if (idx >= ntb_mw_count(dev)) 3045 return (EINVAL); 3046 3047 idx = ntb_user_mw_to_idx(ntb, idx); 3048 return (ntb_mw_set_wc_internal(ntb, idx, mode)); 3049} 3050 3051static int 3052ntb_mw_set_wc_internal(struct ntb_softc *ntb, unsigned idx, vm_memattr_t mode) 3053{ 3054 struct ntb_pci_bar_info *bar; 3055 int rc; 3056 3057 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, idx)]; 3058 if (bar->map_mode == mode) 3059 return (0); 3060 3061 rc = pmap_change_attr((vm_offset_t)bar->vbase, bar->size, mode); 3062 if (rc == 0) 3063 bar->map_mode = mode; 3064 3065 return (rc); 3066} 3067 3068static void 3069ntb_peer_db_set(device_t dev, uint64_t bit) 3070{ 3071 struct ntb_softc *ntb = device_get_softc(dev); 3072 3073 if (HAS_FEATURE(ntb, NTB_SB01BASE_LOCKUP)) { 3074 struct ntb_pci_bar_info *lapic; 3075 unsigned i; 3076 3077 lapic = ntb->peer_lapic_bar; 3078 3079 for (i = 0; i < XEON_NONLINK_DB_MSIX_BITS; i++) { 3080 if ((bit & ntb_db_vector_mask(dev, i)) != 0) 3081 bus_space_write_4(lapic->pci_bus_tag, 3082 lapic->pci_bus_handle, 3083 ntb->peer_msix_data[i].nmd_ofs, 3084 ntb->peer_msix_data[i].nmd_data); 3085 } 3086 return; 3087 } 3088 3089 if (HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3090 ntb_mw_write(2, XEON_PDOORBELL_OFFSET, bit); 3091 return; 3092 } 3093 3094 db_iowrite(ntb, ntb->peer_reg->db_bell, bit); 3095} 3096 3097static int 3098ntb_peer_db_addr(device_t dev, bus_addr_t *db_addr, vm_size_t *db_size) 3099{ 3100 struct ntb_softc *ntb = device_get_softc(dev); 3101 struct ntb_pci_bar_info *bar; 3102 uint64_t regoff; 3103 3104 KASSERT((db_addr != NULL && db_size != NULL), ("must be non-NULL")); 3105 3106 if (!HAS_FEATURE(ntb, NTB_SDOORBELL_LOCKUP)) { 3107 bar = &ntb->bar_info[NTB_CONFIG_BAR]; 3108 regoff = ntb->peer_reg->db_bell; 3109 } else { 3110 KASSERT(ntb->b2b_mw_idx != B2B_MW_DISABLED, 3111 ("invalid b2b idx")); 3112 3113 bar = &ntb->bar_info[ntb_mw_to_bar(ntb, ntb->b2b_mw_idx)]; 3114 regoff = XEON_PDOORBELL_OFFSET; 3115 } 3116 KASSERT(bar->pci_bus_tag != X86_BUS_SPACE_IO, ("uh oh")); 3117 3118 /* HACK: Specific to current x86 bus implementation. */ 3119 *db_addr = ((uint64_t)bar->pci_bus_handle + regoff); 3120 *db_size = ntb->reg->db_size; 3121 return (0); 3122} 3123 3124static uint64_t 3125ntb_db_valid_mask(device_t dev) 3126{ 3127 struct ntb_softc *ntb = device_get_softc(dev); 3128 3129 return (ntb->db_valid_mask); 3130} 3131 3132static int 3133ntb_db_vector_count(device_t dev) 3134{ 3135 struct ntb_softc *ntb = device_get_softc(dev); 3136 3137 return (ntb->db_vec_count); 3138} 3139 3140static uint64_t 3141ntb_db_vector_mask(device_t dev, uint32_t vector) 3142{ 3143 struct ntb_softc *ntb = device_get_softc(dev); 3144 3145 if (vector > ntb->db_vec_count) 3146 return (0); 3147 return (ntb->db_valid_mask & ntb_vec_mask(ntb, vector)); 3148} 3149 3150static bool 3151ntb_link_is_up(device_t dev, enum ntb_speed *speed, enum ntb_width *width) 3152{ 3153 struct ntb_softc *ntb = device_get_softc(dev); 3154 3155 if (speed != NULL) 3156 *speed = ntb_link_sta_speed(ntb); 3157 if (width != NULL) 3158 *width = ntb_link_sta_width(ntb); 3159 return (link_is_up(ntb)); 3160} 3161 3162static void 3163save_bar_parameters(struct ntb_pci_bar_info *bar) 3164{ 3165 3166 bar->pci_bus_tag = rman_get_bustag(bar->pci_resource); 3167 bar->pci_bus_handle = rman_get_bushandle(bar->pci_resource); 3168 bar->pbase = rman_get_start(bar->pci_resource); 3169 bar->size = rman_get_size(bar->pci_resource); 3170 bar->vbase = rman_get_virtual(bar->pci_resource); 3171} 3172 3173static device_method_t ntb_intel_methods[] = { 3174 /* Device interface */ 3175 DEVMETHOD(device_probe, ntb_probe), 3176 DEVMETHOD(device_attach, ntb_attach), 3177 DEVMETHOD(device_detach, ntb_detach), 3178 /* NTB interface */ 3179 DEVMETHOD(ntb_link_is_up, ntb_link_is_up), 3180 DEVMETHOD(ntb_link_enable, ntb_link_enable), 3181 DEVMETHOD(ntb_link_disable, ntb_link_disable), 3182 DEVMETHOD(ntb_link_enabled, ntb_link_enabled), 3183 DEVMETHOD(ntb_set_ctx, ntb_set_ctx), 3184 DEVMETHOD(ntb_get_ctx, ntb_get_ctx), 3185 DEVMETHOD(ntb_clear_ctx, ntb_clear_ctx), 3186 DEVMETHOD(ntb_mw_count, ntb_mw_count), 3187 DEVMETHOD(ntb_mw_get_range, ntb_mw_get_range), 3188 DEVMETHOD(ntb_mw_set_trans, ntb_mw_set_trans), 3189 DEVMETHOD(ntb_mw_clear_trans, ntb_mw_clear_trans), 3190 DEVMETHOD(ntb_mw_get_wc, ntb_mw_get_wc), 3191 DEVMETHOD(ntb_mw_set_wc, ntb_mw_set_wc), 3192 DEVMETHOD(ntb_spad_count, ntb_spad_count), 3193 DEVMETHOD(ntb_spad_clear, ntb_spad_clear), 3194 DEVMETHOD(ntb_spad_write, ntb_spad_write), 3195 DEVMETHOD(ntb_spad_read, ntb_spad_read), 3196 DEVMETHOD(ntb_peer_spad_write, ntb_peer_spad_write), 3197 DEVMETHOD(ntb_peer_spad_read, ntb_peer_spad_read), 3198 DEVMETHOD(ntb_db_valid_mask, ntb_db_valid_mask), 3199 DEVMETHOD(ntb_db_vector_count, ntb_db_vector_count), 3200 DEVMETHOD(ntb_db_vector_mask, ntb_db_vector_mask), 3201 DEVMETHOD(ntb_db_clear, ntb_db_clear), 3202 DEVMETHOD(ntb_db_clear_mask, ntb_db_clear_mask), 3203 DEVMETHOD(ntb_db_read, ntb_db_read), 3204 DEVMETHOD(ntb_db_set_mask, ntb_db_set_mask), 3205 DEVMETHOD(ntb_peer_db_addr, ntb_peer_db_addr), 3206 DEVMETHOD(ntb_peer_db_set, ntb_peer_db_set), 3207 DEVMETHOD_END 3208}; 3209 3210static DEFINE_CLASS_0(ntb_hw, ntb_intel_driver, ntb_intel_methods, 3211 sizeof(struct ntb_softc)); 3212DRIVER_MODULE(ntb_intel, pci, ntb_intel_driver, ntb_hw_devclass, NULL, NULL); 3213MODULE_DEPEND(ntb_intel, ntb, 1, 1, 1); 3214MODULE_VERSION(ntb_intel, 1); 3215