1238046Smarcel/*- 2238046Smarcel * Copyright (C) 2012 Juniper Networks, Inc. 3238046Smarcel * Copyright (C) 2009-2012 Semihalf 4238046Smarcel * All rights reserved. 5238046Smarcel * 6238046Smarcel * Redistribution and use in source and binary forms, with or without 7238046Smarcel * modification, are permitted provided that the following conditions 8238046Smarcel * are met: 9238046Smarcel * 1. Redistributions of source code must retain the above copyright 10238046Smarcel * notice, this list of conditions and the following disclaimer. 11238046Smarcel * 2. Redistributions in binary form must reproduce the above copyright 12238046Smarcel * notice, this list of conditions and the following disclaimer in the 13238046Smarcel * documentation and/or other materials provided with the distribution. 14238046Smarcel * 15238046Smarcel * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 16238046Smarcel * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 17238046Smarcel * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 18238046Smarcel * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 19238046Smarcel * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 20238046Smarcel * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 21238046Smarcel * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 22238046Smarcel * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 23238046Smarcel * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 24238046Smarcel * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 25238046Smarcel * SUCH DAMAGE. 26238046Smarcel * 27238046Smarcel * $FreeBSD$ 28238046Smarcel */ 29238046Smarcel 30238046Smarcel#ifndef _NAND_NFC_FSL_H_ 31238046Smarcel#define _NAND_NFC_FSL_H_ 32238046Smarcel 33238046Smarcel/* LBC BR/OR Registers layout definitions */ 34238046Smarcel#define BR_V 0x00000001 35238046Smarcel#define BR_V_SHIFT 0 36238046Smarcel#define BR_MSEL 0x000000E0 37238046Smarcel#define BR_MSEL_SHIFT 5 38238046Smarcel#define BR_DECC_CHECK_MODE 0x00000600 39238046Smarcel#define BR_DECC_CHECK_GEN 0x00000400 40238046Smarcel 41238046Smarcel#define OR_FCM_PAGESIZE 0x00000400 42238046Smarcel 43238046Smarcel/* Options definitions */ 44238046Smarcel#define NAND_OPT_ECC_MODE_HW 1 45238046Smarcel#define NAND_OPT_ECC_MODE_SOFT (1 << 1) 46238046Smarcel 47238046Smarcel/* FMR - Flash Mode Register */ 48238046Smarcel#define FMR_CWTO 0xF000 49238046Smarcel#define FMR_CWTO_SHIFT 12 50238046Smarcel#define FMR_BOOT 0x0800 51238046Smarcel#define FMR_ECCM 0x0100 52238046Smarcel#define FMR_AL 0x0030 53238046Smarcel#define FMR_AL_SHIFT 4 54238046Smarcel#define FMR_OP 0x0003 55238046Smarcel#define FMR_OP_SHIFT 0 56238046Smarcel 57238046Smarcel#define FIR_OP_NOP 0x0 /* No operation and end of sequence */ 58238046Smarcel#define FIR_OP_CA 0x1 /* Issue current column address */ 59238046Smarcel#define FIR_OP_PA 0x2 /* Issue current block+page address */ 60238046Smarcel#define FIR_OP_UA 0x3 /* Issue user defined address */ 61238046Smarcel#define FIR_OP_CM(x) (4 + (x)) /* Issue command from FCR[CMD(x)] */ 62238046Smarcel#define FIR_OP_WB 0x8 /* Write FBCR bytes from FCM buffer */ 63238046Smarcel#define FIR_OP_WS 0x9 /* Write 1 or 2 bytes from MDR[AS] */ 64238046Smarcel#define FIR_OP_RB 0xA /* Read FBCR bytes to FCM buffer */ 65238046Smarcel#define FIR_OP_RS 0xB /* Read 1 or 2 bytes to MDR[AS] */ 66238046Smarcel#define FIR_OP_CW0 0xC /* Wait then issue FCR[CMD0] */ 67238046Smarcel#define FIR_OP_CW1 0xD /* Wait then issue FCR[CMD1] */ 68238046Smarcel#define FIR_OP_RBW 0xE /* Wait then read FBCR bytes */ 69238046Smarcel#define FIR_OP_RSW 0xF /* Wait then read 1 or 2 bytes */ 70238046Smarcel 71238046Smarcel/* LTESR - Transfer Error Status Register */ 72238046Smarcel#define LTESR_BM 0x80000000 73238046Smarcel#define LTESR_FCT 0x40000000 74238046Smarcel#define LTESR_PAR 0x20000000 75238046Smarcel#define LTESR_WP 0x04000000 76238046Smarcel#define LTESR_ATMW 0x00800000 77238046Smarcel#define LTESR_ATMR 0x00400000 78238046Smarcel#define LTESR_CS 0x00080000 79238046Smarcel#define LTESR_CC 0x00000001 80238046Smarcel 81238046Smarcel#define LTESR_NAND_MASK (LTESR_FCT | LTESR_CC | LTESR_CS) 82238046Smarcel 83238046Smarcel/* FPAR - Flash Page Address Register */ 84238046Smarcel#define FPAR_SP_PI 0x00007C00 85238046Smarcel#define FPAR_SP_PI_SHIFT 10 86238046Smarcel#define FPAR_SP_MS 0x00000200 87238046Smarcel#define FPAR_SP_CI 0x000001FF 88238046Smarcel#define FPAR_SP_CI_SHIFT 0 89238046Smarcel#define FPAR_LP_PI 0x0003F000 90238046Smarcel#define FPAR_LP_PI_SHIFT 12 91238046Smarcel#define FPAR_LP_MS 0x00000800 92238046Smarcel#define FPAR_LP_CI 0x000007FF 93238046Smarcel#define FPAR_LP_CI_SHIFT 0 94238046Smarcel 95238046Smarcel#define FSL_FCM_WAIT_TIMEOUT 10 96238046Smarcel 97238046Smarcel#endif /* _NAND_NFC_FSL_H_ */ 98