1139749Simp/*- 293746Sjulian * Copyright (c) 2002 Myson Technology Inc. 393746Sjulian * All rights reserved. 493746Sjulian * 593746Sjulian * Redistribution and use in source and binary forms, with or without 693746Sjulian * modification, are permitted provided that the following conditions 793746Sjulian * are met: 893746Sjulian * 1. Redistributions of source code must retain the above copyright 993746Sjulian * notice, this list of conditions, and the following disclaimer, 1093746Sjulian * without modification, immediately at the beginning of the file. 1193746Sjulian * 2. The name of the author may not be used to endorse or promote products 1293746Sjulian * derived from this software without specific prior written permission. 1393746Sjulian * 1493746Sjulian * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 1593746Sjulian * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 1693746Sjulian * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 1793746Sjulian * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE FOR 1893746Sjulian * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 1993746Sjulian * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 2093746Sjulian * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 2193746Sjulian * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 2293746Sjulian * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 2393746Sjulian * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 2493746Sjulian * SUCH DAMAGE. 2593746Sjulian * 2693746Sjulian * Written by: yen_cw@myson.com.tw available at: http://www.myson.com.tw/ 2793746Sjulian * 2893746Sjulian * $FreeBSD$ 2993746Sjulian * 3093746Sjulian * Myson MTD80x register definitions. 3193746Sjulian * 3293746Sjulian */ 3393746Sjulian#define MY_PAR0 0x0 /* physical address 0-3 */ 3493746Sjulian#define MY_PAR1 0x04 /* physical address 4-5 */ 3593746Sjulian#define MY_MAR0 0x08 /* multicast address 0-3 */ 3693746Sjulian#define MY_MAR1 0x0C /* multicast address 4-7 */ 3793746Sjulian#define MY_FAR0 0x10 /* flow-control address 0-3 */ 3893746Sjulian#define MY_FAR1 0x14 /* flow-control address 4-5 */ 3993746Sjulian#define MY_TCRRCR 0x18 /* receive & transmit configuration */ 4093746Sjulian#define MY_BCR 0x1C /* bus command */ 4193746Sjulian#define MY_TXPDR 0x20 /* transmit polling demand */ 4293746Sjulian#define MY_RXPDR 0x24 /* receive polling demand */ 4393746Sjulian#define MY_RXCWP 0x28 /* receive current word pointer */ 4493746Sjulian#define MY_TXLBA 0x2C /* transmit list base address */ 4593746Sjulian#define MY_RXLBA 0x30 /* receive list base address */ 4693746Sjulian#define MY_ISR 0x34 /* interrupt status */ 4793746Sjulian#define MY_IMR 0x38 /* interrupt mask */ 4893746Sjulian#define MY_FTH 0x3C /* flow control high/low threshold */ 4993746Sjulian#define MY_MANAGEMENT 0x40 /* bootrom/eeprom and mii management */ 5093746Sjulian#define MY_TALLY 0x44 /* tally counters for crc and mpa */ 5193746Sjulian#define MY_TSR 0x48 /* tally counter for transmit status */ 5293746Sjulian#define MY_PHYBASE 0x4c 5393746Sjulian 5493746Sjulian/* 5593746Sjulian * Receive Configuration Register 5693746Sjulian */ 5793746Sjulian#define MY_RXRUN 0x00008000 /* receive running status */ 5893746Sjulian#define MY_EIEN 0x00004000 /* early interrupt enable */ 5993746Sjulian#define MY_RFCEN 0x00002000 /* receive flow control packet enable */ 6093746Sjulian#define MY_NDFA 0x00001000 /* not defined flow control address */ 6193746Sjulian#define MY_RBLEN 0x00000800 /* receive burst length enable */ 6293746Sjulian#define MY_RPBLE1 0x00000000 /* 1 word */ 6393746Sjulian#define MY_RPBLE4 0x00000100 /* 4 words */ 6493746Sjulian#define MY_RPBLE8 0x00000200 /* 8 words */ 6593746Sjulian#define MY_RPBLE16 0x00000300 /* 16 words */ 6693746Sjulian#define MY_RPBLE32 0x00000400 /* 32 words */ 6793746Sjulian#define MY_RPBLE64 0x00000500 /* 64 words */ 6893746Sjulian#define MY_RPBLE128 0x00000600 /* 128 words */ 6993746Sjulian#define MY_RPBLE512 0x00000700 /* 512 words */ 7093746Sjulian#define MY_PROM 0x000000080 /* promiscuous mode */ 7193746Sjulian#define MY_AB 0x000000040 /* accept broadcast */ 7293746Sjulian#define MY_AM 0x000000020 /* accept mutlicast */ 7393746Sjulian#define MY_ARP 0x000000008 /* receive runt pkt */ 7493746Sjulian#define MY_ALP 0x000000004 /* receive long pkt */ 7593746Sjulian#define MY_SEP 0x000000002 /* receive error pkt */ 7693746Sjulian#define MY_RE 0x000000001 /* receive enable */ 7793746Sjulian 7893746Sjulian/* 7993746Sjulian * Transmit Configuration Register 8093746Sjulian */ 8193746Sjulian#define MY_TXRUN 0x04000000 /* transmit running status */ 8293746Sjulian#define MY_Enhanced 0x02000000 /* transmit enhanced mode */ 8393746Sjulian#define MY_TFCEN 0x01000000 /* tx flow control packet enable */ 8493746Sjulian#define MY_TFT64 0x00000000 /* 64 bytes */ 8593746Sjulian#define MY_TFT32 0x00200000 /* 32 bytes */ 8693746Sjulian#define MY_TFT128 0x00400000 /* 128 bytes */ 8793746Sjulian#define MY_TFT256 0x00600000 /* 256 bytes */ 8893746Sjulian#define MY_TFT512 0x00800000 /* 512 bytes */ 8993746Sjulian#define MY_TFT768 0x00A00000 /* 768 bytes */ 9093746Sjulian#define MY_TFT1024 0x00C00000 /* 1024 bytes */ 9193746Sjulian#define MY_TFTSF 0x00E00000 /* store and forward */ 9293746Sjulian#define MY_FD 0x00100000 /* full duplex mode */ 9393746Sjulian#define MY_PS10 0x00080000 /* port speed is 10M */ 9493746Sjulian#define MY_TE 0x00040000 /* transmit enable */ 9593746Sjulian#define MY_PS1000 0x00010000 /* port speed is 1000M */ 9693746Sjulian/* 9793746Sjulian * Bus Command Register 9893746Sjulian */ 9993746Sjulian#define MY_PROG 0x00000200 /* programming */ 10093746Sjulian#define MY_RLE 0x00000100 /* read line command enable */ 10193746Sjulian#define MY_RME 0x00000080 /* read multiple command enable */ 10293746Sjulian#define MY_WIE 0x00000040 /* write and invalidate cmd enable */ 10393746Sjulian#define MY_PBL1 0x00000000 /* 1 dword */ 10493746Sjulian#define MY_PBL4 0x00000008 /* 4 dwords */ 10593746Sjulian#define MY_PBL8 0x00000010 /* 8 dwords */ 10693746Sjulian#define MY_PBL16 0x00000018 /* 16 dwords */ 10793746Sjulian#define MY_PBL32 0x00000020 /* 32 dwords */ 10893746Sjulian#define MY_PBL64 0x00000028 /* 64 dwords */ 10993746Sjulian#define MY_PBL128 0x00000030 /* 128 dwords */ 11093746Sjulian#define MY_PBL512 0x00000038 /* 512 dwords */ 11193746Sjulian#define MY_ABR 0x00000004 /* arbitration rule */ 11293746Sjulian#define MY_BLS 0x00000002 /* big/little endian select */ 11393746Sjulian#define MY_SWR 0x00000001 /* software reset */ 11493746Sjulian 11593746Sjulian/* 11693746Sjulian * Transmit Poll Demand Register 11793746Sjulian */ 11893746Sjulian#define MY_TxPollDemand 0x1 11993746Sjulian 12093746Sjulian/* 12193746Sjulian * Receive Poll Demand Register 12293746Sjulian */ 12393746Sjulian#define MY_RxPollDemand 0x01 12493746Sjulian 12593746Sjulian/* 12693746Sjulian * Interrupt Status Register 12793746Sjulian */ 12893746Sjulian#define MY_RFCON 0x00020000 /* receive flow control xon packet */ 12993746Sjulian#define MY_RFCOFF 0x00010000 /* receive flow control xoff packet */ 13093746Sjulian#define MY_LSCStatus 0x00008000 /* link status change */ 13193746Sjulian#define MY_ANCStatus 0x00004000 /* autonegotiation completed */ 13293746Sjulian#define MY_FBE 0x00002000 /* fatal bus error */ 13393746Sjulian#define MY_FBEMask 0x00001800 13493746Sjulian#define MY_ParityErr 0x00000000 /* parity error */ 13593746Sjulian#define MY_MasterErr 0x00000800 /* master error */ 13693746Sjulian#define MY_TargetErr 0x00001000 /* target abort */ 13793746Sjulian#define MY_TUNF 0x00000400 /* transmit underflow */ 13893746Sjulian#define MY_ROVF 0x00000200 /* receive overflow */ 13993746Sjulian#define MY_ETI 0x00000100 /* transmit early int */ 14093746Sjulian#define MY_ERI 0x00000080 /* receive early int */ 14193746Sjulian#define MY_CNTOVF 0x00000040 /* counter overflow */ 14293746Sjulian#define MY_RBU 0x00000020 /* receive buffer unavailable */ 14393746Sjulian#define MY_TBU 0x00000010 /* transmit buffer unavilable */ 14493746Sjulian#define MY_TI 0x00000008 /* transmit interrupt */ 14593746Sjulian#define MY_RI 0x00000004 /* receive interrupt */ 14693746Sjulian#define MY_RxErr 0x00000002 /* receive error */ 14793746Sjulian 14893746Sjulian/* 14993746Sjulian * Interrupt Mask Register 15093746Sjulian */ 15193746Sjulian#define MY_MRFCON 0x00020000 /* receive flow control xon packet */ 15293746Sjulian#define MY_MRFCOFF 0x00010000 /* receive flow control xoff packet */ 15393746Sjulian#define MY_MLSCStatus 0x00008000 /* link status change */ 15493746Sjulian#define MY_MANCStatus 0x00004000 /* autonegotiation completed */ 15593746Sjulian#define MY_MFBE 0x00002000 /* fatal bus error */ 15693746Sjulian#define MY_MFBEMask 0x00001800 15793746Sjulian#define MY_MTUNF 0x00000400 /* transmit underflow */ 15893746Sjulian#define MY_MROVF 0x00000200 /* receive overflow */ 15993746Sjulian#define MY_METI 0x00000100 /* transmit early int */ 16093746Sjulian#define MY_MERI 0x00000080 /* receive early int */ 16193746Sjulian#define MY_MCNTOVF 0x00000040 /* counter overflow */ 16293746Sjulian#define MY_MRBU 0x00000020 /* receive buffer unavailable */ 16393746Sjulian#define MY_MTBU 0x00000010 /* transmit buffer unavilable */ 16493746Sjulian#define MY_MTI 0x00000008 /* transmit interrupt */ 16593746Sjulian#define MY_MRI 0x00000004 /* receive interrupt */ 16693746Sjulian#define MY_MRxErr 0x00000002 /* receive error */ 16793746Sjulian 16893746Sjulian/* 90/1/18 delete */ 16993746Sjulian/* #define MY_INTRS MY_FBE|MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI */ 17093746Sjulian#define MY_INTRS MY_MRBU|MY_TBU|MY_MTI|MY_MRI|MY_METI 17193746Sjulian 17293746Sjulian/* 17393746Sjulian * Flow Control High/Low Threshold Register 17493746Sjulian */ 17593746Sjulian#define MY_FCHTShift 16 /* flow control high threshold */ 17693746Sjulian#define MY_FCLTShift 0 /* flow control low threshold */ 17793746Sjulian 17893746Sjulian/* 17993746Sjulian * BootROM/EEPROM/MII Management Register 18093746Sjulian */ 18193746Sjulian#define MY_MASK_MIIR_MII_READ 0x00000000 18293746Sjulian#define MY_MASK_MIIR_MII_WRITE 0x00000008 18393746Sjulian#define MY_MASK_MIIR_MII_MDO 0x00000004 18493746Sjulian#define MY_MASK_MIIR_MII_MDI 0x00000002 18593746Sjulian#define MY_MASK_MIIR_MII_MDC 0x00000001 18693746Sjulian 18793746Sjulian/* 18893746Sjulian * Tally Counter for CRC and MPA 18993746Sjulian */ 19093746Sjulian#define MY_TCOVF 0x80000000 /* crc tally counter overflow */ 19193746Sjulian#define MY_CRCMask 0x7fff0000 /* crc number: bit 16-30 */ 19293746Sjulian#define MY_CRCShift 16 19393746Sjulian#define MY_TMOVF 0x00008000 /* mpa tally counter overflow */ 19493746Sjulian#define MY_MPAMask 0x00007fff /* mpa number: bit 0-14 */ 19593746Sjulian#define MY_MPAShift 0 19693746Sjulian 19793746Sjulian/* 19893746Sjulian * Tally Counters for transmit status 19993746Sjulian */ 20093746Sjulian#define MY_AbortMask 0xff000000 /* transmit abort number */ 20193746Sjulian#define MY_AbortShift 24 20293746Sjulian#define MY_LColMask 0x00ff0000 /* transmit late collisions */ 20393746Sjulian#define MY_LColShift 16 20493746Sjulian#define MY_NCRMask 0x0000ffff /* transmit retry number */ 20593746Sjulian#define MY_NCRShift 0 20693746Sjulian 20793746Sjulian/* 20893746Sjulian * Myson TX/RX descriptor structure. 20993746Sjulian */ 21093746Sjulian 21193746Sjulianstruct my_desc { 21293746Sjulian u_int32_t my_status; 21393746Sjulian u_int32_t my_ctl; 21493746Sjulian u_int32_t my_data; 21593746Sjulian u_int32_t my_next; 21693746Sjulian}; 21793746Sjulian 21893746Sjulian/* 21993746Sjulian * for tx/rx descriptors 22093746Sjulian */ 22193746Sjulian#define MY_OWNByNIC 0x80000000 22293746Sjulian#define MY_OWNByDriver 0x0 22393746Sjulian 22493746Sjulian/* 22593746Sjulian * receive descriptor 0 22693746Sjulian */ 22793746Sjulian#define MY_RXOWN 0x80000000 /* own bit */ 22893746Sjulian#define MY_FLNGMASK 0x0fff0000 /* frame length */ 22993746Sjulian#define MY_FLNGShift 16 23093746Sjulian#define MY_MARSTATUS 0x00004000 /* multicast address received */ 23193746Sjulian#define MY_BARSTATUS 0x00002000 /* broadcast address received */ 23293746Sjulian#define MY_PHYSTATUS 0x00001000 /* physical address received */ 23393746Sjulian#define MY_RXFSD 0x00000800 /* first descriptor */ 23493746Sjulian#define MY_RXLSD 0x00000400 /* last descriptor */ 23593746Sjulian#define MY_ES 0x00000080 /* error summary */ 23693746Sjulian#define MY_RUNT 0x00000040 /* runt packet received */ 23793746Sjulian#define MY_LONG 0x00000020 /* long packet received */ 23893746Sjulian#define MY_FAE 0x00000010 /* frame align error */ 23993746Sjulian#define MY_CRC 0x00000008 /* crc error */ 24093746Sjulian#define MY_RXER 0x00000004 /* receive error */ 24193746Sjulian#define MY_RDES0CHECK 0x000078fc /* only check MAR, BAR, PHY, ES, RUNT, 24293746Sjulian LONG, FAE, CRC and RXER bits */ 24393746Sjulian 24493746Sjulian/* 24593746Sjulian * receive descriptor 1 24693746Sjulian */ 24793746Sjulian#define MY_RXIC 0x00800000 /* interrupt control */ 24893746Sjulian#define MY_RBSMASK 0x000007ff /* receive buffer size */ 24993746Sjulian#define MY_RBSShift 0 25093746Sjulian 25193746Sjulian/* 25293746Sjulian * transmit descriptor 0 25393746Sjulian */ 25493746Sjulian#define MY_TXERR 0x00008000 /* transmit error */ 25593746Sjulian#define MY_JABTO 0x00004000 /* jabber timeout */ 25693746Sjulian#define MY_CSL 0x00002000 /* carrier sense lost */ 25793746Sjulian#define MY_LC 0x00001000 /* late collision */ 25893746Sjulian#define MY_EC 0x00000800 /* excessive collision */ 25993746Sjulian#define MY_UDF 0x00000400 /* fifo underflow */ 26093746Sjulian#define MY_DFR 0x00000200 /* deferred */ 26193746Sjulian#define MY_HF 0x00000100 /* heartbeat fail */ 26293746Sjulian#define MY_NCRMASK 0x000000ff /* collision retry count */ 26393746Sjulian#define MY_NCRShift 0 26493746Sjulian 26593746Sjulian/* 26693746Sjulian * tx descriptor 1 26793746Sjulian */ 26893746Sjulian#define MY_TXIC 0x80000000 /* interrupt control */ 26993746Sjulian#define MY_ETIControl 0x40000000 /* early transmit interrupt */ 27093746Sjulian#define MY_TXLD 0x20000000 /* last descriptor */ 27193746Sjulian#define MY_TXFD 0x10000000 /* first descriptor */ 27293746Sjulian#define MY_CRCDisable 0x00000000 /* crc control */ 27393746Sjulian#define MY_CRCEnable 0x08000000 27493746Sjulian#define MY_PADDisable 0x00000000 /* padding control */ 27593746Sjulian#define MY_PADEnable 0x04000000 27693746Sjulian#define MY_RetryTxLC 0x02000000 /* retry late collision */ 27793746Sjulian#define MY_PKTShift 11 /* transmit pkt size */ 27893746Sjulian#define MY_TBSMASK 0x000007ff 27993746Sjulian#define MY_TBSShift 0 /* transmit buffer size */ 28093746Sjulian 28193746Sjulian#define MY_MAXFRAGS 1 28293746Sjulian#define MY_RX_LIST_CNT 64 28393746Sjulian#define MY_TX_LIST_CNT 64 28493746Sjulian#define MY_MIN_FRAMELEN 60 28593746Sjulian 28693746Sjulian/* 28793746Sjulian * A transmit 'super descriptor' is actually MY_MAXFRAGS regular 28893746Sjulian * descriptors clumped together. The idea here is to emulate the 28993746Sjulian * multi-fragment descriptor layout found in devices such as the 29093746Sjulian * Texas Instruments ThunderLAN and 3Com boomerang and cylone chips. 29193746Sjulian * The advantage to using this scheme is that it avoids buffer copies. 29293746Sjulian * The disadvantage is that there's a certain amount of overhead due 29393746Sjulian * to the fact that each 'fragment' is 16 bytes long. In my tests, 29493746Sjulian * this limits top speed to about 10.5MB/sec. It should be more like 29593746Sjulian * 11.5MB/sec. However, the upshot is that you can achieve better 29693746Sjulian * results on slower machines: a Pentium 200 can pump out packets at 29793746Sjulian * same speed as a PII 400. 29893746Sjulian */ 29993746Sjulianstruct my_txdesc { 30093746Sjulian struct my_desc my_frag[MY_MAXFRAGS]; 30193746Sjulian}; 30293746Sjulian 30393746Sjulian#define MY_TXSTATUS(x) x->my_ptr->my_frag[x->my_lastdesc].my_status 30493746Sjulian#define MY_TXCTL(x) x->my_ptr->my_frag[x->my_lastdesc].my_ctl 30593746Sjulian#define MY_TXDATA(x) x->my_ptr->my_frag[x->my_lastdesc].my_data 30693746Sjulian#define MY_TXNEXT(x) x->my_ptr->my_frag[x->my_lastdesc].my_next 30793746Sjulian 30893746Sjulian#define MY_TXOWN(x) x->my_ptr->my_frag[0].my_status 30993746Sjulian 31093746Sjulian#define MY_UNSENT 0x1234 31193746Sjulian 31293746Sjulianstruct my_list_data { 31393746Sjulian struct my_desc my_rx_list[MY_RX_LIST_CNT]; 31493746Sjulian struct my_txdesc my_tx_list[MY_TX_LIST_CNT]; 31593746Sjulian}; 31693746Sjulian 31793746Sjulianstruct my_chain { 31893746Sjulian struct my_txdesc *my_ptr; 31993746Sjulian struct mbuf *my_mbuf; 32093746Sjulian struct my_chain *my_nextdesc; 32193746Sjulian u_int8_t my_lastdesc; 32293746Sjulian}; 32393746Sjulian 32493746Sjulianstruct my_chain_onefrag { 32593746Sjulian struct my_desc *my_ptr; 32693746Sjulian struct mbuf *my_mbuf; 32793746Sjulian struct my_chain_onefrag *my_nextdesc; 32893746Sjulian u_int8_t my_rlast; 32993746Sjulian}; 33093746Sjulian 33193746Sjulianstruct my_chain_data { 33293746Sjulian struct my_chain_onefrag my_rx_chain[MY_RX_LIST_CNT]; 33393746Sjulian struct my_chain my_tx_chain[MY_TX_LIST_CNT]; 33493746Sjulian 33593746Sjulian struct my_chain_onefrag *my_rx_head; 33693746Sjulian 33793746Sjulian struct my_chain *my_tx_head; 33893746Sjulian struct my_chain *my_tx_tail; 33993746Sjulian struct my_chain *my_tx_free; 34093746Sjulian}; 34193746Sjulian 34293746Sjulianstruct my_type { 34393746Sjulian u_int16_t my_vid; 34493746Sjulian u_int16_t my_did; 34593746Sjulian char *my_name; 34693746Sjulian}; 34793746Sjulian 34893746Sjulian#define MY_FLAG_FORCEDELAY 1 34993746Sjulian#define MY_FLAG_SCHEDDELAY 2 35093746Sjulian#define MY_FLAG_DELAYTIMEO 3 35193746Sjulian 35293746Sjulianstruct my_softc { 353147256Sbrooks struct ifnet *my_ifp; 354162321Sglebius device_t my_dev; 35593746Sjulian struct ifmedia ifmedia; /* media info */ 35693746Sjulian bus_space_handle_t my_bhandle; 35793746Sjulian bus_space_tag_t my_btag; 35893746Sjulian struct my_type *my_info; /* adapter info */ 35993746Sjulian struct my_type *my_pinfo; /* phy info */ 36093746Sjulian struct resource *my_res; 36193746Sjulian struct resource *my_irq; 36293746Sjulian void *my_intrhand; 36393746Sjulian u_int8_t my_phy_addr; /* PHY address */ 36493746Sjulian u_int8_t my_tx_pend; /* TX pending */ 36593746Sjulian u_int8_t my_want_auto; 36693746Sjulian u_int8_t my_autoneg; 36793746Sjulian u_int16_t my_txthresh; 36893746Sjulian u_int8_t my_stats_no_timeout; 36993746Sjulian caddr_t my_ldata_ptr; 37093746Sjulian struct my_list_data *my_ldata; 37193746Sjulian struct my_chain_data my_cdata; 37293746Sjulian device_t my_miibus; 37393746Sjulian/* Add by Surfer 2001/12/2 */ 374199540Sjhb struct mtx my_mtx; 375199540Sjhb struct callout my_autoneg_timer; 376199540Sjhb struct callout my_watchdog; 377199540Sjhb int my_timer; 37893746Sjulian}; 37993746Sjulian 38093746Sjulian/* Add by Surfer 2001/12/2 */ 38193746Sjulian#define MY_LOCK(_sc) mtx_lock(&(_sc)->my_mtx) 38293746Sjulian#define MY_UNLOCK(_sc) mtx_unlock(&(_sc)->my_mtx) 383149151Sjhb#define MY_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->my_mtx, MA_OWNED) 38493746Sjulian 38593746Sjulian/* 38693746Sjulian * register space access macros 38793746Sjulian */ 38893746Sjulian#define CSR_WRITE_4(sc, reg, val) \ 38993746Sjulian bus_space_write_4(sc->my_btag, sc->my_bhandle, reg, val) 39093746Sjulian#define CSR_WRITE_2(sc, reg, val) \ 39193746Sjulian bus_space_write_2(sc->my_btag, sc->my_bhandle, reg, val) 39293746Sjulian#define CSR_WRITE_1(sc, reg, val) \ 39393746Sjulian bus_space_write_1(sc->my_btag, sc->my_bhandle, reg, val) 39493746Sjulian 39593746Sjulian#define CSR_READ_4(sc, reg) \ 39693746Sjulian bus_space_read_4(sc->my_btag, sc->my_bhandle, reg) 39793746Sjulian#define CSR_READ_2(sc, reg) \ 39893746Sjulian bus_space_read_2(sc->my_btag, sc->my_bhandle, reg) 39993746Sjulian#define CSR_READ_1(sc, reg) \ 40093746Sjulian bus_space_read_1(sc->my_btag, sc->my_bhandle, reg) 40193746Sjulian 40293746Sjulian#define MY_TIMEOUT 1000 40393746Sjulian 40493746Sjulian/* 40593746Sjulian * General constants that are fun to know. 40693746Sjulian * 40793746Sjulian * MYSON PCI vendor ID 40893746Sjulian */ 40993746Sjulian#define MYSONVENDORID 0x1516 41093746Sjulian 41193746Sjulian/* 41293746Sjulian * MYSON device IDs. 41393746Sjulian */ 41493746Sjulian#define MTD800ID 0x0800 41593746Sjulian#define MTD803ID 0x0803 41693746Sjulian#define MTD891ID 0x0891 41793746Sjulian 41893746Sjulian/* 41993746Sjulian * ST+OP+PHYAD+REGAD+TA 42093746Sjulian */ 42193746Sjulian#define MY_OP_READ 0x6000 /* ST:01+OP:10+PHYAD+REGAD+TA:Z0 */ 42293746Sjulian#define MY_OP_WRITE 0x5002 /* ST:01+OP:01+PHYAD+REGAD+TA:10 */ 42393746Sjulian 42493746Sjulian/* 42593746Sjulian * Constansts for Myson PHY 42693746Sjulian */ 42793746Sjulian#define MysonPHYID0 0x0300 42893746Sjulian 42993746Sjulian/* 43093746Sjulian * Constansts for Seeq 80225 PHY 43193746Sjulian */ 43293746Sjulian#define SeeqPHYID0 0x0016 43393746Sjulian 43493746Sjulian#define SEEQ_MIIRegister18 18 43593746Sjulian#define SEEQ_SPD_DET_100 0x80 43693746Sjulian#define SEEQ_DPLX_DET_FULL 0x40 43793746Sjulian 43893746Sjulian/* 43993746Sjulian * Constansts for Ahdoc 101 PHY 44093746Sjulian */ 44193746Sjulian#define AhdocPHYID0 0x0022 44293746Sjulian 44393746Sjulian#define AHDOC_DiagnosticReg 18 44493746Sjulian#define AHDOC_DPLX_FULL 0x0800 44593746Sjulian#define AHDOC_Speed_100 0x0400 44693746Sjulian 44793746Sjulian/* 44893746Sjulian * Constansts for Marvell 88E1000/88E1000S PHY and LevelOne PHY 44993746Sjulian */ 45093746Sjulian#define MarvellPHYID0 0x0141 45193746Sjulian#define LevelOnePHYID0 0x0013 45293746Sjulian 45393746Sjulian#define Marvell_SpecificStatus 17 45493746Sjulian#define Marvell_Speed1000 0x8000 45593746Sjulian#define Marvell_Speed100 0x4000 45693746Sjulian#define Marvell_FullDuplex 0x2000 45793746Sjulian 45893746Sjulian/* 45993746Sjulian * PCI low memory base and low I/O base register, and 46093746Sjulian * other PCI registers. Note: some are only available on 46193746Sjulian * the 3c905B, in particular those that related to power management. 46293746Sjulian */ 46393746Sjulian#define MY_PCI_VENDOR_ID 0x00 46493746Sjulian#define MY_PCI_DEVICE_ID 0x02 46593746Sjulian#define MY_PCI_COMMAND 0x04 46693746Sjulian#define MY_PCI_STATUS 0x06 46793746Sjulian#define MY_PCI_CLASSCODE 0x09 46893746Sjulian#define MY_PCI_LATENCY_TIMER 0x0D 46993746Sjulian#define MY_PCI_HEADER_TYPE 0x0E 47093746Sjulian#define MY_PCI_LOIO 0x10 47193746Sjulian#define MY_PCI_LOMEM 0x14 47293746Sjulian#define MY_PCI_BIOSROM 0x30 47393746Sjulian#define MY_PCI_INTLINE 0x3C 47493746Sjulian#define MY_PCI_INTPIN 0x3D 47593746Sjulian#define MY_PCI_MINGNT 0x3E 47693746Sjulian#define MY_PCI_MINLAT 0x0F 47793746Sjulian#define MY_PCI_RESETOPT 0x48 47893746Sjulian#define MY_PCI_EEPROM_DATA 0x4C 47993746Sjulian 48093746Sjulian#define PHY_UNKNOWN 3 48193746Sjulian 48293746Sjulian#define MY_PHYADDR_MIN 0x00 48393746Sjulian#define MY_PHYADDR_MAX 0x1F 48493746Sjulian 48593746Sjulian#define PHY_BMCR 0x00 48693746Sjulian#define PHY_BMSR 0x01 48793746Sjulian#define PHY_VENID 0x02 48893746Sjulian#define PHY_DEVID 0x03 48993746Sjulian#define PHY_ANAR 0x04 49093746Sjulian#define PHY_LPAR 0x05 49193746Sjulian#define PHY_ANEXP 0x06 49293746Sjulian#define PHY_NPTR 0x07 49393746Sjulian#define PHY_LPNPR 0x08 49493746Sjulian#define PHY_1000CR 0x09 49593746Sjulian#define PHY_1000SR 0x0a 49693746Sjulian 49793746Sjulian#define PHY_ANAR_NEXTPAGE 0x8000 49893746Sjulian#define PHY_ANAR_RSVD0 0x4000 49993746Sjulian#define PHY_ANAR_TLRFLT 0x2000 50093746Sjulian#define PHY_ANAR_RSVD1 0x1000 50193746Sjulian#define PHY_ANAR_RSVD2 0x0800 50293746Sjulian#define PHY_ANAR_RSVD3 0x0400 50393746Sjulian#define PHY_ANAR_100BT4 0x0200L 50493746Sjulian#define PHY_ANAR_100BTXFULL 0x0100 50593746Sjulian#define PHY_ANAR_100BTXHALF 0x0080 50693746Sjulian#define PHY_ANAR_10BTFULL 0x0040 50793746Sjulian#define PHY_ANAR_10BTHALF 0x0020 50893746Sjulian#define PHY_ANAR_PROTO4 0x0010 50993746Sjulian#define PHY_ANAR_PROTO3 0x0008 51093746Sjulian#define PHY_ANAR_PROTO2 0x0004 51193746Sjulian#define PHY_ANAR_PROTO1 0x0002 51293746Sjulian#define PHY_ANAR_PROTO0 0x0001 51393746Sjulian 51493746Sjulian#define PHY_1000SR_1000BTXFULL 0x0800 51593746Sjulian#define PHY_1000SR_1000BTXHALF 0x0400 51693746Sjulian 51793746Sjulian/* 51893746Sjulian * These are the register definitions for the PHY (physical layer 51993746Sjulian * interface chip). 52093746Sjulian */ 52193746Sjulian/* 52293746Sjulian * PHY BMCR Basic Mode Control Register 52393746Sjulian */ 52493746Sjulian#define PHY_BMCR_RESET 0x8000 52593746Sjulian#define PHY_BMCR_LOOPBK 0x4000 52693746Sjulian#define PHY_BMCR_SPEEDSEL 0x2000 52793746Sjulian#define PHY_BMCR_AUTONEGENBL 0x1000 52893746Sjulian#define PHY_BMCR_RSVD0 0x0800 /* write as zero */ 52993746Sjulian#define PHY_BMCR_ISOLATE 0x0400 53093746Sjulian#define PHY_BMCR_AUTONEGRSTR 0x0200 53193746Sjulian#define PHY_BMCR_DUPLEX 0x0100 53293746Sjulian#define PHY_BMCR_COLLTEST 0x0080 53393746Sjulian#define PHY_BMCR_1000 0x0040 /* only used for Marvell PHY */ 53493746Sjulian#define PHY_BMCR_RSVD2 0x0020 /* write as zero, don't care */ 53593746Sjulian#define PHY_BMCR_RSVD3 0x0010 /* write as zero, don't care */ 53693746Sjulian#define PHY_BMCR_RSVD4 0x0008 /* write as zero, don't care */ 53793746Sjulian#define PHY_BMCR_RSVD5 0x0004 /* write as zero, don't care */ 53893746Sjulian#define PHY_BMCR_RSVD6 0x0002 /* write as zero, don't care */ 53993746Sjulian#define PHY_BMCR_RSVD7 0x0001 /* write as zero, don't care */ 54093746Sjulian 54193746Sjulian/* 54293746Sjulian * RESET: 1 == software reset, 0 == normal operation 54393746Sjulian * Resets status and control registers to default values. 54493746Sjulian * Relatches all hardware config values. 54593746Sjulian * 54693746Sjulian * LOOPBK: 1 == loopback operation enabled, 0 == normal operation 54793746Sjulian * 54893746Sjulian * SPEEDSEL: 1 == 100Mb/s, 0 == 10Mb/s 54993746Sjulian * Link speed is selected byt his bit or if auto-negotiation if bit 55093746Sjulian * 12 (AUTONEGENBL) is set (in which case the value of this register 55193746Sjulian * is ignored). 55293746Sjulian * 55393746Sjulian * AUTONEGENBL: 1 == Autonegotiation enabled, 0 == Autonegotiation disabled 55493746Sjulian * Bits 8 and 13 are ignored when autoneg is set, otherwise bits 8 and 13 55593746Sjulian * determine speed and mode. Should be cleared and then set if PHY configured 55693746Sjulian * for no autoneg on startup. 55793746Sjulian * 55893746Sjulian * ISOLATE: 1 == isolate PHY from MII, 0 == normal operation 55993746Sjulian * 56093746Sjulian * AUTONEGRSTR: 1 == restart autonegotiation, 0 = normal operation 56193746Sjulian * 56293746Sjulian * DUPLEX: 1 == full duplex mode, 0 == half duplex mode 56393746Sjulian * 56493746Sjulian * COLLTEST: 1 == collision test enabled, 0 == normal operation 56593746Sjulian */ 56693746Sjulian 56793746Sjulian/* 56893746Sjulian * PHY, BMSR Basic Mode Status Register 56993746Sjulian */ 57093746Sjulian#define PHY_BMSR_100BT4 0x8000 57193746Sjulian#define PHY_BMSR_100BTXFULL 0x4000 57293746Sjulian#define PHY_BMSR_100BTXHALF 0x2000 57393746Sjulian#define PHY_BMSR_10BTFULL 0x1000 57493746Sjulian#define PHY_BMSR_10BTHALF 0x0800 57593746Sjulian#define PHY_BMSR_RSVD1 0x0400 /* write as zero, don't care */ 57693746Sjulian#define PHY_BMSR_RSVD2 0x0200 /* write as zero, don't care */ 57793746Sjulian#define PHY_BMSR_RSVD3 0x0100 /* write as zero, don't care */ 57893746Sjulian#define PHY_BMSR_RSVD4 0x0080 /* write as zero, don't care */ 57993746Sjulian#define PHY_BMSR_MFPRESUP 0x0040 58093746Sjulian#define PHY_BMSR_AUTONEGCOMP 0x0020 58193746Sjulian#define PHY_BMSR_REMFAULT 0x0010 58293746Sjulian#define PHY_BMSR_CANAUTONEG 0x0008 58393746Sjulian#define PHY_BMSR_LINKSTAT 0x0004 58493746Sjulian#define PHY_BMSR_JABBER 0x0002 58593746Sjulian#define PHY_BMSR_EXTENDED 0x0001 58693746Sjulian 58793746Sjulian 588