1290650Shselasky/*- 2290650Shselasky * Copyright (c) 2013-2015, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/10/sys/dev/mlx5/qp.h 356074 2019-12-25 09:34:16Z hselasky $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_QP_H 29290650Shselasky#define MLX5_QP_H 30290650Shselasky 31290650Shselasky#include <dev/mlx5/device.h> 32290650Shselasky#include <dev/mlx5/driver.h> 33290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 34290650Shselasky 35290650Shselasky#define MLX5_INVALID_LKEY 0x100 36290650Shselasky#define MLX5_SIG_WQE_SIZE (MLX5_SEND_WQE_BB * 5) 37290650Shselasky#define MLX5_DIF_SIZE 8 38290650Shselasky#define MLX5_STRIDE_BLOCK_OP 0x400 39290650Shselasky#define MLX5_CPY_GRD_MASK 0xc0 40290650Shselasky#define MLX5_CPY_APP_MASK 0x30 41290650Shselasky#define MLX5_CPY_REF_MASK 0x0f 42290650Shselasky#define MLX5_BSF_INC_REFTAG (1 << 6) 43290650Shselasky#define MLX5_BSF_INL_VALID (1 << 15) 44290650Shselasky#define MLX5_BSF_REFRESH_DIF (1 << 14) 45290650Shselasky#define MLX5_BSF_REPEAT_BLOCK (1 << 7) 46290650Shselasky#define MLX5_BSF_APPTAG_ESCAPE 0x1 47290650Shselasky#define MLX5_BSF_APPREF_ESCAPE 0x2 48290650Shselasky 49290650Shselaskyenum mlx5_qp_optpar { 50290650Shselasky MLX5_QP_OPTPAR_ALT_ADDR_PATH = 1 << 0, 51290650Shselasky MLX5_QP_OPTPAR_RRE = 1 << 1, 52290650Shselasky MLX5_QP_OPTPAR_RAE = 1 << 2, 53290650Shselasky MLX5_QP_OPTPAR_RWE = 1 << 3, 54290650Shselasky MLX5_QP_OPTPAR_PKEY_INDEX = 1 << 4, 55290650Shselasky MLX5_QP_OPTPAR_Q_KEY = 1 << 5, 56290650Shselasky MLX5_QP_OPTPAR_RNR_TIMEOUT = 1 << 6, 57290650Shselasky MLX5_QP_OPTPAR_PRIMARY_ADDR_PATH = 1 << 7, 58290650Shselasky MLX5_QP_OPTPAR_SRA_MAX = 1 << 8, 59290650Shselasky MLX5_QP_OPTPAR_RRA_MAX = 1 << 9, 60290650Shselasky MLX5_QP_OPTPAR_PM_STATE = 1 << 10, 61290650Shselasky MLX5_QP_OPTPAR_RETRY_COUNT = 1 << 12, 62290650Shselasky MLX5_QP_OPTPAR_RNR_RETRY = 1 << 13, 63290650Shselasky MLX5_QP_OPTPAR_ACK_TIMEOUT = 1 << 14, 64290650Shselasky MLX5_QP_OPTPAR_PRI_PORT = 1 << 16, 65290650Shselasky MLX5_QP_OPTPAR_SRQN = 1 << 18, 66290650Shselasky MLX5_QP_OPTPAR_CQN_RCV = 1 << 19, 67290650Shselasky MLX5_QP_OPTPAR_DC_HS = 1 << 20, 68290650Shselasky MLX5_QP_OPTPAR_DC_KEY = 1 << 21, 69290650Shselasky}; 70290650Shselasky 71290650Shselaskyenum mlx5_qp_state { 72290650Shselasky MLX5_QP_STATE_RST = 0, 73290650Shselasky MLX5_QP_STATE_INIT = 1, 74290650Shselasky MLX5_QP_STATE_RTR = 2, 75290650Shselasky MLX5_QP_STATE_RTS = 3, 76290650Shselasky MLX5_QP_STATE_SQER = 4, 77290650Shselasky MLX5_QP_STATE_SQD = 5, 78290650Shselasky MLX5_QP_STATE_ERR = 6, 79290650Shselasky MLX5_QP_STATE_SQ_DRAINING = 7, 80290650Shselasky MLX5_QP_STATE_SUSPENDED = 9, 81290650Shselasky MLX5_QP_NUM_STATE 82290650Shselasky}; 83290650Shselasky 84290650Shselaskyenum { 85290650Shselasky MLX5_QP_ST_RC = 0x0, 86290650Shselasky MLX5_QP_ST_UC = 0x1, 87290650Shselasky MLX5_QP_ST_UD = 0x2, 88290650Shselasky MLX5_QP_ST_XRC = 0x3, 89290650Shselasky MLX5_QP_ST_MLX = 0x4, 90290650Shselasky MLX5_QP_ST_DCI = 0x5, 91290650Shselasky MLX5_QP_ST_DCT = 0x6, 92290650Shselasky MLX5_QP_ST_QP0 = 0x7, 93290650Shselasky MLX5_QP_ST_QP1 = 0x8, 94290650Shselasky MLX5_QP_ST_RAW_ETHERTYPE = 0x9, 95290650Shselasky MLX5_QP_ST_RAW_IPV6 = 0xa, 96290650Shselasky MLX5_QP_ST_SNIFFER = 0xb, 97290650Shselasky MLX5_QP_ST_SYNC_UMR = 0xe, 98290650Shselasky MLX5_QP_ST_PTP_1588 = 0xd, 99290650Shselasky MLX5_QP_ST_REG_UMR = 0xc, 100306244Shselasky MLX5_QP_ST_SW_CNAK = 0x10, 101290650Shselasky MLX5_QP_ST_MAX 102290650Shselasky}; 103290650Shselasky 104290650Shselaskyenum { 105290650Shselasky MLX5_NON_ZERO_RQ = 0 << 24, 106290650Shselasky MLX5_SRQ_RQ = 1 << 24, 107290650Shselasky MLX5_CRQ_RQ = 2 << 24, 108290650Shselasky MLX5_ZERO_LEN_RQ = 3 << 24 109290650Shselasky}; 110290650Shselasky 111290650Shselaskyenum { 112290650Shselasky /* params1 */ 113290650Shselasky MLX5_QP_BIT_SRE = 1 << 15, 114290650Shselasky MLX5_QP_BIT_SWE = 1 << 14, 115290650Shselasky MLX5_QP_BIT_SAE = 1 << 13, 116290650Shselasky /* params2 */ 117290650Shselasky MLX5_QP_BIT_RRE = 1 << 15, 118290650Shselasky MLX5_QP_BIT_RWE = 1 << 14, 119290650Shselasky MLX5_QP_BIT_RAE = 1 << 13, 120290650Shselasky MLX5_QP_BIT_RIC = 1 << 4, 121306244Shselasky MLX5_QP_BIT_COLL_SYNC_RQ = 1 << 2, 122306244Shselasky MLX5_QP_BIT_COLL_SYNC_SQ = 1 << 1, 123306244Shselasky MLX5_QP_BIT_COLL_MASTER = 1 << 0 124290650Shselasky}; 125290650Shselasky 126290650Shselaskyenum { 127306244Shselasky MLX5_DCT_BIT_RRE = 1 << 19, 128306244Shselasky MLX5_DCT_BIT_RWE = 1 << 18, 129306244Shselasky MLX5_DCT_BIT_RAE = 1 << 17, 130306244Shselasky}; 131306244Shselasky 132306244Shselaskyenum { 133290650Shselasky MLX5_WQE_CTRL_CQ_UPDATE = 2 << 2, 134290650Shselasky MLX5_WQE_CTRL_CQ_UPDATE_AND_EQE = 3 << 2, 135290650Shselasky MLX5_WQE_CTRL_SOLICITED = 1 << 1, 136290650Shselasky}; 137290650Shselasky 138356074Shselasky#define MLX5_SEND_WQE_DS 16 139356074Shselasky#define MLX5_SEND_WQE_BB 64 140290650Shselasky#define MLX5_SEND_WQEBB_NUM_DS (MLX5_SEND_WQE_BB / MLX5_SEND_WQE_DS) 141290650Shselasky 142290650Shselaskyenum { 143290650Shselasky MLX5_SEND_WQE_MAX_WQEBBS = 16, 144290650Shselasky}; 145290650Shselasky 146290650Shselaskyenum { 147290650Shselasky MLX5_WQE_FMR_PERM_LOCAL_READ = 1 << 27, 148290650Shselasky MLX5_WQE_FMR_PERM_LOCAL_WRITE = 1 << 28, 149290650Shselasky MLX5_WQE_FMR_PERM_REMOTE_READ = 1 << 29, 150290650Shselasky MLX5_WQE_FMR_PERM_REMOTE_WRITE = 1 << 30, 151290650Shselasky MLX5_WQE_FMR_PERM_ATOMIC = 1 << 31 152290650Shselasky}; 153290650Shselasky 154290650Shselaskyenum { 155290650Shselasky MLX5_FENCE_MODE_NONE = 0 << 5, 156290650Shselasky MLX5_FENCE_MODE_INITIATOR_SMALL = 1 << 5, 157290650Shselasky MLX5_FENCE_MODE_STRONG_ORDERING = 3 << 5, 158290650Shselasky MLX5_FENCE_MODE_SMALL_AND_FENCE = 4 << 5, 159290650Shselasky}; 160290650Shselasky 161290650Shselaskyenum { 162306244Shselasky MLX5_QP_DRAIN_SIGERR = 1 << 26, 163290650Shselasky MLX5_QP_LAT_SENSITIVE = 1 << 28, 164290650Shselasky MLX5_QP_BLOCK_MCAST = 1 << 30, 165290650Shselasky MLX5_QP_ENABLE_SIG = 1 << 31, 166290650Shselasky}; 167290650Shselasky 168290650Shselaskyenum { 169290650Shselasky MLX5_RCV_DBR = 0, 170290650Shselasky MLX5_SND_DBR = 1, 171290650Shselasky}; 172290650Shselasky 173290650Shselaskyenum { 174290650Shselasky MLX5_FLAGS_INLINE = 1<<7, 175290650Shselasky MLX5_FLAGS_CHECK_FREE = 1<<5, 176290650Shselasky}; 177290650Shselasky 178290650Shselaskystruct mlx5_wqe_fmr_seg { 179290650Shselasky __be32 flags; 180290650Shselasky __be32 mem_key; 181290650Shselasky __be64 buf_list; 182290650Shselasky __be64 start_addr; 183290650Shselasky __be64 reg_len; 184290650Shselasky __be32 offset; 185290650Shselasky __be32 page_size; 186290650Shselasky u32 reserved[2]; 187290650Shselasky}; 188290650Shselasky 189290650Shselaskystruct mlx5_wqe_ctrl_seg { 190290650Shselasky __be32 opmod_idx_opcode; 191290650Shselasky __be32 qpn_ds; 192290650Shselasky u8 signature; 193290650Shselasky u8 rsvd[2]; 194290650Shselasky u8 fm_ce_se; 195290650Shselasky __be32 imm; 196290650Shselasky}; 197290650Shselasky 198290650Shselaskyenum { 199306244Shselasky MLX5_MLX_FLAG_MASK_VL15 = 0x40, 200306244Shselasky MLX5_MLX_FLAG_MASK_SLR = 0x20, 201306244Shselasky MLX5_MLX_FLAG_MASK_ICRC = 0x8, 202306244Shselasky MLX5_MLX_FLAG_MASK_FL = 4 203306244Shselasky}; 204306244Shselasky 205306244Shselaskystruct mlx5_mlx_seg { 206306244Shselasky __be32 rsvd0; 207306244Shselasky u8 flags; 208306244Shselasky u8 stat_rate_sl; 209306244Shselasky u8 rsvd1[8]; 210306244Shselasky __be16 dlid; 211306244Shselasky}; 212306244Shselasky 213306244Shselaskyenum { 214290650Shselasky MLX5_ETH_WQE_L3_INNER_CSUM = 1 << 4, 215290650Shselasky MLX5_ETH_WQE_L4_INNER_CSUM = 1 << 5, 216290650Shselasky MLX5_ETH_WQE_L3_CSUM = 1 << 6, 217290650Shselasky MLX5_ETH_WQE_L4_CSUM = 1 << 7, 218290650Shselasky}; 219290650Shselasky 220308684Shselaskyenum { 221308684Shselasky MLX5_ETH_WQE_SWP_OUTER_L3_TYPE = 1 << 0, 222308684Shselasky MLX5_ETH_WQE_SWP_OUTER_L4_TYPE = 1 << 1, 223308684Shselasky MLX5_ETH_WQE_SWP_INNER_L3_TYPE = 1 << 4, 224308684Shselasky MLX5_ETH_WQE_SWP_INNER_L4_TYPE = 1 << 5, 225308684Shselasky}; 226308684Shselasky 227290650Shselaskystruct mlx5_wqe_eth_seg { 228308684Shselasky u8 swp_outer_l4_offset; 229308684Shselasky u8 swp_outer_l3_offset; 230308684Shselasky u8 swp_inner_l4_offset; 231308684Shselasky u8 swp_inner_l3_offset; 232290650Shselasky u8 cs_flags; 233308684Shselasky u8 swp_flags; 234290650Shselasky __be16 mss; 235290650Shselasky __be32 rsvd2; 236337742Shselasky union { 237337742Shselasky struct { 238337742Shselasky __be16 inline_hdr_sz; 239337742Shselasky u8 inline_hdr_start[2]; 240337742Shselasky }; 241337742Shselasky struct { 242337742Shselasky __be16 vlan_cmd; 243337742Shselasky __be16 vlan_hdr; 244337742Shselasky }; 245337742Shselasky }; 246290650Shselasky}; 247290650Shselasky 248290650Shselaskystruct mlx5_wqe_xrc_seg { 249290650Shselasky __be32 xrc_srqn; 250290650Shselasky u8 rsvd[12]; 251290650Shselasky}; 252290650Shselasky 253290650Shselaskystruct mlx5_wqe_masked_atomic_seg { 254290650Shselasky __be64 swap_add; 255290650Shselasky __be64 compare; 256290650Shselasky __be64 swap_add_mask; 257290650Shselasky __be64 compare_mask; 258290650Shselasky}; 259290650Shselasky 260290650Shselaskystruct mlx5_av { 261290650Shselasky union { 262290650Shselasky struct { 263290650Shselasky __be32 qkey; 264290650Shselasky __be32 reserved; 265290650Shselasky } qkey; 266290650Shselasky __be64 dc_key; 267290650Shselasky } key; 268290650Shselasky __be32 dqp_dct; 269290650Shselasky u8 stat_rate_sl; 270290650Shselasky u8 fl_mlid; 271290650Shselasky union { 272290650Shselasky __be16 rlid; 273290650Shselasky __be16 udp_sport; 274290650Shselasky }; 275290650Shselasky u8 reserved0[4]; 276290650Shselasky u8 rmac[6]; 277290650Shselasky u8 tclass; 278290650Shselasky u8 hop_limit; 279290650Shselasky __be32 grh_gid_fl; 280290650Shselasky u8 rgid[16]; 281290650Shselasky}; 282290650Shselasky 283290650Shselaskystruct mlx5_wqe_datagram_seg { 284290650Shselasky struct mlx5_av av; 285290650Shselasky}; 286290650Shselasky 287290650Shselaskystruct mlx5_wqe_raddr_seg { 288290650Shselasky __be64 raddr; 289290650Shselasky __be32 rkey; 290290650Shselasky u32 reserved; 291290650Shselasky}; 292290650Shselasky 293290650Shselaskystruct mlx5_wqe_atomic_seg { 294290650Shselasky __be64 swap_add; 295290650Shselasky __be64 compare; 296290650Shselasky}; 297290650Shselasky 298290650Shselaskystruct mlx5_wqe_data_seg { 299290650Shselasky __be32 byte_count; 300290650Shselasky __be32 lkey; 301290650Shselasky __be64 addr; 302290650Shselasky}; 303290650Shselasky 304290650Shselaskystruct mlx5_wqe_umr_ctrl_seg { 305290650Shselasky u8 flags; 306290650Shselasky u8 rsvd0[3]; 307290650Shselasky __be16 klm_octowords; 308290650Shselasky __be16 bsf_octowords; 309290650Shselasky __be64 mkey_mask; 310290650Shselasky u8 rsvd1[32]; 311290650Shselasky}; 312290650Shselasky 313290650Shselaskystruct mlx5_seg_set_psv { 314290650Shselasky __be32 psv_num; 315290650Shselasky __be16 syndrome; 316290650Shselasky __be16 status; 317290650Shselasky __be32 transient_sig; 318290650Shselasky __be32 ref_tag; 319290650Shselasky}; 320290650Shselasky 321290650Shselaskystruct mlx5_seg_get_psv { 322290650Shselasky u8 rsvd[19]; 323290650Shselasky u8 num_psv; 324290650Shselasky __be32 l_key; 325290650Shselasky __be64 va; 326290650Shselasky __be32 psv_index[4]; 327290650Shselasky}; 328290650Shselasky 329290650Shselaskystruct mlx5_seg_check_psv { 330290650Shselasky u8 rsvd0[2]; 331290650Shselasky __be16 err_coalescing_op; 332290650Shselasky u8 rsvd1[2]; 333290650Shselasky __be16 xport_err_op; 334290650Shselasky u8 rsvd2[2]; 335290650Shselasky __be16 xport_err_mask; 336290650Shselasky u8 rsvd3[7]; 337290650Shselasky u8 num_psv; 338290650Shselasky __be32 l_key; 339290650Shselasky __be64 va; 340290650Shselasky __be32 psv_index[4]; 341290650Shselasky}; 342290650Shselasky 343290650Shselaskystruct mlx5_rwqe_sig { 344290650Shselasky u8 rsvd0[4]; 345290650Shselasky u8 signature; 346290650Shselasky u8 rsvd1[11]; 347290650Shselasky}; 348290650Shselasky 349290650Shselaskystruct mlx5_wqe_signature_seg { 350290650Shselasky u8 rsvd0[4]; 351290650Shselasky u8 signature; 352290650Shselasky u8 rsvd1[11]; 353290650Shselasky}; 354290650Shselasky 355290650Shselaskystruct mlx5_wqe_inline_seg { 356290650Shselasky __be32 byte_count; 357290650Shselasky}; 358290650Shselasky 359290650Shselaskyenum mlx5_sig_type { 360290650Shselasky MLX5_DIF_CRC = 0x1, 361290650Shselasky MLX5_DIF_IPCS = 0x2, 362290650Shselasky}; 363290650Shselasky 364290650Shselaskystruct mlx5_bsf_inl { 365290650Shselasky __be16 vld_refresh; 366290650Shselasky __be16 dif_apptag; 367290650Shselasky __be32 dif_reftag; 368290650Shselasky u8 sig_type; 369290650Shselasky u8 rp_inv_seed; 370290650Shselasky u8 rsvd[3]; 371290650Shselasky u8 dif_inc_ref_guard_check; 372290650Shselasky __be16 dif_app_bitmask_check; 373290650Shselasky}; 374290650Shselasky 375290650Shselaskystruct mlx5_bsf { 376290650Shselasky struct mlx5_bsf_basic { 377290650Shselasky u8 bsf_size_sbs; 378290650Shselasky u8 check_byte_mask; 379290650Shselasky union { 380290650Shselasky u8 copy_byte_mask; 381290650Shselasky u8 bs_selector; 382290650Shselasky u8 rsvd_wflags; 383290650Shselasky } wire; 384290650Shselasky union { 385290650Shselasky u8 bs_selector; 386290650Shselasky u8 rsvd_mflags; 387290650Shselasky } mem; 388290650Shselasky __be32 raw_data_size; 389290650Shselasky __be32 w_bfs_psv; 390290650Shselasky __be32 m_bfs_psv; 391290650Shselasky } basic; 392290650Shselasky struct mlx5_bsf_ext { 393290650Shselasky __be32 t_init_gen_pro_size; 394290650Shselasky __be32 rsvd_epi_size; 395290650Shselasky __be32 w_tfs_psv; 396290650Shselasky __be32 m_tfs_psv; 397290650Shselasky } ext; 398290650Shselasky struct mlx5_bsf_inl w_inl; 399290650Shselasky struct mlx5_bsf_inl m_inl; 400290650Shselasky}; 401290650Shselasky 402290650Shselaskystruct mlx5_klm { 403290650Shselasky __be32 bcount; 404290650Shselasky __be32 key; 405290650Shselasky __be64 va; 406290650Shselasky}; 407290650Shselasky 408290650Shselaskystruct mlx5_stride_block_entry { 409290650Shselasky __be16 stride; 410290650Shselasky __be16 bcount; 411290650Shselasky __be32 key; 412290650Shselasky __be64 va; 413290650Shselasky}; 414290650Shselasky 415290650Shselaskystruct mlx5_stride_block_ctrl_seg { 416290650Shselasky __be32 bcount_per_cycle; 417290650Shselasky __be32 op; 418290650Shselasky __be32 repeat_count; 419290650Shselasky u16 rsvd; 420290650Shselasky __be16 num_entries; 421290650Shselasky}; 422290650Shselasky 423290650Shselaskystruct mlx5_core_qp { 424290650Shselasky struct mlx5_core_rsc_common common; /* must be first */ 425290650Shselasky void (*event) (struct mlx5_core_qp *, int); 426290650Shselasky int qpn; 427290650Shselasky struct mlx5_rsc_debug *dbg; 428290650Shselasky int pid; 429290650Shselasky}; 430290650Shselasky 431290650Shselaskystruct mlx5_qp_path { 432290650Shselasky u8 fl_free_ar; 433290650Shselasky u8 rsvd3; 434290650Shselasky __be16 pkey_index; 435290650Shselasky u8 rsvd0; 436290650Shselasky u8 grh_mlid; 437290650Shselasky __be16 rlid; 438290650Shselasky u8 ackto_lt; 439290650Shselasky u8 mgid_index; 440290650Shselasky u8 static_rate; 441290650Shselasky u8 hop_limit; 442290650Shselasky __be32 tclass_flowlabel; 443290650Shselasky union { 444290650Shselasky u8 rgid[16]; 445290650Shselasky u8 rip[16]; 446290650Shselasky }; 447290650Shselasky u8 f_dscp_ecn_prio; 448290650Shselasky u8 ecn_dscp; 449290650Shselasky __be16 udp_sport; 450290650Shselasky u8 dci_cfi_prio_sl; 451290650Shselasky u8 port; 452290650Shselasky u8 rmac[6]; 453290650Shselasky}; 454290650Shselasky 455290650Shselaskystruct mlx5_qp_context { 456290650Shselasky __be32 flags; 457290650Shselasky __be32 flags_pd; 458290650Shselasky u8 mtu_msgmax; 459290650Shselasky u8 rq_size_stride; 460290650Shselasky __be16 sq_crq_size; 461290650Shselasky __be32 qp_counter_set_usr_page; 462290650Shselasky __be32 wire_qpn; 463290650Shselasky __be32 log_pg_sz_remote_qpn; 464290650Shselasky struct mlx5_qp_path pri_path; 465290650Shselasky struct mlx5_qp_path alt_path; 466290650Shselasky __be32 params1; 467290650Shselasky u8 reserved2[4]; 468290650Shselasky __be32 next_send_psn; 469290650Shselasky __be32 cqn_send; 470290650Shselasky u8 reserved3[8]; 471290650Shselasky __be32 last_acked_psn; 472290650Shselasky __be32 ssn; 473290650Shselasky __be32 params2; 474290650Shselasky __be32 rnr_nextrecvpsn; 475290650Shselasky __be32 xrcd; 476290650Shselasky __be32 cqn_recv; 477290650Shselasky __be64 db_rec_addr; 478290650Shselasky __be32 qkey; 479290650Shselasky __be32 rq_type_srqn; 480290650Shselasky __be32 rmsn; 481290650Shselasky __be16 hw_sq_wqe_counter; 482290650Shselasky __be16 sw_sq_wqe_counter; 483290650Shselasky __be16 hw_rcyclic_byte_counter; 484290650Shselasky __be16 hw_rq_counter; 485290650Shselasky __be16 sw_rcyclic_byte_counter; 486290650Shselasky __be16 sw_rq_counter; 487290650Shselasky u8 rsvd0[5]; 488290650Shselasky u8 cgs; 489290650Shselasky u8 cs_req; 490290650Shselasky u8 cs_res; 491290650Shselasky __be64 dc_access_key; 492290650Shselasky u8 rsvd1[24]; 493290650Shselasky}; 494290650Shselasky 495290650Shselaskystruct mlx5_create_qp_mbox_in { 496290650Shselasky struct mlx5_inbox_hdr hdr; 497290650Shselasky __be32 input_qpn; 498290650Shselasky u8 rsvd0[4]; 499290650Shselasky __be32 opt_param_mask; 500290650Shselasky u8 rsvd1[4]; 501290650Shselasky struct mlx5_qp_context ctx; 502290650Shselasky u8 rsvd3[16]; 503290650Shselasky __be64 pas[0]; 504290650Shselasky}; 505290650Shselasky 506306244Shselaskystruct mlx5_dct_context { 507306244Shselasky u8 state; 508306244Shselasky u8 rsvd0[7]; 509306244Shselasky __be32 cqn; 510306244Shselasky __be32 flags; 511306244Shselasky u8 rsvd1; 512306244Shselasky u8 cs_res; 513306244Shselasky u8 min_rnr; 514306244Shselasky u8 rsvd2; 515306244Shselasky __be32 srqn; 516306244Shselasky __be32 pdn; 517306244Shselasky __be32 tclass_flow_label; 518306244Shselasky __be64 access_key; 519306244Shselasky u8 mtu; 520306244Shselasky u8 port; 521306244Shselasky __be16 pkey_index; 522306244Shselasky u8 rsvd4; 523306244Shselasky u8 mgid_index; 524306244Shselasky u8 rsvd5; 525306244Shselasky u8 hop_limit; 526306244Shselasky __be32 access_violations; 527306244Shselasky u8 rsvd[12]; 528306244Shselasky}; 529306244Shselasky 530306244Shselaskystruct mlx5_create_dct_mbox_in { 531306244Shselasky struct mlx5_inbox_hdr hdr; 532306244Shselasky u8 rsvd0[8]; 533306244Shselasky struct mlx5_dct_context context; 534306244Shselasky u8 rsvd[48]; 535306244Shselasky}; 536306244Shselasky 537306244Shselaskystruct mlx5_create_dct_mbox_out { 538306244Shselasky struct mlx5_outbox_hdr hdr; 539306244Shselasky __be32 dctn; 540306244Shselasky u8 rsvd0[4]; 541306244Shselasky}; 542306244Shselasky 543306244Shselaskystruct mlx5_destroy_dct_mbox_in { 544306244Shselasky struct mlx5_inbox_hdr hdr; 545306244Shselasky __be32 dctn; 546306244Shselasky u8 rsvd0[4]; 547306244Shselasky}; 548306244Shselasky 549306244Shselaskystruct mlx5_destroy_dct_mbox_out { 550306244Shselasky struct mlx5_outbox_hdr hdr; 551306244Shselasky u8 rsvd0[8]; 552306244Shselasky}; 553306244Shselasky 554306244Shselaskystruct mlx5_drain_dct_mbox_in { 555306244Shselasky struct mlx5_inbox_hdr hdr; 556306244Shselasky __be32 dctn; 557306244Shselasky u8 rsvd0[4]; 558306244Shselasky}; 559306244Shselasky 560306244Shselaskystruct mlx5_drain_dct_mbox_out { 561306244Shselasky struct mlx5_outbox_hdr hdr; 562306244Shselasky u8 rsvd0[8]; 563306244Shselasky}; 564306244Shselasky 565290650Shselaskystruct mlx5_create_qp_mbox_out { 566290650Shselasky struct mlx5_outbox_hdr hdr; 567290650Shselasky __be32 qpn; 568290650Shselasky u8 rsvd0[4]; 569290650Shselasky}; 570290650Shselasky 571290650Shselaskystruct mlx5_destroy_qp_mbox_in { 572290650Shselasky struct mlx5_inbox_hdr hdr; 573290650Shselasky __be32 qpn; 574290650Shselasky u8 rsvd0[4]; 575290650Shselasky}; 576290650Shselasky 577290650Shselaskystruct mlx5_destroy_qp_mbox_out { 578290650Shselasky struct mlx5_outbox_hdr hdr; 579290650Shselasky u8 rsvd0[8]; 580290650Shselasky}; 581290650Shselasky 582290650Shselaskystruct mlx5_modify_qp_mbox_in { 583290650Shselasky struct mlx5_inbox_hdr hdr; 584290650Shselasky __be32 qpn; 585290650Shselasky u8 rsvd1[4]; 586290650Shselasky __be32 optparam; 587290650Shselasky u8 rsvd0[4]; 588290650Shselasky struct mlx5_qp_context ctx; 589306244Shselasky u8 rsvd2[16]; 590290650Shselasky}; 591290650Shselasky 592290650Shselaskystruct mlx5_modify_qp_mbox_out { 593290650Shselasky struct mlx5_outbox_hdr hdr; 594290650Shselasky u8 rsvd0[8]; 595290650Shselasky}; 596290650Shselasky 597290650Shselaskystruct mlx5_query_qp_mbox_in { 598290650Shselasky struct mlx5_inbox_hdr hdr; 599290650Shselasky __be32 qpn; 600290650Shselasky u8 rsvd[4]; 601290650Shselasky}; 602290650Shselasky 603290650Shselaskystruct mlx5_query_qp_mbox_out { 604290650Shselasky struct mlx5_outbox_hdr hdr; 605290650Shselasky u8 rsvd1[8]; 606290650Shselasky __be32 optparam; 607290650Shselasky u8 rsvd0[4]; 608290650Shselasky struct mlx5_qp_context ctx; 609290650Shselasky u8 rsvd2[16]; 610290650Shselasky __be64 pas[0]; 611290650Shselasky}; 612290650Shselasky 613306244Shselaskystruct mlx5_query_dct_mbox_in { 614306244Shselasky struct mlx5_inbox_hdr hdr; 615306244Shselasky __be32 dctn; 616306244Shselasky u8 rsvd[4]; 617306244Shselasky}; 618306244Shselasky 619306244Shselaskystruct mlx5_query_dct_mbox_out { 620306244Shselasky struct mlx5_outbox_hdr hdr; 621306244Shselasky u8 rsvd0[8]; 622306244Shselasky struct mlx5_dct_context ctx; 623306244Shselasky u8 rsvd1[48]; 624306244Shselasky}; 625306244Shselasky 626306244Shselaskystruct mlx5_arm_dct_mbox_in { 627306244Shselasky struct mlx5_inbox_hdr hdr; 628306244Shselasky __be32 dctn; 629306244Shselasky u8 rsvd[4]; 630306244Shselasky}; 631306244Shselasky 632306244Shselaskystruct mlx5_arm_dct_mbox_out { 633306244Shselasky struct mlx5_outbox_hdr hdr; 634306244Shselasky u8 rsvd0[8]; 635306244Shselasky}; 636306244Shselasky 637290650Shselaskystruct mlx5_conf_sqp_mbox_in { 638290650Shselasky struct mlx5_inbox_hdr hdr; 639290650Shselasky __be32 qpn; 640290650Shselasky u8 rsvd[3]; 641290650Shselasky u8 type; 642290650Shselasky}; 643290650Shselasky 644290650Shselaskystruct mlx5_conf_sqp_mbox_out { 645290650Shselasky struct mlx5_outbox_hdr hdr; 646290650Shselasky u8 rsvd[8]; 647290650Shselasky}; 648290650Shselasky 649290650Shselaskystatic inline struct mlx5_core_qp *__mlx5_qp_lookup(struct mlx5_core_dev *dev, u32 qpn) 650290650Shselasky{ 651290650Shselasky return radix_tree_lookup(&dev->priv.qp_table.tree, qpn); 652290650Shselasky} 653290650Shselasky 654290650Shselaskystatic inline struct mlx5_core_mr *__mlx5_mr_lookup(struct mlx5_core_dev *dev, u32 key) 655290650Shselasky{ 656290650Shselasky return radix_tree_lookup(&dev->priv.mr_table.tree, key); 657290650Shselasky} 658290650Shselasky 659290650Shselaskyint mlx5_core_create_qp(struct mlx5_core_dev *dev, 660290650Shselasky struct mlx5_core_qp *qp, 661290650Shselasky struct mlx5_create_qp_mbox_in *in, 662290650Shselasky int inlen); 663306244Shselaskyint mlx5_core_qp_modify(struct mlx5_core_dev *dev, u16 operation, 664290650Shselasky struct mlx5_modify_qp_mbox_in *in, int sqd_event, 665290650Shselasky struct mlx5_core_qp *qp); 666290650Shselaskyint mlx5_core_destroy_qp(struct mlx5_core_dev *dev, 667290650Shselasky struct mlx5_core_qp *qp); 668290650Shselaskyint mlx5_core_qp_query(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp, 669290650Shselasky struct mlx5_query_qp_mbox_out *out, int outlen); 670306244Shselaskyint mlx5_core_dct_query(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct, 671306244Shselasky struct mlx5_query_dct_mbox_out *out); 672306244Shselaskyint mlx5_core_arm_dct(struct mlx5_core_dev *dev, struct mlx5_core_dct *dct); 673290650Shselasky 674290650Shselaskyint mlx5_core_xrcd_alloc(struct mlx5_core_dev *dev, u32 *xrcdn); 675290650Shselaskyint mlx5_core_xrcd_dealloc(struct mlx5_core_dev *dev, u32 xrcdn); 676306244Shselaskyint mlx5_core_create_dct(struct mlx5_core_dev *dev, 677306244Shselasky struct mlx5_core_dct *dct, 678306244Shselasky struct mlx5_create_dct_mbox_in *in); 679306244Shselaskyint mlx5_core_destroy_dct(struct mlx5_core_dev *dev, 680306244Shselasky struct mlx5_core_dct *dct); 681306244Shselaskyint mlx5_core_create_rq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 682306244Shselasky struct mlx5_core_qp *rq); 683306244Shselaskyvoid mlx5_core_destroy_rq_tracked(struct mlx5_core_dev *dev, 684306244Shselasky struct mlx5_core_qp *rq); 685306244Shselaskyint mlx5_core_create_sq_tracked(struct mlx5_core_dev *dev, u32 *in, int inlen, 686306244Shselasky struct mlx5_core_qp *sq); 687306244Shselaskyvoid mlx5_core_destroy_sq_tracked(struct mlx5_core_dev *dev, 688306244Shselasky struct mlx5_core_qp *sq); 689290650Shselaskyvoid mlx5_init_qp_table(struct mlx5_core_dev *dev); 690290650Shselaskyvoid mlx5_cleanup_qp_table(struct mlx5_core_dev *dev); 691290650Shselaskyint mlx5_debug_qp_add(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 692290650Shselaskyvoid mlx5_debug_qp_remove(struct mlx5_core_dev *dev, struct mlx5_core_qp *qp); 693290650Shselasky 694290650Shselaskystatic inline const char *mlx5_qp_type_str(int type) 695290650Shselasky{ 696290650Shselasky switch (type) { 697290650Shselasky case MLX5_QP_ST_RC: return "RC"; 698290650Shselasky case MLX5_QP_ST_UC: return "C"; 699290650Shselasky case MLX5_QP_ST_UD: return "UD"; 700290650Shselasky case MLX5_QP_ST_XRC: return "XRC"; 701290650Shselasky case MLX5_QP_ST_MLX: return "MLX"; 702306244Shselasky case MLX5_QP_ST_DCI: return "DCI"; 703290650Shselasky case MLX5_QP_ST_QP0: return "QP0"; 704290650Shselasky case MLX5_QP_ST_QP1: return "QP1"; 705290650Shselasky case MLX5_QP_ST_RAW_ETHERTYPE: return "RAW_ETHERTYPE"; 706290650Shselasky case MLX5_QP_ST_RAW_IPV6: return "RAW_IPV6"; 707290650Shselasky case MLX5_QP_ST_SNIFFER: return "SNIFFER"; 708290650Shselasky case MLX5_QP_ST_SYNC_UMR: return "SYNC_UMR"; 709290650Shselasky case MLX5_QP_ST_PTP_1588: return "PTP_1588"; 710290650Shselasky case MLX5_QP_ST_REG_UMR: return "REG_UMR"; 711306244Shselasky case MLX5_QP_ST_SW_CNAK: return "DC_CNAK"; 712290650Shselasky default: return "Invalid transport type"; 713290650Shselasky } 714290650Shselasky} 715290650Shselasky 716290650Shselaskystatic inline const char *mlx5_qp_state_str(int state) 717290650Shselasky{ 718290650Shselasky switch (state) { 719290650Shselasky case MLX5_QP_STATE_RST: 720290650Shselasky return "RST"; 721290650Shselasky case MLX5_QP_STATE_INIT: 722290650Shselasky return "INIT"; 723290650Shselasky case MLX5_QP_STATE_RTR: 724290650Shselasky return "RTR"; 725290650Shselasky case MLX5_QP_STATE_RTS: 726290650Shselasky return "RTS"; 727290650Shselasky case MLX5_QP_STATE_SQER: 728290650Shselasky return "SQER"; 729290650Shselasky case MLX5_QP_STATE_SQD: 730290650Shselasky return "SQD"; 731290650Shselasky case MLX5_QP_STATE_ERR: 732290650Shselasky return "ERR"; 733290650Shselasky case MLX5_QP_STATE_SQ_DRAINING: 734290650Shselasky return "SQ_DRAINING"; 735290650Shselasky case MLX5_QP_STATE_SUSPENDED: 736290650Shselasky return "SUSPENDED"; 737290650Shselasky default: return "Invalid QP state"; 738290650Shselasky } 739290650Shselasky} 740290650Shselasky 741290650Shselasky#endif /* MLX5_QP_H */ 742