1290650Shselasky/*- 2322151Shselasky * Copyright (c) 2013-2017, Mellanox Technologies, Ltd. All rights reserved. 3290650Shselasky * 4290650Shselasky * Redistribution and use in source and binary forms, with or without 5290650Shselasky * modification, are permitted provided that the following conditions 6290650Shselasky * are met: 7290650Shselasky * 1. Redistributions of source code must retain the above copyright 8290650Shselasky * notice, this list of conditions and the following disclaimer. 9290650Shselasky * 2. Redistributions in binary form must reproduce the above copyright 10290650Shselasky * notice, this list of conditions and the following disclaimer in the 11290650Shselasky * documentation and/or other materials provided with the distribution. 12290650Shselasky * 13290650Shselasky * THIS SOFTWARE IS PROVIDED BY AUTHOR AND CONTRIBUTORS `AS IS' AND 14290650Shselasky * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 15290650Shselasky * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 16290650Shselasky * ARE DISCLAIMED. IN NO EVENT SHALL AUTHOR OR CONTRIBUTORS BE LIABLE 17290650Shselasky * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 18290650Shselasky * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 19290650Shselasky * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 20290650Shselasky * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 21290650Shselasky * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 22290650Shselasky * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 23290650Shselasky * SUCH DAMAGE. 24290650Shselasky * 25290650Shselasky * $FreeBSD: stable/10/sys/dev/mlx5/device.h 339713 2018-10-25 14:12:48Z slavash $ 26290650Shselasky */ 27290650Shselasky 28290650Shselasky#ifndef MLX5_DEVICE_H 29290650Shselasky#define MLX5_DEVICE_H 30290650Shselasky 31290650Shselasky#include <linux/types.h> 32290650Shselasky#include <rdma/ib_verbs.h> 33290650Shselasky#include <dev/mlx5/mlx5_ifc.h> 34290650Shselasky 35290650Shselasky#define FW_INIT_TIMEOUT_MILI 2000 36290650Shselasky#define FW_INIT_WAIT_MS 2 37290650Shselasky 38290650Shselasky#if defined(__LITTLE_ENDIAN) 39290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0 40290650Shselasky#elif defined(__BIG_ENDIAN) 41290650Shselasky#define MLX5_SET_HOST_ENDIANNESS 0x80 42290650Shselasky#else 43290650Shselasky#error Host endianness not defined 44290650Shselasky#endif 45290650Shselasky 46290650Shselasky/* helper macros */ 47290650Shselasky#define __mlx5_nullp(typ) ((struct mlx5_ifc_##typ##_bits *)0) 48290650Shselasky#define __mlx5_bit_sz(typ, fld) sizeof(__mlx5_nullp(typ)->fld) 49290650Shselasky#define __mlx5_bit_off(typ, fld) __offsetof(struct mlx5_ifc_##typ##_bits, fld) 50290650Shselasky#define __mlx5_dw_off(typ, fld) (__mlx5_bit_off(typ, fld) / 32) 51290650Shselasky#define __mlx5_64_off(typ, fld) (__mlx5_bit_off(typ, fld) / 64) 52290650Shselasky#define __mlx5_dw_bit_off(typ, fld) (32 - __mlx5_bit_sz(typ, fld) - (__mlx5_bit_off(typ, fld) & 0x1f)) 53290650Shselasky#define __mlx5_mask(typ, fld) ((u32)((1ull << __mlx5_bit_sz(typ, fld)) - 1)) 54290650Shselasky#define __mlx5_dw_mask(typ, fld) (__mlx5_mask(typ, fld) << __mlx5_dw_bit_off(typ, fld)) 55290650Shselasky#define __mlx5_st_sz_bits(typ) sizeof(struct mlx5_ifc_##typ##_bits) 56290650Shselasky 57290650Shselasky#define MLX5_FLD_SZ_BYTES(typ, fld) (__mlx5_bit_sz(typ, fld) / 8) 58290650Shselasky#define MLX5_ST_SZ_BYTES(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 8) 59290650Shselasky#define MLX5_ST_SZ_DW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 32) 60306244Shselasky#define MLX5_ST_SZ_QW(typ) (sizeof(struct mlx5_ifc_##typ##_bits) / 64) 61290650Shselasky#define MLX5_UN_SZ_BYTES(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 8) 62290650Shselasky#define MLX5_UN_SZ_DW(typ) (sizeof(union mlx5_ifc_##typ##_bits) / 32) 63290650Shselasky#define MLX5_BYTE_OFF(typ, fld) (__mlx5_bit_off(typ, fld) / 8) 64290650Shselasky#define MLX5_ADDR_OF(typ, p, fld) ((char *)(p) + MLX5_BYTE_OFF(typ, fld)) 65290650Shselasky 66290650Shselasky/* insert a value to a struct */ 67290650Shselasky#define MLX5_SET(typ, p, fld, v) do { \ 68290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 69290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 70290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 71290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 72290650Shselasky (~__mlx5_dw_mask(typ, fld))) | (((v) & __mlx5_mask(typ, fld)) \ 73290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 74290650Shselasky} while (0) 75290650Shselasky 76290650Shselasky#define MLX5_SET_TO_ONES(typ, p, fld) do { \ 77290650Shselasky BUILD_BUG_ON(__mlx5_st_sz_bits(typ) % 32); \ 78290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) > 32); \ 79290650Shselasky *((__be32 *)(p) + __mlx5_dw_off(typ, fld)) = \ 80290650Shselasky cpu_to_be32((be32_to_cpu(*((__be32 *)(p) + __mlx5_dw_off(typ, fld))) & \ 81290650Shselasky (~__mlx5_dw_mask(typ, fld))) | ((__mlx5_mask(typ, fld)) \ 82290650Shselasky << __mlx5_dw_bit_off(typ, fld))); \ 83290650Shselasky} while (0) 84290650Shselasky 85290650Shselasky#define MLX5_GET(typ, p, fld) ((be32_to_cpu(*((__be32 *)(p) +\ 86290650Shselasky__mlx5_dw_off(typ, fld))) >> __mlx5_dw_bit_off(typ, fld)) & \ 87290650Shselasky__mlx5_mask(typ, fld)) 88290650Shselasky 89290650Shselasky#define MLX5_GET_PR(typ, p, fld) ({ \ 90290650Shselasky u32 ___t = MLX5_GET(typ, p, fld); \ 91290650Shselasky pr_debug(#fld " = 0x%x\n", ___t); \ 92290650Shselasky ___t; \ 93290650Shselasky}) 94290650Shselasky 95290650Shselasky#define MLX5_SET64(typ, p, fld, v) do { \ 96290650Shselasky BUILD_BUG_ON(__mlx5_bit_sz(typ, fld) != 64); \ 97290650Shselasky BUILD_BUG_ON(__mlx5_bit_off(typ, fld) % 64); \ 98290650Shselasky *((__be64 *)(p) + __mlx5_64_off(typ, fld)) = cpu_to_be64(v); \ 99290650Shselasky} while (0) 100290650Shselasky 101290650Shselasky#define MLX5_GET64(typ, p, fld) be64_to_cpu(*((__be64 *)(p) + __mlx5_64_off(typ, fld))) 102290650Shselasky 103290650Shselaskyenum { 104290650Shselasky MLX5_MAX_COMMANDS = 32, 105290650Shselasky MLX5_CMD_DATA_BLOCK_SIZE = 512, 106322151Shselasky MLX5_CMD_MBOX_SIZE = 1024, 107290650Shselasky MLX5_PCI_CMD_XPORT = 7, 108290650Shselasky MLX5_MKEY_BSF_OCTO_SIZE = 4, 109290650Shselasky MLX5_MAX_PSVS = 4, 110290650Shselasky}; 111290650Shselasky 112290650Shselaskyenum { 113290650Shselasky MLX5_EXTENDED_UD_AV = 0x80000000, 114290650Shselasky}; 115290650Shselasky 116290650Shselaskyenum { 117306244Shselasky MLX5_CQ_FLAGS_OI = 2, 118306244Shselasky}; 119306244Shselasky 120306244Shselaskyenum { 121290650Shselasky MLX5_STAT_RATE_OFFSET = 5, 122290650Shselasky}; 123290650Shselasky 124290650Shselaskyenum { 125290650Shselasky MLX5_INLINE_SEG = 0x80000000, 126290650Shselasky}; 127290650Shselasky 128290650Shselaskyenum { 129290650Shselasky MLX5_HW_START_PADDING = MLX5_INLINE_SEG, 130290650Shselasky}; 131290650Shselasky 132290650Shselaskyenum { 133290650Shselasky MLX5_MIN_PKEY_TABLE_SIZE = 128, 134290650Shselasky MLX5_MAX_LOG_PKEY_TABLE = 5, 135290650Shselasky}; 136290650Shselasky 137290650Shselaskyenum { 138306244Shselasky MLX5_MKEY_INBOX_PG_ACCESS = 1 << 31 139306244Shselasky}; 140306244Shselasky 141306244Shselaskyenum { 142290650Shselasky MLX5_PERM_LOCAL_READ = 1 << 2, 143290650Shselasky MLX5_PERM_LOCAL_WRITE = 1 << 3, 144290650Shselasky MLX5_PERM_REMOTE_READ = 1 << 4, 145290650Shselasky MLX5_PERM_REMOTE_WRITE = 1 << 5, 146290650Shselasky MLX5_PERM_ATOMIC = 1 << 6, 147290650Shselasky MLX5_PERM_UMR_EN = 1 << 7, 148290650Shselasky}; 149290650Shselasky 150290650Shselaskyenum { 151290650Shselasky MLX5_PCIE_CTRL_SMALL_FENCE = 1 << 0, 152290650Shselasky MLX5_PCIE_CTRL_RELAXED_ORDERING = 1 << 2, 153290650Shselasky MLX5_PCIE_CTRL_NO_SNOOP = 1 << 3, 154290650Shselasky MLX5_PCIE_CTRL_TLP_PROCE_EN = 1 << 6, 155290650Shselasky MLX5_PCIE_CTRL_TPH_MASK = 3 << 4, 156290650Shselasky}; 157290650Shselasky 158290650Shselaskyenum { 159290650Shselasky MLX5_MKEY_REMOTE_INVAL = 1 << 24, 160290650Shselasky MLX5_MKEY_FLAG_SYNC_UMR = 1 << 29, 161290650Shselasky MLX5_MKEY_BSF_EN = 1 << 30, 162290650Shselasky MLX5_MKEY_LEN64 = 1 << 31, 163290650Shselasky}; 164290650Shselasky 165290650Shselaskyenum { 166290650Shselasky MLX5_EN_RD = (u64)1, 167290650Shselasky MLX5_EN_WR = (u64)2 168290650Shselasky}; 169290650Shselasky 170290650Shselaskyenum { 171290650Shselasky MLX5_BF_REGS_PER_PAGE = 4, 172290650Shselasky MLX5_MAX_UAR_PAGES = 1 << 8, 173290650Shselasky MLX5_NON_FP_BF_REGS_PER_PAGE = 2, 174290650Shselasky MLX5_MAX_UUARS = MLX5_MAX_UAR_PAGES * MLX5_NON_FP_BF_REGS_PER_PAGE, 175290650Shselasky}; 176290650Shselasky 177290650Shselaskyenum { 178290650Shselasky MLX5_MKEY_MASK_LEN = 1ull << 0, 179290650Shselasky MLX5_MKEY_MASK_PAGE_SIZE = 1ull << 1, 180290650Shselasky MLX5_MKEY_MASK_START_ADDR = 1ull << 6, 181290650Shselasky MLX5_MKEY_MASK_PD = 1ull << 7, 182290650Shselasky MLX5_MKEY_MASK_EN_RINVAL = 1ull << 8, 183290650Shselasky MLX5_MKEY_MASK_EN_SIGERR = 1ull << 9, 184290650Shselasky MLX5_MKEY_MASK_BSF_EN = 1ull << 12, 185290650Shselasky MLX5_MKEY_MASK_KEY = 1ull << 13, 186290650Shselasky MLX5_MKEY_MASK_QPN = 1ull << 14, 187290650Shselasky MLX5_MKEY_MASK_LR = 1ull << 17, 188290650Shselasky MLX5_MKEY_MASK_LW = 1ull << 18, 189290650Shselasky MLX5_MKEY_MASK_RR = 1ull << 19, 190290650Shselasky MLX5_MKEY_MASK_RW = 1ull << 20, 191290650Shselasky MLX5_MKEY_MASK_A = 1ull << 21, 192290650Shselasky MLX5_MKEY_MASK_SMALL_FENCE = 1ull << 23, 193290650Shselasky MLX5_MKEY_MASK_FREE = 1ull << 29, 194290650Shselasky}; 195290650Shselasky 196290650Shselaskyenum { 197306244Shselasky MLX5_UMR_TRANSLATION_OFFSET_EN = (1 << 4), 198306244Shselasky 199306244Shselasky MLX5_UMR_CHECK_NOT_FREE = (1 << 5), 200306244Shselasky MLX5_UMR_CHECK_FREE = (2 << 5), 201306244Shselasky 202306244Shselasky MLX5_UMR_INLINE = (1 << 7), 203306244Shselasky}; 204306244Shselasky 205306244Shselasky#define MLX5_UMR_MTT_ALIGNMENT 0x40 206306244Shselasky#define MLX5_UMR_MTT_MASK (MLX5_UMR_MTT_ALIGNMENT - 1) 207306244Shselasky#define MLX5_UMR_MTT_MIN_CHUNK_SIZE MLX5_UMR_MTT_ALIGNMENT 208306244Shselasky 209306244Shselaskyenum { 210306244Shselasky MLX5_EVENT_QUEUE_TYPE_QP = 0, 211306244Shselasky MLX5_EVENT_QUEUE_TYPE_RQ = 1, 212306244Shselasky MLX5_EVENT_QUEUE_TYPE_SQ = 2, 213306244Shselasky}; 214306244Shselasky 215306244Shselaskyenum { 216290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_DOWN = 1, 217290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_ACTIVE = 4, 218290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_INITIALIZED = 5, 219290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_LID = 6, 220290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_PKEY = 7, 221290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_GUID = 8, 222290650Shselasky MLX5_PORT_CHANGE_SUBTYPE_CLIENT_REREG = 9, 223290650Shselasky}; 224290650Shselasky 225290650Shselaskyenum { 226306244Shselasky MLX5_DCBX_EVENT_SUBTYPE_ERROR_STATE_DCBX = 1, 227306244Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_CHANGE, 228306244Shselasky MLX5_DCBX_EVENT_SUBTYPE_LOCAL_OPER_CHANGE, 229306244Shselasky MLX5_DCBX_EVENT_SUBTYPE_REMOTE_CONFIG_APP_PRIORITY_CHANGE, 230306244Shselasky MLX5_MAX_INLINE_RECEIVE_SIZE = 64 231306244Shselasky}; 232306244Shselasky 233306244Shselaskyenum { 234290650Shselasky MLX5_DEV_CAP_FLAG_XRC = 1LL << 3, 235290650Shselasky MLX5_DEV_CAP_FLAG_BAD_PKEY_CNTR = 1LL << 8, 236290650Shselasky MLX5_DEV_CAP_FLAG_BAD_QKEY_CNTR = 1LL << 9, 237290650Shselasky MLX5_DEV_CAP_FLAG_APM = 1LL << 17, 238290650Shselasky MLX5_DEV_CAP_FLAG_SCQE_BRK_MOD = 1LL << 21, 239290650Shselasky MLX5_DEV_CAP_FLAG_BLOCK_MCAST = 1LL << 23, 240290650Shselasky MLX5_DEV_CAP_FLAG_CQ_MODER = 1LL << 29, 241290650Shselasky MLX5_DEV_CAP_FLAG_RESIZE_CQ = 1LL << 30, 242306244Shselasky MLX5_DEV_CAP_FLAG_ATOMIC = 1LL << 33, 243290650Shselasky MLX5_DEV_CAP_FLAG_ROCE = 1LL << 34, 244290650Shselasky MLX5_DEV_CAP_FLAG_DCT = 1LL << 37, 245290650Shselasky MLX5_DEV_CAP_FLAG_SIG_HAND_OVER = 1LL << 40, 246290650Shselasky MLX5_DEV_CAP_FLAG_CMDIF_CSUM = 3LL << 46, 247306244Shselasky MLX5_DEV_CAP_FLAG_DRAIN_SIGERR = 1LL << 48, 248290650Shselasky}; 249290650Shselasky 250290650Shselaskyenum { 251290650Shselasky MLX5_ROCE_VERSION_1 = 0, 252290650Shselasky MLX5_ROCE_VERSION_1_5 = 1, 253290650Shselasky MLX5_ROCE_VERSION_2 = 2, 254290650Shselasky}; 255290650Shselasky 256290650Shselaskyenum { 257290650Shselasky MLX5_ROCE_VERSION_1_CAP = 1 << MLX5_ROCE_VERSION_1, 258290650Shselasky MLX5_ROCE_VERSION_1_5_CAP = 1 << MLX5_ROCE_VERSION_1_5, 259290650Shselasky MLX5_ROCE_VERSION_2_CAP = 1 << MLX5_ROCE_VERSION_2, 260290650Shselasky}; 261290650Shselasky 262290650Shselaskyenum { 263290650Shselasky MLX5_ROCE_L3_TYPE_IPV4 = 0, 264290650Shselasky MLX5_ROCE_L3_TYPE_IPV6 = 1, 265290650Shselasky}; 266290650Shselasky 267290650Shselaskyenum { 268290650Shselasky MLX5_ROCE_L3_TYPE_IPV4_CAP = 1 << 1, 269290650Shselasky MLX5_ROCE_L3_TYPE_IPV6_CAP = 1 << 2, 270290650Shselasky}; 271290650Shselasky 272290650Shselaskyenum { 273290650Shselasky MLX5_OPCODE_NOP = 0x00, 274290650Shselasky MLX5_OPCODE_SEND_INVAL = 0x01, 275290650Shselasky MLX5_OPCODE_RDMA_WRITE = 0x08, 276290650Shselasky MLX5_OPCODE_RDMA_WRITE_IMM = 0x09, 277290650Shselasky MLX5_OPCODE_SEND = 0x0a, 278290650Shselasky MLX5_OPCODE_SEND_IMM = 0x0b, 279290650Shselasky MLX5_OPCODE_LSO = 0x0e, 280290650Shselasky MLX5_OPCODE_RDMA_READ = 0x10, 281290650Shselasky MLX5_OPCODE_ATOMIC_CS = 0x11, 282290650Shselasky MLX5_OPCODE_ATOMIC_FA = 0x12, 283290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_CS = 0x14, 284290650Shselasky MLX5_OPCODE_ATOMIC_MASKED_FA = 0x15, 285290650Shselasky MLX5_OPCODE_BIND_MW = 0x18, 286290650Shselasky MLX5_OPCODE_CONFIG_CMD = 0x1f, 287290650Shselasky 288290650Shselasky MLX5_RECV_OPCODE_RDMA_WRITE_IMM = 0x00, 289290650Shselasky MLX5_RECV_OPCODE_SEND = 0x01, 290290650Shselasky MLX5_RECV_OPCODE_SEND_IMM = 0x02, 291290650Shselasky MLX5_RECV_OPCODE_SEND_INVAL = 0x03, 292290650Shselasky 293290650Shselasky MLX5_CQE_OPCODE_ERROR = 0x1e, 294290650Shselasky MLX5_CQE_OPCODE_RESIZE = 0x16, 295290650Shselasky 296290650Shselasky MLX5_OPCODE_SET_PSV = 0x20, 297290650Shselasky MLX5_OPCODE_GET_PSV = 0x21, 298290650Shselasky MLX5_OPCODE_CHECK_PSV = 0x22, 299290650Shselasky MLX5_OPCODE_RGET_PSV = 0x26, 300290650Shselasky MLX5_OPCODE_RCHECK_PSV = 0x27, 301290650Shselasky 302290650Shselasky MLX5_OPCODE_UMR = 0x25, 303290650Shselasky 304306244Shselasky MLX5_OPCODE_SIGNATURE_CANCELED = (1 << 15), 305290650Shselasky}; 306290650Shselasky 307290650Shselaskyenum { 308290650Shselasky MLX5_SET_PORT_RESET_QKEY = 0, 309290650Shselasky MLX5_SET_PORT_GUID0 = 16, 310290650Shselasky MLX5_SET_PORT_NODE_GUID = 17, 311290650Shselasky MLX5_SET_PORT_SYS_GUID = 18, 312290650Shselasky MLX5_SET_PORT_GID_TABLE = 19, 313290650Shselasky MLX5_SET_PORT_PKEY_TABLE = 20, 314290650Shselasky}; 315290650Shselasky 316290650Shselaskyenum { 317290650Shselasky MLX5_MAX_PAGE_SHIFT = 31 318290650Shselasky}; 319290650Shselasky 320290650Shselaskyenum { 321290650Shselasky MLX5_ADAPTER_PAGE_SHIFT = 12, 322290650Shselasky MLX5_ADAPTER_PAGE_SIZE = 1 << MLX5_ADAPTER_PAGE_SHIFT, 323290650Shselasky}; 324290650Shselasky 325290650Shselaskyenum { 326290650Shselasky MLX5_CAP_OFF_CMDIF_CSUM = 46, 327290650Shselasky}; 328290650Shselasky 329290650Shselaskystruct mlx5_inbox_hdr { 330290650Shselasky __be16 opcode; 331290650Shselasky u8 rsvd[4]; 332290650Shselasky __be16 opmod; 333290650Shselasky}; 334290650Shselasky 335290650Shselaskystruct mlx5_outbox_hdr { 336290650Shselasky u8 status; 337290650Shselasky u8 rsvd[3]; 338290650Shselasky __be32 syndrome; 339290650Shselasky}; 340290650Shselasky 341306244Shselaskystruct mlx5_cmd_set_dc_cnak_mbox_in { 342306244Shselasky struct mlx5_inbox_hdr hdr; 343306244Shselasky u8 enable; 344306244Shselasky u8 reserved[47]; 345306244Shselasky __be64 pa; 346306244Shselasky}; 347306244Shselasky 348306244Shselaskystruct mlx5_cmd_set_dc_cnak_mbox_out { 349306244Shselasky struct mlx5_outbox_hdr hdr; 350306244Shselasky u8 rsvd[8]; 351306244Shselasky}; 352306244Shselasky 353290650Shselaskystruct mlx5_cmd_layout { 354290650Shselasky u8 type; 355290650Shselasky u8 rsvd0[3]; 356290650Shselasky __be32 inlen; 357290650Shselasky __be64 in_ptr; 358290650Shselasky __be32 in[4]; 359290650Shselasky __be32 out[4]; 360290650Shselasky __be64 out_ptr; 361290650Shselasky __be32 outlen; 362290650Shselasky u8 token; 363290650Shselasky u8 sig; 364290650Shselasky u8 rsvd1; 365290650Shselasky u8 status_own; 366290650Shselasky}; 367290650Shselasky 368290650Shselasky 369290650Shselaskystruct mlx5_health_buffer { 370290650Shselasky __be32 assert_var[5]; 371290650Shselasky __be32 rsvd0[3]; 372290650Shselasky __be32 assert_exit_ptr; 373290650Shselasky __be32 assert_callra; 374290650Shselasky __be32 rsvd1[2]; 375290650Shselasky __be32 fw_ver; 376290650Shselasky __be32 hw_id; 377290650Shselasky __be32 rsvd2; 378290650Shselasky u8 irisc_index; 379290650Shselasky u8 synd; 380290650Shselasky __be16 ext_sync; 381290650Shselasky}; 382290650Shselasky 383290650Shselaskystruct mlx5_init_seg { 384290650Shselasky __be32 fw_rev; 385290650Shselasky __be32 cmdif_rev_fw_sub; 386290650Shselasky __be32 rsvd0[2]; 387290650Shselasky __be32 cmdq_addr_h; 388290650Shselasky __be32 cmdq_addr_l_sz; 389290650Shselasky __be32 cmd_dbell; 390290650Shselasky __be32 rsvd1[120]; 391290650Shselasky __be32 initializing; 392290650Shselasky struct mlx5_health_buffer health; 393306244Shselasky __be32 rsvd2[880]; 394306244Shselasky __be32 internal_timer_h; 395306244Shselasky __be32 internal_timer_l; 396306244Shselasky __be32 rsvd3[2]; 397290650Shselasky __be32 health_counter; 398306244Shselasky __be32 rsvd4[1019]; 399290650Shselasky __be64 ieee1588_clk; 400290650Shselasky __be32 ieee1588_clk_type; 401290650Shselasky __be32 clr_intx; 402290650Shselasky}; 403290650Shselasky 404290650Shselaskystruct mlx5_eqe_comp { 405290650Shselasky __be32 reserved[6]; 406290650Shselasky __be32 cqn; 407290650Shselasky}; 408290650Shselasky 409290650Shselaskystruct mlx5_eqe_qp_srq { 410290650Shselasky __be32 reserved[6]; 411290650Shselasky __be32 qp_srq_n; 412290650Shselasky}; 413290650Shselasky 414290650Shselaskystruct mlx5_eqe_cq_err { 415290650Shselasky __be32 cqn; 416290650Shselasky u8 reserved1[7]; 417290650Shselasky u8 syndrome; 418290650Shselasky}; 419290650Shselasky 420290650Shselaskystruct mlx5_eqe_port_state { 421290650Shselasky u8 reserved0[8]; 422290650Shselasky u8 port; 423290650Shselasky}; 424290650Shselasky 425290650Shselaskystruct mlx5_eqe_gpio { 426290650Shselasky __be32 reserved0[2]; 427290650Shselasky __be64 gpio_event; 428290650Shselasky}; 429290650Shselasky 430290650Shselaskystruct mlx5_eqe_congestion { 431290650Shselasky u8 type; 432290650Shselasky u8 rsvd0; 433290650Shselasky u8 congestion_level; 434290650Shselasky}; 435290650Shselasky 436290650Shselaskystruct mlx5_eqe_stall_vl { 437290650Shselasky u8 rsvd0[3]; 438290650Shselasky u8 port_vl; 439290650Shselasky}; 440290650Shselasky 441290650Shselaskystruct mlx5_eqe_cmd { 442290650Shselasky __be32 vector; 443290650Shselasky __be32 rsvd[6]; 444290650Shselasky}; 445290650Shselasky 446290650Shselaskystruct mlx5_eqe_page_req { 447290650Shselasky u8 rsvd0[2]; 448290650Shselasky __be16 func_id; 449290650Shselasky __be32 num_pages; 450290650Shselasky __be32 rsvd1[5]; 451290650Shselasky}; 452290650Shselasky 453290650Shselaskystruct mlx5_eqe_vport_change { 454290650Shselasky u8 rsvd0[2]; 455290650Shselasky __be16 vport_num; 456290650Shselasky __be32 rsvd1[6]; 457290650Shselasky}; 458290650Shselasky 459290650Shselasky 460290650Shselasky#define PORT_MODULE_EVENT_MODULE_STATUS_MASK 0xF 461290650Shselasky#define PORT_MODULE_EVENT_ERROR_TYPE_MASK 0xF 462290650Shselasky 463290650Shselaskyenum { 464290650Shselasky MLX5_MODULE_STATUS_PLUGGED = 0x1, 465290650Shselasky MLX5_MODULE_STATUS_UNPLUGGED = 0x2, 466290650Shselasky MLX5_MODULE_STATUS_ERROR = 0x3, 467290650Shselasky}; 468290650Shselasky 469290650Shselaskyenum { 470290650Shselasky MLX5_MODULE_EVENT_ERROR_POWER_BUDGET_EXCEEDED = 0x0, 471290650Shselasky MLX5_MODULE_EVENT_ERROR_LONG_RANGE_FOR_NON_MLNX_CABLE_MODULE = 0x1, 472290650Shselasky MLX5_MODULE_EVENT_ERROR_BUS_STUCK = 0x2, 473290650Shselasky MLX5_MODULE_EVENT_ERROR_NO_EEPROM_RETRY_TIMEOUT = 0x3, 474290650Shselasky MLX5_MODULE_EVENT_ERROR_ENFORCE_PART_NUMBER_LIST = 0x4, 475290650Shselasky MLX5_MODULE_EVENT_ERROR_UNKNOWN_IDENTIFIER = 0x5, 476290650Shselasky MLX5_MODULE_EVENT_ERROR_HIGH_TEMPERATURE = 0x6, 477306244Shselasky MLX5_MODULE_EVENT_ERROR_CABLE_IS_SHORTED = 0x7, 478339713Sslavash MLX5_MODULE_EVENT_ERROR_PCIE_SYSTEM_POWER_SLOT_EXCEEDED = 0xc, 479290650Shselasky}; 480290650Shselasky 481290650Shselaskystruct mlx5_eqe_port_module_event { 482290650Shselasky u8 rsvd0; 483290650Shselasky u8 module; 484290650Shselasky u8 rsvd1; 485290650Shselasky u8 module_status; 486290650Shselasky u8 rsvd2[2]; 487290650Shselasky u8 error_type; 488290650Shselasky}; 489290650Shselasky 490290650Shselaskyunion ev_data { 491290650Shselasky __be32 raw[7]; 492290650Shselasky struct mlx5_eqe_cmd cmd; 493290650Shselasky struct mlx5_eqe_comp comp; 494290650Shselasky struct mlx5_eqe_qp_srq qp_srq; 495290650Shselasky struct mlx5_eqe_cq_err cq_err; 496290650Shselasky struct mlx5_eqe_port_state port; 497290650Shselasky struct mlx5_eqe_gpio gpio; 498290650Shselasky struct mlx5_eqe_congestion cong; 499290650Shselasky struct mlx5_eqe_stall_vl stall_vl; 500290650Shselasky struct mlx5_eqe_page_req req_pages; 501290650Shselasky struct mlx5_eqe_port_module_event port_module_event; 502290650Shselasky struct mlx5_eqe_vport_change vport_change; 503290650Shselasky} __packed; 504290650Shselasky 505290650Shselaskystruct mlx5_eqe { 506290650Shselasky u8 rsvd0; 507290650Shselasky u8 type; 508290650Shselasky u8 rsvd1; 509290650Shselasky u8 sub_type; 510290650Shselasky __be32 rsvd2[7]; 511290650Shselasky union ev_data data; 512290650Shselasky __be16 rsvd3; 513290650Shselasky u8 signature; 514290650Shselasky u8 owner; 515290650Shselasky} __packed; 516290650Shselasky 517290650Shselaskystruct mlx5_cmd_prot_block { 518290650Shselasky u8 data[MLX5_CMD_DATA_BLOCK_SIZE]; 519290650Shselasky u8 rsvd0[48]; 520290650Shselasky __be64 next; 521290650Shselasky __be32 block_num; 522290650Shselasky u8 rsvd1; 523290650Shselasky u8 token; 524290650Shselasky u8 ctrl_sig; 525290650Shselasky u8 sig; 526290650Shselasky}; 527290650Shselasky 528322151Shselasky#define MLX5_NUM_CMDS_IN_ADAPTER_PAGE \ 529322151Shselasky (MLX5_ADAPTER_PAGE_SIZE / MLX5_CMD_MBOX_SIZE) 530322151ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE >= sizeof(struct mlx5_cmd_prot_block)); 531322151ShselaskyCTASSERT(MLX5_CMD_MBOX_SIZE <= MLX5_ADAPTER_PAGE_SIZE); 532322151Shselasky 533290650Shselaskyenum { 534290650Shselasky MLX5_CQE_SYND_FLUSHED_IN_ERROR = 5, 535290650Shselasky}; 536290650Shselasky 537290650Shselaskystruct mlx5_err_cqe { 538290650Shselasky u8 rsvd0[32]; 539290650Shselasky __be32 srqn; 540290650Shselasky u8 rsvd1[18]; 541290650Shselasky u8 vendor_err_synd; 542290650Shselasky u8 syndrome; 543290650Shselasky __be32 s_wqe_opcode_qpn; 544290650Shselasky __be16 wqe_counter; 545290650Shselasky u8 signature; 546290650Shselasky u8 op_own; 547290650Shselasky}; 548290650Shselasky 549290650Shselaskystruct mlx5_cqe64 { 550290650Shselasky u8 tunneled_etc; 551290650Shselasky u8 rsvd0[3]; 552290650Shselasky u8 lro_tcppsh_abort_dupack; 553290650Shselasky u8 lro_min_ttl; 554290650Shselasky __be16 lro_tcp_win; 555290650Shselasky __be32 lro_ack_seq_num; 556290650Shselasky __be32 rss_hash_result; 557290650Shselasky u8 rss_hash_type; 558290650Shselasky u8 ml_path; 559290650Shselasky u8 rsvd20[2]; 560290650Shselasky __be16 check_sum; 561290650Shselasky __be16 slid; 562290650Shselasky __be32 flags_rqpn; 563290650Shselasky u8 hds_ip_ext; 564290650Shselasky u8 l4_hdr_type_etc; 565290650Shselasky __be16 vlan_info; 566290650Shselasky __be32 srqn; /* [31:24]: lro_num_seg, [23:0]: srqn */ 567290650Shselasky __be32 imm_inval_pkey; 568290650Shselasky u8 rsvd40[4]; 569290650Shselasky __be32 byte_cnt; 570290650Shselasky __be64 timestamp; 571290650Shselasky __be32 sop_drop_qpn; 572290650Shselasky __be16 wqe_counter; 573290650Shselasky u8 signature; 574290650Shselasky u8 op_own; 575290650Shselasky}; 576290650Shselasky 577290650Shselaskystatic inline bool get_cqe_lro_timestamp_valid(struct mlx5_cqe64 *cqe) 578290650Shselasky{ 579290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 7) & 1; 580290650Shselasky} 581290650Shselasky 582290650Shselaskystatic inline bool get_cqe_lro_tcppsh(struct mlx5_cqe64 *cqe) 583290650Shselasky{ 584290650Shselasky return (cqe->lro_tcppsh_abort_dupack >> 6) & 1; 585290650Shselasky} 586290650Shselasky 587290650Shselaskystatic inline u8 get_cqe_l4_hdr_type(struct mlx5_cqe64 *cqe) 588290650Shselasky{ 589290650Shselasky return (cqe->l4_hdr_type_etc >> 4) & 0x7; 590290650Shselasky} 591290650Shselasky 592290650Shselaskystatic inline u16 get_cqe_vlan(struct mlx5_cqe64 *cqe) 593290650Shselasky{ 594290650Shselasky return be16_to_cpu(cqe->vlan_info) & 0xfff; 595290650Shselasky} 596290650Shselasky 597290650Shselaskystatic inline void get_cqe_smac(struct mlx5_cqe64 *cqe, u8 *smac) 598290650Shselasky{ 599290650Shselasky memcpy(smac, &cqe->rss_hash_type , 4); 600290650Shselasky memcpy(smac + 4, &cqe->slid , 2); 601290650Shselasky} 602290650Shselasky 603290650Shselaskystatic inline bool cqe_has_vlan(struct mlx5_cqe64 *cqe) 604290650Shselasky{ 605290650Shselasky return cqe->l4_hdr_type_etc & 0x1; 606290650Shselasky} 607290650Shselasky 608290650Shselaskystatic inline bool cqe_is_tunneled(struct mlx5_cqe64 *cqe) 609290650Shselasky{ 610290650Shselasky return cqe->tunneled_etc & 0x1; 611290650Shselasky} 612290650Shselasky 613290650Shselaskyenum { 614290650Shselasky CQE_L4_HDR_TYPE_NONE = 0x0, 615290650Shselasky CQE_L4_HDR_TYPE_TCP_NO_ACK = 0x1, 616290650Shselasky CQE_L4_HDR_TYPE_UDP = 0x2, 617290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_NO_DATA = 0x3, 618290650Shselasky CQE_L4_HDR_TYPE_TCP_ACK_AND_DATA = 0x4, 619290650Shselasky}; 620290650Shselasky 621290650Shselaskyenum { 622290650Shselasky /* source L3 hash types */ 623290650Shselasky CQE_RSS_SRC_HTYPE_IP = 0x3 << 0, 624290650Shselasky CQE_RSS_SRC_HTYPE_IPV4 = 0x1 << 0, 625290650Shselasky CQE_RSS_SRC_HTYPE_IPV6 = 0x2 << 0, 626290650Shselasky 627290650Shselasky /* destination L3 hash types */ 628290650Shselasky CQE_RSS_DST_HTYPE_IP = 0x3 << 2, 629290650Shselasky CQE_RSS_DST_HTYPE_IPV4 = 0x1 << 2, 630290650Shselasky CQE_RSS_DST_HTYPE_IPV6 = 0x2 << 2, 631290650Shselasky 632290650Shselasky /* source L4 hash types */ 633290650Shselasky CQE_RSS_SRC_HTYPE_L4 = 0x3 << 4, 634290650Shselasky CQE_RSS_SRC_HTYPE_TCP = 0x1 << 4, 635290650Shselasky CQE_RSS_SRC_HTYPE_UDP = 0x2 << 4, 636290650Shselasky CQE_RSS_SRC_HTYPE_IPSEC = 0x3 << 4, 637290650Shselasky 638290650Shselasky /* destination L4 hash types */ 639290650Shselasky CQE_RSS_DST_HTYPE_L4 = 0x3 << 6, 640290650Shselasky CQE_RSS_DST_HTYPE_TCP = 0x1 << 6, 641290650Shselasky CQE_RSS_DST_HTYPE_UDP = 0x2 << 6, 642290650Shselasky CQE_RSS_DST_HTYPE_IPSEC = 0x3 << 6, 643290650Shselasky}; 644290650Shselasky 645290650Shselaskyenum { 646290650Shselasky CQE_ROCE_L3_HEADER_TYPE_GRH = 0x0, 647290650Shselasky CQE_ROCE_L3_HEADER_TYPE_IPV6 = 0x1, 648290650Shselasky CQE_ROCE_L3_HEADER_TYPE_IPV4 = 0x2, 649290650Shselasky}; 650290650Shselasky 651290650Shselaskyenum { 652290650Shselasky CQE_L2_OK = 1 << 0, 653290650Shselasky CQE_L3_OK = 1 << 1, 654290650Shselasky CQE_L4_OK = 1 << 2, 655290650Shselasky}; 656290650Shselasky 657290650Shselaskystruct mlx5_sig_err_cqe { 658290650Shselasky u8 rsvd0[16]; 659290650Shselasky __be32 expected_trans_sig; 660290650Shselasky __be32 actual_trans_sig; 661290650Shselasky __be32 expected_reftag; 662290650Shselasky __be32 actual_reftag; 663290650Shselasky __be16 syndrome; 664290650Shselasky u8 rsvd22[2]; 665290650Shselasky __be32 mkey; 666290650Shselasky __be64 err_offset; 667290650Shselasky u8 rsvd30[8]; 668290650Shselasky __be32 qpn; 669290650Shselasky u8 rsvd38[2]; 670290650Shselasky u8 signature; 671290650Shselasky u8 op_own; 672290650Shselasky}; 673290650Shselasky 674290650Shselaskystruct mlx5_wqe_srq_next_seg { 675290650Shselasky u8 rsvd0[2]; 676290650Shselasky __be16 next_wqe_index; 677290650Shselasky u8 signature; 678290650Shselasky u8 rsvd1[11]; 679290650Shselasky}; 680290650Shselasky 681290650Shselaskyunion mlx5_ext_cqe { 682290650Shselasky struct ib_grh grh; 683290650Shselasky u8 inl[64]; 684290650Shselasky}; 685290650Shselasky 686290650Shselaskystruct mlx5_cqe128 { 687290650Shselasky union mlx5_ext_cqe inl_grh; 688290650Shselasky struct mlx5_cqe64 cqe64; 689290650Shselasky}; 690290650Shselasky 691290650Shselaskystruct mlx5_srq_ctx { 692290650Shselasky u8 state_log_sz; 693290650Shselasky u8 rsvd0[3]; 694290650Shselasky __be32 flags_xrcd; 695290650Shselasky __be32 pgoff_cqn; 696290650Shselasky u8 rsvd1[4]; 697290650Shselasky u8 log_pg_sz; 698290650Shselasky u8 rsvd2[7]; 699290650Shselasky __be32 pd; 700290650Shselasky __be16 lwm; 701290650Shselasky __be16 wqe_cnt; 702290650Shselasky u8 rsvd3[8]; 703290650Shselasky __be64 db_record; 704290650Shselasky}; 705290650Shselasky 706290650Shselaskystruct mlx5_create_srq_mbox_in { 707290650Shselasky struct mlx5_inbox_hdr hdr; 708290650Shselasky __be32 input_srqn; 709290650Shselasky u8 rsvd0[4]; 710290650Shselasky struct mlx5_srq_ctx ctx; 711290650Shselasky u8 rsvd1[208]; 712290650Shselasky __be64 pas[0]; 713290650Shselasky}; 714290650Shselasky 715290650Shselaskystruct mlx5_create_srq_mbox_out { 716290650Shselasky struct mlx5_outbox_hdr hdr; 717290650Shselasky __be32 srqn; 718290650Shselasky u8 rsvd[4]; 719290650Shselasky}; 720290650Shselasky 721290650Shselaskystruct mlx5_destroy_srq_mbox_in { 722290650Shselasky struct mlx5_inbox_hdr hdr; 723290650Shselasky __be32 srqn; 724290650Shselasky u8 rsvd[4]; 725290650Shselasky}; 726290650Shselasky 727290650Shselaskystruct mlx5_destroy_srq_mbox_out { 728290650Shselasky struct mlx5_outbox_hdr hdr; 729290650Shselasky u8 rsvd[8]; 730290650Shselasky}; 731290650Shselasky 732290650Shselaskystruct mlx5_query_srq_mbox_in { 733290650Shselasky struct mlx5_inbox_hdr hdr; 734290650Shselasky __be32 srqn; 735290650Shselasky u8 rsvd0[4]; 736290650Shselasky}; 737290650Shselasky 738290650Shselaskystruct mlx5_query_srq_mbox_out { 739290650Shselasky struct mlx5_outbox_hdr hdr; 740290650Shselasky u8 rsvd0[8]; 741290650Shselasky struct mlx5_srq_ctx ctx; 742290650Shselasky u8 rsvd1[32]; 743290650Shselasky __be64 pas[0]; 744290650Shselasky}; 745290650Shselasky 746290650Shselaskystruct mlx5_arm_srq_mbox_in { 747290650Shselasky struct mlx5_inbox_hdr hdr; 748290650Shselasky __be32 srqn; 749290650Shselasky __be16 rsvd; 750290650Shselasky __be16 lwm; 751290650Shselasky}; 752290650Shselasky 753290650Shselaskystruct mlx5_arm_srq_mbox_out { 754290650Shselasky struct mlx5_outbox_hdr hdr; 755290650Shselasky u8 rsvd[8]; 756290650Shselasky}; 757290650Shselasky 758290650Shselaskystruct mlx5_cq_context { 759290650Shselasky u8 status; 760290650Shselasky u8 cqe_sz_flags; 761290650Shselasky u8 st; 762290650Shselasky u8 rsvd3; 763290650Shselasky u8 rsvd4[6]; 764290650Shselasky __be16 page_offset; 765290650Shselasky __be32 log_sz_usr_page; 766290650Shselasky __be16 cq_period; 767290650Shselasky __be16 cq_max_count; 768290650Shselasky __be16 rsvd20; 769290650Shselasky __be16 c_eqn; 770290650Shselasky u8 log_pg_sz; 771290650Shselasky u8 rsvd25[7]; 772290650Shselasky __be32 last_notified_index; 773290650Shselasky __be32 solicit_producer_index; 774290650Shselasky __be32 consumer_counter; 775290650Shselasky __be32 producer_counter; 776290650Shselasky u8 rsvd48[8]; 777290650Shselasky __be64 db_record_addr; 778290650Shselasky}; 779290650Shselasky 780290650Shselaskystruct mlx5_create_cq_mbox_in { 781290650Shselasky struct mlx5_inbox_hdr hdr; 782290650Shselasky __be32 input_cqn; 783290650Shselasky u8 rsvdx[4]; 784290650Shselasky struct mlx5_cq_context ctx; 785290650Shselasky u8 rsvd6[192]; 786290650Shselasky __be64 pas[0]; 787290650Shselasky}; 788290650Shselasky 789290650Shselaskystruct mlx5_create_cq_mbox_out { 790290650Shselasky struct mlx5_outbox_hdr hdr; 791290650Shselasky __be32 cqn; 792290650Shselasky u8 rsvd0[4]; 793290650Shselasky}; 794290650Shselasky 795290650Shselaskystruct mlx5_destroy_cq_mbox_in { 796290650Shselasky struct mlx5_inbox_hdr hdr; 797290650Shselasky __be32 cqn; 798290650Shselasky u8 rsvd0[4]; 799290650Shselasky}; 800290650Shselasky 801290650Shselaskystruct mlx5_destroy_cq_mbox_out { 802290650Shselasky struct mlx5_outbox_hdr hdr; 803290650Shselasky u8 rsvd0[8]; 804290650Shselasky}; 805290650Shselasky 806290650Shselaskystruct mlx5_query_cq_mbox_in { 807290650Shselasky struct mlx5_inbox_hdr hdr; 808290650Shselasky __be32 cqn; 809290650Shselasky u8 rsvd0[4]; 810290650Shselasky}; 811290650Shselasky 812290650Shselaskystruct mlx5_query_cq_mbox_out { 813290650Shselasky struct mlx5_outbox_hdr hdr; 814290650Shselasky u8 rsvd0[8]; 815290650Shselasky struct mlx5_cq_context ctx; 816290650Shselasky u8 rsvd6[16]; 817290650Shselasky __be64 pas[0]; 818290650Shselasky}; 819290650Shselasky 820290650Shselaskystruct mlx5_modify_cq_mbox_in { 821290650Shselasky struct mlx5_inbox_hdr hdr; 822290650Shselasky __be32 cqn; 823290650Shselasky __be32 field_select; 824290650Shselasky struct mlx5_cq_context ctx; 825290650Shselasky u8 rsvd[192]; 826290650Shselasky __be64 pas[0]; 827290650Shselasky}; 828290650Shselasky 829290650Shselaskystruct mlx5_modify_cq_mbox_out { 830290650Shselasky struct mlx5_outbox_hdr hdr; 831290650Shselasky u8 rsvd[8]; 832290650Shselasky}; 833290650Shselasky 834290650Shselaskystruct mlx5_eq_context { 835290650Shselasky u8 status; 836290650Shselasky u8 ec_oi; 837290650Shselasky u8 st; 838290650Shselasky u8 rsvd2[7]; 839290650Shselasky __be16 page_pffset; 840290650Shselasky __be32 log_sz_usr_page; 841290650Shselasky u8 rsvd3[7]; 842290650Shselasky u8 intr; 843290650Shselasky u8 log_page_size; 844290650Shselasky u8 rsvd4[15]; 845290650Shselasky __be32 consumer_counter; 846290650Shselasky __be32 produser_counter; 847290650Shselasky u8 rsvd5[16]; 848290650Shselasky}; 849290650Shselasky 850290650Shselaskystruct mlx5_create_eq_mbox_in { 851290650Shselasky struct mlx5_inbox_hdr hdr; 852290650Shselasky u8 rsvd0[3]; 853290650Shselasky u8 input_eqn; 854290650Shselasky u8 rsvd1[4]; 855290650Shselasky struct mlx5_eq_context ctx; 856290650Shselasky u8 rsvd2[8]; 857290650Shselasky __be64 events_mask; 858290650Shselasky u8 rsvd3[176]; 859290650Shselasky __be64 pas[0]; 860290650Shselasky}; 861290650Shselasky 862290650Shselaskystruct mlx5_create_eq_mbox_out { 863290650Shselasky struct mlx5_outbox_hdr hdr; 864290650Shselasky u8 rsvd0[3]; 865290650Shselasky u8 eq_number; 866290650Shselasky u8 rsvd1[4]; 867290650Shselasky}; 868290650Shselasky 869290650Shselaskystruct mlx5_map_eq_mbox_in { 870290650Shselasky struct mlx5_inbox_hdr hdr; 871290650Shselasky __be64 mask; 872290650Shselasky u8 mu; 873290650Shselasky u8 rsvd0[2]; 874290650Shselasky u8 eqn; 875290650Shselasky u8 rsvd1[24]; 876290650Shselasky}; 877290650Shselasky 878290650Shselaskystruct mlx5_map_eq_mbox_out { 879290650Shselasky struct mlx5_outbox_hdr hdr; 880290650Shselasky u8 rsvd[8]; 881290650Shselasky}; 882290650Shselasky 883290650Shselaskystruct mlx5_query_eq_mbox_in { 884290650Shselasky struct mlx5_inbox_hdr hdr; 885290650Shselasky u8 rsvd0[3]; 886290650Shselasky u8 eqn; 887290650Shselasky u8 rsvd1[4]; 888290650Shselasky}; 889290650Shselasky 890290650Shselaskystruct mlx5_query_eq_mbox_out { 891290650Shselasky struct mlx5_outbox_hdr hdr; 892290650Shselasky u8 rsvd[8]; 893290650Shselasky struct mlx5_eq_context ctx; 894290650Shselasky}; 895290650Shselasky 896306244Shselaskyenum { 897306244Shselasky MLX5_MKEY_STATUS_FREE = 1 << 6, 898306244Shselasky}; 899306244Shselasky 900290650Shselaskystruct mlx5_mkey_seg { 901290650Shselasky /* This is a two bit field occupying bits 31-30. 902290650Shselasky * bit 31 is always 0, 903290650Shselasky * bit 30 is zero for regular MRs and 1 (e.g free) for UMRs that do not have tanslation 904290650Shselasky */ 905290650Shselasky u8 status; 906290650Shselasky u8 pcie_control; 907290650Shselasky u8 flags; 908290650Shselasky u8 version; 909290650Shselasky __be32 qpn_mkey7_0; 910290650Shselasky u8 rsvd1[4]; 911290650Shselasky __be32 flags_pd; 912290650Shselasky __be64 start_addr; 913290650Shselasky __be64 len; 914290650Shselasky __be32 bsfs_octo_size; 915290650Shselasky u8 rsvd2[16]; 916290650Shselasky __be32 xlt_oct_size; 917290650Shselasky u8 rsvd3[3]; 918290650Shselasky u8 log2_page_size; 919290650Shselasky u8 rsvd4[4]; 920290650Shselasky}; 921290650Shselasky 922290650Shselaskystruct mlx5_query_special_ctxs_mbox_in { 923290650Shselasky struct mlx5_inbox_hdr hdr; 924290650Shselasky u8 rsvd[8]; 925290650Shselasky}; 926290650Shselasky 927290650Shselaskystruct mlx5_query_special_ctxs_mbox_out { 928290650Shselasky struct mlx5_outbox_hdr hdr; 929290650Shselasky __be32 dump_fill_mkey; 930290650Shselasky __be32 reserved_lkey; 931290650Shselasky}; 932290650Shselasky 933290650Shselaskystruct mlx5_create_mkey_mbox_in { 934290650Shselasky struct mlx5_inbox_hdr hdr; 935290650Shselasky __be32 input_mkey_index; 936306244Shselasky __be32 flags; 937290650Shselasky struct mlx5_mkey_seg seg; 938290650Shselasky u8 rsvd1[16]; 939290650Shselasky __be32 xlat_oct_act_size; 940290650Shselasky __be32 rsvd2; 941290650Shselasky u8 rsvd3[168]; 942290650Shselasky __be64 pas[0]; 943290650Shselasky}; 944290650Shselasky 945290650Shselaskystruct mlx5_create_mkey_mbox_out { 946290650Shselasky struct mlx5_outbox_hdr hdr; 947290650Shselasky __be32 mkey; 948290650Shselasky u8 rsvd[4]; 949290650Shselasky}; 950290650Shselasky 951290650Shselaskystruct mlx5_query_mkey_mbox_in { 952290650Shselasky struct mlx5_inbox_hdr hdr; 953290650Shselasky __be32 mkey; 954290650Shselasky}; 955290650Shselasky 956290650Shselaskystruct mlx5_query_mkey_mbox_out { 957290650Shselasky struct mlx5_outbox_hdr hdr; 958290650Shselasky __be64 pas[0]; 959290650Shselasky}; 960290650Shselasky 961290650Shselaskystruct mlx5_modify_mkey_mbox_in { 962290650Shselasky struct mlx5_inbox_hdr hdr; 963290650Shselasky __be32 mkey; 964290650Shselasky __be64 pas[0]; 965290650Shselasky}; 966290650Shselasky 967290650Shselaskystruct mlx5_modify_mkey_mbox_out { 968290650Shselasky struct mlx5_outbox_hdr hdr; 969290650Shselasky u8 rsvd[8]; 970290650Shselasky}; 971290650Shselasky 972290650Shselaskystruct mlx5_dump_mkey_mbox_in { 973290650Shselasky struct mlx5_inbox_hdr hdr; 974290650Shselasky}; 975290650Shselasky 976290650Shselaskystruct mlx5_dump_mkey_mbox_out { 977290650Shselasky struct mlx5_outbox_hdr hdr; 978290650Shselasky __be32 mkey; 979290650Shselasky}; 980290650Shselasky 981290650Shselaskystruct mlx5_mad_ifc_mbox_in { 982290650Shselasky struct mlx5_inbox_hdr hdr; 983290650Shselasky __be16 remote_lid; 984290650Shselasky u8 rsvd0; 985290650Shselasky u8 port; 986290650Shselasky u8 rsvd1[4]; 987290650Shselasky u8 data[256]; 988290650Shselasky}; 989290650Shselasky 990290650Shselaskystruct mlx5_mad_ifc_mbox_out { 991290650Shselasky struct mlx5_outbox_hdr hdr; 992290650Shselasky u8 rsvd[8]; 993290650Shselasky u8 data[256]; 994290650Shselasky}; 995290650Shselasky 996290650Shselaskystruct mlx5_access_reg_mbox_in { 997290650Shselasky struct mlx5_inbox_hdr hdr; 998290650Shselasky u8 rsvd0[2]; 999290650Shselasky __be16 register_id; 1000290650Shselasky __be32 arg; 1001290650Shselasky __be32 data[0]; 1002290650Shselasky}; 1003290650Shselasky 1004290650Shselaskystruct mlx5_access_reg_mbox_out { 1005290650Shselasky struct mlx5_outbox_hdr hdr; 1006290650Shselasky u8 rsvd[8]; 1007290650Shselasky __be32 data[0]; 1008290650Shselasky}; 1009290650Shselasky 1010290650Shselasky#define MLX5_ATTR_EXTENDED_PORT_INFO cpu_to_be16(0xff90) 1011290650Shselasky 1012290650Shselaskyenum { 1013290650Shselasky MLX_EXT_PORT_CAP_FLAG_EXTENDED_PORT_INFO = 1 << 0 1014290650Shselasky}; 1015290650Shselasky 1016290650Shselaskystruct mlx5_allocate_psv_in { 1017290650Shselasky struct mlx5_inbox_hdr hdr; 1018290650Shselasky __be32 npsv_pd; 1019290650Shselasky __be32 rsvd_psv0; 1020290650Shselasky}; 1021290650Shselasky 1022290650Shselaskystruct mlx5_allocate_psv_out { 1023290650Shselasky struct mlx5_outbox_hdr hdr; 1024290650Shselasky u8 rsvd[8]; 1025290650Shselasky __be32 psv_idx[4]; 1026290650Shselasky}; 1027290650Shselasky 1028290650Shselaskystruct mlx5_destroy_psv_in { 1029290650Shselasky struct mlx5_inbox_hdr hdr; 1030290650Shselasky __be32 psv_number; 1031290650Shselasky u8 rsvd[4]; 1032290650Shselasky}; 1033290650Shselasky 1034290650Shselaskystruct mlx5_destroy_psv_out { 1035290650Shselasky struct mlx5_outbox_hdr hdr; 1036290650Shselasky u8 rsvd[8]; 1037290650Shselasky}; 1038290650Shselasky 1039306244Shselaskystatic inline int mlx5_host_is_le(void) 1040306244Shselasky{ 1041306244Shselasky#if defined(__LITTLE_ENDIAN) 1042306244Shselasky return 1; 1043306244Shselasky#elif defined(__BIG_ENDIAN) 1044306244Shselasky return 0; 1045306244Shselasky#else 1046306244Shselasky#error Host endianness not defined 1047306244Shselasky#endif 1048306244Shselasky} 1049306244Shselasky 1050290650Shselasky#define MLX5_CMD_OP_MAX 0x939 1051290650Shselasky 1052290650Shselaskyenum { 1053290650Shselasky VPORT_STATE_DOWN = 0x0, 1054290650Shselasky VPORT_STATE_UP = 0x1, 1055290650Shselasky}; 1056290650Shselasky 1057290650Shselaskyenum { 1058290650Shselasky MLX5_L3_PROT_TYPE_IPV4 = 0, 1059290650Shselasky MLX5_L3_PROT_TYPE_IPV6 = 1, 1060290650Shselasky}; 1061290650Shselasky 1062290650Shselaskyenum { 1063290650Shselasky MLX5_L4_PROT_TYPE_TCP = 0, 1064290650Shselasky MLX5_L4_PROT_TYPE_UDP = 1, 1065290650Shselasky}; 1066290650Shselasky 1067290650Shselaskyenum { 1068290650Shselasky MLX5_HASH_FIELD_SEL_SRC_IP = 1 << 0, 1069290650Shselasky MLX5_HASH_FIELD_SEL_DST_IP = 1 << 1, 1070290650Shselasky MLX5_HASH_FIELD_SEL_L4_SPORT = 1 << 2, 1071290650Shselasky MLX5_HASH_FIELD_SEL_L4_DPORT = 1 << 3, 1072290650Shselasky MLX5_HASH_FIELD_SEL_IPSEC_SPI = 1 << 4, 1073290650Shselasky}; 1074290650Shselasky 1075290650Shselaskyenum { 1076290650Shselasky MLX5_MATCH_OUTER_HEADERS = 1 << 0, 1077290650Shselasky MLX5_MATCH_MISC_PARAMETERS = 1 << 1, 1078290650Shselasky MLX5_MATCH_INNER_HEADERS = 1 << 2, 1079290650Shselasky 1080290650Shselasky}; 1081290650Shselasky 1082290650Shselaskyenum { 1083290650Shselasky MLX5_FLOW_TABLE_TYPE_NIC_RCV = 0, 1084290650Shselasky MLX5_FLOW_TABLE_TYPE_EGRESS_ACL = 2, 1085290650Shselasky MLX5_FLOW_TABLE_TYPE_INGRESS_ACL = 3, 1086290650Shselasky MLX5_FLOW_TABLE_TYPE_ESWITCH = 4, 1087306244Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_RX = 5, 1088306244Shselasky MLX5_FLOW_TABLE_TYPE_SNIFFER_TX = 6, 1089290650Shselasky}; 1090290650Shselasky 1091290650Shselaskyenum { 1092290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_NONE = 0, 1093290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_IF_NO_VLAN = 1, 1094290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_CVLAN_INSERT_OVERWRITE = 2 1095290650Shselasky}; 1096290650Shselasky 1097290650Shselaskyenum { 1098290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_STRIP = 1 << 0, 1099290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_STRIP = 1 << 1, 1100290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_SVLAN_INSERT = 1 << 2, 1101290650Shselasky MLX5_MODIFY_ESW_VPORT_CONTEXT_FIELD_SELECT_CVLAN_INSERT = 1 << 3 1102290650Shselasky}; 1103290650Shselasky 1104292196Shselaskyenum { 1105292196Shselasky MLX5_UC_ADDR_CHANGE = (1 << 0), 1106292196Shselasky MLX5_MC_ADDR_CHANGE = (1 << 1), 1107292196Shselasky MLX5_VLAN_CHANGE = (1 << 2), 1108292196Shselasky MLX5_PROMISC_CHANGE = (1 << 3), 1109292196Shselasky MLX5_MTU_CHANGE = (1 << 4), 1110292196Shselasky}; 1111292196Shselasky 1112292196Shselaskyenum mlx5_list_type { 1113292196Shselasky MLX5_NIC_VPORT_LIST_TYPE_UC = 0x0, 1114292196Shselasky MLX5_NIC_VPORT_LIST_TYPE_MC = 0x1, 1115292196Shselasky MLX5_NIC_VPORT_LIST_TYPE_VLAN = 0x2, 1116292196Shselasky}; 1117292196Shselasky 1118292196Shselaskyenum { 1119292196Shselasky MLX5_ESW_VPORT_ADMIN_STATE_DOWN = 0x0, 1120292196Shselasky MLX5_ESW_VPORT_ADMIN_STATE_UP = 0x1, 1121292196Shselasky MLX5_ESW_VPORT_ADMIN_STATE_AUTO = 0x2, 1122292196Shselasky}; 1123293155Shselasky 1124290650Shselasky/* MLX5 DEV CAPs */ 1125290650Shselasky 1126290650Shselasky/* TODO: EAT.ME */ 1127290650Shselaskyenum mlx5_cap_mode { 1128290650Shselasky HCA_CAP_OPMOD_GET_MAX = 0, 1129290650Shselasky HCA_CAP_OPMOD_GET_CUR = 1, 1130290650Shselasky}; 1131290650Shselasky 1132290650Shselaskyenum mlx5_cap_type { 1133290650Shselasky MLX5_CAP_GENERAL = 0, 1134290650Shselasky MLX5_CAP_ETHERNET_OFFLOADS, 1135290650Shselasky MLX5_CAP_ODP, 1136290650Shselasky MLX5_CAP_ATOMIC, 1137290650Shselasky MLX5_CAP_ROCE, 1138290650Shselasky MLX5_CAP_IPOIB_OFFLOADS, 1139290650Shselasky MLX5_CAP_EOIB_OFFLOADS, 1140290650Shselasky MLX5_CAP_FLOW_TABLE, 1141290650Shselasky MLX5_CAP_ESWITCH_FLOW_TABLE, 1142290650Shselasky MLX5_CAP_ESWITCH, 1143306244Shselasky MLX5_CAP_SNAPSHOT, 1144306244Shselasky MLX5_CAP_VECTOR_CALC, 1145306244Shselasky MLX5_CAP_QOS, 1146306244Shselasky MLX5_CAP_DEBUG, 1147290650Shselasky /* NUM OF CAP Types */ 1148290650Shselasky MLX5_CAP_NUM 1149290650Shselasky}; 1150290650Shselasky 1151290650Shselasky/* GET Dev Caps macros */ 1152290650Shselasky#define MLX5_CAP_GEN(mdev, cap) \ 1153290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_cur[MLX5_CAP_GENERAL], cap) 1154290650Shselasky 1155290650Shselasky#define MLX5_CAP_GEN_MAX(mdev, cap) \ 1156290650Shselasky MLX5_GET(cmd_hca_cap, mdev->hca_caps_max[MLX5_CAP_GENERAL], cap) 1157290650Shselasky 1158290650Shselasky#define MLX5_CAP_ETH(mdev, cap) \ 1159290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1160290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1161290650Shselasky 1162290650Shselasky#define MLX5_CAP_ETH_MAX(mdev, cap) \ 1163290650Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1164290650Shselasky mdev->hca_caps_max[MLX5_CAP_ETHERNET_OFFLOADS], cap) 1165290650Shselasky 1166290650Shselasky#define MLX5_CAP_ROCE(mdev, cap) \ 1167290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_cur[MLX5_CAP_ROCE], cap) 1168290650Shselasky 1169290650Shselasky#define MLX5_CAP_ROCE_MAX(mdev, cap) \ 1170290650Shselasky MLX5_GET(roce_cap, mdev->hca_caps_max[MLX5_CAP_ROCE], cap) 1171290650Shselasky 1172290650Shselasky#define MLX5_CAP_ATOMIC(mdev, cap) \ 1173290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_cur[MLX5_CAP_ATOMIC], cap) 1174290650Shselasky 1175290650Shselasky#define MLX5_CAP_ATOMIC_MAX(mdev, cap) \ 1176290650Shselasky MLX5_GET(atomic_caps, mdev->hca_caps_max[MLX5_CAP_ATOMIC], cap) 1177290650Shselasky 1178290650Shselasky#define MLX5_CAP_FLOWTABLE(mdev, cap) \ 1179290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_cur[MLX5_CAP_FLOW_TABLE], cap) 1180290650Shselasky 1181290650Shselasky#define MLX5_CAP_FLOWTABLE_MAX(mdev, cap) \ 1182290650Shselasky MLX5_GET(flow_table_nic_cap, mdev->hca_caps_max[MLX5_CAP_FLOW_TABLE], cap) 1183290650Shselasky 1184290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE(mdev, cap) \ 1185290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 1186290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1187290650Shselasky 1188290650Shselasky#define MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, cap) \ 1189290650Shselasky MLX5_GET(flow_table_eswitch_cap, \ 1190290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH_FLOW_TABLE], cap) 1191290650Shselasky 1192306244Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB(mdev, cap) \ 1193306244Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_nic_esw_fdb.cap) 1194292196Shselasky 1195306244Shselasky#define MLX5_CAP_ESW_FLOWTABLE_FDB_MAX(mdev, cap) \ 1196306244Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_nic_esw_fdb.cap) 1197292196Shselasky 1198306244Shselasky#define MLX5_CAP_ESW_EGRESS_ACL(mdev, cap) \ 1199306244Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_egress.cap) 1200292196Shselasky 1201306244Shselasky#define MLX5_CAP_ESW_EGRESS_ACL_MAX(mdev, cap) \ 1202306244Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_egress.cap) 1203292196Shselasky 1204306244Shselasky#define MLX5_CAP_ESW_INGRESS_ACL(mdev, cap) \ 1205306244Shselasky MLX5_CAP_ESW_FLOWTABLE(mdev, flow_table_properties_esw_acl_ingress.cap) 1206306244Shselasky 1207306244Shselasky#define MLX5_CAP_ESW_INGRESS_ACL_MAX(mdev, cap) \ 1208306244Shselasky MLX5_CAP_ESW_FLOWTABLE_MAX(mdev, flow_table_properties_esw_acl_ingress.cap) 1209306244Shselasky 1210290650Shselasky#define MLX5_CAP_ESW(mdev, cap) \ 1211290650Shselasky MLX5_GET(e_switch_cap, \ 1212290650Shselasky mdev->hca_caps_cur[MLX5_CAP_ESWITCH], cap) 1213290650Shselasky 1214290650Shselasky#define MLX5_CAP_ESW_MAX(mdev, cap) \ 1215290650Shselasky MLX5_GET(e_switch_cap, \ 1216290650Shselasky mdev->hca_caps_max[MLX5_CAP_ESWITCH], cap) 1217290650Shselasky 1218290650Shselasky#define MLX5_CAP_ODP(mdev, cap)\ 1219290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_cur[MLX5_CAP_ODP], cap) 1220290650Shselasky 1221290650Shselasky#define MLX5_CAP_ODP_MAX(mdev, cap)\ 1222290650Shselasky MLX5_GET(odp_cap, mdev->hca_caps_max[MLX5_CAP_ODP], cap) 1223290650Shselasky 1224306244Shselasky#define MLX5_CAP_SNAPSHOT(mdev, cap) \ 1225306244Shselasky MLX5_GET(snapshot_cap, \ 1226306244Shselasky mdev->hca_caps_cur[MLX5_CAP_SNAPSHOT], cap) 1227306244Shselasky 1228306244Shselasky#define MLX5_CAP_SNAPSHOT_MAX(mdev, cap) \ 1229306244Shselasky MLX5_GET(snapshot_cap, \ 1230306244Shselasky mdev->hca_caps_max[MLX5_CAP_SNAPSHOT], cap) 1231306244Shselasky 1232306244Shselasky#define MLX5_CAP_EOIB_OFFLOADS(mdev, cap) \ 1233306244Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1234306244Shselasky mdev->hca_caps_cur[MLX5_CAP_EOIB_OFFLOADS], cap) 1235306244Shselasky 1236306244Shselasky#define MLX5_CAP_EOIB_OFFLOADS_MAX(mdev, cap) \ 1237306244Shselasky MLX5_GET(per_protocol_networking_offload_caps,\ 1238306244Shselasky mdev->hca_caps_max[MLX5_CAP_EOIB_OFFLOADS], cap) 1239306244Shselasky 1240306244Shselasky#define MLX5_CAP_DEBUG(mdev, cap) \ 1241306244Shselasky MLX5_GET(debug_cap, \ 1242306244Shselasky mdev->hca_caps_cur[MLX5_CAP_DEBUG], cap) 1243306244Shselasky 1244306244Shselasky#define MLX5_CAP_DEBUG_MAX(mdev, cap) \ 1245306244Shselasky MLX5_GET(debug_cap, \ 1246306244Shselasky mdev->hca_caps_max[MLX5_CAP_DEBUG], cap) 1247306244Shselasky 1248306244Shselasky#define MLX5_CAP_QOS(mdev, cap) \ 1249306244Shselasky MLX5_GET(qos_cap,\ 1250306244Shselasky mdev->hca_caps_cur[MLX5_CAP_QOS], cap) 1251306244Shselasky 1252306244Shselasky#define MLX5_CAP_QOS_MAX(mdev, cap) \ 1253306244Shselasky MLX5_GET(qos_cap,\ 1254306244Shselasky mdev->hca_caps_max[MLX5_CAP_QOS], cap) 1255306244Shselasky 1256290650Shselaskyenum { 1257290650Shselasky MLX5_CMD_STAT_OK = 0x0, 1258290650Shselasky MLX5_CMD_STAT_INT_ERR = 0x1, 1259290650Shselasky MLX5_CMD_STAT_BAD_OP_ERR = 0x2, 1260290650Shselasky MLX5_CMD_STAT_BAD_PARAM_ERR = 0x3, 1261290650Shselasky MLX5_CMD_STAT_BAD_SYS_STATE_ERR = 0x4, 1262290650Shselasky MLX5_CMD_STAT_BAD_RES_ERR = 0x5, 1263290650Shselasky MLX5_CMD_STAT_RES_BUSY = 0x6, 1264290650Shselasky MLX5_CMD_STAT_LIM_ERR = 0x8, 1265290650Shselasky MLX5_CMD_STAT_BAD_RES_STATE_ERR = 0x9, 1266290650Shselasky MLX5_CMD_STAT_IX_ERR = 0xa, 1267290650Shselasky MLX5_CMD_STAT_NO_RES_ERR = 0xf, 1268290650Shselasky MLX5_CMD_STAT_BAD_INP_LEN_ERR = 0x50, 1269290650Shselasky MLX5_CMD_STAT_BAD_OUTP_LEN_ERR = 0x51, 1270290650Shselasky MLX5_CMD_STAT_BAD_QP_STATE_ERR = 0x10, 1271290650Shselasky MLX5_CMD_STAT_BAD_PKT_ERR = 0x30, 1272290650Shselasky MLX5_CMD_STAT_BAD_SIZE_OUTS_CQES_ERR = 0x40, 1273290650Shselasky}; 1274290650Shselasky 1275290650Shselaskyenum { 1276290650Shselasky MLX5_IEEE_802_3_COUNTERS_GROUP = 0x0, 1277290650Shselasky MLX5_RFC_2863_COUNTERS_GROUP = 0x1, 1278290650Shselasky MLX5_RFC_2819_COUNTERS_GROUP = 0x2, 1279290650Shselasky MLX5_RFC_3635_COUNTERS_GROUP = 0x3, 1280290650Shselasky MLX5_ETHERNET_EXTENDED_COUNTERS_GROUP = 0x5, 1281308684Shselasky MLX5_ETHERNET_DISCARD_COUNTERS_GROUP = 0x6, 1282290650Shselasky MLX5_PER_PRIORITY_COUNTERS_GROUP = 0x10, 1283290650Shselasky MLX5_PER_TRAFFIC_CLASS_COUNTERS_GROUP = 0x11, 1284290650Shselasky MLX5_PHYSICAL_LAYER_COUNTERS_GROUP = 0x12, 1285308684Shselasky MLX5_INFINIBAND_PORT_COUNTERS_GROUP = 0x20, 1286290650Shselasky}; 1287290650Shselasky 1288290650Shselaskyenum { 1289306244Shselasky MLX5_PCIE_PERFORMANCE_COUNTERS_GROUP = 0x0, 1290306244Shselasky MLX5_PCIE_LANE_COUNTERS_GROUP = 0x1, 1291306244Shselasky MLX5_PCIE_TIMERS_AND_STATES_COUNTERS_GROUP = 0x2, 1292306244Shselasky}; 1293306244Shselasky 1294306244Shselaskyenum { 1295306244Shselasky MLX5_NUM_UUARS_PER_PAGE = MLX5_NON_FP_BF_REGS_PER_PAGE, 1296306244Shselasky MLX5_DEF_TOT_UUARS = 8 * MLX5_NUM_UUARS_PER_PAGE, 1297306244Shselasky}; 1298306244Shselasky 1299306244Shselaskyenum { 1300306244Shselasky NUM_DRIVER_UARS = 4, 1301306244Shselasky NUM_LOW_LAT_UUARS = 4, 1302306244Shselasky}; 1303306244Shselasky 1304306244Shselaskyenum { 1305290650Shselasky MLX5_CAP_PORT_TYPE_IB = 0x0, 1306290650Shselasky MLX5_CAP_PORT_TYPE_ETH = 0x1, 1307290650Shselasky}; 1308290650Shselasky 1309290650Shselaskyenum { 1310290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_L2 = 0x0, 1311290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_VPORT_CONFIG = 0x1, 1312290650Shselasky MLX5_CMD_HCA_CAP_MIN_WQE_INLINE_MODE_NOT_REQUIRED = 0x2 1313290650Shselasky}; 1314290650Shselasky 1315337742Shselaskyenum mlx5_inline_modes { 1316337742Shselasky MLX5_INLINE_MODE_NONE, 1317337742Shselasky MLX5_INLINE_MODE_L2, 1318337742Shselasky MLX5_INLINE_MODE_IP, 1319337742Shselasky MLX5_INLINE_MODE_TCP_UDP, 1320337742Shselasky}; 1321337742Shselasky 1322290650Shselaskyenum { 1323290650Shselasky MLX5_QUERY_VPORT_STATE_OUT_STATE_FOLLOW = 0x2, 1324290650Shselasky}; 1325290650Shselasky 1326290650Shselaskystatic inline u16 mlx5_to_sw_pkey_sz(int pkey_sz) 1327290650Shselasky{ 1328290650Shselasky if (pkey_sz > MLX5_MAX_LOG_PKEY_TABLE) 1329290650Shselasky return 0; 1330290650Shselasky return MLX5_MIN_PKEY_TABLE_SIZE << pkey_sz; 1331290650Shselasky} 1332290650Shselasky 1333290650Shselaskystruct mlx5_ifc_mcia_reg_bits { 1334290650Shselasky u8 l[0x1]; 1335290650Shselasky u8 reserved_0[0x7]; 1336290650Shselasky u8 module[0x8]; 1337290650Shselasky u8 reserved_1[0x8]; 1338290650Shselasky u8 status[0x8]; 1339290650Shselasky 1340290650Shselasky u8 i2c_device_address[0x8]; 1341290650Shselasky u8 page_number[0x8]; 1342290650Shselasky u8 device_address[0x10]; 1343290650Shselasky 1344290650Shselasky u8 reserved_2[0x10]; 1345290650Shselasky u8 size[0x10]; 1346290650Shselasky 1347290650Shselasky u8 reserved_3[0x20]; 1348290650Shselasky 1349290650Shselasky u8 dword_0[0x20]; 1350290650Shselasky u8 dword_1[0x20]; 1351290650Shselasky u8 dword_2[0x20]; 1352290650Shselasky u8 dword_3[0x20]; 1353290650Shselasky u8 dword_4[0x20]; 1354290650Shselasky u8 dword_5[0x20]; 1355290650Shselasky u8 dword_6[0x20]; 1356290650Shselasky u8 dword_7[0x20]; 1357290650Shselasky u8 dword_8[0x20]; 1358290650Shselasky u8 dword_9[0x20]; 1359290650Shselasky u8 dword_10[0x20]; 1360290650Shselasky u8 dword_11[0x20]; 1361290650Shselasky}; 1362290650Shselasky 1363290650Shselasky#define MLX5_CMD_OP_QUERY_EEPROM 0x93c 1364293155Shselasky 1365293155Shselaskystruct mlx5_mini_cqe8 { 1366293155Shselasky union { 1367308682Shselasky __be32 rx_hash_result; 1368308682Shselasky __be16 checksum; 1369308682Shselasky __be16 rsvd; 1370293155Shselasky struct { 1371308682Shselasky __be16 wqe_counter; 1372293155Shselasky u8 s_wqe_opcode; 1373293155Shselasky u8 reserved; 1374293155Shselasky } s_wqe_info; 1375293155Shselasky }; 1376308682Shselasky __be32 byte_cnt; 1377293155Shselasky}; 1378293155Shselasky 1379293155Shselaskyenum { 1380293155Shselasky MLX5_NO_INLINE_DATA, 1381293155Shselasky MLX5_INLINE_DATA32_SEG, 1382293155Shselasky MLX5_INLINE_DATA64_SEG, 1383293155Shselasky MLX5_COMPRESSED, 1384293155Shselasky}; 1385293155Shselasky 1386293155Shselaskyenum mlx5_exp_cqe_zip_recv_type { 1387293155Shselasky MLX5_CQE_FORMAT_HASH, 1388293155Shselasky MLX5_CQE_FORMAT_CSUM, 1389293155Shselasky}; 1390293155Shselasky 1391293155Shselasky#define MLX5E_CQE_FORMAT_MASK 0xc 1392293155Shselaskystatic inline int mlx5_get_cqe_format(const struct mlx5_cqe64 *cqe) 1393293155Shselasky{ 1394293155Shselasky return (cqe->op_own & MLX5E_CQE_FORMAT_MASK) >> 2; 1395293155Shselasky} 1396293155Shselasky 1397306244Shselasky/* 8 regular priorities + 1 for multicast */ 1398306244Shselasky#define MLX5_NUM_BYPASS_FTS 9 1399306244Shselasky 1400290650Shselasky#endif /* MLX5_DEVICE_H */ 1401