atphy.c revision 266000 
1/*-
2 * Copyright (c) 2008, Pyun YongHyeon <yongari@FreeBSD.org>
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions
7 * are met:
8 * 1. Redistributions of source code must retain the above copyright
9 *    notice unmodified, this list of conditions, and the following
10 *    disclaimer.
11 * 2. Redistributions in binary form must reproduce the above copyright
12 *    notice, this list of conditions and the following disclaimer in the
13 *    documentation and/or other materials provided with the distribution.
14 *
15 * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND
16 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
17 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
18 * ARE DISCLAIMED.  IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE
19 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
20 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS
21 * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
22 * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
23 * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY
24 * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF
25 * SUCH DAMAGE.
26 */
27
28#include <sys/cdefs.h>
29__FBSDID("$FreeBSD: stable/10/sys/dev/mii/atphy.c 266000 2014-05-14 01:53:20Z ian $");
30
31/*
32 * Driver for the Attansic/Atheros F1 10/100/1000 PHY.
33 */
34
35#include <sys/param.h>
36#include <sys/systm.h>
37#include <sys/kernel.h>
38#include <sys/module.h>
39#include <sys/socket.h>
40#include <sys/bus.h>
41
42#include <net/if.h>
43#include <net/if_media.h>
44
45#include <dev/mii/mii.h>
46#include <dev/mii/miivar.h>
47#include "miidevs.h"
48
49#include <dev/mii/atphyreg.h>
50
51#include "miibus_if.h"
52
53static int atphy_probe(device_t);
54static int atphy_attach(device_t);
55
56static device_method_t atphy_methods[] = {
57	/* Device interface. */
58	DEVMETHOD(device_probe,		atphy_probe),
59	DEVMETHOD(device_attach,	atphy_attach),
60	DEVMETHOD(device_detach,	mii_phy_detach),
61	DEVMETHOD(device_shutdown,	bus_generic_shutdown),
62	DEVMETHOD_END
63};
64
65static devclass_t atphy_devclass;
66static driver_t atphy_driver = {
67	"atphy",
68	atphy_methods,
69	sizeof(struct mii_softc)
70};
71
72DRIVER_MODULE(atphy, miibus, atphy_driver, atphy_devclass, 0, 0);
73
74static int	atphy_service(struct mii_softc *, struct mii_data *, int);
75static void	atphy_status(struct mii_softc *);
76static void	atphy_reset(struct mii_softc *);
77static uint16_t	atphy_anar(struct ifmedia_entry *);
78static int	atphy_setmedia(struct mii_softc *, int);
79
80static const struct mii_phydesc atphys[] = {
81	MII_PHY_DESC(xxATHEROS, F1),
82	MII_PHY_DESC(xxATHEROS, F1_7),
83	MII_PHY_DESC(xxATHEROS, AR8021),
84	MII_PHY_DESC(xxATHEROS, F2),
85	MII_PHY_END
86};
87
88static const struct mii_phy_funcs atphy_funcs = {
89	atphy_service,
90	atphy_status,
91	atphy_reset
92};
93
94static int
95atphy_probe(device_t dev)
96{
97
98	return (mii_phy_dev_probe(dev, atphys, BUS_PROBE_DEFAULT));
99}
100
101static int
102atphy_attach(device_t dev)
103{
104
105	mii_phy_dev_attach(dev, MIIF_NOMANPAUSE, &atphy_funcs, 1);
106	return (0);
107}
108
109static int
110atphy_service(struct mii_softc *sc, struct mii_data *mii, int cmd)
111{
112	struct ifmedia_entry *ife = mii->mii_media.ifm_cur;
113	uint16_t anar, bmcr, bmsr;
114
115	switch (cmd) {
116	case MII_POLLSTAT:
117		break;
118
119	case MII_MEDIACHG:
120		/*
121		 * If the interface is not up, don't do anything.
122		 */
123		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
124			break;
125
126		if (IFM_SUBTYPE(ife->ifm_media) == IFM_AUTO ||
127		    IFM_SUBTYPE(ife->ifm_media) == IFM_1000_T) {
128			atphy_setmedia(sc, ife->ifm_media);
129			break;
130		}
131
132		bmcr = 0;
133		switch (IFM_SUBTYPE(ife->ifm_media)) {
134		case IFM_100_TX:
135			bmcr = BMCR_S100;
136			break;
137		case IFM_10_T:
138			bmcr = BMCR_S10;
139			break;
140		case IFM_NONE:
141			bmcr = PHY_READ(sc, MII_BMCR);
142			/*
143			 * XXX
144			 * Due to an unknown reason powering down PHY resulted
145			 * in unexpected results such as inaccessibility of
146			 * hardware of freshly rebooted system. Disable
147			 * powering down PHY until I got more information for
148			 * Attansic/Atheros PHY hardwares.
149			 */
150			PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_ISO);
151			goto done;
152		default:
153			return (EINVAL);
154		}
155
156		anar = atphy_anar(ife);
157		if ((ife->ifm_media & IFM_FDX) != 0) {
158			bmcr |= BMCR_FDX;
159			if ((ife->ifm_media & IFM_FLOW) != 0 ||
160			    (sc->mii_flags & MIIF_FORCEPAUSE) != 0)
161				anar |= ANAR_PAUSE_TOWARDS;
162		}
163
164		if ((sc->mii_extcapabilities & (EXTSR_1000TFDX |
165		    EXTSR_1000THDX)) != 0)
166			PHY_WRITE(sc, MII_100T2CR, 0);
167		PHY_WRITE(sc, MII_ANAR, anar | ANAR_CSMA);
168
169		/*
170		 * Reset the PHY so all changes take effect.
171		 */
172		PHY_WRITE(sc, MII_BMCR, bmcr | BMCR_RESET | BMCR_AUTOEN |
173		    BMCR_STARTNEG);
174done:
175		break;
176
177	case MII_TICK:
178		/*
179		 * Is the interface even up?
180		 */
181		if ((mii->mii_ifp->if_flags & IFF_UP) == 0)
182			return (0);
183
184		/*
185		 * Only used for autonegotiation.
186		 */
187		if (IFM_SUBTYPE(ife->ifm_media) != IFM_AUTO) {
188			sc->mii_ticks = 0;
189			break;
190		}
191
192		/*
193		 * Check for link.
194		 * Read the status register twice; BMSR_LINK is latch-low.
195		 */
196		bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
197		if (bmsr & BMSR_LINK) {
198			sc->mii_ticks = 0;
199			break;
200		}
201
202		/* Announce link loss right after it happens. */
203		if (sc->mii_ticks++ == 0)
204			break;
205		if (sc->mii_ticks <= sc->mii_anegticks)
206			return (0);
207
208		sc->mii_ticks = 0;
209		atphy_setmedia(sc, ife->ifm_media);
210		break;
211	}
212
213	/* Update the media status. */
214	PHY_STATUS(sc);
215
216	/* Callback if something changed. */
217	mii_phy_update(sc, cmd);
218	return (0);
219}
220
221static void
222atphy_status(struct mii_softc *sc)
223{
224	struct mii_data *mii = sc->mii_pdata;
225	uint32_t bmsr, bmcr, ssr;
226
227	mii->mii_media_status = IFM_AVALID;
228	mii->mii_media_active = IFM_ETHER;
229
230	bmsr = PHY_READ(sc, MII_BMSR) | PHY_READ(sc, MII_BMSR);
231	if ((bmsr & BMSR_LINK) != 0)
232		mii->mii_media_status |= IFM_ACTIVE;
233
234	bmcr = PHY_READ(sc, MII_BMCR);
235	if ((bmcr & BMCR_ISO) != 0) {
236		mii->mii_media_active |= IFM_NONE;
237		mii->mii_media_status = 0;
238		return;
239	}
240
241	if ((bmcr & BMCR_LOOP) != 0)
242		mii->mii_media_active |= IFM_LOOP;
243
244	ssr = PHY_READ(sc, ATPHY_SSR);
245	if ((ssr & ATPHY_SSR_SPD_DPLX_RESOLVED) == 0) {
246		/* Erg, still trying, I guess... */
247		mii->mii_media_active |= IFM_NONE;
248		return;
249	}
250
251	switch (ssr & ATPHY_SSR_SPEED_MASK) {
252	case ATPHY_SSR_1000MBS:
253		mii->mii_media_active |= IFM_1000_T;
254		/*
255		 * atphy(4) has a valid link so reset mii_ticks.
256		 * Resetting mii_ticks is needed in order to
257		 * detect link loss after auto-negotiation.
258		 */
259		sc->mii_ticks = 0;
260		break;
261	case ATPHY_SSR_100MBS:
262		mii->mii_media_active |= IFM_100_TX;
263		sc->mii_ticks = 0;
264		break;
265	case ATPHY_SSR_10MBS:
266		mii->mii_media_active |= IFM_10_T;
267		sc->mii_ticks = 0;
268		break;
269	default:
270		mii->mii_media_active |= IFM_NONE;
271		return;
272	}
273
274	if ((ssr & ATPHY_SSR_DUPLEX) != 0)
275		mii->mii_media_active |= IFM_FDX | mii_phy_flowstatus(sc);
276	else
277		mii->mii_media_active |= IFM_HDX;
278
279	if ((IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) &&
280	    (PHY_READ(sc, MII_100T2SR) & GTSR_MS_RES) != 0)
281		mii->mii_media_active |= IFM_ETH_MASTER;
282}
283
284static void
285atphy_reset(struct mii_softc *sc)
286{
287	struct ifmedia_entry *ife = sc->mii_pdata->mii_media.ifm_cur;
288	uint32_t reg;
289	int i;
290
291	/* Take PHY out of power down mode. */
292	PHY_WRITE(sc, 29, 0x29);
293	PHY_WRITE(sc, 30, 0);
294
295	reg = PHY_READ(sc, ATPHY_SCR);
296	/* Enable automatic crossover. */
297	reg |= ATPHY_SCR_AUTO_X_MODE;
298	/* Disable power down. */
299	reg &= ~ATPHY_SCR_MAC_PDOWN;
300	/* Enable CRS on Tx. */
301	reg |= ATPHY_SCR_ASSERT_CRS_ON_TX;
302	/* Auto correction for reversed cable polarity. */
303	reg |= ATPHY_SCR_POLARITY_REVERSAL;
304	PHY_WRITE(sc, ATPHY_SCR, reg);
305
306	/* Workaround F1 bug to reset phy. */
307	atphy_setmedia(sc, ife == NULL ? IFM_AUTO : ife->ifm_media);
308
309	for (i = 0; i < 1000; i++) {
310		DELAY(1);
311		if ((PHY_READ(sc, MII_BMCR) & BMCR_RESET) == 0)
312			break;
313	}
314}
315
316static uint16_t
317atphy_anar(struct ifmedia_entry *ife)
318{
319	uint16_t anar;
320
321	anar = 0;
322	switch (IFM_SUBTYPE(ife->ifm_media)) {
323	case IFM_AUTO:
324		anar |= ANAR_TX_FD | ANAR_TX | ANAR_10_FD | ANAR_10;
325		return (anar);
326	case IFM_1000_T:
327		return (anar);
328	case IFM_100_TX:
329		anar |= ANAR_TX;
330		break;
331	case IFM_10_T:
332		anar |= ANAR_10;
333		break;
334	default:
335		return (0);
336	}
337
338	if ((ife->ifm_media & IFM_FDX) != 0) {
339		if (IFM_SUBTYPE(ife->ifm_media) == IFM_100_TX)
340			anar |= ANAR_TX_FD;
341		else
342			anar |= ANAR_10_FD;
343	}
344
345	return (anar);
346}
347
348static int
349atphy_setmedia(struct mii_softc *sc, int media)
350{
351	uint16_t anar;
352
353	anar = BMSR_MEDIA_TO_ANAR(sc->mii_capabilities) | ANAR_CSMA;
354	if ((IFM_SUBTYPE(media) == IFM_AUTO || (media & IFM_FDX) != 0) &&
355	    ((media & IFM_FLOW) != 0 ||
356	    (sc->mii_flags & MIIF_FORCEPAUSE) != 0))
357		anar |= ANAR_PAUSE_TOWARDS;
358	PHY_WRITE(sc, MII_ANAR, anar);
359	if ((sc->mii_extcapabilities &
360	     (EXTSR_1000TFDX | EXTSR_1000THDX)) != 0)
361		PHY_WRITE(sc, MII_100T2CR, GTCR_ADV_1000TFDX |
362		    GTCR_ADV_1000THDX);
363	else if (sc->mii_mpd_model == MII_MODEL_xxATHEROS_F1) {
364		/*
365		 * AR8132 has 10/100 PHY and the PHY uses the same
366		 * model number of F1 gigabit PHY.  The PHY has no
367		 * ability to establish gigabit link so explicitly
368		 * disable 1000baseT configuration for the PHY.
369		 * Otherwise, there is a case that atphy(4) could
370		 * not establish a link against gigabit link partner
371		 * unless the link partner supports down-shifting.
372		 */
373		PHY_WRITE(sc, MII_100T2CR, 0);
374	}
375	PHY_WRITE(sc, MII_BMCR, BMCR_RESET | BMCR_AUTOEN | BMCR_STARTNEG);
376
377	return (EJUSTRETURN);
378}
379