if_lge.c revision 119291
1/* 2 * Copyright (c) 2001 Wind River Systems 3 * Copyright (c) 1997, 1998, 1999, 2000, 2001 4 * Bill Paul <william.paul@windriver.com>. All rights reserved. 5 * 6 * Redistribution and use in source and binary forms, with or without 7 * modification, are permitted provided that the following conditions 8 * are met: 9 * 1. Redistributions of source code must retain the above copyright 10 * notice, this list of conditions and the following disclaimer. 11 * 2. Redistributions in binary form must reproduce the above copyright 12 * notice, this list of conditions and the following disclaimer in the 13 * documentation and/or other materials provided with the distribution. 14 * 3. All advertising materials mentioning features or use of this software 15 * must display the following acknowledgement: 16 * This product includes software developed by Bill Paul. 17 * 4. Neither the name of the author nor the names of any co-contributors 18 * may be used to endorse or promote products derived from this software 19 * without specific prior written permission. 20 * 21 * THIS SOFTWARE IS PROVIDED BY Bill Paul AND CONTRIBUTORS ``AS IS'' AND 22 * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 23 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 24 * ARE DISCLAIMED. IN NO EVENT SHALL Bill Paul OR THE VOICES IN HIS HEAD 25 * BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 26 * CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 27 * SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 28 * INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 29 * CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 30 * ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF 31 * THE POSSIBILITY OF SUCH DAMAGE. 32 */ 33 34/* 35 * Level 1 LXT1001 gigabit ethernet driver for FreeBSD. Public 36 * documentation not available, but ask me nicely. 37 * 38 * The Level 1 chip is used on some D-Link, SMC and Addtron NICs. 39 * It's a 64-bit PCI part that supports TCP/IP checksum offload, 40 * VLAN tagging/insertion, GMII and TBI (1000baseX) ports. There 41 * are three supported methods for data transfer between host and 42 * NIC: programmed I/O, traditional scatter/gather DMA and Packet 43 * Propulsion Technology (tm) DMA. The latter mechanism is a form 44 * of double buffer DMA where the packet data is copied to a 45 * pre-allocated DMA buffer who's physical address has been loaded 46 * into a table at device initialization time. The rationale is that 47 * the virtual to physical address translation needed for normal 48 * scatter/gather DMA is more expensive than the data copy needed 49 * for double buffering. This may be true in Windows NT and the like, 50 * but it isn't true for us, at least on the x86 arch. This driver 51 * uses the scatter/gather I/O method for both TX and RX. 52 * 53 * The LXT1001 only supports TCP/IP checksum offload on receive. 54 * Also, the VLAN tagging is done using a 16-entry table which allows 55 * the chip to perform hardware filtering based on VLAN tags. Sadly, 56 * our vlan support doesn't currently play well with this kind of 57 * hardware support. 58 * 59 * Special thanks to: 60 * - Jeff James at Intel, for arranging to have the LXT1001 manual 61 * released (at long last) 62 * - Beny Chen at D-Link, for actually sending it to me 63 * - Brad Short and Keith Alexis at SMC, for sending me sample 64 * SMC9462SX and SMC9462TX adapters for testing 65 * - Paul Saab at Y!, for not killing me (though it remains to be seen 66 * if in fact he did me much of a favor) 67 */ 68 69#include <sys/cdefs.h> 70__FBSDID("$FreeBSD: head/sys/dev/lge/if_lge.c 119291 2003-08-22 07:39:05Z imp $"); 71 72#include <sys/param.h> 73#include <sys/systm.h> 74#include <sys/sockio.h> 75#include <sys/mbuf.h> 76#include <sys/malloc.h> 77#include <sys/kernel.h> 78#include <sys/socket.h> 79 80#include <net/if.h> 81#include <net/if_arp.h> 82#include <net/ethernet.h> 83#include <net/if_dl.h> 84#include <net/if_media.h> 85 86#include <net/bpf.h> 87 88#include <vm/vm.h> /* for vtophys */ 89#include <vm/pmap.h> /* for vtophys */ 90#include <machine/clock.h> /* for DELAY */ 91#include <machine/bus_pio.h> 92#include <machine/bus_memio.h> 93#include <machine/bus.h> 94#include <machine/resource.h> 95#include <sys/bus.h> 96#include <sys/rman.h> 97 98#include <dev/mii/mii.h> 99#include <dev/mii/miivar.h> 100 101#include <dev/pci/pcireg.h> 102#include <dev/pci/pcivar.h> 103 104#define LGE_USEIOSPACE 105 106#include <dev/lge/if_lgereg.h> 107 108/* "controller miibus0" required. See GENERIC if you get errors here. */ 109#include "miibus_if.h" 110 111/* 112 * Various supported device vendors/types and their names. 113 */ 114static struct lge_type lge_devs[] = { 115 { LGE_VENDORID, LGE_DEVICEID, "Level 1 Gigabit Ethernet" }, 116 { 0, 0, NULL } 117}; 118 119static int lge_probe(device_t); 120static int lge_attach(device_t); 121static int lge_detach(device_t); 122 123static int lge_alloc_jumbo_mem(struct lge_softc *); 124static void lge_free_jumbo_mem(struct lge_softc *); 125static void *lge_jalloc(struct lge_softc *); 126static void lge_jfree(void *, void *); 127 128static int lge_newbuf(struct lge_softc *, struct lge_rx_desc *, struct mbuf *); 129static int lge_encap(struct lge_softc *, struct mbuf *, u_int32_t *); 130static void lge_rxeof(struct lge_softc *, int); 131static void lge_rxeoc(struct lge_softc *); 132static void lge_txeof(struct lge_softc *); 133static void lge_intr(void *); 134static void lge_tick(void *); 135static void lge_start(struct ifnet *); 136static int lge_ioctl(struct ifnet *, u_long, caddr_t); 137static void lge_init(void *); 138static void lge_stop(struct lge_softc *); 139static void lge_watchdog(struct ifnet *); 140static void lge_shutdown(device_t); 141static int lge_ifmedia_upd(struct ifnet *); 142static void lge_ifmedia_sts(struct ifnet *, struct ifmediareq *); 143 144static void lge_eeprom_getword(struct lge_softc *, int, u_int16_t *); 145static void lge_read_eeprom(struct lge_softc *, caddr_t, int, int, int); 146 147static int lge_miibus_readreg(device_t, int, int); 148static int lge_miibus_writereg(device_t, int, int, int); 149static void lge_miibus_statchg(device_t); 150 151static void lge_setmulti(struct lge_softc *); 152static u_int32_t lge_crc(struct lge_softc *, caddr_t); 153static void lge_reset(struct lge_softc *); 154static int lge_list_rx_init(struct lge_softc *); 155static int lge_list_tx_init(struct lge_softc *); 156 157#ifdef LGE_USEIOSPACE 158#define LGE_RES SYS_RES_IOPORT 159#define LGE_RID LGE_PCI_LOIO 160#else 161#define LGE_RES SYS_RES_MEMORY 162#define LGE_RID LGE_PCI_LOMEM 163#endif 164 165static device_method_t lge_methods[] = { 166 /* Device interface */ 167 DEVMETHOD(device_probe, lge_probe), 168 DEVMETHOD(device_attach, lge_attach), 169 DEVMETHOD(device_detach, lge_detach), 170 DEVMETHOD(device_shutdown, lge_shutdown), 171 172 /* bus interface */ 173 DEVMETHOD(bus_print_child, bus_generic_print_child), 174 DEVMETHOD(bus_driver_added, bus_generic_driver_added), 175 176 /* MII interface */ 177 DEVMETHOD(miibus_readreg, lge_miibus_readreg), 178 DEVMETHOD(miibus_writereg, lge_miibus_writereg), 179 DEVMETHOD(miibus_statchg, lge_miibus_statchg), 180 181 { 0, 0 } 182}; 183 184static driver_t lge_driver = { 185 "lge", 186 lge_methods, 187 sizeof(struct lge_softc) 188}; 189 190static devclass_t lge_devclass; 191 192DRIVER_MODULE(lge, pci, lge_driver, lge_devclass, 0, 0); 193DRIVER_MODULE(miibus, lge, miibus_driver, miibus_devclass, 0, 0); 194MODULE_DEPEND(lge, pci, 1, 1, 1); 195MODULE_DEPEND(lge, ether, 1, 1, 1); 196MODULE_DEPEND(lge, miibus, 1, 1, 1); 197 198#define LGE_SETBIT(sc, reg, x) \ 199 CSR_WRITE_4(sc, reg, \ 200 CSR_READ_4(sc, reg) | (x)) 201 202#define LGE_CLRBIT(sc, reg, x) \ 203 CSR_WRITE_4(sc, reg, \ 204 CSR_READ_4(sc, reg) & ~(x)) 205 206#define SIO_SET(x) \ 207 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) | x) 208 209#define SIO_CLR(x) \ 210 CSR_WRITE_4(sc, LGE_MEAR, CSR_READ_4(sc, LGE_MEAR) & ~x) 211 212/* 213 * Read a word of data stored in the EEPROM at address 'addr.' 214 */ 215static void 216lge_eeprom_getword(sc, addr, dest) 217 struct lge_softc *sc; 218 int addr; 219 u_int16_t *dest; 220{ 221 register int i; 222 u_int32_t val; 223 224 CSR_WRITE_4(sc, LGE_EECTL, LGE_EECTL_CMD_READ| 225 LGE_EECTL_SINGLEACCESS|((addr >> 1) << 8)); 226 227 for (i = 0; i < LGE_TIMEOUT; i++) 228 if (!(CSR_READ_4(sc, LGE_EECTL) & LGE_EECTL_CMD_READ)) 229 break; 230 231 if (i == LGE_TIMEOUT) { 232 printf("lge%d: EEPROM read timed out\n", sc->lge_unit); 233 return; 234 } 235 236 val = CSR_READ_4(sc, LGE_EEDATA); 237 238 if (addr & 1) 239 *dest = (val >> 16) & 0xFFFF; 240 else 241 *dest = val & 0xFFFF; 242 243 return; 244} 245 246/* 247 * Read a sequence of words from the EEPROM. 248 */ 249static void 250lge_read_eeprom(sc, dest, off, cnt, swap) 251 struct lge_softc *sc; 252 caddr_t dest; 253 int off; 254 int cnt; 255 int swap; 256{ 257 int i; 258 u_int16_t word = 0, *ptr; 259 260 for (i = 0; i < cnt; i++) { 261 lge_eeprom_getword(sc, off + i, &word); 262 ptr = (u_int16_t *)(dest + (i * 2)); 263 if (swap) 264 *ptr = ntohs(word); 265 else 266 *ptr = word; 267 } 268 269 return; 270} 271 272static int 273lge_miibus_readreg(dev, phy, reg) 274 device_t dev; 275 int phy, reg; 276{ 277 struct lge_softc *sc; 278 int i; 279 280 sc = device_get_softc(dev); 281 282 /* 283 * If we have a non-PCS PHY, pretend that the internal 284 * autoneg stuff at PHY address 0 isn't there so that 285 * the miibus code will find only the GMII PHY. 286 */ 287 if (sc->lge_pcs == 0 && phy == 0) 288 return(0); 289 290 CSR_WRITE_4(sc, LGE_GMIICTL, (phy << 8) | reg | LGE_GMIICMD_READ); 291 292 for (i = 0; i < LGE_TIMEOUT; i++) 293 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 294 break; 295 296 if (i == LGE_TIMEOUT) { 297 printf("lge%d: PHY read timed out\n", sc->lge_unit); 298 return(0); 299 } 300 301 return(CSR_READ_4(sc, LGE_GMIICTL) >> 16); 302} 303 304static int 305lge_miibus_writereg(dev, phy, reg, data) 306 device_t dev; 307 int phy, reg, data; 308{ 309 struct lge_softc *sc; 310 int i; 311 312 sc = device_get_softc(dev); 313 314 CSR_WRITE_4(sc, LGE_GMIICTL, 315 (data << 16) | (phy << 8) | reg | LGE_GMIICMD_WRITE); 316 317 for (i = 0; i < LGE_TIMEOUT; i++) 318 if (!(CSR_READ_4(sc, LGE_GMIICTL) & LGE_GMIICTL_CMDBUSY)) 319 break; 320 321 if (i == LGE_TIMEOUT) { 322 printf("lge%d: PHY write timed out\n", sc->lge_unit); 323 return(0); 324 } 325 326 return(0); 327} 328 329static void 330lge_miibus_statchg(dev) 331 device_t dev; 332{ 333 struct lge_softc *sc; 334 struct mii_data *mii; 335 336 sc = device_get_softc(dev); 337 mii = device_get_softc(sc->lge_miibus); 338 339 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_SPEED); 340 switch (IFM_SUBTYPE(mii->mii_media_active)) { 341 case IFM_1000_T: 342 case IFM_1000_SX: 343 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 344 break; 345 case IFM_100_TX: 346 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_100); 347 break; 348 case IFM_10_T: 349 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_10); 350 break; 351 default: 352 /* 353 * Choose something, even if it's wrong. Clearing 354 * all the bits will hose autoneg on the internal 355 * PHY. 356 */ 357 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_SPEED_1000); 358 break; 359 } 360 361 if ((mii->mii_media_active & IFM_GMASK) == IFM_FDX) { 362 LGE_SETBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 363 } else { 364 LGE_CLRBIT(sc, LGE_GMIIMODE, LGE_GMIIMODE_FDX); 365 } 366 367 return; 368} 369 370static u_int32_t 371lge_crc(sc, addr) 372 struct lge_softc *sc; 373 caddr_t addr; 374{ 375 u_int32_t crc, carry; 376 int i, j; 377 u_int8_t c; 378 379 /* Compute CRC for the address value. */ 380 crc = 0xFFFFFFFF; /* initial value */ 381 382 for (i = 0; i < 6; i++) { 383 c = *(addr + i); 384 for (j = 0; j < 8; j++) { 385 carry = ((crc & 0x80000000) ? 1 : 0) ^ (c & 0x01); 386 crc <<= 1; 387 c >>= 1; 388 if (carry) 389 crc = (crc ^ 0x04c11db6) | carry; 390 } 391 } 392 393 /* 394 * return the filter bit position 395 */ 396 return((crc >> 26) & 0x0000003F); 397} 398 399static void 400lge_setmulti(sc) 401 struct lge_softc *sc; 402{ 403 struct ifnet *ifp; 404 struct ifmultiaddr *ifma; 405 u_int32_t h = 0, hashes[2] = { 0, 0 }; 406 407 ifp = &sc->arpcom.ac_if; 408 409 /* Make sure multicast hash table is enabled. */ 410 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_MCAST); 411 412 if (ifp->if_flags & IFF_ALLMULTI || ifp->if_flags & IFF_PROMISC) { 413 CSR_WRITE_4(sc, LGE_MAR0, 0xFFFFFFFF); 414 CSR_WRITE_4(sc, LGE_MAR1, 0xFFFFFFFF); 415 return; 416 } 417 418 /* first, zot all the existing hash bits */ 419 CSR_WRITE_4(sc, LGE_MAR0, 0); 420 CSR_WRITE_4(sc, LGE_MAR1, 0); 421 422 /* now program new ones */ 423 TAILQ_FOREACH(ifma, &ifp->if_multiaddrs, ifma_link) { 424 if (ifma->ifma_addr->sa_family != AF_LINK) 425 continue; 426 h = lge_crc(sc, LLADDR((struct sockaddr_dl *)ifma->ifma_addr)); 427 if (h < 32) 428 hashes[0] |= (1 << h); 429 else 430 hashes[1] |= (1 << (h - 32)); 431 } 432 433 CSR_WRITE_4(sc, LGE_MAR0, hashes[0]); 434 CSR_WRITE_4(sc, LGE_MAR1, hashes[1]); 435 436 return; 437} 438 439static void 440lge_reset(sc) 441 struct lge_softc *sc; 442{ 443 register int i; 444 445 LGE_SETBIT(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_SOFTRST); 446 447 for (i = 0; i < LGE_TIMEOUT; i++) { 448 if (!(CSR_READ_4(sc, LGE_MODE1) & LGE_MODE1_SOFTRST)) 449 break; 450 } 451 452 if (i == LGE_TIMEOUT) 453 printf("lge%d: reset never completed\n", sc->lge_unit); 454 455 /* Wait a little while for the chip to get its brains in order. */ 456 DELAY(1000); 457 458 return; 459} 460 461/* 462 * Probe for a Level 1 chip. Check the PCI vendor and device 463 * IDs against our list and return a device name if we find a match. 464 */ 465static int 466lge_probe(dev) 467 device_t dev; 468{ 469 struct lge_type *t; 470 471 t = lge_devs; 472 473 while(t->lge_name != NULL) { 474 if ((pci_get_vendor(dev) == t->lge_vid) && 475 (pci_get_device(dev) == t->lge_did)) { 476 device_set_desc(dev, t->lge_name); 477 return(0); 478 } 479 t++; 480 } 481 482 return(ENXIO); 483} 484 485/* 486 * Attach the interface. Allocate softc structures, do ifmedia 487 * setup and ethernet/BPF attach. 488 */ 489static int 490lge_attach(dev) 491 device_t dev; 492{ 493 int s; 494 u_char eaddr[ETHER_ADDR_LEN]; 495 struct lge_softc *sc; 496 struct ifnet *ifp; 497 int unit, error = 0, rid; 498 499 s = splimp(); 500 501 sc = device_get_softc(dev); 502 unit = device_get_unit(dev); 503 bzero(sc, sizeof(struct lge_softc)); 504#ifndef BURN_BRIDGES 505 /* 506 * Handle power management nonsense. 507 */ 508 if (pci_get_powerstate(dev) != PCI_POWERSTATE_D0) { 509 u_int32_t iobase, membase, irq; 510 511 /* Save important PCI config data. */ 512 iobase = pci_read_config(dev, LGE_PCI_LOIO, 4); 513 membase = pci_read_config(dev, LGE_PCI_LOMEM, 4); 514 irq = pci_read_config(dev, LGE_PCI_INTLINE, 4); 515 516 /* Reset the power state. */ 517 printf("lge%d: chip is in D%d power mode " 518 "-- setting to D0\n", unit, 519 pci_get_powerstate(dev)); 520 pci_set_powerstate(dev, PCI_POWERSTATE_D0); 521 522 /* Restore PCI config data. */ 523 pci_write_config(dev, LGE_PCI_LOIO, iobase, 4); 524 pci_write_config(dev, LGE_PCI_LOMEM, membase, 4); 525 pci_write_config(dev, LGE_PCI_INTLINE, irq, 4); 526 } 527#endif 528 /* 529 * Map control/status registers. 530 */ 531 pci_enable_busmaster(dev); 532 533 rid = LGE_RID; 534 sc->lge_res = bus_alloc_resource(dev, LGE_RES, &rid, 535 0, ~0, 1, RF_ACTIVE); 536 537 if (sc->lge_res == NULL) { 538 printf("lge%d: couldn't map ports/memory\n", unit); 539 error = ENXIO; 540 goto fail; 541 } 542 543 sc->lge_btag = rman_get_bustag(sc->lge_res); 544 sc->lge_bhandle = rman_get_bushandle(sc->lge_res); 545 546 /* Allocate interrupt */ 547 rid = 0; 548 sc->lge_irq = bus_alloc_resource(dev, SYS_RES_IRQ, &rid, 0, ~0, 1, 549 RF_SHAREABLE | RF_ACTIVE); 550 551 if (sc->lge_irq == NULL) { 552 printf("lge%d: couldn't map interrupt\n", unit); 553 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 554 error = ENXIO; 555 goto fail; 556 } 557 558 error = bus_setup_intr(dev, sc->lge_irq, INTR_TYPE_NET, 559 lge_intr, sc, &sc->lge_intrhand); 560 561 if (error) { 562 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 563 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 564 printf("lge%d: couldn't set up irq\n", unit); 565 goto fail; 566 } 567 568 /* Reset the adapter. */ 569 lge_reset(sc); 570 571 /* 572 * Get station address from the EEPROM. 573 */ 574 lge_read_eeprom(sc, (caddr_t)&eaddr[0], LGE_EE_NODEADDR_0, 1, 0); 575 lge_read_eeprom(sc, (caddr_t)&eaddr[2], LGE_EE_NODEADDR_1, 1, 0); 576 lge_read_eeprom(sc, (caddr_t)&eaddr[4], LGE_EE_NODEADDR_2, 1, 0); 577 578 /* 579 * A Level 1 chip was detected. Inform the world. 580 */ 581 printf("lge%d: Ethernet address: %6D\n", unit, eaddr, ":"); 582 583 sc->lge_unit = unit; 584 callout_handle_init(&sc->lge_stat_ch); 585 bcopy(eaddr, (char *)&sc->arpcom.ac_enaddr, ETHER_ADDR_LEN); 586 587 sc->lge_ldata = contigmalloc(sizeof(struct lge_list_data), M_DEVBUF, 588 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 589 590 if (sc->lge_ldata == NULL) { 591 printf("lge%d: no memory for list buffers!\n", unit); 592 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 593 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 594 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 595 error = ENXIO; 596 goto fail; 597 } 598 bzero(sc->lge_ldata, sizeof(struct lge_list_data)); 599 600 /* Try to allocate memory for jumbo buffers. */ 601 if (lge_alloc_jumbo_mem(sc)) { 602 printf("lge%d: jumbo buffer allocation failed\n", 603 sc->lge_unit); 604 contigfree(sc->lge_ldata, 605 sizeof(struct lge_list_data), M_DEVBUF); 606 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 607 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 608 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 609 error = ENXIO; 610 goto fail; 611 } 612 613 ifp = &sc->arpcom.ac_if; 614 ifp->if_softc = sc; 615 ifp->if_unit = unit; 616 ifp->if_name = "lge"; 617 ifp->if_mtu = ETHERMTU; 618 ifp->if_flags = IFF_BROADCAST | IFF_SIMPLEX | IFF_MULTICAST; 619 ifp->if_ioctl = lge_ioctl; 620 ifp->if_output = ether_output; 621 ifp->if_start = lge_start; 622 ifp->if_watchdog = lge_watchdog; 623 ifp->if_init = lge_init; 624 ifp->if_baudrate = 1000000000; 625 ifp->if_snd.ifq_maxlen = LGE_TX_LIST_CNT - 1; 626 ifp->if_capabilities = IFCAP_RXCSUM; 627 ifp->if_capenable = ifp->if_capabilities; 628 629 if (CSR_READ_4(sc, LGE_GMIIMODE) & LGE_GMIIMODE_PCSENH) 630 sc->lge_pcs = 1; 631 else 632 sc->lge_pcs = 0; 633 634 /* 635 * Do MII setup. 636 */ 637 if (mii_phy_probe(dev, &sc->lge_miibus, 638 lge_ifmedia_upd, lge_ifmedia_sts)) { 639 printf("lge%d: MII without any PHY!\n", sc->lge_unit); 640 contigfree(sc->lge_ldata, 641 sizeof(struct lge_list_data), M_DEVBUF); 642 lge_free_jumbo_mem(sc); 643 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 644 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 645 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 646 error = ENXIO; 647 goto fail; 648 } 649 650 /* 651 * Call MI attach routine. 652 */ 653 ether_ifattach(ifp, eaddr); 654 callout_handle_init(&sc->lge_stat_ch); 655 656fail: 657 splx(s); 658 return(error); 659} 660 661static int 662lge_detach(dev) 663 device_t dev; 664{ 665 struct lge_softc *sc; 666 struct ifnet *ifp; 667 int s; 668 669 s = splimp(); 670 671 sc = device_get_softc(dev); 672 ifp = &sc->arpcom.ac_if; 673 674 lge_reset(sc); 675 lge_stop(sc); 676 ether_ifdetach(ifp); 677 678 bus_generic_detach(dev); 679 device_delete_child(dev, sc->lge_miibus); 680 681 bus_teardown_intr(dev, sc->lge_irq, sc->lge_intrhand); 682 bus_release_resource(dev, SYS_RES_IRQ, 0, sc->lge_irq); 683 bus_release_resource(dev, LGE_RES, LGE_RID, sc->lge_res); 684 685 contigfree(sc->lge_ldata, sizeof(struct lge_list_data), M_DEVBUF); 686 lge_free_jumbo_mem(sc); 687 688 splx(s); 689 690 return(0); 691} 692 693/* 694 * Initialize the transmit descriptors. 695 */ 696static int 697lge_list_tx_init(sc) 698 struct lge_softc *sc; 699{ 700 struct lge_list_data *ld; 701 struct lge_ring_data *cd; 702 int i; 703 704 cd = &sc->lge_cdata; 705 ld = sc->lge_ldata; 706 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 707 ld->lge_tx_list[i].lge_mbuf = NULL; 708 ld->lge_tx_list[i].lge_ctl = 0; 709 } 710 711 cd->lge_tx_prod = cd->lge_tx_cons = 0; 712 713 return(0); 714} 715 716 717/* 718 * Initialize the RX descriptors and allocate mbufs for them. Note that 719 * we arralge the descriptors in a closed ring, so that the last descriptor 720 * points back to the first. 721 */ 722static int 723lge_list_rx_init(sc) 724 struct lge_softc *sc; 725{ 726 struct lge_list_data *ld; 727 struct lge_ring_data *cd; 728 int i; 729 730 ld = sc->lge_ldata; 731 cd = &sc->lge_cdata; 732 733 cd->lge_rx_prod = cd->lge_rx_cons = 0; 734 735 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 736 737 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 738 if (CSR_READ_1(sc, LGE_RXCMDFREE_8BIT) == 0) 739 break; 740 if (lge_newbuf(sc, &ld->lge_rx_list[i], NULL) == ENOBUFS) 741 return(ENOBUFS); 742 } 743 744 /* Clear possible 'rx command queue empty' interrupt. */ 745 CSR_READ_4(sc, LGE_ISR); 746 747 return(0); 748} 749 750/* 751 * Initialize an RX descriptor and attach an MBUF cluster. 752 */ 753static int 754lge_newbuf(sc, c, m) 755 struct lge_softc *sc; 756 struct lge_rx_desc *c; 757 struct mbuf *m; 758{ 759 struct mbuf *m_new = NULL; 760 caddr_t *buf = NULL; 761 762 if (m == NULL) { 763 MGETHDR(m_new, M_DONTWAIT, MT_DATA); 764 if (m_new == NULL) { 765 printf("lge%d: no memory for rx list " 766 "-- packet dropped!\n", sc->lge_unit); 767 return(ENOBUFS); 768 } 769 770 /* Allocate the jumbo buffer */ 771 buf = lge_jalloc(sc); 772 if (buf == NULL) { 773#ifdef LGE_VERBOSE 774 printf("lge%d: jumbo allocation failed " 775 "-- packet dropped!\n", sc->lge_unit); 776#endif 777 m_freem(m_new); 778 return(ENOBUFS); 779 } 780 /* Attach the buffer to the mbuf */ 781 m_new->m_data = (void *)buf; 782 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 783 MEXTADD(m_new, buf, LGE_JUMBO_FRAMELEN, lge_jfree, 784 (struct lge_softc *)sc, 0, EXT_NET_DRV); 785 } else { 786 m_new = m; 787 m_new->m_len = m_new->m_pkthdr.len = LGE_JUMBO_FRAMELEN; 788 m_new->m_data = m_new->m_ext.ext_buf; 789 } 790 791 /* 792 * Adjust alignment so packet payload begins on a 793 * longword boundary. Mandatory for Alpha, useful on 794 * x86 too. 795 */ 796 m_adj(m_new, ETHER_ALIGN); 797 798 c->lge_mbuf = m_new; 799 c->lge_fragptr_hi = 0; 800 c->lge_fragptr_lo = vtophys(mtod(m_new, caddr_t)); 801 c->lge_fraglen = m_new->m_len; 802 c->lge_ctl = m_new->m_len | LGE_RXCTL_WANTINTR | LGE_FRAGCNT(1); 803 c->lge_sts = 0; 804 805 /* 806 * Put this buffer in the RX command FIFO. To do this, 807 * we just write the physical address of the descriptor 808 * into the RX descriptor address registers. Note that 809 * there are two registers, one high DWORD and one low 810 * DWORD, which lets us specify a 64-bit address if 811 * desired. We only use a 32-bit address for now. 812 * Writing to the low DWORD register is what actually 813 * causes the command to be issued, so we do that 814 * last. 815 */ 816 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_LO, vtophys(c)); 817 LGE_INC(sc->lge_cdata.lge_rx_prod, LGE_RX_LIST_CNT); 818 819 return(0); 820} 821 822static int 823lge_alloc_jumbo_mem(sc) 824 struct lge_softc *sc; 825{ 826 caddr_t ptr; 827 register int i; 828 struct lge_jpool_entry *entry; 829 830 /* Grab a big chunk o' storage. */ 831 sc->lge_cdata.lge_jumbo_buf = contigmalloc(LGE_JMEM, M_DEVBUF, 832 M_NOWAIT, 0, 0xffffffff, PAGE_SIZE, 0); 833 834 if (sc->lge_cdata.lge_jumbo_buf == NULL) { 835 printf("lge%d: no memory for jumbo buffers!\n", sc->lge_unit); 836 return(ENOBUFS); 837 } 838 839 SLIST_INIT(&sc->lge_jfree_listhead); 840 SLIST_INIT(&sc->lge_jinuse_listhead); 841 842 /* 843 * Now divide it up into 9K pieces and save the addresses 844 * in an array. 845 */ 846 ptr = sc->lge_cdata.lge_jumbo_buf; 847 for (i = 0; i < LGE_JSLOTS; i++) { 848 sc->lge_cdata.lge_jslots[i] = ptr; 849 ptr += LGE_JLEN; 850 entry = malloc(sizeof(struct lge_jpool_entry), 851 M_DEVBUF, M_NOWAIT); 852 if (entry == NULL) { 853 printf("lge%d: no memory for jumbo " 854 "buffer queue!\n", sc->lge_unit); 855 return(ENOBUFS); 856 } 857 entry->slot = i; 858 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, 859 entry, jpool_entries); 860 } 861 862 return(0); 863} 864 865static void 866lge_free_jumbo_mem(sc) 867 struct lge_softc *sc; 868{ 869 int i; 870 struct lge_jpool_entry *entry; 871 872 for (i = 0; i < LGE_JSLOTS; i++) { 873 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 874 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 875 free(entry, M_DEVBUF); 876 } 877 878 contigfree(sc->lge_cdata.lge_jumbo_buf, LGE_JMEM, M_DEVBUF); 879 880 return; 881} 882 883/* 884 * Allocate a jumbo buffer. 885 */ 886static void * 887lge_jalloc(sc) 888 struct lge_softc *sc; 889{ 890 struct lge_jpool_entry *entry; 891 892 entry = SLIST_FIRST(&sc->lge_jfree_listhead); 893 894 if (entry == NULL) { 895#ifdef LGE_VERBOSE 896 printf("lge%d: no free jumbo buffers\n", sc->lge_unit); 897#endif 898 return(NULL); 899 } 900 901 SLIST_REMOVE_HEAD(&sc->lge_jfree_listhead, jpool_entries); 902 SLIST_INSERT_HEAD(&sc->lge_jinuse_listhead, entry, jpool_entries); 903 return(sc->lge_cdata.lge_jslots[entry->slot]); 904} 905 906/* 907 * Release a jumbo buffer. 908 */ 909static void 910lge_jfree(buf, args) 911 void *buf; 912 void *args; 913{ 914 struct lge_softc *sc; 915 int i; 916 struct lge_jpool_entry *entry; 917 918 /* Extract the softc struct pointer. */ 919 sc = args; 920 921 if (sc == NULL) 922 panic("lge_jfree: can't find softc pointer!"); 923 924 /* calculate the slot this buffer belongs to */ 925 i = ((vm_offset_t)buf 926 - (vm_offset_t)sc->lge_cdata.lge_jumbo_buf) / LGE_JLEN; 927 928 if ((i < 0) || (i >= LGE_JSLOTS)) 929 panic("lge_jfree: asked to free buffer that we don't manage!"); 930 931 entry = SLIST_FIRST(&sc->lge_jinuse_listhead); 932 if (entry == NULL) 933 panic("lge_jfree: buffer not in use!"); 934 entry->slot = i; 935 SLIST_REMOVE_HEAD(&sc->lge_jinuse_listhead, jpool_entries); 936 SLIST_INSERT_HEAD(&sc->lge_jfree_listhead, entry, jpool_entries); 937 938 return; 939} 940 941/* 942 * A frame has been uploaded: pass the resulting mbuf chain up to 943 * the higher level protocols. 944 */ 945static void 946lge_rxeof(sc, cnt) 947 struct lge_softc *sc; 948 int cnt; 949{ 950 struct mbuf *m; 951 struct ifnet *ifp; 952 struct lge_rx_desc *cur_rx; 953 int c, i, total_len = 0; 954 u_int32_t rxsts, rxctl; 955 956 ifp = &sc->arpcom.ac_if; 957 958 /* Find out how many frames were processed. */ 959 c = cnt; 960 i = sc->lge_cdata.lge_rx_cons; 961 962 /* Suck them in. */ 963 while(c) { 964 struct mbuf *m0 = NULL; 965 966 cur_rx = &sc->lge_ldata->lge_rx_list[i]; 967 rxctl = cur_rx->lge_ctl; 968 rxsts = cur_rx->lge_sts; 969 m = cur_rx->lge_mbuf; 970 cur_rx->lge_mbuf = NULL; 971 total_len = LGE_RXBYTES(cur_rx); 972 LGE_INC(i, LGE_RX_LIST_CNT); 973 c--; 974 975 /* 976 * If an error occurs, update stats, clear the 977 * status word and leave the mbuf cluster in place: 978 * it should simply get re-used next time this descriptor 979 * comes up in the ring. 980 */ 981 if (rxctl & LGE_RXCTL_ERRMASK) { 982 ifp->if_ierrors++; 983 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 984 continue; 985 } 986 987 if (lge_newbuf(sc, &LGE_RXTAIL(sc), NULL) == ENOBUFS) { 988 m0 = m_devget(mtod(m, char *), total_len, ETHER_ALIGN, 989 ifp, NULL); 990 lge_newbuf(sc, &LGE_RXTAIL(sc), m); 991 if (m0 == NULL) { 992 printf("lge%d: no receive buffers " 993 "available -- packet dropped!\n", 994 sc->lge_unit); 995 ifp->if_ierrors++; 996 continue; 997 } 998 m = m0; 999 } else { 1000 m->m_pkthdr.rcvif = ifp; 1001 m->m_pkthdr.len = m->m_len = total_len; 1002 } 1003 1004 ifp->if_ipackets++; 1005 1006 /* Do IP checksum checking. */ 1007 if (rxsts & LGE_RXSTS_ISIP) 1008 m->m_pkthdr.csum_flags |= CSUM_IP_CHECKED; 1009 if (!(rxsts & LGE_RXSTS_IPCSUMERR)) 1010 m->m_pkthdr.csum_flags |= CSUM_IP_VALID; 1011 if ((rxsts & LGE_RXSTS_ISTCP && 1012 !(rxsts & LGE_RXSTS_TCPCSUMERR)) || 1013 (rxsts & LGE_RXSTS_ISUDP && 1014 !(rxsts & LGE_RXSTS_UDPCSUMERR))) { 1015 m->m_pkthdr.csum_flags |= 1016 CSUM_DATA_VALID|CSUM_PSEUDO_HDR; 1017 m->m_pkthdr.csum_data = 0xffff; 1018 } 1019 1020 (*ifp->if_input)(ifp, m); 1021 } 1022 1023 sc->lge_cdata.lge_rx_cons = i; 1024 1025 return; 1026} 1027 1028static void 1029lge_rxeoc(sc) 1030 struct lge_softc *sc; 1031{ 1032 struct ifnet *ifp; 1033 1034 ifp = &sc->arpcom.ac_if; 1035 ifp->if_flags &= ~IFF_RUNNING; 1036 lge_init(sc); 1037 return; 1038} 1039 1040/* 1041 * A frame was downloaded to the chip. It's safe for us to clean up 1042 * the list buffers. 1043 */ 1044 1045static void 1046lge_txeof(sc) 1047 struct lge_softc *sc; 1048{ 1049 struct lge_tx_desc *cur_tx = NULL; 1050 struct ifnet *ifp; 1051 u_int32_t idx, txdone; 1052 1053 ifp = &sc->arpcom.ac_if; 1054 1055 /* Clear the timeout timer. */ 1056 ifp->if_timer = 0; 1057 1058 /* 1059 * Go through our tx list and free mbufs for those 1060 * frames that have been transmitted. 1061 */ 1062 idx = sc->lge_cdata.lge_tx_cons; 1063 txdone = CSR_READ_1(sc, LGE_TXDMADONE_8BIT); 1064 1065 while (idx != sc->lge_cdata.lge_tx_prod && txdone) { 1066 cur_tx = &sc->lge_ldata->lge_tx_list[idx]; 1067 1068 ifp->if_opackets++; 1069 if (cur_tx->lge_mbuf != NULL) { 1070 m_freem(cur_tx->lge_mbuf); 1071 cur_tx->lge_mbuf = NULL; 1072 } 1073 cur_tx->lge_ctl = 0; 1074 1075 txdone--; 1076 LGE_INC(idx, LGE_TX_LIST_CNT); 1077 ifp->if_timer = 0; 1078 } 1079 1080 sc->lge_cdata.lge_tx_cons = idx; 1081 1082 if (cur_tx != NULL) 1083 ifp->if_flags &= ~IFF_OACTIVE; 1084 1085 return; 1086} 1087 1088static void 1089lge_tick(xsc) 1090 void *xsc; 1091{ 1092 struct lge_softc *sc; 1093 struct mii_data *mii; 1094 struct ifnet *ifp; 1095 int s; 1096 1097 s = splimp(); 1098 1099 sc = xsc; 1100 ifp = &sc->arpcom.ac_if; 1101 1102 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_SINGLE_COLL_PKTS); 1103 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1104 CSR_WRITE_4(sc, LGE_STATSIDX, LGE_STATS_MULTI_COLL_PKTS); 1105 ifp->if_collisions += CSR_READ_4(sc, LGE_STATSVAL); 1106 1107 if (!sc->lge_link) { 1108 mii = device_get_softc(sc->lge_miibus); 1109 mii_tick(mii); 1110 if (mii->mii_media_status & IFM_ACTIVE && 1111 IFM_SUBTYPE(mii->mii_media_active) != IFM_NONE) { 1112 sc->lge_link++; 1113 if (IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_SX|| 1114 IFM_SUBTYPE(mii->mii_media_active) == IFM_1000_T) 1115 printf("lge%d: gigabit link up\n", 1116 sc->lge_unit); 1117 if (ifp->if_snd.ifq_head != NULL) 1118 lge_start(ifp); 1119 } 1120 } 1121 1122 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1123 1124 splx(s); 1125 1126 return; 1127} 1128 1129static void 1130lge_intr(arg) 1131 void *arg; 1132{ 1133 struct lge_softc *sc; 1134 struct ifnet *ifp; 1135 u_int32_t status; 1136 1137 sc = arg; 1138 ifp = &sc->arpcom.ac_if; 1139 1140 /* Supress unwanted interrupts */ 1141 if (!(ifp->if_flags & IFF_UP)) { 1142 lge_stop(sc); 1143 return; 1144 } 1145 1146 for (;;) { 1147 /* 1148 * Reading the ISR register clears all interrupts, and 1149 * clears the 'interrupts enabled' bit in the IMR 1150 * register. 1151 */ 1152 status = CSR_READ_4(sc, LGE_ISR); 1153 1154 if ((status & LGE_INTRS) == 0) 1155 break; 1156 1157 if ((status & (LGE_ISR_TXCMDFIFO_EMPTY|LGE_ISR_TXDMA_DONE))) 1158 lge_txeof(sc); 1159 1160 if (status & LGE_ISR_RXDMA_DONE) 1161 lge_rxeof(sc, LGE_RX_DMACNT(status)); 1162 1163 if (status & LGE_ISR_RXCMDFIFO_EMPTY) 1164 lge_rxeoc(sc); 1165 1166 if (status & LGE_ISR_PHY_INTR) { 1167 sc->lge_link = 0; 1168 untimeout(lge_tick, sc, sc->lge_stat_ch); 1169 lge_tick(sc); 1170 } 1171 } 1172 1173 /* Re-enable interrupts. */ 1174 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0|LGE_IMR_INTR_ENB); 1175 1176 if (ifp->if_snd.ifq_head != NULL) 1177 lge_start(ifp); 1178 1179 return; 1180} 1181 1182/* 1183 * Encapsulate an mbuf chain in a descriptor by coupling the mbuf data 1184 * pointers to the fragment pointers. 1185 */ 1186static int 1187lge_encap(sc, m_head, txidx) 1188 struct lge_softc *sc; 1189 struct mbuf *m_head; 1190 u_int32_t *txidx; 1191{ 1192 struct lge_frag *f = NULL; 1193 struct lge_tx_desc *cur_tx; 1194 struct mbuf *m; 1195 int frag = 0, tot_len = 0; 1196 1197 /* 1198 * Start packing the mbufs in this chain into 1199 * the fragment pointers. Stop when we run out 1200 * of fragments or hit the end of the mbuf chain. 1201 */ 1202 m = m_head; 1203 cur_tx = &sc->lge_ldata->lge_tx_list[*txidx]; 1204 frag = 0; 1205 1206 for (m = m_head; m != NULL; m = m->m_next) { 1207 if (m->m_len != 0) { 1208 tot_len += m->m_len; 1209 f = &cur_tx->lge_frags[frag]; 1210 f->lge_fraglen = m->m_len; 1211 f->lge_fragptr_lo = vtophys(mtod(m, vm_offset_t)); 1212 f->lge_fragptr_hi = 0; 1213 frag++; 1214 } 1215 } 1216 1217 if (m != NULL) 1218 return(ENOBUFS); 1219 1220 cur_tx->lge_mbuf = m_head; 1221 cur_tx->lge_ctl = LGE_TXCTL_WANTINTR|LGE_FRAGCNT(frag)|tot_len; 1222 LGE_INC((*txidx), LGE_TX_LIST_CNT); 1223 1224 /* Queue for transmit */ 1225 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_LO, vtophys(cur_tx)); 1226 1227 return(0); 1228} 1229 1230/* 1231 * Main transmit routine. To avoid having to do mbuf copies, we put pointers 1232 * to the mbuf data regions directly in the transmit lists. We also save a 1233 * copy of the pointers since the transmit list fragment pointers are 1234 * physical addresses. 1235 */ 1236 1237static void 1238lge_start(ifp) 1239 struct ifnet *ifp; 1240{ 1241 struct lge_softc *sc; 1242 struct mbuf *m_head = NULL; 1243 u_int32_t idx; 1244 1245 sc = ifp->if_softc; 1246 1247 if (!sc->lge_link) 1248 return; 1249 1250 idx = sc->lge_cdata.lge_tx_prod; 1251 1252 if (ifp->if_flags & IFF_OACTIVE) 1253 return; 1254 1255 while(sc->lge_ldata->lge_tx_list[idx].lge_mbuf == NULL) { 1256 if (CSR_READ_1(sc, LGE_TXCMDFREE_8BIT) == 0) 1257 break; 1258 1259 IF_DEQUEUE(&ifp->if_snd, m_head); 1260 if (m_head == NULL) 1261 break; 1262 1263 if (lge_encap(sc, m_head, &idx)) { 1264 IF_PREPEND(&ifp->if_snd, m_head); 1265 ifp->if_flags |= IFF_OACTIVE; 1266 break; 1267 } 1268 1269 /* 1270 * If there's a BPF listener, bounce a copy of this frame 1271 * to him. 1272 */ 1273 BPF_MTAP(ifp, m_head); 1274 } 1275 1276 sc->lge_cdata.lge_tx_prod = idx; 1277 1278 /* 1279 * Set a timeout in case the chip goes out to lunch. 1280 */ 1281 ifp->if_timer = 5; 1282 1283 return; 1284} 1285 1286static void 1287lge_init(xsc) 1288 void *xsc; 1289{ 1290 struct lge_softc *sc = xsc; 1291 struct ifnet *ifp = &sc->arpcom.ac_if; 1292 struct mii_data *mii; 1293 int s; 1294 1295 if (ifp->if_flags & IFF_RUNNING) 1296 return; 1297 1298 s = splimp(); 1299 1300 /* 1301 * Cancel pending I/O and free all RX/TX buffers. 1302 */ 1303 lge_stop(sc); 1304 lge_reset(sc); 1305 1306 mii = device_get_softc(sc->lge_miibus); 1307 1308 /* Set MAC address */ 1309 CSR_WRITE_4(sc, LGE_PAR0, *(u_int32_t *)(&sc->arpcom.ac_enaddr[0])); 1310 CSR_WRITE_4(sc, LGE_PAR1, *(u_int32_t *)(&sc->arpcom.ac_enaddr[4])); 1311 1312 /* Init circular RX list. */ 1313 if (lge_list_rx_init(sc) == ENOBUFS) { 1314 printf("lge%d: initialization failed: no " 1315 "memory for rx buffers\n", sc->lge_unit); 1316 lge_stop(sc); 1317 (void)splx(s); 1318 return; 1319 } 1320 1321 /* 1322 * Init tx descriptors. 1323 */ 1324 lge_list_tx_init(sc); 1325 1326 /* Set initial value for MODE1 register. */ 1327 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_UCAST| 1328 LGE_MODE1_TX_CRC|LGE_MODE1_TXPAD| 1329 LGE_MODE1_RX_FLOWCTL|LGE_MODE1_SETRST_CTL0| 1330 LGE_MODE1_SETRST_CTL1|LGE_MODE1_SETRST_CTL2); 1331 1332 /* If we want promiscuous mode, set the allframes bit. */ 1333 if (ifp->if_flags & IFF_PROMISC) { 1334 CSR_WRITE_4(sc, LGE_MODE1, 1335 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_PROMISC); 1336 } else { 1337 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_PROMISC); 1338 } 1339 1340 /* 1341 * Set the capture broadcast bit to capture broadcast frames. 1342 */ 1343 if (ifp->if_flags & IFF_BROADCAST) { 1344 CSR_WRITE_4(sc, LGE_MODE1, 1345 LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_BCAST); 1346 } else { 1347 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_BCAST); 1348 } 1349 1350 /* Packet padding workaround? */ 1351 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RMVPAD); 1352 1353 /* No error frames */ 1354 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ERRPKTS); 1355 1356 /* Receive large frames */ 1357 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_GIANTS); 1358 1359 /* Workaround: disable RX/TX flow control */ 1360 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_TX_FLOWCTL); 1361 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_FLOWCTL); 1362 1363 /* Make sure to strip CRC from received frames */ 1364 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_CRC); 1365 1366 /* Turn off magic packet mode */ 1367 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_MPACK_ENB); 1368 1369 /* Turn off all VLAN stuff */ 1370 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_VLAN_RX|LGE_MODE1_VLAN_TX| 1371 LGE_MODE1_VLAN_STRIP|LGE_MODE1_VLAN_INSERT); 1372 1373 /* Workarond: FIFO overflow */ 1374 CSR_WRITE_2(sc, LGE_RXFIFO_HIWAT, 0x3FFF); 1375 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL1|LGE_IMR_RXFIFO_WAT); 1376 1377 /* 1378 * Load the multicast filter. 1379 */ 1380 lge_setmulti(sc); 1381 1382 /* 1383 * Enable hardware checksum validation for all received IPv4 1384 * packets, do not reject packets with bad checksums. 1385 */ 1386 CSR_WRITE_4(sc, LGE_MODE2, LGE_MODE2_RX_IPCSUM| 1387 LGE_MODE2_RX_TCPCSUM|LGE_MODE2_RX_UDPCSUM| 1388 LGE_MODE2_RX_ERRCSUM); 1389 1390 /* 1391 * Enable the delivery of PHY interrupts based on 1392 * link/speed/duplex status chalges. 1393 */ 1394 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL0|LGE_MODE1_GMIIPOLL); 1395 1396 /* Enable receiver and transmitter. */ 1397 CSR_WRITE_4(sc, LGE_RXDESC_ADDR_HI, 0); 1398 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_RX_ENB); 1399 1400 CSR_WRITE_4(sc, LGE_TXDESC_ADDR_HI, 0); 1401 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_SETRST_CTL1|LGE_MODE1_TX_ENB); 1402 1403 /* 1404 * Enable interrupts. 1405 */ 1406 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_SETRST_CTL0| 1407 LGE_IMR_SETRST_CTL1|LGE_IMR_INTR_ENB|LGE_INTRS); 1408 1409 lge_ifmedia_upd(ifp); 1410 1411 ifp->if_flags |= IFF_RUNNING; 1412 ifp->if_flags &= ~IFF_OACTIVE; 1413 1414 (void)splx(s); 1415 1416 sc->lge_stat_ch = timeout(lge_tick, sc, hz); 1417 1418 return; 1419} 1420 1421/* 1422 * Set media options. 1423 */ 1424static int 1425lge_ifmedia_upd(ifp) 1426 struct ifnet *ifp; 1427{ 1428 struct lge_softc *sc; 1429 struct mii_data *mii; 1430 1431 sc = ifp->if_softc; 1432 1433 mii = device_get_softc(sc->lge_miibus); 1434 sc->lge_link = 0; 1435 if (mii->mii_instance) { 1436 struct mii_softc *miisc; 1437 for (miisc = LIST_FIRST(&mii->mii_phys); miisc != NULL; 1438 miisc = LIST_NEXT(miisc, mii_list)) 1439 mii_phy_reset(miisc); 1440 } 1441 mii_mediachg(mii); 1442 1443 return(0); 1444} 1445 1446/* 1447 * Report current media status. 1448 */ 1449static void 1450lge_ifmedia_sts(ifp, ifmr) 1451 struct ifnet *ifp; 1452 struct ifmediareq *ifmr; 1453{ 1454 struct lge_softc *sc; 1455 struct mii_data *mii; 1456 1457 sc = ifp->if_softc; 1458 1459 mii = device_get_softc(sc->lge_miibus); 1460 mii_pollstat(mii); 1461 ifmr->ifm_active = mii->mii_media_active; 1462 ifmr->ifm_status = mii->mii_media_status; 1463 1464 return; 1465} 1466 1467static int 1468lge_ioctl(ifp, command, data) 1469 struct ifnet *ifp; 1470 u_long command; 1471 caddr_t data; 1472{ 1473 struct lge_softc *sc = ifp->if_softc; 1474 struct ifreq *ifr = (struct ifreq *) data; 1475 struct mii_data *mii; 1476 int s, error = 0; 1477 1478 s = splimp(); 1479 1480 switch(command) { 1481 case SIOCSIFMTU: 1482 if (ifr->ifr_mtu > LGE_JUMBO_MTU) 1483 error = EINVAL; 1484 else 1485 ifp->if_mtu = ifr->ifr_mtu; 1486 break; 1487 case SIOCSIFFLAGS: 1488 if (ifp->if_flags & IFF_UP) { 1489 if (ifp->if_flags & IFF_RUNNING && 1490 ifp->if_flags & IFF_PROMISC && 1491 !(sc->lge_if_flags & IFF_PROMISC)) { 1492 CSR_WRITE_4(sc, LGE_MODE1, 1493 LGE_MODE1_SETRST_CTL1| 1494 LGE_MODE1_RX_PROMISC); 1495 } else if (ifp->if_flags & IFF_RUNNING && 1496 !(ifp->if_flags & IFF_PROMISC) && 1497 sc->lge_if_flags & IFF_PROMISC) { 1498 CSR_WRITE_4(sc, LGE_MODE1, 1499 LGE_MODE1_RX_PROMISC); 1500 } else { 1501 ifp->if_flags &= ~IFF_RUNNING; 1502 lge_init(sc); 1503 } 1504 } else { 1505 if (ifp->if_flags & IFF_RUNNING) 1506 lge_stop(sc); 1507 } 1508 sc->lge_if_flags = ifp->if_flags; 1509 error = 0; 1510 break; 1511 case SIOCADDMULTI: 1512 case SIOCDELMULTI: 1513 lge_setmulti(sc); 1514 error = 0; 1515 break; 1516 case SIOCGIFMEDIA: 1517 case SIOCSIFMEDIA: 1518 mii = device_get_softc(sc->lge_miibus); 1519 error = ifmedia_ioctl(ifp, ifr, &mii->mii_media, command); 1520 break; 1521 default: 1522 error = ether_ioctl(ifp, command, data); 1523 break; 1524 } 1525 1526 (void)splx(s); 1527 1528 return(error); 1529} 1530 1531static void 1532lge_watchdog(ifp) 1533 struct ifnet *ifp; 1534{ 1535 struct lge_softc *sc; 1536 1537 sc = ifp->if_softc; 1538 1539 ifp->if_oerrors++; 1540 printf("lge%d: watchdog timeout\n", sc->lge_unit); 1541 1542 lge_stop(sc); 1543 lge_reset(sc); 1544 ifp->if_flags &= ~IFF_RUNNING; 1545 lge_init(sc); 1546 1547 if (ifp->if_snd.ifq_head != NULL) 1548 lge_start(ifp); 1549 1550 return; 1551} 1552 1553/* 1554 * Stop the adapter and free any mbufs allocated to the 1555 * RX and TX lists. 1556 */ 1557static void 1558lge_stop(sc) 1559 struct lge_softc *sc; 1560{ 1561 register int i; 1562 struct ifnet *ifp; 1563 1564 ifp = &sc->arpcom.ac_if; 1565 ifp->if_timer = 0; 1566 untimeout(lge_tick, sc, sc->lge_stat_ch); 1567 CSR_WRITE_4(sc, LGE_IMR, LGE_IMR_INTR_ENB); 1568 1569 /* Disable receiver and transmitter. */ 1570 CSR_WRITE_4(sc, LGE_MODE1, LGE_MODE1_RX_ENB|LGE_MODE1_TX_ENB); 1571 sc->lge_link = 0; 1572 1573 /* 1574 * Free data in the RX lists. 1575 */ 1576 for (i = 0; i < LGE_RX_LIST_CNT; i++) { 1577 if (sc->lge_ldata->lge_rx_list[i].lge_mbuf != NULL) { 1578 m_freem(sc->lge_ldata->lge_rx_list[i].lge_mbuf); 1579 sc->lge_ldata->lge_rx_list[i].lge_mbuf = NULL; 1580 } 1581 } 1582 bzero((char *)&sc->lge_ldata->lge_rx_list, 1583 sizeof(sc->lge_ldata->lge_rx_list)); 1584 1585 /* 1586 * Free the TX list buffers. 1587 */ 1588 for (i = 0; i < LGE_TX_LIST_CNT; i++) { 1589 if (sc->lge_ldata->lge_tx_list[i].lge_mbuf != NULL) { 1590 m_freem(sc->lge_ldata->lge_tx_list[i].lge_mbuf); 1591 sc->lge_ldata->lge_tx_list[i].lge_mbuf = NULL; 1592 } 1593 } 1594 1595 bzero((char *)&sc->lge_ldata->lge_tx_list, 1596 sizeof(sc->lge_ldata->lge_tx_list)); 1597 1598 ifp->if_flags &= ~(IFF_RUNNING | IFF_OACTIVE); 1599 1600 return; 1601} 1602 1603/* 1604 * Stop all chip I/O so that the kernel's probe routines don't 1605 * get confused by errant DMAs when rebooting. 1606 */ 1607static void 1608lge_shutdown(dev) 1609 device_t dev; 1610{ 1611 struct lge_softc *sc; 1612 1613 sc = device_get_softc(dev); 1614 1615 lge_reset(sc); 1616 lge_stop(sc); 1617 1618 return; 1619} 1620