19313Ssos/*- 29313Ssos * SPDX-License-Identifier: BSD-2-Clause-FreeBSD 39313Ssos * 49313Ssos * Authors: Ravi Pokala (rpokala@freebsd.org) 59313Ssos * 69313Ssos * Copyright (c) 2018 Panasas 79313Ssos * All rights reserved. 89313Ssos * 99313Ssos * Redistribution and use in source and binary forms, with or without 109313Ssos * modification, are permitted provided that the following conditions 119313Ssos * are met: 129313Ssos * 1. Redistributions of source code must retain the above copyright 139313Ssos * notice, this list of conditions and the following disclaimer. 149313Ssos * 2. Redistributions in binary form must reproduce the above copyright 1597748Sschweikh * notice, this list of conditions and the following disclaimer in the 169313Ssos * documentation and/or other materials provided with the distribution. 179313Ssos * 189313Ssos * THIS SOFTWARE IS PROVIDED BY THE AUTHOR AND CONTRIBUTORS ``AS IS'' AND 199313Ssos * ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 209313Ssos * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 219313Ssos * ARE DISCLAIMED. IN NO EVENT SHALL THE AUTHOR OR CONTRIBUTORS BE LIABLE 229313Ssos * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL 239313Ssos * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS 249313Ssos * OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) 259313Ssos * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT 269313Ssos * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY 279313Ssos * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF 289313Ssos * SUCH DAMAGE. 29115705Sobrien * 30115705Sobrien * $FreeBSD: stable/10/sys/dev/jedec_dimm/jedec_dimm.h 329843 2018-02-22 23:18:46Z rpokala $ 31115705Sobrien */ 329313Ssos 339313Ssos#ifndef _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 349313Ssos#define _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ 359313Ssos 3614331Speter/* JEDEC DIMMs include one or more SMBus devices. 3768583Smarcel * 3883221Smarcel * At a minimum, they have an EEPROM containing either 256 bytes (DDR3) or 512 3912458Sbde * bytes (DDR4) of "Serial Presence Detect" (SPD) information. The SPD contains 4049850Smarcel * data used by the memory controller to configure itself, and it also includes 4149850Smarcel * asset information. The layout of SPD data is defined in: 4249850Smarcel * 4383221Smarcel * JEDEC Standard 21-C, Annex K (DDR3) 4449850Smarcel * JEDEC Standard 21-C, Annex L (DDR4) 4549850Smarcel * 4650345Smarcel * DIMMs may also include a "Thermal Sensor on DIMM" (TSOD), which reports 4749850Smarcel * temperature data. While not strictly required, the TSOD is so often included 4849850Smarcel * that JEDEC defined standards for single chips which include both SPD and TSOD 4949850Smarcel * functions. They respond on multiple SMBus addresses, depending on the 5049850Smarcel * function. 5149850Smarcel * 5249850Smarcel * JEDEC Standard 21-C, TSE2002av (DDR3) 5349850Smarcel * JEDEC Standard 21-C, TSE2004av (DDR4) 5449850Smarcel */ 5550345Smarcel 5650345Smarcel/* TSE2004av defines several Device Type Identifiers (DTIs), which are the high 5750345Smarcel * nybble of the SMBus address. Addresses with DTIs of PROTECT (or PAGE, which 5850345Smarcel * has the same value) are essentially "broadcast" addresses; all SPD devices 5950345Smarcel * respond to them, changing their mode based on the Logical Serial Address 6050345Smarcel * (LSA) encoded in bits [3:1]. For normal SPD access, bits [3:1] encode the 6150345Smarcel * DIMM slot number. 6250345Smarcel */ 6350345Smarcel#define JEDEC_SPD_PAGE_SIZE 256 6450345Smarcel#define JEDEC_DTI_SPD 0xa0 6555784Smarcel#define JEDEC_DTI_TSOD 0x30 6683221Smarcel#define JEDEC_DTI_PROTECT 0x60 6783221Smarcel#define JEDEC_LSA_PROTECT_SET0 0x02 6883221Smarcel#define JEDEC_LSA_PROTECT_SET1 0x08 6983221Smarcel#define JEDEC_LSA_PROTECT_SET2 0x0a 70122802Ssobomax#define JEDEC_LSA_PROTECT_SET3 0x00 71159799Snetchild#define JEDEC_LSA_PROTECT_CLR 0x06 72159799Snetchild#define JEDEC_LSA_PROTECT_GET0 0x03 73159799Snetchild#define JEDEC_LSA_PROTECT_GET1 0x09 74159799Snetchild#define JEDEC_LSA_PROTECT_GET2 0x0b 75159799Snetchild#define JEDEC_LSA_PROTECT_GET3 0x01 76159799Snetchild#define JEDEC_DTI_PAGE 0x60 77159799Snetchild#define JEDEC_LSA_PAGE_SET0 0x0c 78159799Snetchild#define JEDEC_LSA_PAGE_SET1 0x0e 79159799Snetchild#define JEDEC_LSA_PAGE_GET 0x0d 80159799Snetchild 81159799Snetchild/* The offsets and lengths of various SPD bytes are defined in Annex K (DDR3) 82159799Snetchild * and Annex L (DDR4). Conveniently, the DRAM type is at the same offset for 83159799Snetchild * both versions. 84159799Snetchild * 85159799Snetchild * This list only includes information needed to get the asset information and 86159799Snetchild * calculate the DIMM capacity. 87159799Snetchild */ 88159799Snetchild#define SPD_OFFSET_DRAM_TYPE 2 89159799Snetchild#define SPD_OFFSET_DDR3_SDRAM_CAPACITY 4 90159799Snetchild#define SPD_OFFSET_DDR3_DIMM_RANKS 7 91159799Snetchild#define SPD_OFFSET_DDR3_SDRAM_WIDTH 7 92159799Snetchild#define SPD_OFFSET_DDR3_BUS_WIDTH 8 93159799Snetchild#define SPD_OFFSET_DDR3_TSOD_PRESENT 32 94159799Snetchild#define SPD_OFFSET_DDR3_SERIAL 122 95159799Snetchild#define SPD_LEN_DDR3_SERIAL 4 96159799Snetchild#define SPD_OFFSET_DDR3_PARTNUM 128 97159799Snetchild#define SPD_LEN_DDR3_PARTNUM 18 98159799Snetchild#define SPD_OFFSET_DDR4_SDRAM_CAPACITY 4 99159799Snetchild#define SPD_OFFSET_DDR4_SDRAM_PKG_TYPE 6 100159799Snetchild#define SPD_OFFSET_DDR4_DIMM_RANKS 12 101159799Snetchild#define SPD_OFFSET_DDR4_SDRAM_WIDTH 12 102159799Snetchild#define SPD_OFFSET_DDR4_BUS_WIDTH 13 103159799Snetchild#define SPD_OFFSET_DDR4_TSOD_PRESENT 14 104159799Snetchild#define SPD_OFFSET_DDR4_SERIAL 325 105159799Snetchild#define SPD_LEN_DDR4_SERIAL 4 106159799Snetchild#define SPD_OFFSET_DDR4_PARTNUM 329 107159799Snetchild#define SPD_LEN_DDR4_PARTNUM 20 108159799Snetchild 109159799Snetchild/* The "DRAM Type" field of the SPD enumerates various memory technologies which 110159799Snetchild * have been used over the years. The list is append-only, so we need only refer 111159799Snetchild * to the latest SPD specification. In this case, Annex L for DDR4. 112159799Snetchild */ 113159799Snetchildenum dram_type { 114159799Snetchild DRAM_TYPE_RESERVED = 0x00, 115159799Snetchild DRAM_TYPE_FAST_PAGE_MODE = 0x01, 116159799Snetchild DRAM_TYPE_EDO = 0x02, 117159799Snetchild DRAM_TYPE_PIPLEINED_NYBBLE = 0x03, 118159799Snetchild DRAM_TYPE_SDRAM = 0x04, 119159799Snetchild DRAM_TYPE_ROM = 0x05, 120159799Snetchild DRAM_TYPE_DDR_SGRAM = 0x06, 121159799Snetchild DRAM_TYPE_DDR_SDRAM = 0x07, 122159799Snetchild DRAM_TYPE_DDR2_SDRAM = 0x08, 123159799Snetchild DRAM_TYPE_DDR2_SDRAM_FBDIMM = 0x09, 124159799Snetchild DRAM_TYPE_DDR2_SDRAM_FBDIMM_PROBE = 0x0a, 125159799Snetchild DRAM_TYPE_DDR3_SDRAM = 0x0b, 126159799Snetchild DRAM_TYPE_DDR4_SDRAM = 0x0c, 127122802Ssobomax DRAM_TYPE_RESERVED_0D = 0x0d, 128122802Ssobomax DRAM_TYPE_DDR4E_SDRAM = 0x0e, 129122802Ssobomax DRAM_TYPE_LPDDR3_SDRAM = 0x0f, 130122802Ssobomax DRAM_TYPE_LPDDR4_SDRAM = 0x10, 131122802Ssobomax}; 132122802Ssobomax 133122802Ssobomax/* The TSOD is accessed using a simple word interface, which is identical 134122802Ssobomax * between TSE2002av (DDR3) and TSE2004av (DDR4). 135122802Ssobomax */ 136122802Ssobomax#define TSOD_REG_CAPABILITES 0 137122802Ssobomax#define TSOD_REG_CONFIG 1 138122802Ssobomax#define TSOD_REG_LIM_HIGH 2 139122802Ssobomax#define TSOD_REG_LIM_LOW 3 140122802Ssobomax#define TSOD_REG_LIM_CRIT 4 141122802Ssobomax#define TSOD_REG_TEMPERATURE 5 142122802Ssobomax#define TSOD_REG_MANUFACTURER 6 143122802Ssobomax#define TSOD_REG_DEV_REV 7 144122802Ssobomax 145122802Ssobomax#endif /* _DEV__JEDEC_DIMM__JEDEC_DIMM_H_ */ 146122802Ssobomax 147122802Ssobomax/* vi: set ts=8 sw=4 sts=8 noet: */ 148