i40e_adminq_cmd.h revision 270631
155682Smarkm/****************************************************************************** 2102644Snectar 355682Smarkm Copyright (c) 2013-2014, Intel Corporation 455682Smarkm All rights reserved. 555682Smarkm 655682Smarkm Redistribution and use in source and binary forms, with or without 755682Smarkm modification, are permitted provided that the following conditions are met: 855682Smarkm 955682Smarkm 1. Redistributions of source code must retain the above copyright notice, 1055682Smarkm this list of conditions and the following disclaimer. 1155682Smarkm 1255682Smarkm 2. Redistributions in binary form must reproduce the above copyright 1355682Smarkm notice, this list of conditions and the following disclaimer in the 1455682Smarkm documentation and/or other materials provided with the distribution. 1555682Smarkm 1655682Smarkm 3. Neither the name of the Intel Corporation nor the names of its 1755682Smarkm contributors may be used to endorse or promote products derived from 1855682Smarkm this software without specific prior written permission. 1955682Smarkm 2055682Smarkm THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 2155682Smarkm AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 2255682Smarkm IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 2355682Smarkm ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 2455682Smarkm LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 2555682Smarkm CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 2655682Smarkm SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 2755682Smarkm INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 2855682Smarkm CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 2955682Smarkm ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 3055682Smarkm POSSIBILITY OF SUCH DAMAGE. 3155682Smarkm 3255682Smarkm******************************************************************************/ 3355682Smarkm/*$FreeBSD: stable/10/sys/dev/ixl/i40e_adminq_cmd.h 270631 2014-08-25 22:04:29Z jfv $*/ 3455682Smarkm 35102644Snectar#ifndef _I40E_ADMINQ_CMD_H_ 3655682Smarkm#define _I40E_ADMINQ_CMD_H_ 37102644Snectar 3855682Smarkm/* This header file defines the i40e Admin Queue commands and is shared between 3955682Smarkm * i40e Firmware and Software. 4055682Smarkm * 4155682Smarkm * This file needs to comply with the Linux Kernel coding style. 4255682Smarkm */ 4355682Smarkm 4455682Smarkm#define I40E_FW_API_VERSION_MAJOR 0x0001 4555682Smarkm#define I40E_FW_API_VERSION_MINOR 0x0002 4655682Smarkm 4755682Smarkmstruct i40e_aq_desc { 4855682Smarkm __le16 flags; 4955682Smarkm __le16 opcode; 5055682Smarkm __le16 datalen; 5155682Smarkm __le16 retval; 5255682Smarkm __le32 cookie_high; 5355682Smarkm __le32 cookie_low; 5455682Smarkm union { 5555682Smarkm struct { 5655682Smarkm __le32 param0; 5772445Sassar __le32 param1; 5855682Smarkm __le32 param2; 5955682Smarkm __le32 param3; 6055682Smarkm } internal; 6155682Smarkm struct { 6255682Smarkm __le32 param0; 6355682Smarkm __le32 param1; 6455682Smarkm __le32 addr_high; 6555682Smarkm __le32 addr_low; 6655682Smarkm } external; 6755682Smarkm u8 raw[16]; 6855682Smarkm } params; 6955682Smarkm}; 7055682Smarkm 7155682Smarkm/* Flags sub-structure 7255682Smarkm * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 7355682Smarkm * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 7455682Smarkm */ 7555682Smarkm 7655682Smarkm/* command flags and offsets*/ 7755682Smarkm#define I40E_AQ_FLAG_DD_SHIFT 0 7855682Smarkm#define I40E_AQ_FLAG_CMP_SHIFT 1 7955682Smarkm#define I40E_AQ_FLAG_ERR_SHIFT 2 8055682Smarkm#define I40E_AQ_FLAG_VFE_SHIFT 3 8155682Smarkm#define I40E_AQ_FLAG_LB_SHIFT 9 8255682Smarkm#define I40E_AQ_FLAG_RD_SHIFT 10 8355682Smarkm#define I40E_AQ_FLAG_VFC_SHIFT 11 8455682Smarkm#define I40E_AQ_FLAG_BUF_SHIFT 12 8555682Smarkm#define I40E_AQ_FLAG_SI_SHIFT 13 8655682Smarkm#define I40E_AQ_FLAG_EI_SHIFT 14 8755682Smarkm#define I40E_AQ_FLAG_FE_SHIFT 15 8855682Smarkm 8955682Smarkm#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 9055682Smarkm#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 9155682Smarkm#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 9255682Smarkm#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 9355682Smarkm#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 9455682Smarkm#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 9555682Smarkm#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 9655682Smarkm#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 9755682Smarkm#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 9855682Smarkm#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 9955682Smarkm#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 10055682Smarkm 10155682Smarkm/* error codes */ 10255682Smarkmenum i40e_admin_queue_err { 10355682Smarkm I40E_AQ_RC_OK = 0, /* success */ 104102644Snectar I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 10555682Smarkm I40E_AQ_RC_ENOENT = 2, /* No such element */ 10655682Smarkm I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 10755682Smarkm I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 10855682Smarkm I40E_AQ_RC_EIO = 5, /* I/O error */ 10955682Smarkm I40E_AQ_RC_ENXIO = 6, /* No such resource */ 11055682Smarkm I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 11155682Smarkm I40E_AQ_RC_EAGAIN = 8, /* Try again */ 11255682Smarkm I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 11355682Smarkm I40E_AQ_RC_EACCES = 10, /* Permission denied */ 11455682Smarkm I40E_AQ_RC_EFAULT = 11, /* Bad address */ 11555682Smarkm I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 11655682Smarkm I40E_AQ_RC_EEXIST = 13, /* object already exists */ 11755682Smarkm I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 11855682Smarkm I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 11955682Smarkm I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 120 I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 121 I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 122 I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 123 I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 124 I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 125 I40E_AQ_RC_EFBIG = 22, /* File too large */ 126}; 127 128/* Admin Queue command opcodes */ 129enum i40e_admin_queue_opc { 130 /* aq commands */ 131 i40e_aqc_opc_get_version = 0x0001, 132 i40e_aqc_opc_driver_version = 0x0002, 133 i40e_aqc_opc_queue_shutdown = 0x0003, 134 i40e_aqc_opc_set_pf_context = 0x0004, 135 136 /* resource ownership */ 137 i40e_aqc_opc_request_resource = 0x0008, 138 i40e_aqc_opc_release_resource = 0x0009, 139 140 i40e_aqc_opc_list_func_capabilities = 0x000A, 141 i40e_aqc_opc_list_dev_capabilities = 0x000B, 142 143 i40e_aqc_opc_set_cppm_configuration = 0x0103, 144 i40e_aqc_opc_set_arp_proxy_entry = 0x0104, 145 i40e_aqc_opc_set_ns_proxy_entry = 0x0105, 146 147 /* LAA */ 148 i40e_aqc_opc_mng_laa = 0x0106, /* AQ obsolete */ 149 i40e_aqc_opc_mac_address_read = 0x0107, 150 i40e_aqc_opc_mac_address_write = 0x0108, 151 152 /* PXE */ 153 i40e_aqc_opc_clear_pxe_mode = 0x0110, 154 155 /* internal switch commands */ 156 i40e_aqc_opc_get_switch_config = 0x0200, 157 i40e_aqc_opc_add_statistics = 0x0201, 158 i40e_aqc_opc_remove_statistics = 0x0202, 159 i40e_aqc_opc_set_port_parameters = 0x0203, 160 i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 161 162 i40e_aqc_opc_add_vsi = 0x0210, 163 i40e_aqc_opc_update_vsi_parameters = 0x0211, 164 i40e_aqc_opc_get_vsi_parameters = 0x0212, 165 166 i40e_aqc_opc_add_pv = 0x0220, 167 i40e_aqc_opc_update_pv_parameters = 0x0221, 168 i40e_aqc_opc_get_pv_parameters = 0x0222, 169 170 i40e_aqc_opc_add_veb = 0x0230, 171 i40e_aqc_opc_update_veb_parameters = 0x0231, 172 i40e_aqc_opc_get_veb_parameters = 0x0232, 173 174 i40e_aqc_opc_delete_element = 0x0243, 175 176 i40e_aqc_opc_add_macvlan = 0x0250, 177 i40e_aqc_opc_remove_macvlan = 0x0251, 178 i40e_aqc_opc_add_vlan = 0x0252, 179 i40e_aqc_opc_remove_vlan = 0x0253, 180 i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 181 i40e_aqc_opc_add_tag = 0x0255, 182 i40e_aqc_opc_remove_tag = 0x0256, 183 i40e_aqc_opc_add_multicast_etag = 0x0257, 184 i40e_aqc_opc_remove_multicast_etag = 0x0258, 185 i40e_aqc_opc_update_tag = 0x0259, 186 i40e_aqc_opc_add_control_packet_filter = 0x025A, 187 i40e_aqc_opc_remove_control_packet_filter = 0x025B, 188 i40e_aqc_opc_add_cloud_filters = 0x025C, 189 i40e_aqc_opc_remove_cloud_filters = 0x025D, 190 191 i40e_aqc_opc_add_mirror_rule = 0x0260, 192 i40e_aqc_opc_delete_mirror_rule = 0x0261, 193 194 /* DCB commands */ 195 i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 196 i40e_aqc_opc_dcb_updated = 0x0302, 197 198 /* TX scheduler */ 199 i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 200 i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 201 i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 202 i40e_aqc_opc_query_vsi_bw_config = 0x0408, 203 i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 204 i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 205 206 i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 207 i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 208 i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 209 i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 210 i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 211 i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 212 i40e_aqc_opc_query_port_ets_config = 0x0419, 213 i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 214 i40e_aqc_opc_suspend_port_tx = 0x041B, 215 i40e_aqc_opc_resume_port_tx = 0x041C, 216 i40e_aqc_opc_configure_partition_bw = 0x041D, 217 218 /* hmc */ 219 i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 220 i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 221 222 /* phy commands*/ 223 i40e_aqc_opc_get_phy_abilities = 0x0600, 224 i40e_aqc_opc_set_phy_config = 0x0601, 225 i40e_aqc_opc_set_mac_config = 0x0603, 226 i40e_aqc_opc_set_link_restart_an = 0x0605, 227 i40e_aqc_opc_get_link_status = 0x0607, 228 i40e_aqc_opc_set_phy_int_mask = 0x0613, 229 i40e_aqc_opc_get_local_advt_reg = 0x0614, 230 i40e_aqc_opc_set_local_advt_reg = 0x0615, 231 i40e_aqc_opc_get_partner_advt = 0x0616, 232 i40e_aqc_opc_set_lb_modes = 0x0618, 233 i40e_aqc_opc_get_phy_wol_caps = 0x0621, 234 i40e_aqc_opc_set_phy_debug = 0x0622, 235 i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 236 237 /* NVM commands */ 238 i40e_aqc_opc_nvm_read = 0x0701, 239 i40e_aqc_opc_nvm_erase = 0x0702, 240 i40e_aqc_opc_nvm_update = 0x0703, 241 i40e_aqc_opc_nvm_config_read = 0x0704, 242 i40e_aqc_opc_nvm_config_write = 0x0705, 243 244 /* virtualization commands */ 245 i40e_aqc_opc_send_msg_to_pf = 0x0801, 246 i40e_aqc_opc_send_msg_to_vf = 0x0802, 247 i40e_aqc_opc_send_msg_to_peer = 0x0803, 248 249 /* alternate structure */ 250 i40e_aqc_opc_alternate_write = 0x0900, 251 i40e_aqc_opc_alternate_write_indirect = 0x0901, 252 i40e_aqc_opc_alternate_read = 0x0902, 253 i40e_aqc_opc_alternate_read_indirect = 0x0903, 254 i40e_aqc_opc_alternate_write_done = 0x0904, 255 i40e_aqc_opc_alternate_set_mode = 0x0905, 256 i40e_aqc_opc_alternate_clear_port = 0x0906, 257 258 /* LLDP commands */ 259 i40e_aqc_opc_lldp_get_mib = 0x0A00, 260 i40e_aqc_opc_lldp_update_mib = 0x0A01, 261 i40e_aqc_opc_lldp_add_tlv = 0x0A02, 262 i40e_aqc_opc_lldp_update_tlv = 0x0A03, 263 i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 264 i40e_aqc_opc_lldp_stop = 0x0A05, 265 i40e_aqc_opc_lldp_start = 0x0A06, 266 267 /* Tunnel commands */ 268 i40e_aqc_opc_add_udp_tunnel = 0x0B00, 269 i40e_aqc_opc_del_udp_tunnel = 0x0B01, 270 i40e_aqc_opc_tunnel_key_structure = 0x0B10, 271 272 /* Async Events */ 273 i40e_aqc_opc_event_lan_overflow = 0x1001, 274 275 /* OEM commands */ 276 i40e_aqc_opc_oem_parameter_change = 0xFE00, 277 i40e_aqc_opc_oem_device_status_change = 0xFE01, 278 279 /* debug commands */ 280 i40e_aqc_opc_debug_get_deviceid = 0xFF00, 281 i40e_aqc_opc_debug_set_mode = 0xFF01, 282 i40e_aqc_opc_debug_read_reg = 0xFF03, 283 i40e_aqc_opc_debug_write_reg = 0xFF04, 284 i40e_aqc_opc_debug_modify_reg = 0xFF07, 285 i40e_aqc_opc_debug_dump_internals = 0xFF08, 286 i40e_aqc_opc_debug_modify_internals = 0xFF09, 287}; 288 289/* command structures and indirect data structures */ 290 291/* Structure naming conventions: 292 * - no suffix for direct command descriptor structures 293 * - _data for indirect sent data 294 * - _resp for indirect return data (data which is both will use _data) 295 * - _completion for direct return data 296 * - _element_ for repeated elements (may also be _data or _resp) 297 * 298 * Command structures are expected to overlay the params.raw member of the basic 299 * descriptor, and as such cannot exceed 16 bytes in length. 300 */ 301 302/* This macro is used to generate a compilation error if a structure 303 * is not exactly the correct length. It gives a divide by zero error if the 304 * structure is not of the correct size, otherwise it creates an enum that is 305 * never used. 306 */ 307#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 308 { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 309 310/* This macro is used extensively to ensure that command structures are 16 311 * bytes in length as they have to map to the raw array of that size. 312 */ 313#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 314 315/* internal (0x00XX) commands */ 316 317/* Get version (direct 0x0001) */ 318struct i40e_aqc_get_version { 319 __le32 rom_ver; 320 __le32 fw_build; 321 __le16 fw_major; 322 __le16 fw_minor; 323 __le16 api_major; 324 __le16 api_minor; 325}; 326 327I40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 328 329/* Send driver version (indirect 0x0002) */ 330struct i40e_aqc_driver_version { 331 u8 driver_major_ver; 332 u8 driver_minor_ver; 333 u8 driver_build_ver; 334 u8 driver_subbuild_ver; 335 u8 reserved[4]; 336 __le32 address_high; 337 __le32 address_low; 338}; 339 340I40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 341 342/* Queue Shutdown (direct 0x0003) */ 343struct i40e_aqc_queue_shutdown { 344 __le32 driver_unloading; 345#define I40E_AQ_DRIVER_UNLOADING 0x1 346 u8 reserved[12]; 347}; 348 349I40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 350 351/* Set PF context (0x0004, direct) */ 352struct i40e_aqc_set_pf_context { 353 u8 pf_id; 354 u8 reserved[15]; 355}; 356 357I40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 358 359/* Request resource ownership (direct 0x0008) 360 * Release resource ownership (direct 0x0009) 361 */ 362#define I40E_AQ_RESOURCE_NVM 1 363#define I40E_AQ_RESOURCE_SDP 2 364#define I40E_AQ_RESOURCE_ACCESS_READ 1 365#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 366#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 367#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 368 369struct i40e_aqc_request_resource { 370 __le16 resource_id; 371 __le16 access_type; 372 __le32 timeout; 373 __le32 resource_number; 374 u8 reserved[4]; 375}; 376 377I40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 378 379/* Get function capabilities (indirect 0x000A) 380 * Get device capabilities (indirect 0x000B) 381 */ 382struct i40e_aqc_list_capabilites { 383 u8 command_flags; 384#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 385 u8 pf_index; 386 u8 reserved[2]; 387 __le32 count; 388 __le32 addr_high; 389 __le32 addr_low; 390}; 391 392I40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 393 394struct i40e_aqc_list_capabilities_element_resp { 395 __le16 id; 396 u8 major_rev; 397 u8 minor_rev; 398 __le32 number; 399 __le32 logical_id; 400 __le32 phys_id; 401 u8 reserved[16]; 402}; 403 404/* list of caps */ 405 406#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 407#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 408#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 409#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 410#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 411#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 412#define I40E_AQ_CAP_ID_SRIOV 0x0012 413#define I40E_AQ_CAP_ID_VF 0x0013 414#define I40E_AQ_CAP_ID_VMDQ 0x0014 415#define I40E_AQ_CAP_ID_8021QBG 0x0015 416#define I40E_AQ_CAP_ID_8021QBR 0x0016 417#define I40E_AQ_CAP_ID_VSI 0x0017 418#define I40E_AQ_CAP_ID_DCB 0x0018 419#define I40E_AQ_CAP_ID_FCOE 0x0021 420#define I40E_AQ_CAP_ID_RSS 0x0040 421#define I40E_AQ_CAP_ID_RXQ 0x0041 422#define I40E_AQ_CAP_ID_TXQ 0x0042 423#define I40E_AQ_CAP_ID_MSIX 0x0043 424#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 425#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 426#define I40E_AQ_CAP_ID_1588 0x0046 427#define I40E_AQ_CAP_ID_IWARP 0x0051 428#define I40E_AQ_CAP_ID_LED 0x0061 429#define I40E_AQ_CAP_ID_SDP 0x0062 430#define I40E_AQ_CAP_ID_MDIO 0x0063 431#define I40E_AQ_CAP_ID_FLEX10 0x00F1 432#define I40E_AQ_CAP_ID_CEM 0x00F2 433 434/* Set CPPM Configuration (direct 0x0103) */ 435struct i40e_aqc_cppm_configuration { 436 __le16 command_flags; 437#define I40E_AQ_CPPM_EN_LTRC 0x0800 438#define I40E_AQ_CPPM_EN_DMCTH 0x1000 439#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 440#define I40E_AQ_CPPM_EN_HPTC 0x4000 441#define I40E_AQ_CPPM_EN_DMARC 0x8000 442 __le16 ttlx; 443 __le32 dmacr; 444 __le16 dmcth; 445 u8 hptc; 446 u8 reserved; 447 __le32 pfltrc; 448}; 449 450I40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 451 452/* Set ARP Proxy command / response (indirect 0x0104) */ 453struct i40e_aqc_arp_proxy_data { 454 __le16 command_flags; 455#define I40E_AQ_ARP_INIT_IPV4 0x0008 456#define I40E_AQ_ARP_UNSUP_CTL 0x0010 457#define I40E_AQ_ARP_ENA 0x0020 458#define I40E_AQ_ARP_ADD_IPV4 0x0040 459#define I40E_AQ_ARP_DEL_IPV4 0x0080 460 __le16 table_id; 461 __le32 pfpm_proxyfc; 462 __le32 ip_addr; 463 u8 mac_addr[6]; 464}; 465 466/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 467struct i40e_aqc_ns_proxy_data { 468 __le16 table_idx_mac_addr_0; 469 __le16 table_idx_mac_addr_1; 470 __le16 table_idx_ipv6_0; 471 __le16 table_idx_ipv6_1; 472 __le16 control; 473#define I40E_AQ_NS_PROXY_ADD_0 0x0100 474#define I40E_AQ_NS_PROXY_DEL_0 0x0200 475#define I40E_AQ_NS_PROXY_ADD_1 0x0400 476#define I40E_AQ_NS_PROXY_DEL_1 0x0800 477#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 478#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 479#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 480#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 481#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 482#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 483#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 484 u8 mac_addr_0[6]; 485 u8 mac_addr_1[6]; 486 u8 local_mac_addr[6]; 487 u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 488 u8 ipv6_addr_1[16]; 489}; 490 491/* Manage LAA Command (0x0106) - obsolete */ 492struct i40e_aqc_mng_laa { 493 __le16 command_flags; 494#define I40E_AQ_LAA_FLAG_WR 0x8000 495 u8 reserved[2]; 496 __le32 sal; 497 __le16 sah; 498 u8 reserved2[6]; 499}; 500 501/* Manage MAC Address Read Command (indirect 0x0107) */ 502struct i40e_aqc_mac_address_read { 503 __le16 command_flags; 504#define I40E_AQC_LAN_ADDR_VALID 0x10 505#define I40E_AQC_SAN_ADDR_VALID 0x20 506#define I40E_AQC_PORT_ADDR_VALID 0x40 507#define I40E_AQC_WOL_ADDR_VALID 0x80 508#define I40E_AQC_ADDR_VALID_MASK 0xf0 509 u8 reserved[6]; 510 __le32 addr_high; 511 __le32 addr_low; 512}; 513 514I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 515 516struct i40e_aqc_mac_address_read_data { 517 u8 pf_lan_mac[6]; 518 u8 pf_san_mac[6]; 519 u8 port_mac[6]; 520 u8 pf_wol_mac[6]; 521}; 522 523I40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 524 525/* Manage MAC Address Write Command (0x0108) */ 526struct i40e_aqc_mac_address_write { 527 __le16 command_flags; 528#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 529#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 530#define I40E_AQC_WRITE_TYPE_PORT 0x8000 531#define I40E_AQC_WRITE_TYPE_MASK 0xc000 532 __le16 mac_sah; 533 __le32 mac_sal; 534 u8 reserved[8]; 535}; 536 537I40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 538 539/* PXE commands (0x011x) */ 540 541/* Clear PXE Command and response (direct 0x0110) */ 542struct i40e_aqc_clear_pxe { 543 u8 rx_cnt; 544 u8 reserved[15]; 545}; 546 547I40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 548 549/* Switch configuration commands (0x02xx) */ 550 551/* Used by many indirect commands that only pass an seid and a buffer in the 552 * command 553 */ 554struct i40e_aqc_switch_seid { 555 __le16 seid; 556 u8 reserved[6]; 557 __le32 addr_high; 558 __le32 addr_low; 559}; 560 561I40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 562 563/* Get Switch Configuration command (indirect 0x0200) 564 * uses i40e_aqc_switch_seid for the descriptor 565 */ 566struct i40e_aqc_get_switch_config_header_resp { 567 __le16 num_reported; 568 __le16 num_total; 569 u8 reserved[12]; 570}; 571 572struct i40e_aqc_switch_config_element_resp { 573 u8 element_type; 574#define I40E_AQ_SW_ELEM_TYPE_MAC 1 575#define I40E_AQ_SW_ELEM_TYPE_PF 2 576#define I40E_AQ_SW_ELEM_TYPE_VF 3 577#define I40E_AQ_SW_ELEM_TYPE_EMP 4 578#define I40E_AQ_SW_ELEM_TYPE_BMC 5 579#define I40E_AQ_SW_ELEM_TYPE_PV 16 580#define I40E_AQ_SW_ELEM_TYPE_VEB 17 581#define I40E_AQ_SW_ELEM_TYPE_PA 18 582#define I40E_AQ_SW_ELEM_TYPE_VSI 19 583 u8 revision; 584#define I40E_AQ_SW_ELEM_REV_1 1 585 __le16 seid; 586 __le16 uplink_seid; 587 __le16 downlink_seid; 588 u8 reserved[3]; 589 u8 connection_type; 590#define I40E_AQ_CONN_TYPE_REGULAR 0x1 591#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 592#define I40E_AQ_CONN_TYPE_CASCADED 0x3 593 __le16 scheduler_id; 594 __le16 element_info; 595}; 596 597/* Get Switch Configuration (indirect 0x0200) 598 * an array of elements are returned in the response buffer 599 * the first in the array is the header, remainder are elements 600 */ 601struct i40e_aqc_get_switch_config_resp { 602 struct i40e_aqc_get_switch_config_header_resp header; 603 struct i40e_aqc_switch_config_element_resp element[1]; 604}; 605 606/* Add Statistics (direct 0x0201) 607 * Remove Statistics (direct 0x0202) 608 */ 609struct i40e_aqc_add_remove_statistics { 610 __le16 seid; 611 __le16 vlan; 612 __le16 stat_index; 613 u8 reserved[10]; 614}; 615 616I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 617 618/* Set Port Parameters command (direct 0x0203) */ 619struct i40e_aqc_set_port_parameters { 620 __le16 command_flags; 621#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 622#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 623#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 624 __le16 bad_frame_vsi; 625 __le16 default_seid; /* reserved for command */ 626 u8 reserved[10]; 627}; 628 629I40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 630 631/* Get Switch Resource Allocation (indirect 0x0204) */ 632struct i40e_aqc_get_switch_resource_alloc { 633 u8 num_entries; /* reserved for command */ 634 u8 reserved[7]; 635 __le32 addr_high; 636 __le32 addr_low; 637}; 638 639I40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 640 641/* expect an array of these structs in the response buffer */ 642struct i40e_aqc_switch_resource_alloc_element_resp { 643 u8 resource_type; 644#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 645#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 646#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 647#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 648#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 649#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 650#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 651#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 652#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 653#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 654#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 655#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 656#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 657#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 658#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 659#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 660#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 661#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 662#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 663 u8 reserved1; 664 __le16 guaranteed; 665 __le16 total; 666 __le16 used; 667 __le16 total_unalloced; 668 u8 reserved2[6]; 669}; 670 671/* Add VSI (indirect 0x0210) 672 * this indirect command uses struct i40e_aqc_vsi_properties_data 673 * as the indirect buffer (128 bytes) 674 * 675 * Update VSI (indirect 0x211) 676 * uses the same data structure as Add VSI 677 * 678 * Get VSI (indirect 0x0212) 679 * uses the same completion and data structure as Add VSI 680 */ 681struct i40e_aqc_add_get_update_vsi { 682 __le16 uplink_seid; 683 u8 connection_type; 684#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 685#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 686#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 687 u8 reserved1; 688 u8 vf_id; 689 u8 reserved2; 690 __le16 vsi_flags; 691#define I40E_AQ_VSI_TYPE_SHIFT 0x0 692#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 693#define I40E_AQ_VSI_TYPE_VF 0x0 694#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 695#define I40E_AQ_VSI_TYPE_PF 0x2 696#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 697#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 698 __le32 addr_high; 699 __le32 addr_low; 700}; 701 702I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 703 704struct i40e_aqc_add_get_update_vsi_completion { 705 __le16 seid; 706 __le16 vsi_number; 707 __le16 vsi_used; 708 __le16 vsi_free; 709 __le32 addr_high; 710 __le32 addr_low; 711}; 712 713I40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 714 715struct i40e_aqc_vsi_properties_data { 716 /* first 96 byte are written by SW */ 717 __le16 valid_sections; 718#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 719#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 720#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 721#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 722#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 723#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 724#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 725#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 726#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 727#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 728 /* switch section */ 729 __le16 switch_id; /* 12bit id combined with flags below */ 730#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 731#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 732#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 733#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 734#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 735 u8 sw_reserved[2]; 736 /* security section */ 737 u8 sec_flags; 738#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 739#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 740#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 741 u8 sec_reserved; 742 /* VLAN section */ 743 __le16 pvid; /* VLANS include priority bits */ 744 __le16 fcoe_pvid; 745 u8 port_vlan_flags; 746#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 747#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 748 I40E_AQ_VSI_PVLAN_MODE_SHIFT) 749#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 750#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 751#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 752#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 753#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 754#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 755 I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 756#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 757#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 758#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 759#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 760 u8 pvlan_reserved[3]; 761 /* ingress egress up sections */ 762 __le32 ingress_table; /* bitmap, 3 bits per up */ 763#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 764#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 765 I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 766#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 767#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 768 I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 769#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 770#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 771 I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 772#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 773#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 774 I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 775#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 776#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 777 I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 778#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 779#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 780 I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 781#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 782#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 783 I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 784#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 785#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 786 I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 787 __le32 egress_table; /* same defines as for ingress table */ 788 /* cascaded PV section */ 789 __le16 cas_pv_tag; 790 u8 cas_pv_flags; 791#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 792#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 793 I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 794#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 795#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 796#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 797#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 798#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 799#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 800 u8 cas_pv_reserved; 801 /* queue mapping section */ 802 __le16 mapping_flags; 803#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 804#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 805 __le16 queue_mapping[16]; 806#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 807#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 808 __le16 tc_mapping[8]; 809#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 810#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 811 I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 812#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 813#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 814 I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 815 /* queueing option section */ 816 u8 queueing_opt_flags; 817#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 818#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 819 u8 queueing_opt_reserved[3]; 820 /* scheduler section */ 821 u8 up_enable_bits; 822 u8 sched_reserved; 823 /* outer up section */ 824 __le32 outer_up_table; /* same structure and defines as ingress table */ 825 u8 cmd_reserved[8]; 826 /* last 32 bytes are written by FW */ 827 __le16 qs_handle[8]; 828#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 829 __le16 stat_counter_idx; 830 __le16 sched_id; 831 u8 resp_reserved[12]; 832}; 833 834I40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 835 836/* Add Port Virtualizer (direct 0x0220) 837 * also used for update PV (direct 0x0221) but only flags are used 838 * (IS_CTRL_PORT only works on add PV) 839 */ 840struct i40e_aqc_add_update_pv { 841 __le16 command_flags; 842#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 843#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 844#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 845#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 846 __le16 uplink_seid; 847 __le16 connected_seid; 848 u8 reserved[10]; 849}; 850 851I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 852 853struct i40e_aqc_add_update_pv_completion { 854 /* reserved for update; for add also encodes error if rc == ENOSPC */ 855 __le16 pv_seid; 856#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 857#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 858#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 859#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 860 u8 reserved[14]; 861}; 862 863I40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 864 865/* Get PV Params (direct 0x0222) 866 * uses i40e_aqc_switch_seid for the descriptor 867 */ 868 869struct i40e_aqc_get_pv_params_completion { 870 __le16 seid; 871 __le16 default_stag; 872 __le16 pv_flags; /* same flags as add_pv */ 873#define I40E_AQC_GET_PV_PV_TYPE 0x1 874#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 875#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 876 u8 reserved[8]; 877 __le16 default_port_seid; 878}; 879 880I40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 881 882/* Add VEB (direct 0x0230) */ 883struct i40e_aqc_add_veb { 884 __le16 uplink_seid; 885 __le16 downlink_seid; 886 __le16 veb_flags; 887#define I40E_AQC_ADD_VEB_FLOATING 0x1 888#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 889#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 890 I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 891#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 892#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 893#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 894 u8 enable_tcs; 895 u8 reserved[9]; 896}; 897 898I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 899 900struct i40e_aqc_add_veb_completion { 901 u8 reserved[6]; 902 __le16 switch_seid; 903 /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 904 __le16 veb_seid; 905#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 906#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 907#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 908#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 909 __le16 statistic_index; 910 __le16 vebs_used; 911 __le16 vebs_free; 912}; 913 914I40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 915 916/* Get VEB Parameters (direct 0x0232) 917 * uses i40e_aqc_switch_seid for the descriptor 918 */ 919struct i40e_aqc_get_veb_parameters_completion { 920 __le16 seid; 921 __le16 switch_id; 922 __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 923 __le16 statistic_index; 924 __le16 vebs_used; 925 __le16 vebs_free; 926 u8 reserved[4]; 927}; 928 929I40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 930 931/* Delete Element (direct 0x0243) 932 * uses the generic i40e_aqc_switch_seid 933 */ 934 935/* Add MAC-VLAN (indirect 0x0250) */ 936 937/* used for the command for most vlan commands */ 938struct i40e_aqc_macvlan { 939 __le16 num_addresses; 940 __le16 seid[3]; 941#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 942#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 943 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 944#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 945 __le32 addr_high; 946 __le32 addr_low; 947}; 948 949I40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 950 951/* indirect data for command and response */ 952struct i40e_aqc_add_macvlan_element_data { 953 u8 mac_addr[6]; 954 __le16 vlan_tag; 955 __le16 flags; 956#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 957#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 958#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 959#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 960 __le16 queue_number; 961#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 962#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 963 I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 964 /* response section */ 965 u8 match_method; 966#define I40E_AQC_MM_PERFECT_MATCH 0x01 967#define I40E_AQC_MM_HASH_MATCH 0x02 968#define I40E_AQC_MM_ERR_NO_RES 0xFF 969 u8 reserved1[3]; 970}; 971 972struct i40e_aqc_add_remove_macvlan_completion { 973 __le16 perfect_mac_used; 974 __le16 perfect_mac_free; 975 __le16 unicast_hash_free; 976 __le16 multicast_hash_free; 977 __le32 addr_high; 978 __le32 addr_low; 979}; 980 981I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 982 983/* Remove MAC-VLAN (indirect 0x0251) 984 * uses i40e_aqc_macvlan for the descriptor 985 * data points to an array of num_addresses of elements 986 */ 987 988struct i40e_aqc_remove_macvlan_element_data { 989 u8 mac_addr[6]; 990 __le16 vlan_tag; 991 u8 flags; 992#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 993#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 994#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 995#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 996 u8 reserved[3]; 997 /* reply section */ 998 u8 error_code; 999#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1000#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1001 u8 reply_reserved[3]; 1002}; 1003 1004/* Add VLAN (indirect 0x0252) 1005 * Remove VLAN (indirect 0x0253) 1006 * use the generic i40e_aqc_macvlan for the command 1007 */ 1008struct i40e_aqc_add_remove_vlan_element_data { 1009 __le16 vlan_tag; 1010 u8 vlan_flags; 1011/* flags for add VLAN */ 1012#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1013#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1014#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1015#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1016#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1017#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1018#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1019#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1020#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1021#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1022#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1023#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1024/* flags for remove VLAN */ 1025#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1026 u8 reserved; 1027 u8 result; 1028/* flags for add VLAN */ 1029#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1030#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1031#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1032/* flags for remove VLAN */ 1033#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1034#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1035 u8 reserved1[3]; 1036}; 1037 1038struct i40e_aqc_add_remove_vlan_completion { 1039 u8 reserved[4]; 1040 __le16 vlans_used; 1041 __le16 vlans_free; 1042 __le32 addr_high; 1043 __le32 addr_low; 1044}; 1045 1046/* Set VSI Promiscuous Modes (direct 0x0254) */ 1047struct i40e_aqc_set_vsi_promiscuous_modes { 1048 __le16 promiscuous_flags; 1049 __le16 valid_flags; 1050/* flags used for both fields above */ 1051#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1052#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1053#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1054#define I40E_AQC_SET_VSI_DEFAULT 0x08 1055#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1056 __le16 seid; 1057#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1058 __le16 vlan_tag; 1059#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1060 u8 reserved[8]; 1061}; 1062 1063I40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1064 1065/* Add S/E-tag command (direct 0x0255) 1066 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1067 */ 1068struct i40e_aqc_add_tag { 1069 __le16 flags; 1070#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1071 __le16 seid; 1072#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1073#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1074 I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1075 __le16 tag; 1076 __le16 queue_number; 1077 u8 reserved[8]; 1078}; 1079 1080I40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1081 1082struct i40e_aqc_add_remove_tag_completion { 1083 u8 reserved[12]; 1084 __le16 tags_used; 1085 __le16 tags_free; 1086}; 1087 1088I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1089 1090/* Remove S/E-tag command (direct 0x0256) 1091 * Uses generic i40e_aqc_add_remove_tag_completion for completion 1092 */ 1093struct i40e_aqc_remove_tag { 1094 __le16 seid; 1095#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1096#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1097 I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1098 __le16 tag; 1099 u8 reserved[12]; 1100}; 1101 1102/* Add multicast E-Tag (direct 0x0257) 1103 * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1104 * and no external data 1105 */ 1106struct i40e_aqc_add_remove_mcast_etag { 1107 __le16 pv_seid; 1108 __le16 etag; 1109 u8 num_unicast_etags; 1110 u8 reserved[3]; 1111 __le32 addr_high; /* address of array of 2-byte s-tags */ 1112 __le32 addr_low; 1113}; 1114 1115I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1116 1117struct i40e_aqc_add_remove_mcast_etag_completion { 1118 u8 reserved[4]; 1119 __le16 mcast_etags_used; 1120 __le16 mcast_etags_free; 1121 __le32 addr_high; 1122 __le32 addr_low; 1123 1124}; 1125 1126I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1127 1128/* Update S/E-Tag (direct 0x0259) */ 1129struct i40e_aqc_update_tag { 1130 __le16 seid; 1131#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1132#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1133 I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1134 __le16 old_tag; 1135 __le16 new_tag; 1136 u8 reserved[10]; 1137}; 1138 1139I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1140 1141struct i40e_aqc_update_tag_completion { 1142 u8 reserved[12]; 1143 __le16 tags_used; 1144 __le16 tags_free; 1145}; 1146 1147I40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1148 1149/* Add Control Packet filter (direct 0x025A) 1150 * Remove Control Packet filter (direct 0x025B) 1151 * uses the i40e_aqc_add_oveb_cloud, 1152 * and the generic direct completion structure 1153 */ 1154struct i40e_aqc_add_remove_control_packet_filter { 1155 u8 mac[6]; 1156 __le16 etype; 1157 __le16 flags; 1158#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1159#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1160#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1161#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1162#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1163 __le16 seid; 1164#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1165#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1166 I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1167 __le16 queue; 1168 u8 reserved[2]; 1169}; 1170 1171I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1172 1173struct i40e_aqc_add_remove_control_packet_filter_completion { 1174 __le16 mac_etype_used; 1175 __le16 etype_used; 1176 __le16 mac_etype_free; 1177 __le16 etype_free; 1178 u8 reserved[8]; 1179}; 1180 1181I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1182 1183/* Add Cloud filters (indirect 0x025C) 1184 * Remove Cloud filters (indirect 0x025D) 1185 * uses the i40e_aqc_add_remove_cloud_filters, 1186 * and the generic indirect completion structure 1187 */ 1188struct i40e_aqc_add_remove_cloud_filters { 1189 u8 num_filters; 1190 u8 reserved; 1191 __le16 seid; 1192#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1193#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1194 I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1195 u8 reserved2[4]; 1196 __le32 addr_high; 1197 __le32 addr_low; 1198}; 1199 1200I40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1201 1202struct i40e_aqc_add_remove_cloud_filters_element_data { 1203 u8 outer_mac[6]; 1204 u8 inner_mac[6]; 1205 __le16 inner_vlan; 1206 union { 1207 struct { 1208 u8 reserved[12]; 1209 u8 data[4]; 1210 } v4; 1211 struct { 1212 u8 data[16]; 1213 } v6; 1214 } ipaddr; 1215 __le16 flags; 1216#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1217#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1218 I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1219/* 0x0000 reserved */ 1220#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1221/* 0x0002 reserved */ 1222#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1223#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1224/* 0x0005 reserved */ 1225#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1226/* 0x0007 reserved */ 1227/* 0x0008 reserved */ 1228#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1229#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1230#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1231#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1232 1233#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1234#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1235#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1236#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1237#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1238 1239#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1240#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1241#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1242#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1243#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1244#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1245 1246 __le32 tenant_id; 1247 u8 reserved[4]; 1248 __le16 queue_number; 1249#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1250#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x3F << \ 1251 I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1252 u8 reserved2[14]; 1253 /* response section */ 1254 u8 allocation_result; 1255#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1256#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1257 u8 response_reserved[7]; 1258}; 1259 1260struct i40e_aqc_remove_cloud_filters_completion { 1261 __le16 perfect_ovlan_used; 1262 __le16 perfect_ovlan_free; 1263 __le16 vlan_used; 1264 __le16 vlan_free; 1265 __le32 addr_high; 1266 __le32 addr_low; 1267}; 1268 1269I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1270 1271/* Add Mirror Rule (indirect or direct 0x0260) 1272 * Delete Mirror Rule (indirect or direct 0x0261) 1273 * note: some rule types (4,5) do not use an external buffer. 1274 * take care to set the flags correctly. 1275 */ 1276struct i40e_aqc_add_delete_mirror_rule { 1277 __le16 seid; 1278 __le16 rule_type; 1279#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1280#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1281 I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1282#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1283#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1284#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1285#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1286#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1287 __le16 num_entries; 1288 __le16 destination; /* VSI for add, rule id for delete */ 1289 __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1290 __le32 addr_low; 1291}; 1292 1293I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1294 1295struct i40e_aqc_add_delete_mirror_rule_completion { 1296 u8 reserved[2]; 1297 __le16 rule_id; /* only used on add */ 1298 __le16 mirror_rules_used; 1299 __le16 mirror_rules_free; 1300 __le32 addr_high; 1301 __le32 addr_low; 1302}; 1303 1304I40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1305 1306/* DCB 0x03xx*/ 1307 1308/* PFC Ignore (direct 0x0301) 1309 * the command and response use the same descriptor structure 1310 */ 1311struct i40e_aqc_pfc_ignore { 1312 u8 tc_bitmap; 1313 u8 command_flags; /* unused on response */ 1314#define I40E_AQC_PFC_IGNORE_SET 0x80 1315#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1316 u8 reserved[14]; 1317}; 1318 1319I40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1320 1321/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1322 * with no parameters 1323 */ 1324 1325/* TX scheduler 0x04xx */ 1326 1327/* Almost all the indirect commands use 1328 * this generic struct to pass the SEID in param0 1329 */ 1330struct i40e_aqc_tx_sched_ind { 1331 __le16 vsi_seid; 1332 u8 reserved[6]; 1333 __le32 addr_high; 1334 __le32 addr_low; 1335}; 1336 1337I40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1338 1339/* Several commands respond with a set of queue set handles */ 1340struct i40e_aqc_qs_handles_resp { 1341 __le16 qs_handles[8]; 1342}; 1343 1344/* Configure VSI BW limits (direct 0x0400) */ 1345struct i40e_aqc_configure_vsi_bw_limit { 1346 __le16 vsi_seid; 1347 u8 reserved[2]; 1348 __le16 credit; 1349 u8 reserved1[2]; 1350 u8 max_credit; /* 0-3, limit = 2^max */ 1351 u8 reserved2[7]; 1352}; 1353 1354I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1355 1356/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1357 * responds with i40e_aqc_qs_handles_resp 1358 */ 1359struct i40e_aqc_configure_vsi_ets_sla_bw_data { 1360 u8 tc_valid_bits; 1361 u8 reserved[15]; 1362 __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1363 1364 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1365 __le16 tc_bw_max[2]; 1366 u8 reserved1[28]; 1367}; 1368 1369/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1370 * responds with i40e_aqc_qs_handles_resp 1371 */ 1372struct i40e_aqc_configure_vsi_tc_bw_data { 1373 u8 tc_valid_bits; 1374 u8 reserved[3]; 1375 u8 tc_bw_credits[8]; 1376 u8 reserved1[4]; 1377 __le16 qs_handles[8]; 1378}; 1379 1380/* Query vsi bw configuration (indirect 0x0408) */ 1381struct i40e_aqc_query_vsi_bw_config_resp { 1382 u8 tc_valid_bits; 1383 u8 tc_suspended_bits; 1384 u8 reserved[14]; 1385 __le16 qs_handles[8]; 1386 u8 reserved1[4]; 1387 __le16 port_bw_limit; 1388 u8 reserved2[2]; 1389 u8 max_bw; /* 0-3, limit = 2^max */ 1390 u8 reserved3[23]; 1391}; 1392 1393/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1394struct i40e_aqc_query_vsi_ets_sla_config_resp { 1395 u8 tc_valid_bits; 1396 u8 reserved[3]; 1397 u8 share_credits[8]; 1398 __le16 credits[8]; 1399 1400 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1401 __le16 tc_bw_max[2]; 1402}; 1403 1404/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1405struct i40e_aqc_configure_switching_comp_bw_limit { 1406 __le16 seid; 1407 u8 reserved[2]; 1408 __le16 credit; 1409 u8 reserved1[2]; 1410 u8 max_bw; /* 0-3, limit = 2^max */ 1411 u8 reserved2[7]; 1412}; 1413 1414I40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1415 1416/* Enable Physical Port ETS (indirect 0x0413) 1417 * Modify Physical Port ETS (indirect 0x0414) 1418 * Disable Physical Port ETS (indirect 0x0415) 1419 */ 1420struct i40e_aqc_configure_switching_comp_ets_data { 1421 u8 reserved[4]; 1422 u8 tc_valid_bits; 1423 u8 seepage; 1424#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1425 u8 tc_strict_priority_flags; 1426 u8 reserved1[17]; 1427 u8 tc_bw_share_credits[8]; 1428 u8 reserved2[96]; 1429}; 1430 1431/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1432struct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1433 u8 tc_valid_bits; 1434 u8 reserved[15]; 1435 __le16 tc_bw_credit[8]; 1436 1437 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1438 __le16 tc_bw_max[2]; 1439 u8 reserved1[28]; 1440}; 1441 1442/* Configure Switching Component Bandwidth Allocation per Tc 1443 * (indirect 0x0417) 1444 */ 1445struct i40e_aqc_configure_switching_comp_bw_config_data { 1446 u8 tc_valid_bits; 1447 u8 reserved[2]; 1448 u8 absolute_credits; /* bool */ 1449 u8 tc_bw_share_credits[8]; 1450 u8 reserved1[20]; 1451}; 1452 1453/* Query Switching Component Configuration (indirect 0x0418) */ 1454struct i40e_aqc_query_switching_comp_ets_config_resp { 1455 u8 tc_valid_bits; 1456 u8 reserved[35]; 1457 __le16 port_bw_limit; 1458 u8 reserved1[2]; 1459 u8 tc_bw_max; /* 0-3, limit = 2^max */ 1460 u8 reserved2[23]; 1461}; 1462 1463/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1464struct i40e_aqc_query_port_ets_config_resp { 1465 u8 reserved[4]; 1466 u8 tc_valid_bits; 1467 u8 reserved1; 1468 u8 tc_strict_priority_bits; 1469 u8 reserved2; 1470 u8 tc_bw_share_credits[8]; 1471 __le16 tc_bw_limits[8]; 1472 1473 /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1474 __le16 tc_bw_max[2]; 1475 u8 reserved3[32]; 1476}; 1477 1478/* Query Switching Component Bandwidth Allocation per Traffic Type 1479 * (indirect 0x041A) 1480 */ 1481struct i40e_aqc_query_switching_comp_bw_config_resp { 1482 u8 tc_valid_bits; 1483 u8 reserved[2]; 1484 u8 absolute_credits_enable; /* bool */ 1485 u8 tc_bw_share_credits[8]; 1486 __le16 tc_bw_limits[8]; 1487 1488 /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1489 __le16 tc_bw_max[2]; 1490}; 1491 1492/* Suspend/resume port TX traffic 1493 * (direct 0x041B and 0x041C) uses the generic SEID struct 1494 */ 1495 1496/* Configure partition BW 1497 * (indirect 0x041D) 1498 */ 1499struct i40e_aqc_configure_partition_bw_data { 1500 __le16 pf_valid_bits; 1501 u8 min_bw[16]; /* guaranteed bandwidth */ 1502 u8 max_bw[16]; /* bandwidth limit */ 1503}; 1504 1505/* Get and set the active HMC resource profile and status. 1506 * (direct 0x0500) and (direct 0x0501) 1507 */ 1508struct i40e_aq_get_set_hmc_resource_profile { 1509 u8 pm_profile; 1510 u8 pe_vf_enabled; 1511 u8 reserved[14]; 1512}; 1513 1514I40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1515 1516enum i40e_aq_hmc_profile { 1517 /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1518 I40E_HMC_PROFILE_DEFAULT = 1, 1519 I40E_HMC_PROFILE_FAVOR_VF = 2, 1520 I40E_HMC_PROFILE_EQUAL = 3, 1521}; 1522 1523#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1524#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1525 1526/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1527 1528/* set in param0 for get phy abilities to report qualified modules */ 1529#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1530#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1531 1532enum i40e_aq_phy_type { 1533 I40E_PHY_TYPE_SGMII = 0x0, 1534 I40E_PHY_TYPE_1000BASE_KX = 0x1, 1535 I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1536 I40E_PHY_TYPE_10GBASE_KR = 0x3, 1537 I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1538 I40E_PHY_TYPE_XAUI = 0x5, 1539 I40E_PHY_TYPE_XFI = 0x6, 1540 I40E_PHY_TYPE_SFI = 0x7, 1541 I40E_PHY_TYPE_XLAUI = 0x8, 1542 I40E_PHY_TYPE_XLPPI = 0x9, 1543 I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1544 I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1545 I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1546 I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1547 I40E_PHY_TYPE_100BASE_TX = 0x11, 1548 I40E_PHY_TYPE_1000BASE_T = 0x12, 1549 I40E_PHY_TYPE_10GBASE_T = 0x13, 1550 I40E_PHY_TYPE_10GBASE_SR = 0x14, 1551 I40E_PHY_TYPE_10GBASE_LR = 0x15, 1552 I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1553 I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1554 I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1555 I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1556 I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1557 I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1558 I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1559 I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1560 I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1561 I40E_PHY_TYPE_MAX 1562}; 1563 1564#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1565#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1566#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1567#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1568#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1569 1570enum i40e_aq_link_speed { 1571 I40E_LINK_SPEED_UNKNOWN = 0, 1572 I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1573 I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1574 I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1575 I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1576 I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1577}; 1578 1579struct i40e_aqc_module_desc { 1580 u8 oui[3]; 1581 u8 reserved1; 1582 u8 part_number[16]; 1583 u8 revision[4]; 1584 u8 reserved2[8]; 1585}; 1586 1587struct i40e_aq_get_phy_abilities_resp { 1588 __le32 phy_type; /* bitmap using the above enum for offsets */ 1589 u8 link_speed; /* bitmap using the above enum bit patterns */ 1590 u8 abilities; 1591#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1592#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1593#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1594#define I40E_AQ_PHY_LINK_ENABLED 0x08 1595#define I40E_AQ_PHY_AN_ENABLED 0x10 1596#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1597 __le16 eee_capability; 1598#define I40E_AQ_EEE_100BASE_TX 0x0002 1599#define I40E_AQ_EEE_1000BASE_T 0x0004 1600#define I40E_AQ_EEE_10GBASE_T 0x0008 1601#define I40E_AQ_EEE_1000BASE_KX 0x0010 1602#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1603#define I40E_AQ_EEE_10GBASE_KR 0x0040 1604 __le32 eeer_val; 1605 u8 d3_lpan; 1606#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1607 u8 reserved[3]; 1608 u8 phy_id[4]; 1609 u8 module_type[3]; 1610 u8 qualified_module_count; 1611#define I40E_AQ_PHY_MAX_QMS 16 1612 struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1613}; 1614 1615/* Set PHY Config (direct 0x0601) */ 1616struct i40e_aq_set_phy_config { /* same bits as above in all */ 1617 __le32 phy_type; 1618 u8 link_speed; 1619 u8 abilities; 1620/* bits 0-2 use the values from get_phy_abilities_resp */ 1621#define I40E_AQ_PHY_ENABLE_LINK 0x08 1622#define I40E_AQ_PHY_ENABLE_AN 0x10 1623#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1624 __le16 eee_capability; 1625 __le32 eeer; 1626 u8 low_power_ctrl; 1627 u8 reserved[3]; 1628}; 1629 1630I40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1631 1632/* Set MAC Config command data structure (direct 0x0603) */ 1633struct i40e_aq_set_mac_config { 1634 __le16 max_frame_size; 1635 u8 params; 1636#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1637#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1638#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1639#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1640#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1641#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1642#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1643#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1644#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1645#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1646#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1647#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1648#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1649#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1650 u8 tx_timer_priority; /* bitmap */ 1651 __le16 tx_timer_value; 1652 __le16 fc_refresh_threshold; 1653 u8 reserved[8]; 1654}; 1655 1656I40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1657 1658/* Restart Auto-Negotiation (direct 0x605) */ 1659struct i40e_aqc_set_link_restart_an { 1660 u8 command; 1661#define I40E_AQ_PHY_RESTART_AN 0x02 1662#define I40E_AQ_PHY_LINK_ENABLE 0x04 1663 u8 reserved[15]; 1664}; 1665 1666I40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1667 1668/* Get Link Status cmd & response data structure (direct 0x0607) */ 1669struct i40e_aqc_get_link_status { 1670 __le16 command_flags; /* only field set on command */ 1671#define I40E_AQ_LSE_MASK 0x3 1672#define I40E_AQ_LSE_NOP 0x0 1673#define I40E_AQ_LSE_DISABLE 0x2 1674#define I40E_AQ_LSE_ENABLE 0x3 1675/* only response uses this flag */ 1676#define I40E_AQ_LSE_IS_ENABLED 0x1 1677 u8 phy_type; /* i40e_aq_phy_type */ 1678 u8 link_speed; /* i40e_aq_link_speed */ 1679 u8 link_info; 1680#define I40E_AQ_LINK_UP 0x01 1681#define I40E_AQ_LINK_FAULT 0x02 1682#define I40E_AQ_LINK_FAULT_TX 0x04 1683#define I40E_AQ_LINK_FAULT_RX 0x08 1684#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1685#define I40E_AQ_MEDIA_AVAILABLE 0x40 1686#define I40E_AQ_SIGNAL_DETECT 0x80 1687 u8 an_info; 1688#define I40E_AQ_AN_COMPLETED 0x01 1689#define I40E_AQ_LP_AN_ABILITY 0x02 1690#define I40E_AQ_PD_FAULT 0x04 1691#define I40E_AQ_FEC_EN 0x08 1692#define I40E_AQ_PHY_LOW_POWER 0x10 1693#define I40E_AQ_LINK_PAUSE_TX 0x20 1694#define I40E_AQ_LINK_PAUSE_RX 0x40 1695#define I40E_AQ_QUALIFIED_MODULE 0x80 1696 u8 ext_info; 1697#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1698#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1699#define I40E_AQ_LINK_TX_SHIFT 0x02 1700#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1701#define I40E_AQ_LINK_TX_ACTIVE 0x00 1702#define I40E_AQ_LINK_TX_DRAINED 0x01 1703#define I40E_AQ_LINK_TX_FLUSHED 0x03 1704#define I40E_AQ_LINK_FORCED_40G 0x10 1705 u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1706 __le16 max_frame_size; 1707 u8 config; 1708#define I40E_AQ_CONFIG_CRC_ENA 0x04 1709#define I40E_AQ_CONFIG_PACING_MASK 0x78 1710 u8 reserved[5]; 1711}; 1712 1713I40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1714 1715/* Set event mask command (direct 0x613) */ 1716struct i40e_aqc_set_phy_int_mask { 1717 u8 reserved[8]; 1718 __le16 event_mask; 1719#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1720#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1721#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1722#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1723#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1724#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1725#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1726#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1727#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1728 u8 reserved1[6]; 1729}; 1730 1731I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1732 1733/* Get Local AN advt register (direct 0x0614) 1734 * Set Local AN advt register (direct 0x0615) 1735 * Get Link Partner AN advt register (direct 0x0616) 1736 */ 1737struct i40e_aqc_an_advt_reg { 1738 __le32 local_an_reg0; 1739 __le16 local_an_reg1; 1740 u8 reserved[10]; 1741}; 1742 1743I40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1744 1745/* Set Loopback mode (0x0618) */ 1746struct i40e_aqc_set_lb_mode { 1747 __le16 lb_mode; 1748#define I40E_AQ_LB_PHY_LOCAL 0x01 1749#define I40E_AQ_LB_PHY_REMOTE 0x02 1750#define I40E_AQ_LB_MAC_LOCAL 0x04 1751 u8 reserved[14]; 1752}; 1753 1754I40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1755 1756/* Set PHY Debug command (0x0622) */ 1757struct i40e_aqc_set_phy_debug { 1758 u8 command_flags; 1759#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1760#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1761#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1762 I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1763#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1764#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1765#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1766#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1767 u8 reserved[15]; 1768}; 1769 1770I40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1771 1772enum i40e_aq_phy_reg_type { 1773 I40E_AQC_PHY_REG_INTERNAL = 0x1, 1774 I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1775 I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1776}; 1777 1778/* NVM Read command (indirect 0x0701) 1779 * NVM Erase commands (direct 0x0702) 1780 * NVM Update commands (indirect 0x0703) 1781 */ 1782struct i40e_aqc_nvm_update { 1783 u8 command_flags; 1784#define I40E_AQ_NVM_LAST_CMD 0x01 1785#define I40E_AQ_NVM_FLASH_ONLY 0x80 1786 u8 module_pointer; 1787 __le16 length; 1788 __le32 offset; 1789 __le32 addr_high; 1790 __le32 addr_low; 1791}; 1792 1793I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1794 1795/* NVM Config Read (indirect 0x0704) */ 1796struct i40e_aqc_nvm_config_read { 1797 __le16 cmd_flags; 1798#define ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1799#define ANVM_READ_SINGLE_FEATURE 0 1800#define ANVM_READ_MULTIPLE_FEATURES 1 1801 __le16 element_count; 1802 __le16 element_id; /* Feature/field ID */ 1803 u8 reserved[2]; 1804 __le32 address_high; 1805 __le32 address_low; 1806}; 1807 1808I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1809 1810/* NVM Config Write (indirect 0x0705) */ 1811struct i40e_aqc_nvm_config_write { 1812 __le16 cmd_flags; 1813 __le16 element_count; 1814 u8 reserved[4]; 1815 __le32 address_high; 1816 __le32 address_low; 1817}; 1818 1819I40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1820 1821struct i40e_aqc_nvm_config_data_feature { 1822 __le16 feature_id; 1823 __le16 instance_id; 1824 __le16 feature_options; 1825 __le16 feature_selection; 1826}; 1827 1828struct i40e_aqc_nvm_config_data_immediate_field { 1829#define ANVM_FEATURE_OR_IMMEDIATE_MASK 0x2 1830 __le16 field_id; 1831 __le16 instance_id; 1832 __le16 field_options; 1833 __le16 field_value; 1834}; 1835 1836/* Send to PF command (indirect 0x0801) id is only used by PF 1837 * Send to VF command (indirect 0x0802) id is only used by PF 1838 * Send to Peer PF command (indirect 0x0803) 1839 */ 1840struct i40e_aqc_pf_vf_message { 1841 __le32 id; 1842 u8 reserved[4]; 1843 __le32 addr_high; 1844 __le32 addr_low; 1845}; 1846 1847I40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1848 1849/* Alternate structure */ 1850 1851/* Direct write (direct 0x0900) 1852 * Direct read (direct 0x0902) 1853 */ 1854struct i40e_aqc_alternate_write { 1855 __le32 address0; 1856 __le32 data0; 1857 __le32 address1; 1858 __le32 data1; 1859}; 1860 1861I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1862 1863/* Indirect write (indirect 0x0901) 1864 * Indirect read (indirect 0x0903) 1865 */ 1866 1867struct i40e_aqc_alternate_ind_write { 1868 __le32 address; 1869 __le32 length; 1870 __le32 addr_high; 1871 __le32 addr_low; 1872}; 1873 1874I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1875 1876/* Done alternate write (direct 0x0904) 1877 * uses i40e_aq_desc 1878 */ 1879struct i40e_aqc_alternate_write_done { 1880 __le16 cmd_flags; 1881#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1882#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1883#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1884#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1885 u8 reserved[14]; 1886}; 1887 1888I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1889 1890/* Set OEM mode (direct 0x0905) */ 1891struct i40e_aqc_alternate_set_mode { 1892 __le32 mode; 1893#define I40E_AQ_ALTERNATE_MODE_NONE 0 1894#define I40E_AQ_ALTERNATE_MODE_OEM 1 1895 u8 reserved[12]; 1896}; 1897 1898I40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1899 1900/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1901 1902/* async events 0x10xx */ 1903 1904/* Lan Queue Overflow Event (direct, 0x1001) */ 1905struct i40e_aqc_lan_overflow { 1906 __le32 prtdcb_rupto; 1907 __le32 otx_ctl; 1908 u8 reserved[8]; 1909}; 1910 1911I40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 1912 1913/* Get LLDP MIB (indirect 0x0A00) */ 1914struct i40e_aqc_lldp_get_mib { 1915 u8 type; 1916 u8 reserved1; 1917#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 1918#define I40E_AQ_LLDP_MIB_LOCAL 0x0 1919#define I40E_AQ_LLDP_MIB_REMOTE 0x1 1920#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 1921#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 1922#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 1923#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 1924#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 1925#define I40E_AQ_LLDP_TX_SHIFT 0x4 1926#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 1927/* TX pause flags use I40E_AQ_LINK_TX_* above */ 1928 __le16 local_len; 1929 __le16 remote_len; 1930 u8 reserved2[2]; 1931 __le32 addr_high; 1932 __le32 addr_low; 1933}; 1934 1935I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 1936 1937/* Configure LLDP MIB Change Event (direct 0x0A01) 1938 * also used for the event (with type in the command field) 1939 */ 1940struct i40e_aqc_lldp_update_mib { 1941 u8 command; 1942#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 1943#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 1944 u8 reserved[7]; 1945 __le32 addr_high; 1946 __le32 addr_low; 1947}; 1948 1949I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 1950 1951/* Add LLDP TLV (indirect 0x0A02) 1952 * Delete LLDP TLV (indirect 0x0A04) 1953 */ 1954struct i40e_aqc_lldp_add_tlv { 1955 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1956 u8 reserved1[1]; 1957 __le16 len; 1958 u8 reserved2[4]; 1959 __le32 addr_high; 1960 __le32 addr_low; 1961}; 1962 1963I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 1964 1965/* Update LLDP TLV (indirect 0x0A03) */ 1966struct i40e_aqc_lldp_update_tlv { 1967 u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 1968 u8 reserved; 1969 __le16 old_len; 1970 __le16 new_offset; 1971 __le16 new_len; 1972 __le32 addr_high; 1973 __le32 addr_low; 1974}; 1975 1976I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 1977 1978/* Stop LLDP (direct 0x0A05) */ 1979struct i40e_aqc_lldp_stop { 1980 u8 command; 1981#define I40E_AQ_LLDP_AGENT_STOP 0x0 1982#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 1983 u8 reserved[15]; 1984}; 1985 1986I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 1987 1988/* Start LLDP (direct 0x0A06) */ 1989 1990struct i40e_aqc_lldp_start { 1991 u8 command; 1992#define I40E_AQ_LLDP_AGENT_START 0x1 1993 u8 reserved[15]; 1994}; 1995 1996I40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 1997 1998/* Apply MIB changes (0x0A07) 1999 * uses the generic struc as it contains no data 2000 */ 2001 2002/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2003struct i40e_aqc_add_udp_tunnel { 2004 __le16 udp_port; 2005 u8 reserved0[3]; 2006 u8 protocol_type; 2007#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2008#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2009#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2010 u8 reserved1[10]; 2011}; 2012 2013I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2014 2015struct i40e_aqc_add_udp_tunnel_completion { 2016 __le16 udp_port; 2017 u8 filter_entry_index; 2018 u8 multiple_pfs; 2019#define I40E_AQC_SINGLE_PF 0x0 2020#define I40E_AQC_MULTIPLE_PFS 0x1 2021 u8 total_filters; 2022 u8 reserved[11]; 2023}; 2024 2025I40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2026 2027/* remove UDP Tunnel command (0x0B01) */ 2028struct i40e_aqc_remove_udp_tunnel { 2029 u8 reserved[2]; 2030 u8 index; /* 0 to 15 */ 2031 u8 reserved2[13]; 2032}; 2033 2034I40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2035 2036struct i40e_aqc_del_udp_tunnel_completion { 2037 __le16 udp_port; 2038 u8 index; /* 0 to 15 */ 2039 u8 multiple_pfs; 2040 u8 total_filters_used; 2041 u8 reserved1[11]; 2042}; 2043 2044I40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2045 2046/* tunnel key structure 0x0B10 */ 2047 2048struct i40e_aqc_tunnel_key_structure { 2049 u8 key1_off; 2050 u8 key2_off; 2051 u8 key1_len; /* 0 to 15 */ 2052 u8 key2_len; /* 0 to 15 */ 2053 u8 flags; 2054#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2055/* response flags */ 2056#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2057#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2058#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2059 u8 network_key_index; 2060#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2061#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2062#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2063#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2064 u8 reserved[10]; 2065}; 2066 2067I40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2068 2069/* OEM mode commands (direct 0xFE0x) */ 2070struct i40e_aqc_oem_param_change { 2071 __le32 param_type; 2072#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2073#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2074#define I40E_AQ_OEM_PARAM_MAC 2 2075 __le32 param_value1; 2076 u8 param_value2[8]; 2077}; 2078 2079I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2080 2081struct i40e_aqc_oem_state_change { 2082 __le32 state; 2083#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2084#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2085 u8 reserved[12]; 2086}; 2087 2088I40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2089 2090/* debug commands */ 2091 2092/* get device id (0xFF00) uses the generic structure */ 2093 2094/* set test more (0xFF01, internal) */ 2095 2096struct i40e_acq_set_test_mode { 2097 u8 mode; 2098#define I40E_AQ_TEST_PARTIAL 0 2099#define I40E_AQ_TEST_FULL 1 2100#define I40E_AQ_TEST_NVM 2 2101 u8 reserved[3]; 2102 u8 command; 2103#define I40E_AQ_TEST_OPEN 0 2104#define I40E_AQ_TEST_CLOSE 1 2105#define I40E_AQ_TEST_INC 2 2106 u8 reserved2[3]; 2107 __le32 address_high; 2108 __le32 address_low; 2109}; 2110 2111I40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2112 2113/* Debug Read Register command (0xFF03) 2114 * Debug Write Register command (0xFF04) 2115 */ 2116struct i40e_aqc_debug_reg_read_write { 2117 __le32 reserved; 2118 __le32 address; 2119 __le32 value_high; 2120 __le32 value_low; 2121}; 2122 2123I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2124 2125/* Scatter/gather Reg Read (indirect 0xFF05) 2126 * Scatter/gather Reg Write (indirect 0xFF06) 2127 */ 2128 2129/* i40e_aq_desc is used for the command */ 2130struct i40e_aqc_debug_reg_sg_element_data { 2131 __le32 address; 2132 __le32 value; 2133}; 2134 2135/* Debug Modify register (direct 0xFF07) */ 2136struct i40e_aqc_debug_modify_reg { 2137 __le32 address; 2138 __le32 value; 2139 __le32 clear_mask; 2140 __le32 set_mask; 2141}; 2142 2143I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2144 2145/* dump internal data (0xFF08, indirect) */ 2146 2147#define I40E_AQ_CLUSTER_ID_AUX 0 2148#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2149#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2150#define I40E_AQ_CLUSTER_ID_HMC 3 2151#define I40E_AQ_CLUSTER_ID_MAC0 4 2152#define I40E_AQ_CLUSTER_ID_MAC1 5 2153#define I40E_AQ_CLUSTER_ID_MAC2 6 2154#define I40E_AQ_CLUSTER_ID_MAC3 7 2155#define I40E_AQ_CLUSTER_ID_DCB 8 2156#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2157#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2158#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2159 2160struct i40e_aqc_debug_dump_internals { 2161 u8 cluster_id; 2162 u8 table_id; 2163 __le16 data_size; 2164 __le32 idx; 2165 __le32 address_high; 2166 __le32 address_low; 2167}; 2168 2169I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2170 2171struct i40e_aqc_debug_modify_internals { 2172 u8 cluster_id; 2173 u8 cluster_specific_params[7]; 2174 __le32 address_high; 2175 __le32 address_low; 2176}; 2177 2178I40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2179 2180#endif 2181