1270631Sjfv/****************************************************************************** 2270631Sjfv 3292095Ssmh Copyright (c) 2013-2015, Intel Corporation 4270631Sjfv All rights reserved. 5270631Sjfv 6270631Sjfv Redistribution and use in source and binary forms, with or without 7270631Sjfv modification, are permitted provided that the following conditions are met: 8270631Sjfv 9270631Sjfv 1. Redistributions of source code must retain the above copyright notice, 10270631Sjfv this list of conditions and the following disclaimer. 11270631Sjfv 12270631Sjfv 2. Redistributions in binary form must reproduce the above copyright 13270631Sjfv notice, this list of conditions and the following disclaimer in the 14270631Sjfv documentation and/or other materials provided with the distribution. 15270631Sjfv 16270631Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17270631Sjfv contributors may be used to endorse or promote products derived from 18270631Sjfv this software without specific prior written permission. 19270631Sjfv 20270631Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21270631Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22270631Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23270631Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24270631Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25270631Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26270631Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27270631Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28270631Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29270631Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30270631Sjfv POSSIBILITY OF SUCH DAMAGE. 31270631Sjfv 32270631Sjfv******************************************************************************/ 33270631Sjfv/*$FreeBSD$*/ 34270631Sjfv 35270631Sjfv#ifndef _I40E_ADMINQ_CMD_H_ 36270631Sjfv#define _I40E_ADMINQ_CMD_H_ 37270631Sjfv 38270631Sjfv/* This header file defines the i40e Admin Queue commands and is shared between 39270631Sjfv * i40e Firmware and Software. 40270631Sjfv * 41270631Sjfv * This file needs to comply with the Linux Kernel coding style. 42270631Sjfv */ 43270631Sjfv 44270631Sjfv#define I40E_FW_API_VERSION_MAJOR 0x0001 45292100Ssmh#ifdef X722_SUPPORT 46292100Ssmh#define I40E_FW_API_VERSION_MINOR 0x0003 47292100Ssmh#else 48292100Ssmh#define I40E_FW_API_VERSION_MINOR 0x0004 49292100Ssmh#endif 50270631Sjfv 51270631Sjfvstruct i40e_aq_desc { 52270631Sjfv __le16 flags; 53270631Sjfv __le16 opcode; 54270631Sjfv __le16 datalen; 55270631Sjfv __le16 retval; 56270631Sjfv __le32 cookie_high; 57270631Sjfv __le32 cookie_low; 58270631Sjfv union { 59270631Sjfv struct { 60270631Sjfv __le32 param0; 61270631Sjfv __le32 param1; 62270631Sjfv __le32 param2; 63270631Sjfv __le32 param3; 64270631Sjfv } internal; 65270631Sjfv struct { 66270631Sjfv __le32 param0; 67270631Sjfv __le32 param1; 68270631Sjfv __le32 addr_high; 69270631Sjfv __le32 addr_low; 70270631Sjfv } external; 71270631Sjfv u8 raw[16]; 72270631Sjfv } params; 73270631Sjfv}; 74270631Sjfv 75270631Sjfv/* Flags sub-structure 76270631Sjfv * |0 |1 |2 |3 |4 |5 |6 |7 |8 |9 |10 |11 |12 |13 |14 |15 | 77270631Sjfv * |DD |CMP|ERR|VFE| * * RESERVED * * |LB |RD |VFC|BUF|SI |EI |FE | 78270631Sjfv */ 79270631Sjfv 80270631Sjfv/* command flags and offsets*/ 81270631Sjfv#define I40E_AQ_FLAG_DD_SHIFT 0 82270631Sjfv#define I40E_AQ_FLAG_CMP_SHIFT 1 83270631Sjfv#define I40E_AQ_FLAG_ERR_SHIFT 2 84270631Sjfv#define I40E_AQ_FLAG_VFE_SHIFT 3 85270631Sjfv#define I40E_AQ_FLAG_LB_SHIFT 9 86270631Sjfv#define I40E_AQ_FLAG_RD_SHIFT 10 87270631Sjfv#define I40E_AQ_FLAG_VFC_SHIFT 11 88270631Sjfv#define I40E_AQ_FLAG_BUF_SHIFT 12 89270631Sjfv#define I40E_AQ_FLAG_SI_SHIFT 13 90270631Sjfv#define I40E_AQ_FLAG_EI_SHIFT 14 91270631Sjfv#define I40E_AQ_FLAG_FE_SHIFT 15 92270631Sjfv 93270631Sjfv#define I40E_AQ_FLAG_DD (1 << I40E_AQ_FLAG_DD_SHIFT) /* 0x1 */ 94270631Sjfv#define I40E_AQ_FLAG_CMP (1 << I40E_AQ_FLAG_CMP_SHIFT) /* 0x2 */ 95270631Sjfv#define I40E_AQ_FLAG_ERR (1 << I40E_AQ_FLAG_ERR_SHIFT) /* 0x4 */ 96270631Sjfv#define I40E_AQ_FLAG_VFE (1 << I40E_AQ_FLAG_VFE_SHIFT) /* 0x8 */ 97270631Sjfv#define I40E_AQ_FLAG_LB (1 << I40E_AQ_FLAG_LB_SHIFT) /* 0x200 */ 98270631Sjfv#define I40E_AQ_FLAG_RD (1 << I40E_AQ_FLAG_RD_SHIFT) /* 0x400 */ 99270631Sjfv#define I40E_AQ_FLAG_VFC (1 << I40E_AQ_FLAG_VFC_SHIFT) /* 0x800 */ 100270631Sjfv#define I40E_AQ_FLAG_BUF (1 << I40E_AQ_FLAG_BUF_SHIFT) /* 0x1000 */ 101270631Sjfv#define I40E_AQ_FLAG_SI (1 << I40E_AQ_FLAG_SI_SHIFT) /* 0x2000 */ 102270631Sjfv#define I40E_AQ_FLAG_EI (1 << I40E_AQ_FLAG_EI_SHIFT) /* 0x4000 */ 103270631Sjfv#define I40E_AQ_FLAG_FE (1 << I40E_AQ_FLAG_FE_SHIFT) /* 0x8000 */ 104270631Sjfv 105270631Sjfv/* error codes */ 106270631Sjfvenum i40e_admin_queue_err { 107270631Sjfv I40E_AQ_RC_OK = 0, /* success */ 108270631Sjfv I40E_AQ_RC_EPERM = 1, /* Operation not permitted */ 109270631Sjfv I40E_AQ_RC_ENOENT = 2, /* No such element */ 110270631Sjfv I40E_AQ_RC_ESRCH = 3, /* Bad opcode */ 111270631Sjfv I40E_AQ_RC_EINTR = 4, /* operation interrupted */ 112270631Sjfv I40E_AQ_RC_EIO = 5, /* I/O error */ 113270631Sjfv I40E_AQ_RC_ENXIO = 6, /* No such resource */ 114270631Sjfv I40E_AQ_RC_E2BIG = 7, /* Arg too long */ 115270631Sjfv I40E_AQ_RC_EAGAIN = 8, /* Try again */ 116270631Sjfv I40E_AQ_RC_ENOMEM = 9, /* Out of memory */ 117270631Sjfv I40E_AQ_RC_EACCES = 10, /* Permission denied */ 118270631Sjfv I40E_AQ_RC_EFAULT = 11, /* Bad address */ 119270631Sjfv I40E_AQ_RC_EBUSY = 12, /* Device or resource busy */ 120270631Sjfv I40E_AQ_RC_EEXIST = 13, /* object already exists */ 121270631Sjfv I40E_AQ_RC_EINVAL = 14, /* Invalid argument */ 122270631Sjfv I40E_AQ_RC_ENOTTY = 15, /* Not a typewriter */ 123270631Sjfv I40E_AQ_RC_ENOSPC = 16, /* No space left or alloc failure */ 124270631Sjfv I40E_AQ_RC_ENOSYS = 17, /* Function not implemented */ 125270631Sjfv I40E_AQ_RC_ERANGE = 18, /* Parameter out of range */ 126270631Sjfv I40E_AQ_RC_EFLUSHED = 19, /* Cmd flushed due to prev cmd error */ 127270631Sjfv I40E_AQ_RC_BAD_ADDR = 20, /* Descriptor contains a bad pointer */ 128270631Sjfv I40E_AQ_RC_EMODE = 21, /* Op not allowed in current dev mode */ 129270631Sjfv I40E_AQ_RC_EFBIG = 22, /* File too large */ 130270631Sjfv}; 131270631Sjfv 132270631Sjfv/* Admin Queue command opcodes */ 133270631Sjfvenum i40e_admin_queue_opc { 134270631Sjfv /* aq commands */ 135270631Sjfv i40e_aqc_opc_get_version = 0x0001, 136270631Sjfv i40e_aqc_opc_driver_version = 0x0002, 137270631Sjfv i40e_aqc_opc_queue_shutdown = 0x0003, 138270631Sjfv i40e_aqc_opc_set_pf_context = 0x0004, 139270631Sjfv 140270631Sjfv /* resource ownership */ 141270631Sjfv i40e_aqc_opc_request_resource = 0x0008, 142270631Sjfv i40e_aqc_opc_release_resource = 0x0009, 143270631Sjfv 144270631Sjfv i40e_aqc_opc_list_func_capabilities = 0x000A, 145270631Sjfv i40e_aqc_opc_list_dev_capabilities = 0x000B, 146270631Sjfv 147270631Sjfv /* LAA */ 148270631Sjfv i40e_aqc_opc_mac_address_read = 0x0107, 149270631Sjfv i40e_aqc_opc_mac_address_write = 0x0108, 150270631Sjfv 151270631Sjfv /* PXE */ 152270631Sjfv i40e_aqc_opc_clear_pxe_mode = 0x0110, 153270631Sjfv 154270631Sjfv /* internal switch commands */ 155270631Sjfv i40e_aqc_opc_get_switch_config = 0x0200, 156270631Sjfv i40e_aqc_opc_add_statistics = 0x0201, 157270631Sjfv i40e_aqc_opc_remove_statistics = 0x0202, 158270631Sjfv i40e_aqc_opc_set_port_parameters = 0x0203, 159270631Sjfv i40e_aqc_opc_get_switch_resource_alloc = 0x0204, 160270631Sjfv 161270631Sjfv i40e_aqc_opc_add_vsi = 0x0210, 162270631Sjfv i40e_aqc_opc_update_vsi_parameters = 0x0211, 163270631Sjfv i40e_aqc_opc_get_vsi_parameters = 0x0212, 164270631Sjfv 165270631Sjfv i40e_aqc_opc_add_pv = 0x0220, 166270631Sjfv i40e_aqc_opc_update_pv_parameters = 0x0221, 167270631Sjfv i40e_aqc_opc_get_pv_parameters = 0x0222, 168270631Sjfv 169270631Sjfv i40e_aqc_opc_add_veb = 0x0230, 170270631Sjfv i40e_aqc_opc_update_veb_parameters = 0x0231, 171270631Sjfv i40e_aqc_opc_get_veb_parameters = 0x0232, 172270631Sjfv 173270631Sjfv i40e_aqc_opc_delete_element = 0x0243, 174270631Sjfv 175270631Sjfv i40e_aqc_opc_add_macvlan = 0x0250, 176270631Sjfv i40e_aqc_opc_remove_macvlan = 0x0251, 177270631Sjfv i40e_aqc_opc_add_vlan = 0x0252, 178270631Sjfv i40e_aqc_opc_remove_vlan = 0x0253, 179270631Sjfv i40e_aqc_opc_set_vsi_promiscuous_modes = 0x0254, 180270631Sjfv i40e_aqc_opc_add_tag = 0x0255, 181270631Sjfv i40e_aqc_opc_remove_tag = 0x0256, 182270631Sjfv i40e_aqc_opc_add_multicast_etag = 0x0257, 183270631Sjfv i40e_aqc_opc_remove_multicast_etag = 0x0258, 184270631Sjfv i40e_aqc_opc_update_tag = 0x0259, 185270631Sjfv i40e_aqc_opc_add_control_packet_filter = 0x025A, 186270631Sjfv i40e_aqc_opc_remove_control_packet_filter = 0x025B, 187270631Sjfv i40e_aqc_opc_add_cloud_filters = 0x025C, 188270631Sjfv i40e_aqc_opc_remove_cloud_filters = 0x025D, 189270631Sjfv 190270631Sjfv i40e_aqc_opc_add_mirror_rule = 0x0260, 191270631Sjfv i40e_aqc_opc_delete_mirror_rule = 0x0261, 192270631Sjfv 193270631Sjfv /* DCB commands */ 194270631Sjfv i40e_aqc_opc_dcb_ignore_pfc = 0x0301, 195270631Sjfv i40e_aqc_opc_dcb_updated = 0x0302, 196270631Sjfv 197270631Sjfv /* TX scheduler */ 198270631Sjfv i40e_aqc_opc_configure_vsi_bw_limit = 0x0400, 199270631Sjfv i40e_aqc_opc_configure_vsi_ets_sla_bw_limit = 0x0406, 200270631Sjfv i40e_aqc_opc_configure_vsi_tc_bw = 0x0407, 201270631Sjfv i40e_aqc_opc_query_vsi_bw_config = 0x0408, 202270631Sjfv i40e_aqc_opc_query_vsi_ets_sla_config = 0x040A, 203270631Sjfv i40e_aqc_opc_configure_switching_comp_bw_limit = 0x0410, 204270631Sjfv 205270631Sjfv i40e_aqc_opc_enable_switching_comp_ets = 0x0413, 206270631Sjfv i40e_aqc_opc_modify_switching_comp_ets = 0x0414, 207270631Sjfv i40e_aqc_opc_disable_switching_comp_ets = 0x0415, 208270631Sjfv i40e_aqc_opc_configure_switching_comp_ets_bw_limit = 0x0416, 209270631Sjfv i40e_aqc_opc_configure_switching_comp_bw_config = 0x0417, 210270631Sjfv i40e_aqc_opc_query_switching_comp_ets_config = 0x0418, 211270631Sjfv i40e_aqc_opc_query_port_ets_config = 0x0419, 212270631Sjfv i40e_aqc_opc_query_switching_comp_bw_config = 0x041A, 213270631Sjfv i40e_aqc_opc_suspend_port_tx = 0x041B, 214270631Sjfv i40e_aqc_opc_resume_port_tx = 0x041C, 215270631Sjfv i40e_aqc_opc_configure_partition_bw = 0x041D, 216270631Sjfv 217270631Sjfv /* hmc */ 218270631Sjfv i40e_aqc_opc_query_hmc_resource_profile = 0x0500, 219270631Sjfv i40e_aqc_opc_set_hmc_resource_profile = 0x0501, 220270631Sjfv 221270631Sjfv /* phy commands*/ 222270631Sjfv i40e_aqc_opc_get_phy_abilities = 0x0600, 223270631Sjfv i40e_aqc_opc_set_phy_config = 0x0601, 224270631Sjfv i40e_aqc_opc_set_mac_config = 0x0603, 225270631Sjfv i40e_aqc_opc_set_link_restart_an = 0x0605, 226270631Sjfv i40e_aqc_opc_get_link_status = 0x0607, 227270631Sjfv i40e_aqc_opc_set_phy_int_mask = 0x0613, 228270631Sjfv i40e_aqc_opc_get_local_advt_reg = 0x0614, 229270631Sjfv i40e_aqc_opc_set_local_advt_reg = 0x0615, 230270631Sjfv i40e_aqc_opc_get_partner_advt = 0x0616, 231270631Sjfv i40e_aqc_opc_set_lb_modes = 0x0618, 232270631Sjfv i40e_aqc_opc_get_phy_wol_caps = 0x0621, 233270631Sjfv i40e_aqc_opc_set_phy_debug = 0x0622, 234270631Sjfv i40e_aqc_opc_upload_ext_phy_fm = 0x0625, 235270631Sjfv 236270631Sjfv /* NVM commands */ 237270631Sjfv i40e_aqc_opc_nvm_read = 0x0701, 238270631Sjfv i40e_aqc_opc_nvm_erase = 0x0702, 239270631Sjfv i40e_aqc_opc_nvm_update = 0x0703, 240270631Sjfv i40e_aqc_opc_nvm_config_read = 0x0704, 241270631Sjfv i40e_aqc_opc_nvm_config_write = 0x0705, 242292100Ssmh i40e_aqc_opc_oem_post_update = 0x0720, 243270631Sjfv 244270631Sjfv /* virtualization commands */ 245270631Sjfv i40e_aqc_opc_send_msg_to_pf = 0x0801, 246270631Sjfv i40e_aqc_opc_send_msg_to_vf = 0x0802, 247270631Sjfv i40e_aqc_opc_send_msg_to_peer = 0x0803, 248270631Sjfv 249270631Sjfv /* alternate structure */ 250270631Sjfv i40e_aqc_opc_alternate_write = 0x0900, 251270631Sjfv i40e_aqc_opc_alternate_write_indirect = 0x0901, 252270631Sjfv i40e_aqc_opc_alternate_read = 0x0902, 253270631Sjfv i40e_aqc_opc_alternate_read_indirect = 0x0903, 254270631Sjfv i40e_aqc_opc_alternate_write_done = 0x0904, 255270631Sjfv i40e_aqc_opc_alternate_set_mode = 0x0905, 256270631Sjfv i40e_aqc_opc_alternate_clear_port = 0x0906, 257270631Sjfv 258270631Sjfv /* LLDP commands */ 259270631Sjfv i40e_aqc_opc_lldp_get_mib = 0x0A00, 260270631Sjfv i40e_aqc_opc_lldp_update_mib = 0x0A01, 261270631Sjfv i40e_aqc_opc_lldp_add_tlv = 0x0A02, 262270631Sjfv i40e_aqc_opc_lldp_update_tlv = 0x0A03, 263270631Sjfv i40e_aqc_opc_lldp_delete_tlv = 0x0A04, 264270631Sjfv i40e_aqc_opc_lldp_stop = 0x0A05, 265270631Sjfv i40e_aqc_opc_lldp_start = 0x0A06, 266291248Ssmh i40e_aqc_opc_get_cee_dcb_cfg = 0x0A07, 267291248Ssmh i40e_aqc_opc_lldp_set_local_mib = 0x0A08, 268291248Ssmh i40e_aqc_opc_lldp_stop_start_spec_agent = 0x0A09, 269270631Sjfv 270270631Sjfv /* Tunnel commands */ 271270631Sjfv i40e_aqc_opc_add_udp_tunnel = 0x0B00, 272270631Sjfv i40e_aqc_opc_del_udp_tunnel = 0x0B01, 273292100Ssmh#ifdef X722_SUPPORT 274292100Ssmh i40e_aqc_opc_set_rss_key = 0x0B02, 275292100Ssmh i40e_aqc_opc_set_rss_lut = 0x0B03, 276292100Ssmh i40e_aqc_opc_get_rss_key = 0x0B04, 277292100Ssmh i40e_aqc_opc_get_rss_lut = 0x0B05, 278292100Ssmh#endif 279270631Sjfv 280270631Sjfv /* Async Events */ 281270631Sjfv i40e_aqc_opc_event_lan_overflow = 0x1001, 282270631Sjfv 283270631Sjfv /* OEM commands */ 284270631Sjfv i40e_aqc_opc_oem_parameter_change = 0xFE00, 285270631Sjfv i40e_aqc_opc_oem_device_status_change = 0xFE01, 286291248Ssmh i40e_aqc_opc_oem_ocsd_initialize = 0xFE02, 287291248Ssmh i40e_aqc_opc_oem_ocbb_initialize = 0xFE03, 288270631Sjfv 289270631Sjfv /* debug commands */ 290270631Sjfv i40e_aqc_opc_debug_read_reg = 0xFF03, 291270631Sjfv i40e_aqc_opc_debug_write_reg = 0xFF04, 292270631Sjfv i40e_aqc_opc_debug_modify_reg = 0xFF07, 293270631Sjfv i40e_aqc_opc_debug_dump_internals = 0xFF08, 294270631Sjfv}; 295270631Sjfv 296270631Sjfv/* command structures and indirect data structures */ 297270631Sjfv 298270631Sjfv/* Structure naming conventions: 299270631Sjfv * - no suffix for direct command descriptor structures 300270631Sjfv * - _data for indirect sent data 301270631Sjfv * - _resp for indirect return data (data which is both will use _data) 302270631Sjfv * - _completion for direct return data 303270631Sjfv * - _element_ for repeated elements (may also be _data or _resp) 304270631Sjfv * 305270631Sjfv * Command structures are expected to overlay the params.raw member of the basic 306270631Sjfv * descriptor, and as such cannot exceed 16 bytes in length. 307270631Sjfv */ 308270631Sjfv 309270631Sjfv/* This macro is used to generate a compilation error if a structure 310270631Sjfv * is not exactly the correct length. It gives a divide by zero error if the 311270631Sjfv * structure is not of the correct size, otherwise it creates an enum that is 312270631Sjfv * never used. 313270631Sjfv */ 314270631Sjfv#define I40E_CHECK_STRUCT_LEN(n, X) enum i40e_static_assert_enum_##X \ 315270631Sjfv { i40e_static_assert_##X = (n)/((sizeof(struct X) == (n)) ? 1 : 0) } 316270631Sjfv 317270631Sjfv/* This macro is used extensively to ensure that command structures are 16 318270631Sjfv * bytes in length as they have to map to the raw array of that size. 319270631Sjfv */ 320270631Sjfv#define I40E_CHECK_CMD_LENGTH(X) I40E_CHECK_STRUCT_LEN(16, X) 321270631Sjfv 322270631Sjfv/* internal (0x00XX) commands */ 323270631Sjfv 324270631Sjfv/* Get version (direct 0x0001) */ 325270631Sjfvstruct i40e_aqc_get_version { 326270631Sjfv __le32 rom_ver; 327270631Sjfv __le32 fw_build; 328270631Sjfv __le16 fw_major; 329270631Sjfv __le16 fw_minor; 330270631Sjfv __le16 api_major; 331270631Sjfv __le16 api_minor; 332270631Sjfv}; 333270631Sjfv 334270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_version); 335270631Sjfv 336270631Sjfv/* Send driver version (indirect 0x0002) */ 337270631Sjfvstruct i40e_aqc_driver_version { 338270631Sjfv u8 driver_major_ver; 339270631Sjfv u8 driver_minor_ver; 340270631Sjfv u8 driver_build_ver; 341270631Sjfv u8 driver_subbuild_ver; 342270631Sjfv u8 reserved[4]; 343270631Sjfv __le32 address_high; 344270631Sjfv __le32 address_low; 345270631Sjfv}; 346270631Sjfv 347270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_driver_version); 348270631Sjfv 349270631Sjfv/* Queue Shutdown (direct 0x0003) */ 350270631Sjfvstruct i40e_aqc_queue_shutdown { 351270631Sjfv __le32 driver_unloading; 352270631Sjfv#define I40E_AQ_DRIVER_UNLOADING 0x1 353270631Sjfv u8 reserved[12]; 354270631Sjfv}; 355270631Sjfv 356270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_queue_shutdown); 357270631Sjfv 358270631Sjfv/* Set PF context (0x0004, direct) */ 359270631Sjfvstruct i40e_aqc_set_pf_context { 360270631Sjfv u8 pf_id; 361270631Sjfv u8 reserved[15]; 362270631Sjfv}; 363270631Sjfv 364270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_pf_context); 365270631Sjfv 366270631Sjfv/* Request resource ownership (direct 0x0008) 367270631Sjfv * Release resource ownership (direct 0x0009) 368270631Sjfv */ 369270631Sjfv#define I40E_AQ_RESOURCE_NVM 1 370270631Sjfv#define I40E_AQ_RESOURCE_SDP 2 371270631Sjfv#define I40E_AQ_RESOURCE_ACCESS_READ 1 372270631Sjfv#define I40E_AQ_RESOURCE_ACCESS_WRITE 2 373270631Sjfv#define I40E_AQ_RESOURCE_NVM_READ_TIMEOUT 3000 374270631Sjfv#define I40E_AQ_RESOURCE_NVM_WRITE_TIMEOUT 180000 375270631Sjfv 376270631Sjfvstruct i40e_aqc_request_resource { 377270631Sjfv __le16 resource_id; 378270631Sjfv __le16 access_type; 379270631Sjfv __le32 timeout; 380270631Sjfv __le32 resource_number; 381270631Sjfv u8 reserved[4]; 382270631Sjfv}; 383270631Sjfv 384270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_request_resource); 385270631Sjfv 386270631Sjfv/* Get function capabilities (indirect 0x000A) 387270631Sjfv * Get device capabilities (indirect 0x000B) 388270631Sjfv */ 389270631Sjfvstruct i40e_aqc_list_capabilites { 390270631Sjfv u8 command_flags; 391270631Sjfv#define I40E_AQ_LIST_CAP_PF_INDEX_EN 1 392270631Sjfv u8 pf_index; 393270631Sjfv u8 reserved[2]; 394270631Sjfv __le32 count; 395270631Sjfv __le32 addr_high; 396270631Sjfv __le32 addr_low; 397270631Sjfv}; 398270631Sjfv 399270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_list_capabilites); 400270631Sjfv 401270631Sjfvstruct i40e_aqc_list_capabilities_element_resp { 402270631Sjfv __le16 id; 403270631Sjfv u8 major_rev; 404270631Sjfv u8 minor_rev; 405270631Sjfv __le32 number; 406270631Sjfv __le32 logical_id; 407270631Sjfv __le32 phys_id; 408270631Sjfv u8 reserved[16]; 409270631Sjfv}; 410270631Sjfv 411270631Sjfv/* list of caps */ 412270631Sjfv 413270631Sjfv#define I40E_AQ_CAP_ID_SWITCH_MODE 0x0001 414270631Sjfv#define I40E_AQ_CAP_ID_MNG_MODE 0x0002 415270631Sjfv#define I40E_AQ_CAP_ID_NPAR_ACTIVE 0x0003 416270631Sjfv#define I40E_AQ_CAP_ID_OS2BMC_CAP 0x0004 417270631Sjfv#define I40E_AQ_CAP_ID_FUNCTIONS_VALID 0x0005 418270631Sjfv#define I40E_AQ_CAP_ID_ALTERNATE_RAM 0x0006 419270631Sjfv#define I40E_AQ_CAP_ID_SRIOV 0x0012 420270631Sjfv#define I40E_AQ_CAP_ID_VF 0x0013 421270631Sjfv#define I40E_AQ_CAP_ID_VMDQ 0x0014 422270631Sjfv#define I40E_AQ_CAP_ID_8021QBG 0x0015 423270631Sjfv#define I40E_AQ_CAP_ID_8021QBR 0x0016 424270631Sjfv#define I40E_AQ_CAP_ID_VSI 0x0017 425270631Sjfv#define I40E_AQ_CAP_ID_DCB 0x0018 426270631Sjfv#define I40E_AQ_CAP_ID_FCOE 0x0021 427291248Ssmh#define I40E_AQ_CAP_ID_ISCSI 0x0022 428270631Sjfv#define I40E_AQ_CAP_ID_RSS 0x0040 429270631Sjfv#define I40E_AQ_CAP_ID_RXQ 0x0041 430270631Sjfv#define I40E_AQ_CAP_ID_TXQ 0x0042 431270631Sjfv#define I40E_AQ_CAP_ID_MSIX 0x0043 432270631Sjfv#define I40E_AQ_CAP_ID_VF_MSIX 0x0044 433270631Sjfv#define I40E_AQ_CAP_ID_FLOW_DIRECTOR 0x0045 434270631Sjfv#define I40E_AQ_CAP_ID_1588 0x0046 435270631Sjfv#define I40E_AQ_CAP_ID_IWARP 0x0051 436270631Sjfv#define I40E_AQ_CAP_ID_LED 0x0061 437270631Sjfv#define I40E_AQ_CAP_ID_SDP 0x0062 438270631Sjfv#define I40E_AQ_CAP_ID_MDIO 0x0063 439270631Sjfv#define I40E_AQ_CAP_ID_FLEX10 0x00F1 440270631Sjfv#define I40E_AQ_CAP_ID_CEM 0x00F2 441270631Sjfv 442270631Sjfv/* Set CPPM Configuration (direct 0x0103) */ 443270631Sjfvstruct i40e_aqc_cppm_configuration { 444270631Sjfv __le16 command_flags; 445270631Sjfv#define I40E_AQ_CPPM_EN_LTRC 0x0800 446270631Sjfv#define I40E_AQ_CPPM_EN_DMCTH 0x1000 447270631Sjfv#define I40E_AQ_CPPM_EN_DMCTLX 0x2000 448270631Sjfv#define I40E_AQ_CPPM_EN_HPTC 0x4000 449270631Sjfv#define I40E_AQ_CPPM_EN_DMARC 0x8000 450270631Sjfv __le16 ttlx; 451270631Sjfv __le32 dmacr; 452270631Sjfv __le16 dmcth; 453270631Sjfv u8 hptc; 454270631Sjfv u8 reserved; 455270631Sjfv __le32 pfltrc; 456270631Sjfv}; 457270631Sjfv 458270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_cppm_configuration); 459270631Sjfv 460270631Sjfv/* Set ARP Proxy command / response (indirect 0x0104) */ 461270631Sjfvstruct i40e_aqc_arp_proxy_data { 462270631Sjfv __le16 command_flags; 463270631Sjfv#define I40E_AQ_ARP_INIT_IPV4 0x0008 464270631Sjfv#define I40E_AQ_ARP_UNSUP_CTL 0x0010 465270631Sjfv#define I40E_AQ_ARP_ENA 0x0020 466270631Sjfv#define I40E_AQ_ARP_ADD_IPV4 0x0040 467270631Sjfv#define I40E_AQ_ARP_DEL_IPV4 0x0080 468270631Sjfv __le16 table_id; 469270631Sjfv __le32 pfpm_proxyfc; 470270631Sjfv __le32 ip_addr; 471270631Sjfv u8 mac_addr[6]; 472291248Ssmh u8 reserved[2]; 473270631Sjfv}; 474270631Sjfv 475291248SsmhI40E_CHECK_STRUCT_LEN(0x14, i40e_aqc_arp_proxy_data); 476291248Ssmh 477270631Sjfv/* Set NS Proxy Table Entry Command (indirect 0x0105) */ 478270631Sjfvstruct i40e_aqc_ns_proxy_data { 479270631Sjfv __le16 table_idx_mac_addr_0; 480270631Sjfv __le16 table_idx_mac_addr_1; 481270631Sjfv __le16 table_idx_ipv6_0; 482270631Sjfv __le16 table_idx_ipv6_1; 483270631Sjfv __le16 control; 484270631Sjfv#define I40E_AQ_NS_PROXY_ADD_0 0x0100 485270631Sjfv#define I40E_AQ_NS_PROXY_DEL_0 0x0200 486270631Sjfv#define I40E_AQ_NS_PROXY_ADD_1 0x0400 487270631Sjfv#define I40E_AQ_NS_PROXY_DEL_1 0x0800 488270631Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_0 0x1000 489270631Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_0 0x2000 490270631Sjfv#define I40E_AQ_NS_PROXY_ADD_IPV6_1 0x4000 491270631Sjfv#define I40E_AQ_NS_PROXY_DEL_IPV6_1 0x8000 492270631Sjfv#define I40E_AQ_NS_PROXY_COMMAND_SEQ 0x0001 493270631Sjfv#define I40E_AQ_NS_PROXY_INIT_IPV6_TBL 0x0002 494270631Sjfv#define I40E_AQ_NS_PROXY_INIT_MAC_TBL 0x0004 495270631Sjfv u8 mac_addr_0[6]; 496270631Sjfv u8 mac_addr_1[6]; 497270631Sjfv u8 local_mac_addr[6]; 498270631Sjfv u8 ipv6_addr_0[16]; /* Warning! spec specifies BE byte order */ 499270631Sjfv u8 ipv6_addr_1[16]; 500270631Sjfv}; 501270631Sjfv 502291248SsmhI40E_CHECK_STRUCT_LEN(0x3c, i40e_aqc_ns_proxy_data); 503291248Ssmh 504270631Sjfv/* Manage LAA Command (0x0106) - obsolete */ 505270631Sjfvstruct i40e_aqc_mng_laa { 506270631Sjfv __le16 command_flags; 507270631Sjfv#define I40E_AQ_LAA_FLAG_WR 0x8000 508270631Sjfv u8 reserved[2]; 509270631Sjfv __le32 sal; 510270631Sjfv __le16 sah; 511270631Sjfv u8 reserved2[6]; 512270631Sjfv}; 513270631Sjfv 514291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_mng_laa); 515291248Ssmh 516270631Sjfv/* Manage MAC Address Read Command (indirect 0x0107) */ 517270631Sjfvstruct i40e_aqc_mac_address_read { 518270631Sjfv __le16 command_flags; 519270631Sjfv#define I40E_AQC_LAN_ADDR_VALID 0x10 520270631Sjfv#define I40E_AQC_SAN_ADDR_VALID 0x20 521270631Sjfv#define I40E_AQC_PORT_ADDR_VALID 0x40 522270631Sjfv#define I40E_AQC_WOL_ADDR_VALID 0x80 523292100Ssmh#define I40E_AQC_MC_MAG_EN_VALID 0x100 524292100Ssmh#define I40E_AQC_ADDR_VALID_MASK 0x1F0 525270631Sjfv u8 reserved[6]; 526270631Sjfv __le32 addr_high; 527270631Sjfv __le32 addr_low; 528270631Sjfv}; 529270631Sjfv 530270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_read); 531270631Sjfv 532270631Sjfvstruct i40e_aqc_mac_address_read_data { 533270631Sjfv u8 pf_lan_mac[6]; 534270631Sjfv u8 pf_san_mac[6]; 535270631Sjfv u8 port_mac[6]; 536270631Sjfv u8 pf_wol_mac[6]; 537270631Sjfv}; 538270631Sjfv 539270631SjfvI40E_CHECK_STRUCT_LEN(24, i40e_aqc_mac_address_read_data); 540270631Sjfv 541270631Sjfv/* Manage MAC Address Write Command (0x0108) */ 542270631Sjfvstruct i40e_aqc_mac_address_write { 543270631Sjfv __le16 command_flags; 544270631Sjfv#define I40E_AQC_WRITE_TYPE_LAA_ONLY 0x0000 545270631Sjfv#define I40E_AQC_WRITE_TYPE_LAA_WOL 0x4000 546270631Sjfv#define I40E_AQC_WRITE_TYPE_PORT 0x8000 547292100Ssmh#define I40E_AQC_WRITE_TYPE_UPDATE_MC_MAG 0xC000 548292100Ssmh#define I40E_AQC_WRITE_TYPE_MASK 0xC000 549292100Ssmh 550270631Sjfv __le16 mac_sah; 551270631Sjfv __le32 mac_sal; 552270631Sjfv u8 reserved[8]; 553270631Sjfv}; 554270631Sjfv 555270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_mac_address_write); 556270631Sjfv 557270631Sjfv/* PXE commands (0x011x) */ 558270631Sjfv 559270631Sjfv/* Clear PXE Command and response (direct 0x0110) */ 560270631Sjfvstruct i40e_aqc_clear_pxe { 561270631Sjfv u8 rx_cnt; 562270631Sjfv u8 reserved[15]; 563270631Sjfv}; 564270631Sjfv 565270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_clear_pxe); 566270631Sjfv 567270631Sjfv/* Switch configuration commands (0x02xx) */ 568270631Sjfv 569270631Sjfv/* Used by many indirect commands that only pass an seid and a buffer in the 570270631Sjfv * command 571270631Sjfv */ 572270631Sjfvstruct i40e_aqc_switch_seid { 573270631Sjfv __le16 seid; 574270631Sjfv u8 reserved[6]; 575270631Sjfv __le32 addr_high; 576270631Sjfv __le32 addr_low; 577270631Sjfv}; 578270631Sjfv 579270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_switch_seid); 580270631Sjfv 581270631Sjfv/* Get Switch Configuration command (indirect 0x0200) 582270631Sjfv * uses i40e_aqc_switch_seid for the descriptor 583270631Sjfv */ 584270631Sjfvstruct i40e_aqc_get_switch_config_header_resp { 585270631Sjfv __le16 num_reported; 586270631Sjfv __le16 num_total; 587270631Sjfv u8 reserved[12]; 588270631Sjfv}; 589270631Sjfv 590291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_config_header_resp); 591291248Ssmh 592270631Sjfvstruct i40e_aqc_switch_config_element_resp { 593270631Sjfv u8 element_type; 594270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_MAC 1 595270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_PF 2 596270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_VF 3 597270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_EMP 4 598270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_BMC 5 599270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_PV 16 600270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_VEB 17 601270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_PA 18 602270631Sjfv#define I40E_AQ_SW_ELEM_TYPE_VSI 19 603270631Sjfv u8 revision; 604270631Sjfv#define I40E_AQ_SW_ELEM_REV_1 1 605270631Sjfv __le16 seid; 606270631Sjfv __le16 uplink_seid; 607270631Sjfv __le16 downlink_seid; 608270631Sjfv u8 reserved[3]; 609270631Sjfv u8 connection_type; 610270631Sjfv#define I40E_AQ_CONN_TYPE_REGULAR 0x1 611270631Sjfv#define I40E_AQ_CONN_TYPE_DEFAULT 0x2 612270631Sjfv#define I40E_AQ_CONN_TYPE_CASCADED 0x3 613270631Sjfv __le16 scheduler_id; 614270631Sjfv __le16 element_info; 615270631Sjfv}; 616270631Sjfv 617291248SsmhI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_config_element_resp); 618291248Ssmh 619270631Sjfv/* Get Switch Configuration (indirect 0x0200) 620270631Sjfv * an array of elements are returned in the response buffer 621270631Sjfv * the first in the array is the header, remainder are elements 622270631Sjfv */ 623270631Sjfvstruct i40e_aqc_get_switch_config_resp { 624270631Sjfv struct i40e_aqc_get_switch_config_header_resp header; 625270631Sjfv struct i40e_aqc_switch_config_element_resp element[1]; 626270631Sjfv}; 627270631Sjfv 628291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_switch_config_resp); 629291248Ssmh 630270631Sjfv/* Add Statistics (direct 0x0201) 631270631Sjfv * Remove Statistics (direct 0x0202) 632270631Sjfv */ 633270631Sjfvstruct i40e_aqc_add_remove_statistics { 634270631Sjfv __le16 seid; 635270631Sjfv __le16 vlan; 636270631Sjfv __le16 stat_index; 637270631Sjfv u8 reserved[10]; 638270631Sjfv}; 639270631Sjfv 640270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_statistics); 641270631Sjfv 642270631Sjfv/* Set Port Parameters command (direct 0x0203) */ 643270631Sjfvstruct i40e_aqc_set_port_parameters { 644270631Sjfv __le16 command_flags; 645270631Sjfv#define I40E_AQ_SET_P_PARAMS_SAVE_BAD_PACKETS 1 646270631Sjfv#define I40E_AQ_SET_P_PARAMS_PAD_SHORT_PACKETS 2 /* must set! */ 647270631Sjfv#define I40E_AQ_SET_P_PARAMS_DOUBLE_VLAN_ENA 4 648270631Sjfv __le16 bad_frame_vsi; 649270631Sjfv __le16 default_seid; /* reserved for command */ 650270631Sjfv u8 reserved[10]; 651270631Sjfv}; 652270631Sjfv 653270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_port_parameters); 654270631Sjfv 655270631Sjfv/* Get Switch Resource Allocation (indirect 0x0204) */ 656270631Sjfvstruct i40e_aqc_get_switch_resource_alloc { 657270631Sjfv u8 num_entries; /* reserved for command */ 658270631Sjfv u8 reserved[7]; 659270631Sjfv __le32 addr_high; 660270631Sjfv __le32 addr_low; 661270631Sjfv}; 662270631Sjfv 663270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_switch_resource_alloc); 664270631Sjfv 665270631Sjfv/* expect an array of these structs in the response buffer */ 666270631Sjfvstruct i40e_aqc_switch_resource_alloc_element_resp { 667270631Sjfv u8 resource_type; 668270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VEB 0x0 669270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI 0x1 670270631Sjfv#define I40E_AQ_RESOURCE_TYPE_MACADDR 0x2 671270631Sjfv#define I40E_AQ_RESOURCE_TYPE_STAG 0x3 672270631Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG 0x4 673270631Sjfv#define I40E_AQ_RESOURCE_TYPE_MULTICAST_HASH 0x5 674270631Sjfv#define I40E_AQ_RESOURCE_TYPE_UNICAST_HASH 0x6 675270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN 0x7 676270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VSI_LIST_ENTRY 0x8 677270631Sjfv#define I40E_AQ_RESOURCE_TYPE_ETAG_LIST_ENTRY 0x9 678270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_STAT_POOL 0xA 679270631Sjfv#define I40E_AQ_RESOURCE_TYPE_MIRROR_RULE 0xB 680270631Sjfv#define I40E_AQ_RESOURCE_TYPE_QUEUE_SETS 0xC 681270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VLAN_FILTERS 0xD 682270631Sjfv#define I40E_AQ_RESOURCE_TYPE_INNER_MAC_FILTERS 0xF 683270631Sjfv#define I40E_AQ_RESOURCE_TYPE_IP_FILTERS 0x10 684270631Sjfv#define I40E_AQ_RESOURCE_TYPE_GRE_VN_KEYS 0x11 685270631Sjfv#define I40E_AQ_RESOURCE_TYPE_VN2_KEYS 0x12 686270631Sjfv#define I40E_AQ_RESOURCE_TYPE_TUNNEL_PORTS 0x13 687270631Sjfv u8 reserved1; 688270631Sjfv __le16 guaranteed; 689270631Sjfv __le16 total; 690270631Sjfv __le16 used; 691270631Sjfv __le16 total_unalloced; 692270631Sjfv u8 reserved2[6]; 693270631Sjfv}; 694270631Sjfv 695291248SsmhI40E_CHECK_STRUCT_LEN(0x10, i40e_aqc_switch_resource_alloc_element_resp); 696291248Ssmh 697270631Sjfv/* Add VSI (indirect 0x0210) 698270631Sjfv * this indirect command uses struct i40e_aqc_vsi_properties_data 699270631Sjfv * as the indirect buffer (128 bytes) 700270631Sjfv * 701270631Sjfv * Update VSI (indirect 0x211) 702270631Sjfv * uses the same data structure as Add VSI 703270631Sjfv * 704270631Sjfv * Get VSI (indirect 0x0212) 705270631Sjfv * uses the same completion and data structure as Add VSI 706270631Sjfv */ 707270631Sjfvstruct i40e_aqc_add_get_update_vsi { 708270631Sjfv __le16 uplink_seid; 709270631Sjfv u8 connection_type; 710270631Sjfv#define I40E_AQ_VSI_CONN_TYPE_NORMAL 0x1 711270631Sjfv#define I40E_AQ_VSI_CONN_TYPE_DEFAULT 0x2 712270631Sjfv#define I40E_AQ_VSI_CONN_TYPE_CASCADED 0x3 713270631Sjfv u8 reserved1; 714270631Sjfv u8 vf_id; 715270631Sjfv u8 reserved2; 716270631Sjfv __le16 vsi_flags; 717270631Sjfv#define I40E_AQ_VSI_TYPE_SHIFT 0x0 718270631Sjfv#define I40E_AQ_VSI_TYPE_MASK (0x3 << I40E_AQ_VSI_TYPE_SHIFT) 719270631Sjfv#define I40E_AQ_VSI_TYPE_VF 0x0 720270631Sjfv#define I40E_AQ_VSI_TYPE_VMDQ2 0x1 721270631Sjfv#define I40E_AQ_VSI_TYPE_PF 0x2 722270631Sjfv#define I40E_AQ_VSI_TYPE_EMP_MNG 0x3 723270631Sjfv#define I40E_AQ_VSI_FLAG_CASCADED_PV 0x4 724270631Sjfv __le32 addr_high; 725270631Sjfv __le32 addr_low; 726270631Sjfv}; 727270631Sjfv 728270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi); 729270631Sjfv 730270631Sjfvstruct i40e_aqc_add_get_update_vsi_completion { 731270631Sjfv __le16 seid; 732270631Sjfv __le16 vsi_number; 733270631Sjfv __le16 vsi_used; 734270631Sjfv __le16 vsi_free; 735270631Sjfv __le32 addr_high; 736270631Sjfv __le32 addr_low; 737270631Sjfv}; 738270631Sjfv 739270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_get_update_vsi_completion); 740270631Sjfv 741270631Sjfvstruct i40e_aqc_vsi_properties_data { 742270631Sjfv /* first 96 byte are written by SW */ 743270631Sjfv __le16 valid_sections; 744270631Sjfv#define I40E_AQ_VSI_PROP_SWITCH_VALID 0x0001 745270631Sjfv#define I40E_AQ_VSI_PROP_SECURITY_VALID 0x0002 746270631Sjfv#define I40E_AQ_VSI_PROP_VLAN_VALID 0x0004 747270631Sjfv#define I40E_AQ_VSI_PROP_CAS_PV_VALID 0x0008 748270631Sjfv#define I40E_AQ_VSI_PROP_INGRESS_UP_VALID 0x0010 749270631Sjfv#define I40E_AQ_VSI_PROP_EGRESS_UP_VALID 0x0020 750270631Sjfv#define I40E_AQ_VSI_PROP_QUEUE_MAP_VALID 0x0040 751270631Sjfv#define I40E_AQ_VSI_PROP_QUEUE_OPT_VALID 0x0080 752270631Sjfv#define I40E_AQ_VSI_PROP_OUTER_UP_VALID 0x0100 753270631Sjfv#define I40E_AQ_VSI_PROP_SCHED_VALID 0x0200 754270631Sjfv /* switch section */ 755270631Sjfv __le16 switch_id; /* 12bit id combined with flags below */ 756270631Sjfv#define I40E_AQ_VSI_SW_ID_SHIFT 0x0000 757270631Sjfv#define I40E_AQ_VSI_SW_ID_MASK (0xFFF << I40E_AQ_VSI_SW_ID_SHIFT) 758270631Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_NOT_STAG 0x1000 759270631Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_ALLOW_LB 0x2000 760270631Sjfv#define I40E_AQ_VSI_SW_ID_FLAG_LOCAL_LB 0x4000 761270631Sjfv u8 sw_reserved[2]; 762270631Sjfv /* security section */ 763270631Sjfv u8 sec_flags; 764270631Sjfv#define I40E_AQ_VSI_SEC_FLAG_ALLOW_DEST_OVRD 0x01 765270631Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_VLAN_CHK 0x02 766270631Sjfv#define I40E_AQ_VSI_SEC_FLAG_ENABLE_MAC_CHK 0x04 767270631Sjfv u8 sec_reserved; 768270631Sjfv /* VLAN section */ 769270631Sjfv __le16 pvid; /* VLANS include priority bits */ 770270631Sjfv __le16 fcoe_pvid; 771270631Sjfv u8 port_vlan_flags; 772270631Sjfv#define I40E_AQ_VSI_PVLAN_MODE_SHIFT 0x00 773270631Sjfv#define I40E_AQ_VSI_PVLAN_MODE_MASK (0x03 << \ 774270631Sjfv I40E_AQ_VSI_PVLAN_MODE_SHIFT) 775270631Sjfv#define I40E_AQ_VSI_PVLAN_MODE_TAGGED 0x01 776270631Sjfv#define I40E_AQ_VSI_PVLAN_MODE_UNTAGGED 0x02 777270631Sjfv#define I40E_AQ_VSI_PVLAN_MODE_ALL 0x03 778270631Sjfv#define I40E_AQ_VSI_PVLAN_INSERT_PVID 0x04 779270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_SHIFT 0x03 780270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_MASK (0x3 << \ 781270631Sjfv I40E_AQ_VSI_PVLAN_EMOD_SHIFT) 782270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_BOTH 0x0 783270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR_UP 0x08 784270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_STR 0x10 785270631Sjfv#define I40E_AQ_VSI_PVLAN_EMOD_NOTHING 0x18 786270631Sjfv u8 pvlan_reserved[3]; 787270631Sjfv /* ingress egress up sections */ 788270631Sjfv __le32 ingress_table; /* bitmap, 3 bits per up */ 789270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_SHIFT 0 790270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP0_MASK (0x7 << \ 791270631Sjfv I40E_AQ_VSI_UP_TABLE_UP0_SHIFT) 792270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_SHIFT 3 793270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP1_MASK (0x7 << \ 794270631Sjfv I40E_AQ_VSI_UP_TABLE_UP1_SHIFT) 795270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_SHIFT 6 796270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP2_MASK (0x7 << \ 797270631Sjfv I40E_AQ_VSI_UP_TABLE_UP2_SHIFT) 798270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_SHIFT 9 799270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP3_MASK (0x7 << \ 800270631Sjfv I40E_AQ_VSI_UP_TABLE_UP3_SHIFT) 801270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_SHIFT 12 802270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP4_MASK (0x7 << \ 803270631Sjfv I40E_AQ_VSI_UP_TABLE_UP4_SHIFT) 804270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_SHIFT 15 805270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP5_MASK (0x7 << \ 806270631Sjfv I40E_AQ_VSI_UP_TABLE_UP5_SHIFT) 807270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_SHIFT 18 808270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP6_MASK (0x7 << \ 809270631Sjfv I40E_AQ_VSI_UP_TABLE_UP6_SHIFT) 810270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_SHIFT 21 811270631Sjfv#define I40E_AQ_VSI_UP_TABLE_UP7_MASK (0x7 << \ 812270631Sjfv I40E_AQ_VSI_UP_TABLE_UP7_SHIFT) 813270631Sjfv __le32 egress_table; /* same defines as for ingress table */ 814270631Sjfv /* cascaded PV section */ 815270631Sjfv __le16 cas_pv_tag; 816270631Sjfv u8 cas_pv_flags; 817270631Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_SHIFT 0x00 818270631Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_MASK (0x03 << \ 819270631Sjfv I40E_AQ_VSI_CAS_PV_TAGX_SHIFT) 820270631Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_LEAVE 0x00 821270631Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_REMOVE 0x01 822270631Sjfv#define I40E_AQ_VSI_CAS_PV_TAGX_COPY 0x02 823270631Sjfv#define I40E_AQ_VSI_CAS_PV_INSERT_TAG 0x10 824270631Sjfv#define I40E_AQ_VSI_CAS_PV_ETAG_PRUNE 0x20 825270631Sjfv#define I40E_AQ_VSI_CAS_PV_ACCEPT_HOST_TAG 0x40 826270631Sjfv u8 cas_pv_reserved; 827270631Sjfv /* queue mapping section */ 828270631Sjfv __le16 mapping_flags; 829270631Sjfv#define I40E_AQ_VSI_QUE_MAP_CONTIG 0x0 830270631Sjfv#define I40E_AQ_VSI_QUE_MAP_NONCONTIG 0x1 831270631Sjfv __le16 queue_mapping[16]; 832270631Sjfv#define I40E_AQ_VSI_QUEUE_SHIFT 0x0 833270631Sjfv#define I40E_AQ_VSI_QUEUE_MASK (0x7FF << I40E_AQ_VSI_QUEUE_SHIFT) 834270631Sjfv __le16 tc_mapping[8]; 835270631Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT 0 836270631Sjfv#define I40E_AQ_VSI_TC_QUE_OFFSET_MASK (0x1FF << \ 837270631Sjfv I40E_AQ_VSI_TC_QUE_OFFSET_SHIFT) 838270631Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT 9 839270631Sjfv#define I40E_AQ_VSI_TC_QUE_NUMBER_MASK (0x7 << \ 840270631Sjfv I40E_AQ_VSI_TC_QUE_NUMBER_SHIFT) 841270631Sjfv /* queueing option section */ 842270631Sjfv u8 queueing_opt_flags; 843292100Ssmh#ifdef X722_SUPPORT 844292100Ssmh#define I40E_AQ_VSI_QUE_OPT_MULTICAST_UDP_ENA 0x04 845292100Ssmh#define I40E_AQ_VSI_QUE_OPT_UNICAST_UDP_ENA 0x08 846292100Ssmh#endif 847270631Sjfv#define I40E_AQ_VSI_QUE_OPT_TCP_ENA 0x10 848270631Sjfv#define I40E_AQ_VSI_QUE_OPT_FCOE_ENA 0x20 849292100Ssmh#ifdef X722_SUPPORT 850292100Ssmh#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_PF 0x00 851292100Ssmh#define I40E_AQ_VSI_QUE_OPT_RSS_LUT_VSI 0x40 852292100Ssmh#endif 853270631Sjfv u8 queueing_opt_reserved[3]; 854270631Sjfv /* scheduler section */ 855270631Sjfv u8 up_enable_bits; 856270631Sjfv u8 sched_reserved; 857270631Sjfv /* outer up section */ 858270631Sjfv __le32 outer_up_table; /* same structure and defines as ingress table */ 859270631Sjfv u8 cmd_reserved[8]; 860270631Sjfv /* last 32 bytes are written by FW */ 861270631Sjfv __le16 qs_handle[8]; 862270631Sjfv#define I40E_AQ_VSI_QS_HANDLE_INVALID 0xFFFF 863270631Sjfv __le16 stat_counter_idx; 864270631Sjfv __le16 sched_id; 865270631Sjfv u8 resp_reserved[12]; 866270631Sjfv}; 867270631Sjfv 868270631SjfvI40E_CHECK_STRUCT_LEN(128, i40e_aqc_vsi_properties_data); 869270631Sjfv 870270631Sjfv/* Add Port Virtualizer (direct 0x0220) 871270631Sjfv * also used for update PV (direct 0x0221) but only flags are used 872270631Sjfv * (IS_CTRL_PORT only works on add PV) 873270631Sjfv */ 874270631Sjfvstruct i40e_aqc_add_update_pv { 875270631Sjfv __le16 command_flags; 876270631Sjfv#define I40E_AQC_PV_FLAG_PV_TYPE 0x1 877270631Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_STAG_EN 0x2 878270631Sjfv#define I40E_AQC_PV_FLAG_FWD_UNKNOWN_ETAG_EN 0x4 879270631Sjfv#define I40E_AQC_PV_FLAG_IS_CTRL_PORT 0x8 880270631Sjfv __le16 uplink_seid; 881270631Sjfv __le16 connected_seid; 882270631Sjfv u8 reserved[10]; 883270631Sjfv}; 884270631Sjfv 885270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv); 886270631Sjfv 887270631Sjfvstruct i40e_aqc_add_update_pv_completion { 888270631Sjfv /* reserved for update; for add also encodes error if rc == ENOSPC */ 889270631Sjfv __le16 pv_seid; 890270631Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_PV 0x1 891270631Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_SCHED 0x2 892270631Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_COUNTER 0x4 893270631Sjfv#define I40E_AQC_PV_ERR_FLAG_NO_ENTRY 0x8 894270631Sjfv u8 reserved[14]; 895270631Sjfv}; 896270631Sjfv 897270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_update_pv_completion); 898270631Sjfv 899270631Sjfv/* Get PV Params (direct 0x0222) 900270631Sjfv * uses i40e_aqc_switch_seid for the descriptor 901270631Sjfv */ 902270631Sjfv 903270631Sjfvstruct i40e_aqc_get_pv_params_completion { 904270631Sjfv __le16 seid; 905270631Sjfv __le16 default_stag; 906270631Sjfv __le16 pv_flags; /* same flags as add_pv */ 907270631Sjfv#define I40E_AQC_GET_PV_PV_TYPE 0x1 908270631Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_STAG 0x2 909270631Sjfv#define I40E_AQC_GET_PV_FRWD_UNKNOWN_ETAG 0x4 910270631Sjfv u8 reserved[8]; 911270631Sjfv __le16 default_port_seid; 912270631Sjfv}; 913270631Sjfv 914270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_pv_params_completion); 915270631Sjfv 916270631Sjfv/* Add VEB (direct 0x0230) */ 917270631Sjfvstruct i40e_aqc_add_veb { 918270631Sjfv __le16 uplink_seid; 919270631Sjfv __le16 downlink_seid; 920270631Sjfv __le16 veb_flags; 921270631Sjfv#define I40E_AQC_ADD_VEB_FLOATING 0x1 922270631Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT 1 923270631Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_MASK (0x3 << \ 924270631Sjfv I40E_AQC_ADD_VEB_PORT_TYPE_SHIFT) 925270631Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DEFAULT 0x2 926270631Sjfv#define I40E_AQC_ADD_VEB_PORT_TYPE_DATA 0x4 927270631Sjfv#define I40E_AQC_ADD_VEB_ENABLE_L2_FILTER 0x8 928270631Sjfv u8 enable_tcs; 929270631Sjfv u8 reserved[9]; 930270631Sjfv}; 931270631Sjfv 932270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb); 933270631Sjfv 934270631Sjfvstruct i40e_aqc_add_veb_completion { 935270631Sjfv u8 reserved[6]; 936270631Sjfv __le16 switch_seid; 937270631Sjfv /* also encodes error if rc == ENOSPC; codes are the same as add_pv */ 938270631Sjfv __le16 veb_seid; 939270631Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_VEB 0x1 940270631Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_SCHED 0x2 941270631Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_COUNTER 0x4 942270631Sjfv#define I40E_AQC_VEB_ERR_FLAG_NO_ENTRY 0x8 943270631Sjfv __le16 statistic_index; 944270631Sjfv __le16 vebs_used; 945270631Sjfv __le16 vebs_free; 946270631Sjfv}; 947270631Sjfv 948270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_veb_completion); 949270631Sjfv 950270631Sjfv/* Get VEB Parameters (direct 0x0232) 951270631Sjfv * uses i40e_aqc_switch_seid for the descriptor 952270631Sjfv */ 953270631Sjfvstruct i40e_aqc_get_veb_parameters_completion { 954270631Sjfv __le16 seid; 955270631Sjfv __le16 switch_id; 956270631Sjfv __le16 veb_flags; /* only the first/last flags from 0x0230 is valid */ 957270631Sjfv __le16 statistic_index; 958270631Sjfv __le16 vebs_used; 959270631Sjfv __le16 vebs_free; 960270631Sjfv u8 reserved[4]; 961270631Sjfv}; 962270631Sjfv 963270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_veb_parameters_completion); 964270631Sjfv 965270631Sjfv/* Delete Element (direct 0x0243) 966270631Sjfv * uses the generic i40e_aqc_switch_seid 967270631Sjfv */ 968270631Sjfv 969270631Sjfv/* Add MAC-VLAN (indirect 0x0250) */ 970270631Sjfv 971270631Sjfv/* used for the command for most vlan commands */ 972270631Sjfvstruct i40e_aqc_macvlan { 973270631Sjfv __le16 num_addresses; 974270631Sjfv __le16 seid[3]; 975270631Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT 0 976270631Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_NUM_MASK (0x3FF << \ 977270631Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 978270631Sjfv#define I40E_AQC_MACVLAN_CMD_SEID_VALID 0x8000 979270631Sjfv __le32 addr_high; 980270631Sjfv __le32 addr_low; 981270631Sjfv}; 982270631Sjfv 983270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_macvlan); 984270631Sjfv 985270631Sjfv/* indirect data for command and response */ 986270631Sjfvstruct i40e_aqc_add_macvlan_element_data { 987270631Sjfv u8 mac_addr[6]; 988270631Sjfv __le16 vlan_tag; 989270631Sjfv __le16 flags; 990270631Sjfv#define I40E_AQC_MACVLAN_ADD_PERFECT_MATCH 0x0001 991270631Sjfv#define I40E_AQC_MACVLAN_ADD_HASH_MATCH 0x0002 992270631Sjfv#define I40E_AQC_MACVLAN_ADD_IGNORE_VLAN 0x0004 993270631Sjfv#define I40E_AQC_MACVLAN_ADD_TO_QUEUE 0x0008 994270631Sjfv __le16 queue_number; 995270631Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_SHIFT 0 996270631Sjfv#define I40E_AQC_MACVLAN_CMD_QUEUE_MASK (0x7FF << \ 997270631Sjfv I40E_AQC_MACVLAN_CMD_SEID_NUM_SHIFT) 998270631Sjfv /* response section */ 999270631Sjfv u8 match_method; 1000270631Sjfv#define I40E_AQC_MM_PERFECT_MATCH 0x01 1001270631Sjfv#define I40E_AQC_MM_HASH_MATCH 0x02 1002270631Sjfv#define I40E_AQC_MM_ERR_NO_RES 0xFF 1003270631Sjfv u8 reserved1[3]; 1004270631Sjfv}; 1005270631Sjfv 1006270631Sjfvstruct i40e_aqc_add_remove_macvlan_completion { 1007270631Sjfv __le16 perfect_mac_used; 1008270631Sjfv __le16 perfect_mac_free; 1009270631Sjfv __le16 unicast_hash_free; 1010270631Sjfv __le16 multicast_hash_free; 1011270631Sjfv __le32 addr_high; 1012270631Sjfv __le32 addr_low; 1013270631Sjfv}; 1014270631Sjfv 1015270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_macvlan_completion); 1016270631Sjfv 1017270631Sjfv/* Remove MAC-VLAN (indirect 0x0251) 1018270631Sjfv * uses i40e_aqc_macvlan for the descriptor 1019270631Sjfv * data points to an array of num_addresses of elements 1020270631Sjfv */ 1021270631Sjfv 1022270631Sjfvstruct i40e_aqc_remove_macvlan_element_data { 1023270631Sjfv u8 mac_addr[6]; 1024270631Sjfv __le16 vlan_tag; 1025270631Sjfv u8 flags; 1026270631Sjfv#define I40E_AQC_MACVLAN_DEL_PERFECT_MATCH 0x01 1027270631Sjfv#define I40E_AQC_MACVLAN_DEL_HASH_MATCH 0x02 1028270631Sjfv#define I40E_AQC_MACVLAN_DEL_IGNORE_VLAN 0x08 1029270631Sjfv#define I40E_AQC_MACVLAN_DEL_ALL_VSIS 0x10 1030270631Sjfv u8 reserved[3]; 1031270631Sjfv /* reply section */ 1032270631Sjfv u8 error_code; 1033270631Sjfv#define I40E_AQC_REMOVE_MACVLAN_SUCCESS 0x0 1034270631Sjfv#define I40E_AQC_REMOVE_MACVLAN_FAIL 0xFF 1035270631Sjfv u8 reply_reserved[3]; 1036270631Sjfv}; 1037270631Sjfv 1038270631Sjfv/* Add VLAN (indirect 0x0252) 1039270631Sjfv * Remove VLAN (indirect 0x0253) 1040270631Sjfv * use the generic i40e_aqc_macvlan for the command 1041270631Sjfv */ 1042270631Sjfvstruct i40e_aqc_add_remove_vlan_element_data { 1043270631Sjfv __le16 vlan_tag; 1044270631Sjfv u8 vlan_flags; 1045270631Sjfv/* flags for add VLAN */ 1046270631Sjfv#define I40E_AQC_ADD_VLAN_LOCAL 0x1 1047270631Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SHIFT 1 1048270631Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_MASK (0x3 << I40E_AQC_ADD_PVLAN_TYPE_SHIFT) 1049270631Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_REGULAR 0x0 1050270631Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_PRIMARY 0x2 1051270631Sjfv#define I40E_AQC_ADD_PVLAN_TYPE_SECONDARY 0x4 1052270631Sjfv#define I40E_AQC_VLAN_PTYPE_SHIFT 3 1053270631Sjfv#define I40E_AQC_VLAN_PTYPE_MASK (0x3 << I40E_AQC_VLAN_PTYPE_SHIFT) 1054270631Sjfv#define I40E_AQC_VLAN_PTYPE_REGULAR_VSI 0x0 1055270631Sjfv#define I40E_AQC_VLAN_PTYPE_PROMISC_VSI 0x8 1056270631Sjfv#define I40E_AQC_VLAN_PTYPE_COMMUNITY_VSI 0x10 1057270631Sjfv#define I40E_AQC_VLAN_PTYPE_ISOLATED_VSI 0x18 1058270631Sjfv/* flags for remove VLAN */ 1059270631Sjfv#define I40E_AQC_REMOVE_VLAN_ALL 0x1 1060270631Sjfv u8 reserved; 1061270631Sjfv u8 result; 1062270631Sjfv/* flags for add VLAN */ 1063270631Sjfv#define I40E_AQC_ADD_VLAN_SUCCESS 0x0 1064270631Sjfv#define I40E_AQC_ADD_VLAN_FAIL_REQUEST 0xFE 1065270631Sjfv#define I40E_AQC_ADD_VLAN_FAIL_RESOURCE 0xFF 1066270631Sjfv/* flags for remove VLAN */ 1067270631Sjfv#define I40E_AQC_REMOVE_VLAN_SUCCESS 0x0 1068270631Sjfv#define I40E_AQC_REMOVE_VLAN_FAIL 0xFF 1069270631Sjfv u8 reserved1[3]; 1070270631Sjfv}; 1071270631Sjfv 1072270631Sjfvstruct i40e_aqc_add_remove_vlan_completion { 1073270631Sjfv u8 reserved[4]; 1074270631Sjfv __le16 vlans_used; 1075270631Sjfv __le16 vlans_free; 1076270631Sjfv __le32 addr_high; 1077270631Sjfv __le32 addr_low; 1078270631Sjfv}; 1079270631Sjfv 1080270631Sjfv/* Set VSI Promiscuous Modes (direct 0x0254) */ 1081270631Sjfvstruct i40e_aqc_set_vsi_promiscuous_modes { 1082270631Sjfv __le16 promiscuous_flags; 1083270631Sjfv __le16 valid_flags; 1084270631Sjfv/* flags used for both fields above */ 1085270631Sjfv#define I40E_AQC_SET_VSI_PROMISC_UNICAST 0x01 1086270631Sjfv#define I40E_AQC_SET_VSI_PROMISC_MULTICAST 0x02 1087270631Sjfv#define I40E_AQC_SET_VSI_PROMISC_BROADCAST 0x04 1088270631Sjfv#define I40E_AQC_SET_VSI_DEFAULT 0x08 1089270631Sjfv#define I40E_AQC_SET_VSI_PROMISC_VLAN 0x10 1090270631Sjfv __le16 seid; 1091270631Sjfv#define I40E_AQC_VSI_PROM_CMD_SEID_MASK 0x3FF 1092270631Sjfv __le16 vlan_tag; 1093292100Ssmh#define I40E_AQC_SET_VSI_VLAN_MASK 0x0FFF 1094270631Sjfv#define I40E_AQC_SET_VSI_VLAN_VALID 0x8000 1095270631Sjfv u8 reserved[8]; 1096270631Sjfv}; 1097270631Sjfv 1098270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_vsi_promiscuous_modes); 1099270631Sjfv 1100270631Sjfv/* Add S/E-tag command (direct 0x0255) 1101270631Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1102270631Sjfv */ 1103270631Sjfvstruct i40e_aqc_add_tag { 1104270631Sjfv __le16 flags; 1105270631Sjfv#define I40E_AQC_ADD_TAG_FLAG_TO_QUEUE 0x0001 1106270631Sjfv __le16 seid; 1107270631Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT 0 1108270631Sjfv#define I40E_AQC_ADD_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1109270631Sjfv I40E_AQC_ADD_TAG_CMD_SEID_NUM_SHIFT) 1110270631Sjfv __le16 tag; 1111270631Sjfv __le16 queue_number; 1112270631Sjfv u8 reserved[8]; 1113270631Sjfv}; 1114270631Sjfv 1115270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_tag); 1116270631Sjfv 1117270631Sjfvstruct i40e_aqc_add_remove_tag_completion { 1118270631Sjfv u8 reserved[12]; 1119270631Sjfv __le16 tags_used; 1120270631Sjfv __le16 tags_free; 1121270631Sjfv}; 1122270631Sjfv 1123270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_tag_completion); 1124270631Sjfv 1125270631Sjfv/* Remove S/E-tag command (direct 0x0256) 1126270631Sjfv * Uses generic i40e_aqc_add_remove_tag_completion for completion 1127270631Sjfv */ 1128270631Sjfvstruct i40e_aqc_remove_tag { 1129270631Sjfv __le16 seid; 1130270631Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT 0 1131270631Sjfv#define I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1132270631Sjfv I40E_AQC_REMOVE_TAG_CMD_SEID_NUM_SHIFT) 1133270631Sjfv __le16 tag; 1134270631Sjfv u8 reserved[12]; 1135270631Sjfv}; 1136270631Sjfv 1137291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_tag); 1138291248Ssmh 1139270631Sjfv/* Add multicast E-Tag (direct 0x0257) 1140270631Sjfv * del multicast E-Tag (direct 0x0258) only uses pv_seid and etag fields 1141270631Sjfv * and no external data 1142270631Sjfv */ 1143270631Sjfvstruct i40e_aqc_add_remove_mcast_etag { 1144270631Sjfv __le16 pv_seid; 1145270631Sjfv __le16 etag; 1146270631Sjfv u8 num_unicast_etags; 1147270631Sjfv u8 reserved[3]; 1148270631Sjfv __le32 addr_high; /* address of array of 2-byte s-tags */ 1149270631Sjfv __le32 addr_low; 1150270631Sjfv}; 1151270631Sjfv 1152270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag); 1153270631Sjfv 1154270631Sjfvstruct i40e_aqc_add_remove_mcast_etag_completion { 1155270631Sjfv u8 reserved[4]; 1156270631Sjfv __le16 mcast_etags_used; 1157270631Sjfv __le16 mcast_etags_free; 1158270631Sjfv __le32 addr_high; 1159270631Sjfv __le32 addr_low; 1160270631Sjfv 1161270631Sjfv}; 1162270631Sjfv 1163270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_mcast_etag_completion); 1164270631Sjfv 1165270631Sjfv/* Update S/E-Tag (direct 0x0259) */ 1166270631Sjfvstruct i40e_aqc_update_tag { 1167270631Sjfv __le16 seid; 1168270631Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT 0 1169270631Sjfv#define I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_MASK (0x3FF << \ 1170270631Sjfv I40E_AQC_UPDATE_TAG_CMD_SEID_NUM_SHIFT) 1171270631Sjfv __le16 old_tag; 1172270631Sjfv __le16 new_tag; 1173270631Sjfv u8 reserved[10]; 1174270631Sjfv}; 1175270631Sjfv 1176270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag); 1177270631Sjfv 1178270631Sjfvstruct i40e_aqc_update_tag_completion { 1179270631Sjfv u8 reserved[12]; 1180270631Sjfv __le16 tags_used; 1181270631Sjfv __le16 tags_free; 1182270631Sjfv}; 1183270631Sjfv 1184270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_update_tag_completion); 1185270631Sjfv 1186270631Sjfv/* Add Control Packet filter (direct 0x025A) 1187270631Sjfv * Remove Control Packet filter (direct 0x025B) 1188270631Sjfv * uses the i40e_aqc_add_oveb_cloud, 1189270631Sjfv * and the generic direct completion structure 1190270631Sjfv */ 1191270631Sjfvstruct i40e_aqc_add_remove_control_packet_filter { 1192270631Sjfv u8 mac[6]; 1193270631Sjfv __le16 etype; 1194270631Sjfv __le16 flags; 1195270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_IGNORE_MAC 0x0001 1196270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_DROP 0x0002 1197270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TO_QUEUE 0x0004 1198270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_TX 0x0008 1199270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_FLAGS_RX 0x0000 1200270631Sjfv __le16 seid; 1201270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT 0 1202270631Sjfv#define I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_MASK (0x3FF << \ 1203270631Sjfv I40E_AQC_ADD_CONTROL_PACKET_CMD_SEID_NUM_SHIFT) 1204270631Sjfv __le16 queue; 1205270631Sjfv u8 reserved[2]; 1206270631Sjfv}; 1207270631Sjfv 1208270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter); 1209270631Sjfv 1210270631Sjfvstruct i40e_aqc_add_remove_control_packet_filter_completion { 1211270631Sjfv __le16 mac_etype_used; 1212270631Sjfv __le16 etype_used; 1213270631Sjfv __le16 mac_etype_free; 1214270631Sjfv __le16 etype_free; 1215270631Sjfv u8 reserved[8]; 1216270631Sjfv}; 1217270631Sjfv 1218270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_control_packet_filter_completion); 1219270631Sjfv 1220270631Sjfv/* Add Cloud filters (indirect 0x025C) 1221270631Sjfv * Remove Cloud filters (indirect 0x025D) 1222270631Sjfv * uses the i40e_aqc_add_remove_cloud_filters, 1223270631Sjfv * and the generic indirect completion structure 1224270631Sjfv */ 1225270631Sjfvstruct i40e_aqc_add_remove_cloud_filters { 1226270631Sjfv u8 num_filters; 1227270631Sjfv u8 reserved; 1228270631Sjfv __le16 seid; 1229270631Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT 0 1230270631Sjfv#define I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_MASK (0x3FF << \ 1231270631Sjfv I40E_AQC_ADD_CLOUD_CMD_SEID_NUM_SHIFT) 1232270631Sjfv u8 reserved2[4]; 1233270631Sjfv __le32 addr_high; 1234270631Sjfv __le32 addr_low; 1235270631Sjfv}; 1236270631Sjfv 1237270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_remove_cloud_filters); 1238270631Sjfv 1239270631Sjfvstruct i40e_aqc_add_remove_cloud_filters_element_data { 1240270631Sjfv u8 outer_mac[6]; 1241270631Sjfv u8 inner_mac[6]; 1242270631Sjfv __le16 inner_vlan; 1243270631Sjfv union { 1244270631Sjfv struct { 1245270631Sjfv u8 reserved[12]; 1246270631Sjfv u8 data[4]; 1247270631Sjfv } v4; 1248270631Sjfv struct { 1249270631Sjfv u8 data[16]; 1250270631Sjfv } v6; 1251270631Sjfv } ipaddr; 1252270631Sjfv __le16 flags; 1253270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SHIFT 0 1254291248Ssmh#define I40E_AQC_ADD_CLOUD_FILTER_MASK (0x3F << \ 1255270631Sjfv I40E_AQC_ADD_CLOUD_FILTER_SHIFT) 1256270631Sjfv/* 0x0000 reserved */ 1257270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OIP 0x0001 1258270631Sjfv/* 0x0002 reserved */ 1259270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN 0x0003 1260270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_IVLAN_TEN_ID 0x0004 1261270631Sjfv/* 0x0005 reserved */ 1262270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC_TEN_ID 0x0006 1263270631Sjfv/* 0x0007 reserved */ 1264270631Sjfv/* 0x0008 reserved */ 1265270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC 0x0009 1266270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IMAC 0x000A 1267270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_OMAC_TEN_ID_IMAC 0x000B 1268270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_IIP 0x000C 1269270631Sjfv 1270270631Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_TO_QUEUE 0x0080 1271270631Sjfv#define I40E_AQC_ADD_CLOUD_VNK_SHIFT 6 1272270631Sjfv#define I40E_AQC_ADD_CLOUD_VNK_MASK 0x00C0 1273270631Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV4 0 1274270631Sjfv#define I40E_AQC_ADD_CLOUD_FLAGS_IPV6 0x0100 1275270631Sjfv 1276270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_SHIFT 9 1277270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_MASK 0x1E00 1278270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_XVLAN 0 1279270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NVGRE_OMAC 1 1280270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_NGE 2 1281270631Sjfv#define I40E_AQC_ADD_CLOUD_TNL_TYPE_IP 3 1282270631Sjfv 1283270631Sjfv __le32 tenant_id; 1284270631Sjfv u8 reserved[4]; 1285270631Sjfv __le16 queue_number; 1286270631Sjfv#define I40E_AQC_ADD_CLOUD_QUEUE_SHIFT 0 1287291248Ssmh#define I40E_AQC_ADD_CLOUD_QUEUE_MASK (0x7FF << \ 1288270631Sjfv I40E_AQC_ADD_CLOUD_QUEUE_SHIFT) 1289270631Sjfv u8 reserved2[14]; 1290270631Sjfv /* response section */ 1291270631Sjfv u8 allocation_result; 1292270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_SUCCESS 0x0 1293270631Sjfv#define I40E_AQC_ADD_CLOUD_FILTER_FAIL 0xFF 1294270631Sjfv u8 response_reserved[7]; 1295270631Sjfv}; 1296270631Sjfv 1297270631Sjfvstruct i40e_aqc_remove_cloud_filters_completion { 1298270631Sjfv __le16 perfect_ovlan_used; 1299270631Sjfv __le16 perfect_ovlan_free; 1300270631Sjfv __le16 vlan_used; 1301270631Sjfv __le16 vlan_free; 1302270631Sjfv __le32 addr_high; 1303270631Sjfv __le32 addr_low; 1304270631Sjfv}; 1305270631Sjfv 1306270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_cloud_filters_completion); 1307270631Sjfv 1308270631Sjfv/* Add Mirror Rule (indirect or direct 0x0260) 1309270631Sjfv * Delete Mirror Rule (indirect or direct 0x0261) 1310270631Sjfv * note: some rule types (4,5) do not use an external buffer. 1311270631Sjfv * take care to set the flags correctly. 1312270631Sjfv */ 1313270631Sjfvstruct i40e_aqc_add_delete_mirror_rule { 1314270631Sjfv __le16 seid; 1315270631Sjfv __le16 rule_type; 1316270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_SHIFT 0 1317270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_MASK (0x7 << \ 1318270631Sjfv I40E_AQC_MIRROR_RULE_TYPE_SHIFT) 1319270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_INGRESS 1 1320270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VPORT_EGRESS 2 1321270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_VLAN 3 1322270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_INGRESS 4 1323270631Sjfv#define I40E_AQC_MIRROR_RULE_TYPE_ALL_EGRESS 5 1324270631Sjfv __le16 num_entries; 1325270631Sjfv __le16 destination; /* VSI for add, rule id for delete */ 1326270631Sjfv __le32 addr_high; /* address of array of 2-byte VSI or VLAN ids */ 1327270631Sjfv __le32 addr_low; 1328270631Sjfv}; 1329270631Sjfv 1330270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule); 1331270631Sjfv 1332270631Sjfvstruct i40e_aqc_add_delete_mirror_rule_completion { 1333270631Sjfv u8 reserved[2]; 1334270631Sjfv __le16 rule_id; /* only used on add */ 1335270631Sjfv __le16 mirror_rules_used; 1336270631Sjfv __le16 mirror_rules_free; 1337270631Sjfv __le32 addr_high; 1338270631Sjfv __le32 addr_low; 1339270631Sjfv}; 1340270631Sjfv 1341270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_delete_mirror_rule_completion); 1342270631Sjfv 1343270631Sjfv/* DCB 0x03xx*/ 1344270631Sjfv 1345270631Sjfv/* PFC Ignore (direct 0x0301) 1346270631Sjfv * the command and response use the same descriptor structure 1347270631Sjfv */ 1348270631Sjfvstruct i40e_aqc_pfc_ignore { 1349270631Sjfv u8 tc_bitmap; 1350270631Sjfv u8 command_flags; /* unused on response */ 1351270631Sjfv#define I40E_AQC_PFC_IGNORE_SET 0x80 1352270631Sjfv#define I40E_AQC_PFC_IGNORE_CLEAR 0x0 1353270631Sjfv u8 reserved[14]; 1354270631Sjfv}; 1355270631Sjfv 1356270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pfc_ignore); 1357270631Sjfv 1358270631Sjfv/* DCB Update (direct 0x0302) uses the i40e_aq_desc structure 1359270631Sjfv * with no parameters 1360270631Sjfv */ 1361270631Sjfv 1362270631Sjfv/* TX scheduler 0x04xx */ 1363270631Sjfv 1364270631Sjfv/* Almost all the indirect commands use 1365270631Sjfv * this generic struct to pass the SEID in param0 1366270631Sjfv */ 1367270631Sjfvstruct i40e_aqc_tx_sched_ind { 1368270631Sjfv __le16 vsi_seid; 1369270631Sjfv u8 reserved[6]; 1370270631Sjfv __le32 addr_high; 1371270631Sjfv __le32 addr_low; 1372270631Sjfv}; 1373270631Sjfv 1374270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tx_sched_ind); 1375270631Sjfv 1376270631Sjfv/* Several commands respond with a set of queue set handles */ 1377270631Sjfvstruct i40e_aqc_qs_handles_resp { 1378270631Sjfv __le16 qs_handles[8]; 1379270631Sjfv}; 1380270631Sjfv 1381270631Sjfv/* Configure VSI BW limits (direct 0x0400) */ 1382270631Sjfvstruct i40e_aqc_configure_vsi_bw_limit { 1383270631Sjfv __le16 vsi_seid; 1384270631Sjfv u8 reserved[2]; 1385270631Sjfv __le16 credit; 1386270631Sjfv u8 reserved1[2]; 1387270631Sjfv u8 max_credit; /* 0-3, limit = 2^max */ 1388270631Sjfv u8 reserved2[7]; 1389270631Sjfv}; 1390270631Sjfv 1391270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_vsi_bw_limit); 1392270631Sjfv 1393270631Sjfv/* Configure VSI Bandwidth Limit per Traffic Type (indirect 0x0406) 1394270631Sjfv * responds with i40e_aqc_qs_handles_resp 1395270631Sjfv */ 1396270631Sjfvstruct i40e_aqc_configure_vsi_ets_sla_bw_data { 1397270631Sjfv u8 tc_valid_bits; 1398270631Sjfv u8 reserved[15]; 1399270631Sjfv __le16 tc_bw_credits[8]; /* FW writesback QS handles here */ 1400270631Sjfv 1401270631Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1402270631Sjfv __le16 tc_bw_max[2]; 1403270631Sjfv u8 reserved1[28]; 1404270631Sjfv}; 1405270631Sjfv 1406291248SsmhI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_vsi_ets_sla_bw_data); 1407291248Ssmh 1408270631Sjfv/* Configure VSI Bandwidth Allocation per Traffic Type (indirect 0x0407) 1409270631Sjfv * responds with i40e_aqc_qs_handles_resp 1410270631Sjfv */ 1411270631Sjfvstruct i40e_aqc_configure_vsi_tc_bw_data { 1412270631Sjfv u8 tc_valid_bits; 1413270631Sjfv u8 reserved[3]; 1414270631Sjfv u8 tc_bw_credits[8]; 1415270631Sjfv u8 reserved1[4]; 1416270631Sjfv __le16 qs_handles[8]; 1417270631Sjfv}; 1418270631Sjfv 1419291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_vsi_tc_bw_data); 1420291248Ssmh 1421270631Sjfv/* Query vsi bw configuration (indirect 0x0408) */ 1422270631Sjfvstruct i40e_aqc_query_vsi_bw_config_resp { 1423270631Sjfv u8 tc_valid_bits; 1424270631Sjfv u8 tc_suspended_bits; 1425270631Sjfv u8 reserved[14]; 1426270631Sjfv __le16 qs_handles[8]; 1427270631Sjfv u8 reserved1[4]; 1428270631Sjfv __le16 port_bw_limit; 1429270631Sjfv u8 reserved2[2]; 1430270631Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1431270631Sjfv u8 reserved3[23]; 1432270631Sjfv}; 1433270631Sjfv 1434291248SsmhI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_vsi_bw_config_resp); 1435291248Ssmh 1436270631Sjfv/* Query VSI Bandwidth Allocation per Traffic Type (indirect 0x040A) */ 1437270631Sjfvstruct i40e_aqc_query_vsi_ets_sla_config_resp { 1438270631Sjfv u8 tc_valid_bits; 1439270631Sjfv u8 reserved[3]; 1440270631Sjfv u8 share_credits[8]; 1441270631Sjfv __le16 credits[8]; 1442270631Sjfv 1443270631Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1444270631Sjfv __le16 tc_bw_max[2]; 1445270631Sjfv}; 1446270631Sjfv 1447291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_vsi_ets_sla_config_resp); 1448291248Ssmh 1449270631Sjfv/* Configure Switching Component Bandwidth Limit (direct 0x0410) */ 1450270631Sjfvstruct i40e_aqc_configure_switching_comp_bw_limit { 1451270631Sjfv __le16 seid; 1452270631Sjfv u8 reserved[2]; 1453270631Sjfv __le16 credit; 1454270631Sjfv u8 reserved1[2]; 1455270631Sjfv u8 max_bw; /* 0-3, limit = 2^max */ 1456270631Sjfv u8 reserved2[7]; 1457270631Sjfv}; 1458270631Sjfv 1459270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_configure_switching_comp_bw_limit); 1460270631Sjfv 1461270631Sjfv/* Enable Physical Port ETS (indirect 0x0413) 1462270631Sjfv * Modify Physical Port ETS (indirect 0x0414) 1463270631Sjfv * Disable Physical Port ETS (indirect 0x0415) 1464270631Sjfv */ 1465270631Sjfvstruct i40e_aqc_configure_switching_comp_ets_data { 1466270631Sjfv u8 reserved[4]; 1467270631Sjfv u8 tc_valid_bits; 1468270631Sjfv u8 seepage; 1469270631Sjfv#define I40E_AQ_ETS_SEEPAGE_EN_MASK 0x1 1470270631Sjfv u8 tc_strict_priority_flags; 1471270631Sjfv u8 reserved1[17]; 1472270631Sjfv u8 tc_bw_share_credits[8]; 1473270631Sjfv u8 reserved2[96]; 1474270631Sjfv}; 1475270631Sjfv 1476291248SsmhI40E_CHECK_STRUCT_LEN(0x80, i40e_aqc_configure_switching_comp_ets_data); 1477291248Ssmh 1478270631Sjfv/* Configure Switching Component Bandwidth Limits per Tc (indirect 0x0416) */ 1479270631Sjfvstruct i40e_aqc_configure_switching_comp_ets_bw_limit_data { 1480270631Sjfv u8 tc_valid_bits; 1481270631Sjfv u8 reserved[15]; 1482270631Sjfv __le16 tc_bw_credit[8]; 1483270631Sjfv 1484270631Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1485270631Sjfv __le16 tc_bw_max[2]; 1486270631Sjfv u8 reserved1[28]; 1487270631Sjfv}; 1488270631Sjfv 1489291248SsmhI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_configure_switching_comp_ets_bw_limit_data); 1490291248Ssmh 1491270631Sjfv/* Configure Switching Component Bandwidth Allocation per Tc 1492270631Sjfv * (indirect 0x0417) 1493270631Sjfv */ 1494270631Sjfvstruct i40e_aqc_configure_switching_comp_bw_config_data { 1495270631Sjfv u8 tc_valid_bits; 1496270631Sjfv u8 reserved[2]; 1497270631Sjfv u8 absolute_credits; /* bool */ 1498270631Sjfv u8 tc_bw_share_credits[8]; 1499270631Sjfv u8 reserved1[20]; 1500270631Sjfv}; 1501270631Sjfv 1502291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_configure_switching_comp_bw_config_data); 1503291248Ssmh 1504270631Sjfv/* Query Switching Component Configuration (indirect 0x0418) */ 1505270631Sjfvstruct i40e_aqc_query_switching_comp_ets_config_resp { 1506270631Sjfv u8 tc_valid_bits; 1507270631Sjfv u8 reserved[35]; 1508270631Sjfv __le16 port_bw_limit; 1509270631Sjfv u8 reserved1[2]; 1510270631Sjfv u8 tc_bw_max; /* 0-3, limit = 2^max */ 1511270631Sjfv u8 reserved2[23]; 1512270631Sjfv}; 1513270631Sjfv 1514291248SsmhI40E_CHECK_STRUCT_LEN(0x40, i40e_aqc_query_switching_comp_ets_config_resp); 1515291248Ssmh 1516270631Sjfv/* Query PhysicalPort ETS Configuration (indirect 0x0419) */ 1517270631Sjfvstruct i40e_aqc_query_port_ets_config_resp { 1518270631Sjfv u8 reserved[4]; 1519270631Sjfv u8 tc_valid_bits; 1520270631Sjfv u8 reserved1; 1521270631Sjfv u8 tc_strict_priority_bits; 1522270631Sjfv u8 reserved2; 1523270631Sjfv u8 tc_bw_share_credits[8]; 1524270631Sjfv __le16 tc_bw_limits[8]; 1525270631Sjfv 1526270631Sjfv /* 4 bits per tc 0-7, 4th bit reserved, limit = 2^max */ 1527270631Sjfv __le16 tc_bw_max[2]; 1528270631Sjfv u8 reserved3[32]; 1529270631Sjfv}; 1530270631Sjfv 1531291248SsmhI40E_CHECK_STRUCT_LEN(0x44, i40e_aqc_query_port_ets_config_resp); 1532291248Ssmh 1533270631Sjfv/* Query Switching Component Bandwidth Allocation per Traffic Type 1534270631Sjfv * (indirect 0x041A) 1535270631Sjfv */ 1536270631Sjfvstruct i40e_aqc_query_switching_comp_bw_config_resp { 1537270631Sjfv u8 tc_valid_bits; 1538270631Sjfv u8 reserved[2]; 1539270631Sjfv u8 absolute_credits_enable; /* bool */ 1540270631Sjfv u8 tc_bw_share_credits[8]; 1541270631Sjfv __le16 tc_bw_limits[8]; 1542270631Sjfv 1543270631Sjfv /* 4 bits per tc 0-7, 4th bit is reserved, limit = 2^max */ 1544270631Sjfv __le16 tc_bw_max[2]; 1545270631Sjfv}; 1546270631Sjfv 1547291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_query_switching_comp_bw_config_resp); 1548291248Ssmh 1549270631Sjfv/* Suspend/resume port TX traffic 1550270631Sjfv * (direct 0x041B and 0x041C) uses the generic SEID struct 1551270631Sjfv */ 1552270631Sjfv 1553270631Sjfv/* Configure partition BW 1554270631Sjfv * (indirect 0x041D) 1555270631Sjfv */ 1556270631Sjfvstruct i40e_aqc_configure_partition_bw_data { 1557270631Sjfv __le16 pf_valid_bits; 1558270631Sjfv u8 min_bw[16]; /* guaranteed bandwidth */ 1559270631Sjfv u8 max_bw[16]; /* bandwidth limit */ 1560270631Sjfv}; 1561270631Sjfv 1562291248SsmhI40E_CHECK_STRUCT_LEN(0x22, i40e_aqc_configure_partition_bw_data); 1563291248Ssmh 1564270631Sjfv/* Get and set the active HMC resource profile and status. 1565270631Sjfv * (direct 0x0500) and (direct 0x0501) 1566270631Sjfv */ 1567270631Sjfvstruct i40e_aq_get_set_hmc_resource_profile { 1568270631Sjfv u8 pm_profile; 1569270631Sjfv u8 pe_vf_enabled; 1570270631Sjfv u8 reserved[14]; 1571270631Sjfv}; 1572270631Sjfv 1573270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_get_set_hmc_resource_profile); 1574270631Sjfv 1575270631Sjfvenum i40e_aq_hmc_profile { 1576270631Sjfv /* I40E_HMC_PROFILE_NO_CHANGE = 0, reserved */ 1577270631Sjfv I40E_HMC_PROFILE_DEFAULT = 1, 1578270631Sjfv I40E_HMC_PROFILE_FAVOR_VF = 2, 1579270631Sjfv I40E_HMC_PROFILE_EQUAL = 3, 1580270631Sjfv}; 1581270631Sjfv 1582270631Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_PM_MASK 0xF 1583270631Sjfv#define I40E_AQ_GET_HMC_RESOURCE_PROFILE_COUNT_MASK 0x3F 1584270631Sjfv 1585270631Sjfv/* Get PHY Abilities (indirect 0x0600) uses the generic indirect struct */ 1586270631Sjfv 1587270631Sjfv/* set in param0 for get phy abilities to report qualified modules */ 1588270631Sjfv#define I40E_AQ_PHY_REPORT_QUALIFIED_MODULES 0x0001 1589270631Sjfv#define I40E_AQ_PHY_REPORT_INITIAL_VALUES 0x0002 1590270631Sjfv 1591270631Sjfvenum i40e_aq_phy_type { 1592270631Sjfv I40E_PHY_TYPE_SGMII = 0x0, 1593270631Sjfv I40E_PHY_TYPE_1000BASE_KX = 0x1, 1594270631Sjfv I40E_PHY_TYPE_10GBASE_KX4 = 0x2, 1595270631Sjfv I40E_PHY_TYPE_10GBASE_KR = 0x3, 1596270631Sjfv I40E_PHY_TYPE_40GBASE_KR4 = 0x4, 1597270631Sjfv I40E_PHY_TYPE_XAUI = 0x5, 1598270631Sjfv I40E_PHY_TYPE_XFI = 0x6, 1599270631Sjfv I40E_PHY_TYPE_SFI = 0x7, 1600270631Sjfv I40E_PHY_TYPE_XLAUI = 0x8, 1601270631Sjfv I40E_PHY_TYPE_XLPPI = 0x9, 1602270631Sjfv I40E_PHY_TYPE_40GBASE_CR4_CU = 0xA, 1603270631Sjfv I40E_PHY_TYPE_10GBASE_CR1_CU = 0xB, 1604270631Sjfv I40E_PHY_TYPE_10GBASE_AOC = 0xC, 1605270631Sjfv I40E_PHY_TYPE_40GBASE_AOC = 0xD, 1606270631Sjfv I40E_PHY_TYPE_100BASE_TX = 0x11, 1607270631Sjfv I40E_PHY_TYPE_1000BASE_T = 0x12, 1608270631Sjfv I40E_PHY_TYPE_10GBASE_T = 0x13, 1609270631Sjfv I40E_PHY_TYPE_10GBASE_SR = 0x14, 1610270631Sjfv I40E_PHY_TYPE_10GBASE_LR = 0x15, 1611270631Sjfv I40E_PHY_TYPE_10GBASE_SFPP_CU = 0x16, 1612270631Sjfv I40E_PHY_TYPE_10GBASE_CR1 = 0x17, 1613270631Sjfv I40E_PHY_TYPE_40GBASE_CR4 = 0x18, 1614270631Sjfv I40E_PHY_TYPE_40GBASE_SR4 = 0x19, 1615270631Sjfv I40E_PHY_TYPE_40GBASE_LR4 = 0x1A, 1616270631Sjfv I40E_PHY_TYPE_1000BASE_SX = 0x1B, 1617270631Sjfv I40E_PHY_TYPE_1000BASE_LX = 0x1C, 1618270631Sjfv I40E_PHY_TYPE_1000BASE_T_OPTICAL = 0x1D, 1619270631Sjfv I40E_PHY_TYPE_20GBASE_KR2 = 0x1E, 1620270631Sjfv I40E_PHY_TYPE_MAX 1621270631Sjfv}; 1622270631Sjfv 1623270631Sjfv#define I40E_LINK_SPEED_100MB_SHIFT 0x1 1624270631Sjfv#define I40E_LINK_SPEED_1000MB_SHIFT 0x2 1625270631Sjfv#define I40E_LINK_SPEED_10GB_SHIFT 0x3 1626270631Sjfv#define I40E_LINK_SPEED_40GB_SHIFT 0x4 1627270631Sjfv#define I40E_LINK_SPEED_20GB_SHIFT 0x5 1628270631Sjfv 1629270631Sjfvenum i40e_aq_link_speed { 1630270631Sjfv I40E_LINK_SPEED_UNKNOWN = 0, 1631270631Sjfv I40E_LINK_SPEED_100MB = (1 << I40E_LINK_SPEED_100MB_SHIFT), 1632270631Sjfv I40E_LINK_SPEED_1GB = (1 << I40E_LINK_SPEED_1000MB_SHIFT), 1633270631Sjfv I40E_LINK_SPEED_10GB = (1 << I40E_LINK_SPEED_10GB_SHIFT), 1634270631Sjfv I40E_LINK_SPEED_40GB = (1 << I40E_LINK_SPEED_40GB_SHIFT), 1635270631Sjfv I40E_LINK_SPEED_20GB = (1 << I40E_LINK_SPEED_20GB_SHIFT) 1636270631Sjfv}; 1637270631Sjfv 1638270631Sjfvstruct i40e_aqc_module_desc { 1639270631Sjfv u8 oui[3]; 1640270631Sjfv u8 reserved1; 1641270631Sjfv u8 part_number[16]; 1642270631Sjfv u8 revision[4]; 1643270631Sjfv u8 reserved2[8]; 1644270631Sjfv}; 1645270631Sjfv 1646291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_module_desc); 1647291248Ssmh 1648270631Sjfvstruct i40e_aq_get_phy_abilities_resp { 1649270631Sjfv __le32 phy_type; /* bitmap using the above enum for offsets */ 1650270631Sjfv u8 link_speed; /* bitmap using the above enum bit patterns */ 1651270631Sjfv u8 abilities; 1652270631Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_TX 0x01 1653270631Sjfv#define I40E_AQ_PHY_FLAG_PAUSE_RX 0x02 1654270631Sjfv#define I40E_AQ_PHY_FLAG_LOW_POWER 0x04 1655270631Sjfv#define I40E_AQ_PHY_LINK_ENABLED 0x08 1656270631Sjfv#define I40E_AQ_PHY_AN_ENABLED 0x10 1657270631Sjfv#define I40E_AQ_PHY_FLAG_MODULE_QUAL 0x20 1658270631Sjfv __le16 eee_capability; 1659270631Sjfv#define I40E_AQ_EEE_100BASE_TX 0x0002 1660270631Sjfv#define I40E_AQ_EEE_1000BASE_T 0x0004 1661270631Sjfv#define I40E_AQ_EEE_10GBASE_T 0x0008 1662270631Sjfv#define I40E_AQ_EEE_1000BASE_KX 0x0010 1663270631Sjfv#define I40E_AQ_EEE_10GBASE_KX4 0x0020 1664270631Sjfv#define I40E_AQ_EEE_10GBASE_KR 0x0040 1665270631Sjfv __le32 eeer_val; 1666270631Sjfv u8 d3_lpan; 1667270631Sjfv#define I40E_AQ_SET_PHY_D3_LPAN_ENA 0x01 1668270631Sjfv u8 reserved[3]; 1669270631Sjfv u8 phy_id[4]; 1670270631Sjfv u8 module_type[3]; 1671270631Sjfv u8 qualified_module_count; 1672270631Sjfv#define I40E_AQ_PHY_MAX_QMS 16 1673270631Sjfv struct i40e_aqc_module_desc qualified_module[I40E_AQ_PHY_MAX_QMS]; 1674270631Sjfv}; 1675270631Sjfv 1676291248SsmhI40E_CHECK_STRUCT_LEN(0x218, i40e_aq_get_phy_abilities_resp); 1677291248Ssmh 1678270631Sjfv/* Set PHY Config (direct 0x0601) */ 1679270631Sjfvstruct i40e_aq_set_phy_config { /* same bits as above in all */ 1680270631Sjfv __le32 phy_type; 1681270631Sjfv u8 link_speed; 1682270631Sjfv u8 abilities; 1683270631Sjfv/* bits 0-2 use the values from get_phy_abilities_resp */ 1684270631Sjfv#define I40E_AQ_PHY_ENABLE_LINK 0x08 1685270631Sjfv#define I40E_AQ_PHY_ENABLE_AN 0x10 1686270631Sjfv#define I40E_AQ_PHY_ENABLE_ATOMIC_LINK 0x20 1687270631Sjfv __le16 eee_capability; 1688270631Sjfv __le32 eeer; 1689270631Sjfv u8 low_power_ctrl; 1690270631Sjfv u8 reserved[3]; 1691270631Sjfv}; 1692270631Sjfv 1693270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_phy_config); 1694270631Sjfv 1695270631Sjfv/* Set MAC Config command data structure (direct 0x0603) */ 1696270631Sjfvstruct i40e_aq_set_mac_config { 1697270631Sjfv __le16 max_frame_size; 1698270631Sjfv u8 params; 1699270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_CRC_EN 0x04 1700270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_MASK 0x78 1701270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_SHIFT 3 1702270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_NONE 0x0 1703270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1B_13TX 0xF 1704270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_9TX 0x9 1705270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_4TX 0x8 1706270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_7TX 0x7 1707270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_2DW_3TX 0x6 1708270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_1DW_1TX 0x5 1709270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_3DW_2TX 0x4 1710270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_7DW_3TX 0x3 1711270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_4DW_1TX 0x2 1712270631Sjfv#define I40E_AQ_SET_MAC_CONFIG_PACING_9DW_1TX 0x1 1713270631Sjfv u8 tx_timer_priority; /* bitmap */ 1714270631Sjfv __le16 tx_timer_value; 1715270631Sjfv __le16 fc_refresh_threshold; 1716270631Sjfv u8 reserved[8]; 1717270631Sjfv}; 1718270631Sjfv 1719270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aq_set_mac_config); 1720270631Sjfv 1721270631Sjfv/* Restart Auto-Negotiation (direct 0x605) */ 1722270631Sjfvstruct i40e_aqc_set_link_restart_an { 1723270631Sjfv u8 command; 1724270631Sjfv#define I40E_AQ_PHY_RESTART_AN 0x02 1725270631Sjfv#define I40E_AQ_PHY_LINK_ENABLE 0x04 1726270631Sjfv u8 reserved[15]; 1727270631Sjfv}; 1728270631Sjfv 1729270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_link_restart_an); 1730270631Sjfv 1731270631Sjfv/* Get Link Status cmd & response data structure (direct 0x0607) */ 1732270631Sjfvstruct i40e_aqc_get_link_status { 1733270631Sjfv __le16 command_flags; /* only field set on command */ 1734270631Sjfv#define I40E_AQ_LSE_MASK 0x3 1735270631Sjfv#define I40E_AQ_LSE_NOP 0x0 1736270631Sjfv#define I40E_AQ_LSE_DISABLE 0x2 1737270631Sjfv#define I40E_AQ_LSE_ENABLE 0x3 1738270631Sjfv/* only response uses this flag */ 1739270631Sjfv#define I40E_AQ_LSE_IS_ENABLED 0x1 1740270631Sjfv u8 phy_type; /* i40e_aq_phy_type */ 1741270631Sjfv u8 link_speed; /* i40e_aq_link_speed */ 1742270631Sjfv u8 link_info; 1743292100Ssmh#define I40E_AQ_LINK_UP 0x01 /* obsolete */ 1744292100Ssmh#define I40E_AQ_LINK_UP_FUNCTION 0x01 1745270631Sjfv#define I40E_AQ_LINK_FAULT 0x02 1746270631Sjfv#define I40E_AQ_LINK_FAULT_TX 0x04 1747270631Sjfv#define I40E_AQ_LINK_FAULT_RX 0x08 1748270631Sjfv#define I40E_AQ_LINK_FAULT_REMOTE 0x10 1749292100Ssmh#define I40E_AQ_LINK_UP_PORT 0x20 1750270631Sjfv#define I40E_AQ_MEDIA_AVAILABLE 0x40 1751270631Sjfv#define I40E_AQ_SIGNAL_DETECT 0x80 1752270631Sjfv u8 an_info; 1753270631Sjfv#define I40E_AQ_AN_COMPLETED 0x01 1754270631Sjfv#define I40E_AQ_LP_AN_ABILITY 0x02 1755270631Sjfv#define I40E_AQ_PD_FAULT 0x04 1756270631Sjfv#define I40E_AQ_FEC_EN 0x08 1757270631Sjfv#define I40E_AQ_PHY_LOW_POWER 0x10 1758270631Sjfv#define I40E_AQ_LINK_PAUSE_TX 0x20 1759270631Sjfv#define I40E_AQ_LINK_PAUSE_RX 0x40 1760270631Sjfv#define I40E_AQ_QUALIFIED_MODULE 0x80 1761270631Sjfv u8 ext_info; 1762270631Sjfv#define I40E_AQ_LINK_PHY_TEMP_ALARM 0x01 1763270631Sjfv#define I40E_AQ_LINK_XCESSIVE_ERRORS 0x02 1764270631Sjfv#define I40E_AQ_LINK_TX_SHIFT 0x02 1765270631Sjfv#define I40E_AQ_LINK_TX_MASK (0x03 << I40E_AQ_LINK_TX_SHIFT) 1766270631Sjfv#define I40E_AQ_LINK_TX_ACTIVE 0x00 1767270631Sjfv#define I40E_AQ_LINK_TX_DRAINED 0x01 1768270631Sjfv#define I40E_AQ_LINK_TX_FLUSHED 0x03 1769270631Sjfv#define I40E_AQ_LINK_FORCED_40G 0x10 1770270631Sjfv u8 loopback; /* use defines from i40e_aqc_set_lb_mode */ 1771270631Sjfv __le16 max_frame_size; 1772270631Sjfv u8 config; 1773270631Sjfv#define I40E_AQ_CONFIG_CRC_ENA 0x04 1774270631Sjfv#define I40E_AQ_CONFIG_PACING_MASK 0x78 1775270631Sjfv u8 reserved[5]; 1776270631Sjfv}; 1777270631Sjfv 1778270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_get_link_status); 1779270631Sjfv 1780270631Sjfv/* Set event mask command (direct 0x613) */ 1781270631Sjfvstruct i40e_aqc_set_phy_int_mask { 1782270631Sjfv u8 reserved[8]; 1783270631Sjfv __le16 event_mask; 1784270631Sjfv#define I40E_AQ_EVENT_LINK_UPDOWN 0x0002 1785270631Sjfv#define I40E_AQ_EVENT_MEDIA_NA 0x0004 1786270631Sjfv#define I40E_AQ_EVENT_LINK_FAULT 0x0008 1787270631Sjfv#define I40E_AQ_EVENT_PHY_TEMP_ALARM 0x0010 1788270631Sjfv#define I40E_AQ_EVENT_EXCESSIVE_ERRORS 0x0020 1789270631Sjfv#define I40E_AQ_EVENT_SIGNAL_DETECT 0x0040 1790270631Sjfv#define I40E_AQ_EVENT_AN_COMPLETED 0x0080 1791270631Sjfv#define I40E_AQ_EVENT_MODULE_QUAL_FAIL 0x0100 1792270631Sjfv#define I40E_AQ_EVENT_PORT_TX_SUSPENDED 0x0200 1793270631Sjfv u8 reserved1[6]; 1794270631Sjfv}; 1795270631Sjfv 1796270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_int_mask); 1797270631Sjfv 1798270631Sjfv/* Get Local AN advt register (direct 0x0614) 1799270631Sjfv * Set Local AN advt register (direct 0x0615) 1800270631Sjfv * Get Link Partner AN advt register (direct 0x0616) 1801270631Sjfv */ 1802270631Sjfvstruct i40e_aqc_an_advt_reg { 1803270631Sjfv __le32 local_an_reg0; 1804270631Sjfv __le16 local_an_reg1; 1805270631Sjfv u8 reserved[10]; 1806270631Sjfv}; 1807270631Sjfv 1808270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_an_advt_reg); 1809270631Sjfv 1810270631Sjfv/* Set Loopback mode (0x0618) */ 1811270631Sjfvstruct i40e_aqc_set_lb_mode { 1812270631Sjfv __le16 lb_mode; 1813270631Sjfv#define I40E_AQ_LB_PHY_LOCAL 0x01 1814270631Sjfv#define I40E_AQ_LB_PHY_REMOTE 0x02 1815270631Sjfv#define I40E_AQ_LB_MAC_LOCAL 0x04 1816270631Sjfv u8 reserved[14]; 1817270631Sjfv}; 1818270631Sjfv 1819270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_lb_mode); 1820270631Sjfv 1821270631Sjfv/* Set PHY Debug command (0x0622) */ 1822270631Sjfvstruct i40e_aqc_set_phy_debug { 1823270631Sjfv u8 command_flags; 1824270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_INTERNAL 0x02 1825270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT 2 1826270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_MASK (0x03 << \ 1827270631Sjfv I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SHIFT) 1828270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_NONE 0x00 1829270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_HARD 0x01 1830270631Sjfv#define I40E_AQ_PHY_DEBUG_RESET_EXTERNAL_SOFT 0x02 1831270631Sjfv#define I40E_AQ_PHY_DEBUG_DISABLE_LINK_FW 0x10 1832270631Sjfv u8 reserved[15]; 1833270631Sjfv}; 1834270631Sjfv 1835270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_set_phy_debug); 1836270631Sjfv 1837270631Sjfvenum i40e_aq_phy_reg_type { 1838270631Sjfv I40E_AQC_PHY_REG_INTERNAL = 0x1, 1839270631Sjfv I40E_AQC_PHY_REG_EXERNAL_BASET = 0x2, 1840270631Sjfv I40E_AQC_PHY_REG_EXERNAL_MODULE = 0x3 1841270631Sjfv}; 1842270631Sjfv 1843270631Sjfv/* NVM Read command (indirect 0x0701) 1844270631Sjfv * NVM Erase commands (direct 0x0702) 1845270631Sjfv * NVM Update commands (indirect 0x0703) 1846270631Sjfv */ 1847270631Sjfvstruct i40e_aqc_nvm_update { 1848270631Sjfv u8 command_flags; 1849270631Sjfv#define I40E_AQ_NVM_LAST_CMD 0x01 1850270631Sjfv#define I40E_AQ_NVM_FLASH_ONLY 0x80 1851270631Sjfv u8 module_pointer; 1852270631Sjfv __le16 length; 1853270631Sjfv __le32 offset; 1854270631Sjfv __le32 addr_high; 1855270631Sjfv __le32 addr_low; 1856270631Sjfv}; 1857270631Sjfv 1858270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_update); 1859270631Sjfv 1860270631Sjfv/* NVM Config Read (indirect 0x0704) */ 1861270631Sjfvstruct i40e_aqc_nvm_config_read { 1862270631Sjfv __le16 cmd_flags; 1863291248Ssmh#define I40E_AQ_ANVM_SINGLE_OR_MULTIPLE_FEATURES_MASK 1 1864291248Ssmh#define I40E_AQ_ANVM_READ_SINGLE_FEATURE 0 1865291248Ssmh#define I40E_AQ_ANVM_READ_MULTIPLE_FEATURES 1 1866270631Sjfv __le16 element_count; 1867291248Ssmh __le16 element_id; /* Feature/field ID */ 1868291248Ssmh __le16 element_id_msw; /* MSWord of field ID */ 1869270631Sjfv __le32 address_high; 1870270631Sjfv __le32 address_low; 1871270631Sjfv}; 1872270631Sjfv 1873270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_read); 1874270631Sjfv 1875270631Sjfv/* NVM Config Write (indirect 0x0705) */ 1876270631Sjfvstruct i40e_aqc_nvm_config_write { 1877270631Sjfv __le16 cmd_flags; 1878270631Sjfv __le16 element_count; 1879270631Sjfv u8 reserved[4]; 1880270631Sjfv __le32 address_high; 1881270631Sjfv __le32 address_low; 1882270631Sjfv}; 1883270631Sjfv 1884270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_nvm_config_write); 1885270631Sjfv 1886291248Ssmh/* Used for 0x0704 as well as for 0x0705 commands */ 1887291248Ssmh#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT 1 1888291248Ssmh#define I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_MASK (1 << I40E_AQ_ANVM_FEATURE_OR_IMMEDIATE_SHIFT) 1889291248Ssmh#define I40E_AQ_ANVM_FEATURE 0 1890291248Ssmh#define I40E_AQ_ANVM_IMMEDIATE_FIELD (1 << FEATURE_OR_IMMEDIATE_SHIFT) 1891270631Sjfvstruct i40e_aqc_nvm_config_data_feature { 1892270631Sjfv __le16 feature_id; 1893291248Ssmh#define I40E_AQ_ANVM_FEATURE_OPTION_OEM_ONLY 0x01 1894291248Ssmh#define I40E_AQ_ANVM_FEATURE_OPTION_DWORD_MAP 0x08 1895291248Ssmh#define I40E_AQ_ANVM_FEATURE_OPTION_POR_CSR 0x10 1896270631Sjfv __le16 feature_options; 1897270631Sjfv __le16 feature_selection; 1898270631Sjfv}; 1899270631Sjfv 1900291248SsmhI40E_CHECK_STRUCT_LEN(0x6, i40e_aqc_nvm_config_data_feature); 1901291248Ssmh 1902270631Sjfvstruct i40e_aqc_nvm_config_data_immediate_field { 1903291248Ssmh __le32 field_id; 1904291248Ssmh __le32 field_value; 1905270631Sjfv __le16 field_options; 1906291248Ssmh __le16 reserved; 1907270631Sjfv}; 1908270631Sjfv 1909291248SsmhI40E_CHECK_STRUCT_LEN(0xc, i40e_aqc_nvm_config_data_immediate_field); 1910291248Ssmh 1911292100Ssmh/* OEM Post Update (indirect 0x0720) 1912292100Ssmh * no command data struct used 1913292100Ssmh */ 1914292100Ssmh struct i40e_aqc_nvm_oem_post_update { 1915292100Ssmh#define I40E_AQ_NVM_OEM_POST_UPDATE_EXTERNAL_DATA 0x01 1916292100Ssmh u8 sel_data; 1917292100Ssmh u8 reserved[7]; 1918292100Ssmh}; 1919292100Ssmh 1920292100SsmhI40E_CHECK_STRUCT_LEN(0x8, i40e_aqc_nvm_oem_post_update); 1921292100Ssmh 1922292100Ssmhstruct i40e_aqc_nvm_oem_post_update_buffer { 1923292100Ssmh u8 str_len; 1924292100Ssmh u8 dev_addr; 1925292100Ssmh __le16 eeprom_addr; 1926292100Ssmh u8 data[36]; 1927292100Ssmh}; 1928292100Ssmh 1929292100SsmhI40E_CHECK_STRUCT_LEN(0x28, i40e_aqc_nvm_oem_post_update_buffer); 1930292100Ssmh 1931270631Sjfv/* Send to PF command (indirect 0x0801) id is only used by PF 1932270631Sjfv * Send to VF command (indirect 0x0802) id is only used by PF 1933270631Sjfv * Send to Peer PF command (indirect 0x0803) 1934270631Sjfv */ 1935270631Sjfvstruct i40e_aqc_pf_vf_message { 1936270631Sjfv __le32 id; 1937270631Sjfv u8 reserved[4]; 1938270631Sjfv __le32 addr_high; 1939270631Sjfv __le32 addr_low; 1940270631Sjfv}; 1941270631Sjfv 1942270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_pf_vf_message); 1943270631Sjfv 1944270631Sjfv/* Alternate structure */ 1945270631Sjfv 1946270631Sjfv/* Direct write (direct 0x0900) 1947270631Sjfv * Direct read (direct 0x0902) 1948270631Sjfv */ 1949270631Sjfvstruct i40e_aqc_alternate_write { 1950270631Sjfv __le32 address0; 1951270631Sjfv __le32 data0; 1952270631Sjfv __le32 address1; 1953270631Sjfv __le32 data1; 1954270631Sjfv}; 1955270631Sjfv 1956270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write); 1957270631Sjfv 1958270631Sjfv/* Indirect write (indirect 0x0901) 1959270631Sjfv * Indirect read (indirect 0x0903) 1960270631Sjfv */ 1961270631Sjfv 1962270631Sjfvstruct i40e_aqc_alternate_ind_write { 1963270631Sjfv __le32 address; 1964270631Sjfv __le32 length; 1965270631Sjfv __le32 addr_high; 1966270631Sjfv __le32 addr_low; 1967270631Sjfv}; 1968270631Sjfv 1969270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_ind_write); 1970270631Sjfv 1971270631Sjfv/* Done alternate write (direct 0x0904) 1972270631Sjfv * uses i40e_aq_desc 1973270631Sjfv */ 1974270631Sjfvstruct i40e_aqc_alternate_write_done { 1975270631Sjfv __le16 cmd_flags; 1976270631Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_MASK 1 1977270631Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_LEGACY 0 1978270631Sjfv#define I40E_AQ_ALTERNATE_MODE_BIOS_UEFI 1 1979270631Sjfv#define I40E_AQ_ALTERNATE_RESET_NEEDED 2 1980270631Sjfv u8 reserved[14]; 1981270631Sjfv}; 1982270631Sjfv 1983270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_write_done); 1984270631Sjfv 1985270631Sjfv/* Set OEM mode (direct 0x0905) */ 1986270631Sjfvstruct i40e_aqc_alternate_set_mode { 1987270631Sjfv __le32 mode; 1988270631Sjfv#define I40E_AQ_ALTERNATE_MODE_NONE 0 1989270631Sjfv#define I40E_AQ_ALTERNATE_MODE_OEM 1 1990270631Sjfv u8 reserved[12]; 1991270631Sjfv}; 1992270631Sjfv 1993270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_alternate_set_mode); 1994270631Sjfv 1995270631Sjfv/* Clear port Alternate RAM (direct 0x0906) uses i40e_aq_desc */ 1996270631Sjfv 1997270631Sjfv/* async events 0x10xx */ 1998270631Sjfv 1999270631Sjfv/* Lan Queue Overflow Event (direct, 0x1001) */ 2000270631Sjfvstruct i40e_aqc_lan_overflow { 2001270631Sjfv __le32 prtdcb_rupto; 2002270631Sjfv __le32 otx_ctl; 2003270631Sjfv u8 reserved[8]; 2004270631Sjfv}; 2005270631Sjfv 2006270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lan_overflow); 2007270631Sjfv 2008270631Sjfv/* Get LLDP MIB (indirect 0x0A00) */ 2009270631Sjfvstruct i40e_aqc_lldp_get_mib { 2010270631Sjfv u8 type; 2011270631Sjfv u8 reserved1; 2012270631Sjfv#define I40E_AQ_LLDP_MIB_TYPE_MASK 0x3 2013270631Sjfv#define I40E_AQ_LLDP_MIB_LOCAL 0x0 2014270631Sjfv#define I40E_AQ_LLDP_MIB_REMOTE 0x1 2015270631Sjfv#define I40E_AQ_LLDP_MIB_LOCAL_AND_REMOTE 0x2 2016270631Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_MASK 0xC 2017270631Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_SHIFT 0x2 2018270631Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NEAREST_BRIDGE 0x0 2019270631Sjfv#define I40E_AQ_LLDP_BRIDGE_TYPE_NON_TPMR 0x1 2020270631Sjfv#define I40E_AQ_LLDP_TX_SHIFT 0x4 2021270631Sjfv#define I40E_AQ_LLDP_TX_MASK (0x03 << I40E_AQ_LLDP_TX_SHIFT) 2022270631Sjfv/* TX pause flags use I40E_AQ_LINK_TX_* above */ 2023270631Sjfv __le16 local_len; 2024270631Sjfv __le16 remote_len; 2025270631Sjfv u8 reserved2[2]; 2026270631Sjfv __le32 addr_high; 2027270631Sjfv __le32 addr_low; 2028270631Sjfv}; 2029270631Sjfv 2030270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_get_mib); 2031270631Sjfv 2032270631Sjfv/* Configure LLDP MIB Change Event (direct 0x0A01) 2033270631Sjfv * also used for the event (with type in the command field) 2034270631Sjfv */ 2035270631Sjfvstruct i40e_aqc_lldp_update_mib { 2036270631Sjfv u8 command; 2037270631Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_ENABLE 0x0 2038270631Sjfv#define I40E_AQ_LLDP_MIB_UPDATE_DISABLE 0x1 2039270631Sjfv u8 reserved[7]; 2040270631Sjfv __le32 addr_high; 2041270631Sjfv __le32 addr_low; 2042270631Sjfv}; 2043270631Sjfv 2044270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_mib); 2045270631Sjfv 2046270631Sjfv/* Add LLDP TLV (indirect 0x0A02) 2047270631Sjfv * Delete LLDP TLV (indirect 0x0A04) 2048270631Sjfv */ 2049270631Sjfvstruct i40e_aqc_lldp_add_tlv { 2050270631Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2051270631Sjfv u8 reserved1[1]; 2052270631Sjfv __le16 len; 2053270631Sjfv u8 reserved2[4]; 2054270631Sjfv __le32 addr_high; 2055270631Sjfv __le32 addr_low; 2056270631Sjfv}; 2057270631Sjfv 2058270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_add_tlv); 2059270631Sjfv 2060270631Sjfv/* Update LLDP TLV (indirect 0x0A03) */ 2061270631Sjfvstruct i40e_aqc_lldp_update_tlv { 2062270631Sjfv u8 type; /* only nearest bridge and non-TPMR from 0x0A00 */ 2063270631Sjfv u8 reserved; 2064270631Sjfv __le16 old_len; 2065270631Sjfv __le16 new_offset; 2066270631Sjfv __le16 new_len; 2067270631Sjfv __le32 addr_high; 2068270631Sjfv __le32 addr_low; 2069270631Sjfv}; 2070270631Sjfv 2071270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_update_tlv); 2072270631Sjfv 2073270631Sjfv/* Stop LLDP (direct 0x0A05) */ 2074270631Sjfvstruct i40e_aqc_lldp_stop { 2075270631Sjfv u8 command; 2076270631Sjfv#define I40E_AQ_LLDP_AGENT_STOP 0x0 2077270631Sjfv#define I40E_AQ_LLDP_AGENT_SHUTDOWN 0x1 2078270631Sjfv u8 reserved[15]; 2079270631Sjfv}; 2080270631Sjfv 2081270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop); 2082270631Sjfv 2083270631Sjfv/* Start LLDP (direct 0x0A06) */ 2084270631Sjfv 2085270631Sjfvstruct i40e_aqc_lldp_start { 2086270631Sjfv u8 command; 2087270631Sjfv#define I40E_AQ_LLDP_AGENT_START 0x1 2088270631Sjfv u8 reserved[15]; 2089270631Sjfv}; 2090270631Sjfv 2091270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_start); 2092270631Sjfv 2093291248Ssmh/* Get CEE DCBX Oper Config (0x0A07) 2094291248Ssmh * uses the generic descriptor struct 2095291248Ssmh * returns below as indirect response 2096270631Sjfv */ 2097270631Sjfv 2098291248Ssmh#define I40E_AQC_CEE_APP_FCOE_SHIFT 0x0 2099291248Ssmh#define I40E_AQC_CEE_APP_FCOE_MASK (0x7 << I40E_AQC_CEE_APP_FCOE_SHIFT) 2100291248Ssmh#define I40E_AQC_CEE_APP_ISCSI_SHIFT 0x3 2101291248Ssmh#define I40E_AQC_CEE_APP_ISCSI_MASK (0x7 << I40E_AQC_CEE_APP_ISCSI_SHIFT) 2102291248Ssmh#define I40E_AQC_CEE_APP_FIP_SHIFT 0x8 2103291248Ssmh#define I40E_AQC_CEE_APP_FIP_MASK (0x7 << I40E_AQC_CEE_APP_FIP_SHIFT) 2104292100Ssmh 2105291248Ssmh#define I40E_AQC_CEE_PG_STATUS_SHIFT 0x0 2106291248Ssmh#define I40E_AQC_CEE_PG_STATUS_MASK (0x7 << I40E_AQC_CEE_PG_STATUS_SHIFT) 2107291248Ssmh#define I40E_AQC_CEE_PFC_STATUS_SHIFT 0x3 2108291248Ssmh#define I40E_AQC_CEE_PFC_STATUS_MASK (0x7 << I40E_AQC_CEE_PFC_STATUS_SHIFT) 2109291248Ssmh#define I40E_AQC_CEE_APP_STATUS_SHIFT 0x8 2110291248Ssmh#define I40E_AQC_CEE_APP_STATUS_MASK (0x7 << I40E_AQC_CEE_APP_STATUS_SHIFT) 2111292100Ssmh#define I40E_AQC_CEE_FCOE_STATUS_SHIFT 0x8 2112292100Ssmh#define I40E_AQC_CEE_FCOE_STATUS_MASK (0x7 << I40E_AQC_CEE_FCOE_STATUS_SHIFT) 2113292100Ssmh#define I40E_AQC_CEE_ISCSI_STATUS_SHIFT 0xB 2114292100Ssmh#define I40E_AQC_CEE_ISCSI_STATUS_MASK (0x7 << I40E_AQC_CEE_ISCSI_STATUS_SHIFT) 2115292100Ssmh#define I40E_AQC_CEE_FIP_STATUS_SHIFT 0x10 2116292100Ssmh#define I40E_AQC_CEE_FIP_STATUS_MASK (0x7 << I40E_AQC_CEE_FIP_STATUS_SHIFT) 2117292100Ssmh 2118292100Ssmh/* struct i40e_aqc_get_cee_dcb_cfg_v1_resp was originally defined with 2119292100Ssmh * word boundary layout issues, which the Linux compilers silently deal 2120292100Ssmh * with by adding padding, making the actual struct larger than designed. 2121292100Ssmh * However, the FW compiler for the NIC is less lenient and complains 2122292100Ssmh * about the struct. Hence, the struct defined here has an extra byte in 2123292100Ssmh * fields reserved3 and reserved4 to directly acknowledge that padding, 2124292100Ssmh * and the new length is used in the length check macro. 2125292100Ssmh */ 2126291248Ssmhstruct i40e_aqc_get_cee_dcb_cfg_v1_resp { 2127291248Ssmh u8 reserved1; 2128291248Ssmh u8 oper_num_tc; 2129291248Ssmh u8 oper_prio_tc[4]; 2130291248Ssmh u8 reserved2; 2131291248Ssmh u8 oper_tc_bw[8]; 2132291248Ssmh u8 oper_pfc_en; 2133292100Ssmh u8 reserved3[2]; 2134291248Ssmh __le16 oper_app_prio; 2135292100Ssmh u8 reserved4[2]; 2136291248Ssmh __le16 tlv_status; 2137291248Ssmh}; 2138291248Ssmh 2139291248SsmhI40E_CHECK_STRUCT_LEN(0x18, i40e_aqc_get_cee_dcb_cfg_v1_resp); 2140291248Ssmh 2141291248Ssmhstruct i40e_aqc_get_cee_dcb_cfg_resp { 2142291248Ssmh u8 oper_num_tc; 2143291248Ssmh u8 oper_prio_tc[4]; 2144291248Ssmh u8 oper_tc_bw[8]; 2145291248Ssmh u8 oper_pfc_en; 2146291248Ssmh __le16 oper_app_prio; 2147291248Ssmh __le32 tlv_status; 2148291248Ssmh u8 reserved[12]; 2149291248Ssmh}; 2150291248Ssmh 2151291248SsmhI40E_CHECK_STRUCT_LEN(0x20, i40e_aqc_get_cee_dcb_cfg_resp); 2152291248Ssmh 2153291248Ssmh/* Set Local LLDP MIB (indirect 0x0A08) 2154291248Ssmh * Used to replace the local MIB of a given LLDP agent. e.g. DCBx 2155291248Ssmh */ 2156291248Ssmhstruct i40e_aqc_lldp_set_local_mib { 2157291248Ssmh#define SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT 0 2158291248Ssmh#define SET_LOCAL_MIB_AC_TYPE_DCBX_MASK (1 << SET_LOCAL_MIB_AC_TYPE_DCBX_SHIFT) 2159291248Ssmh u8 type; 2160291248Ssmh u8 reserved0; 2161291248Ssmh __le16 length; 2162291248Ssmh u8 reserved1[4]; 2163291248Ssmh __le32 address_high; 2164291248Ssmh __le32 address_low; 2165291248Ssmh}; 2166291248Ssmh 2167291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_set_local_mib); 2168291248Ssmh 2169291248Ssmh/* Stop/Start LLDP Agent (direct 0x0A09) 2170291248Ssmh * Used for stopping/starting specific LLDP agent. e.g. DCBx 2171291248Ssmh */ 2172291248Ssmhstruct i40e_aqc_lldp_stop_start_specific_agent { 2173291248Ssmh#define I40E_AQC_START_SPECIFIC_AGENT_SHIFT 0 2174291248Ssmh#define I40E_AQC_START_SPECIFIC_AGENT_MASK (1 << I40E_AQC_START_SPECIFIC_AGENT_SHIFT) 2175291248Ssmh u8 command; 2176291248Ssmh u8 reserved[15]; 2177291248Ssmh}; 2178291248Ssmh 2179291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_lldp_stop_start_specific_agent); 2180291248Ssmh 2181270631Sjfv/* Add Udp Tunnel command and completion (direct 0x0B00) */ 2182270631Sjfvstruct i40e_aqc_add_udp_tunnel { 2183270631Sjfv __le16 udp_port; 2184270631Sjfv u8 reserved0[3]; 2185270631Sjfv u8 protocol_type; 2186270631Sjfv#define I40E_AQC_TUNNEL_TYPE_VXLAN 0x00 2187270631Sjfv#define I40E_AQC_TUNNEL_TYPE_NGE 0x01 2188270631Sjfv#define I40E_AQC_TUNNEL_TYPE_TEREDO 0x10 2189270631Sjfv u8 reserved1[10]; 2190270631Sjfv}; 2191270631Sjfv 2192270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel); 2193270631Sjfv 2194270631Sjfvstruct i40e_aqc_add_udp_tunnel_completion { 2195270631Sjfv __le16 udp_port; 2196270631Sjfv u8 filter_entry_index; 2197270631Sjfv u8 multiple_pfs; 2198270631Sjfv#define I40E_AQC_SINGLE_PF 0x0 2199270631Sjfv#define I40E_AQC_MULTIPLE_PFS 0x1 2200270631Sjfv u8 total_filters; 2201270631Sjfv u8 reserved[11]; 2202270631Sjfv}; 2203270631Sjfv 2204270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_add_udp_tunnel_completion); 2205270631Sjfv 2206270631Sjfv/* remove UDP Tunnel command (0x0B01) */ 2207270631Sjfvstruct i40e_aqc_remove_udp_tunnel { 2208270631Sjfv u8 reserved[2]; 2209270631Sjfv u8 index; /* 0 to 15 */ 2210270631Sjfv u8 reserved2[13]; 2211270631Sjfv}; 2212270631Sjfv 2213270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_remove_udp_tunnel); 2214270631Sjfv 2215270631Sjfvstruct i40e_aqc_del_udp_tunnel_completion { 2216270631Sjfv __le16 udp_port; 2217270631Sjfv u8 index; /* 0 to 15 */ 2218270631Sjfv u8 multiple_pfs; 2219270631Sjfv u8 total_filters_used; 2220270631Sjfv u8 reserved1[11]; 2221270631Sjfv}; 2222270631Sjfv 2223270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_del_udp_tunnel_completion); 2224292100Ssmh#ifdef X722_SUPPORT 2225270631Sjfv 2226292100Ssmhstruct i40e_aqc_get_set_rss_key { 2227292100Ssmh#define I40E_AQC_SET_RSS_KEY_VSI_VALID (0x1 << 15) 2228292100Ssmh#define I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT 0 2229292100Ssmh#define I40E_AQC_SET_RSS_KEY_VSI_ID_MASK (0x3FF << \ 2230292100Ssmh I40E_AQC_SET_RSS_KEY_VSI_ID_SHIFT) 2231292100Ssmh __le16 vsi_id; 2232292100Ssmh u8 reserved[6]; 2233292100Ssmh __le32 addr_high; 2234292100Ssmh __le32 addr_low; 2235292100Ssmh}; 2236292100Ssmh 2237292100SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_key); 2238292100Ssmh 2239292100Ssmhstruct i40e_aqc_get_set_rss_key_data { 2240292100Ssmh u8 standard_rss_key[0x28]; 2241292100Ssmh u8 extended_hash_key[0xc]; 2242292100Ssmh}; 2243292100Ssmh 2244292100SsmhI40E_CHECK_STRUCT_LEN(0x34, i40e_aqc_get_set_rss_key_data); 2245292100Ssmh 2246292100Ssmhstruct i40e_aqc_get_set_rss_lut { 2247292100Ssmh#define I40E_AQC_SET_RSS_LUT_VSI_VALID (0x1 << 15) 2248292100Ssmh#define I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT 0 2249292100Ssmh#define I40E_AQC_SET_RSS_LUT_VSI_ID_MASK (0x3FF << \ 2250292100Ssmh I40E_AQC_SET_RSS_LUT_VSI_ID_SHIFT) 2251292100Ssmh __le16 vsi_id; 2252292100Ssmh#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT 0 2253292100Ssmh#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_MASK (0x1 << \ 2254292100Ssmh I40E_AQC_SET_RSS_LUT_TABLE_TYPE_SHIFT) 2255292100Ssmh 2256292100Ssmh#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_VSI 0 2257292100Ssmh#define I40E_AQC_SET_RSS_LUT_TABLE_TYPE_PF 1 2258292100Ssmh __le16 flags; 2259292100Ssmh u8 reserved[4]; 2260292100Ssmh __le32 addr_high; 2261292100Ssmh __le32 addr_low; 2262292100Ssmh}; 2263292100Ssmh 2264292100SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_get_set_rss_lut); 2265292100Ssmh#endif 2266292100Ssmh 2267270631Sjfv/* tunnel key structure 0x0B10 */ 2268270631Sjfv 2269270631Sjfvstruct i40e_aqc_tunnel_key_structure { 2270270631Sjfv u8 key1_off; 2271270631Sjfv u8 key2_off; 2272270631Sjfv u8 key1_len; /* 0 to 15 */ 2273270631Sjfv u8 key2_len; /* 0 to 15 */ 2274270631Sjfv u8 flags; 2275270631Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDE 0x01 2276270631Sjfv/* response flags */ 2277270631Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_SUCCESS 0x01 2278270631Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_MODIFIED 0x02 2279270631Sjfv#define I40E_AQC_TUNNEL_KEY_STRUCT_OVERRIDDEN 0x03 2280270631Sjfv u8 network_key_index; 2281270631Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_VXLAN 0x0 2282270631Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_NGE 0x1 2283270631Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_FLEX_MAC_IN_UDP 0x2 2284270631Sjfv#define I40E_AQC_NETWORK_KEY_INDEX_GRE 0x3 2285270631Sjfv u8 reserved[10]; 2286270631Sjfv}; 2287270631Sjfv 2288270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_tunnel_key_structure); 2289270631Sjfv 2290270631Sjfv/* OEM mode commands (direct 0xFE0x) */ 2291270631Sjfvstruct i40e_aqc_oem_param_change { 2292270631Sjfv __le32 param_type; 2293270631Sjfv#define I40E_AQ_OEM_PARAM_TYPE_PF_CTL 0 2294270631Sjfv#define I40E_AQ_OEM_PARAM_TYPE_BW_CTL 1 2295270631Sjfv#define I40E_AQ_OEM_PARAM_MAC 2 2296270631Sjfv __le32 param_value1; 2297291248Ssmh __le16 param_value2; 2298291248Ssmh u8 reserved[6]; 2299270631Sjfv}; 2300270631Sjfv 2301270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_param_change); 2302270631Sjfv 2303270631Sjfvstruct i40e_aqc_oem_state_change { 2304270631Sjfv __le32 state; 2305270631Sjfv#define I40E_AQ_OEM_STATE_LINK_DOWN 0x0 2306270631Sjfv#define I40E_AQ_OEM_STATE_LINK_UP 0x1 2307270631Sjfv u8 reserved[12]; 2308270631Sjfv}; 2309270631Sjfv 2310270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_oem_state_change); 2311270631Sjfv 2312291248Ssmh/* Initialize OCSD (0xFE02, direct) */ 2313291248Ssmhstruct i40e_aqc_opc_oem_ocsd_initialize { 2314291248Ssmh u8 type_status; 2315291248Ssmh u8 reserved1[3]; 2316291248Ssmh __le32 ocsd_memory_block_addr_high; 2317291248Ssmh __le32 ocsd_memory_block_addr_low; 2318291248Ssmh __le32 requested_update_interval; 2319291248Ssmh}; 2320291248Ssmh 2321291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocsd_initialize); 2322291248Ssmh 2323291248Ssmh/* Initialize OCBB (0xFE03, direct) */ 2324291248Ssmhstruct i40e_aqc_opc_oem_ocbb_initialize { 2325291248Ssmh u8 type_status; 2326291248Ssmh u8 reserved1[3]; 2327291248Ssmh __le32 ocbb_memory_block_addr_high; 2328291248Ssmh __le32 ocbb_memory_block_addr_low; 2329291248Ssmh u8 reserved2[4]; 2330291248Ssmh}; 2331291248Ssmh 2332291248SsmhI40E_CHECK_CMD_LENGTH(i40e_aqc_opc_oem_ocbb_initialize); 2333291248Ssmh 2334270631Sjfv/* debug commands */ 2335270631Sjfv 2336270631Sjfv/* get device id (0xFF00) uses the generic structure */ 2337270631Sjfv 2338270631Sjfv/* set test more (0xFF01, internal) */ 2339270631Sjfv 2340270631Sjfvstruct i40e_acq_set_test_mode { 2341270631Sjfv u8 mode; 2342270631Sjfv#define I40E_AQ_TEST_PARTIAL 0 2343270631Sjfv#define I40E_AQ_TEST_FULL 1 2344270631Sjfv#define I40E_AQ_TEST_NVM 2 2345270631Sjfv u8 reserved[3]; 2346270631Sjfv u8 command; 2347270631Sjfv#define I40E_AQ_TEST_OPEN 0 2348270631Sjfv#define I40E_AQ_TEST_CLOSE 1 2349270631Sjfv#define I40E_AQ_TEST_INC 2 2350270631Sjfv u8 reserved2[3]; 2351270631Sjfv __le32 address_high; 2352270631Sjfv __le32 address_low; 2353270631Sjfv}; 2354270631Sjfv 2355270631SjfvI40E_CHECK_CMD_LENGTH(i40e_acq_set_test_mode); 2356270631Sjfv 2357270631Sjfv/* Debug Read Register command (0xFF03) 2358270631Sjfv * Debug Write Register command (0xFF04) 2359270631Sjfv */ 2360270631Sjfvstruct i40e_aqc_debug_reg_read_write { 2361270631Sjfv __le32 reserved; 2362270631Sjfv __le32 address; 2363270631Sjfv __le32 value_high; 2364270631Sjfv __le32 value_low; 2365270631Sjfv}; 2366270631Sjfv 2367270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_reg_read_write); 2368270631Sjfv 2369270631Sjfv/* Scatter/gather Reg Read (indirect 0xFF05) 2370270631Sjfv * Scatter/gather Reg Write (indirect 0xFF06) 2371270631Sjfv */ 2372270631Sjfv 2373270631Sjfv/* i40e_aq_desc is used for the command */ 2374270631Sjfvstruct i40e_aqc_debug_reg_sg_element_data { 2375270631Sjfv __le32 address; 2376270631Sjfv __le32 value; 2377270631Sjfv}; 2378270631Sjfv 2379270631Sjfv/* Debug Modify register (direct 0xFF07) */ 2380270631Sjfvstruct i40e_aqc_debug_modify_reg { 2381270631Sjfv __le32 address; 2382270631Sjfv __le32 value; 2383270631Sjfv __le32 clear_mask; 2384270631Sjfv __le32 set_mask; 2385270631Sjfv}; 2386270631Sjfv 2387270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_reg); 2388270631Sjfv 2389270631Sjfv/* dump internal data (0xFF08, indirect) */ 2390270631Sjfv 2391270631Sjfv#define I40E_AQ_CLUSTER_ID_AUX 0 2392270631Sjfv#define I40E_AQ_CLUSTER_ID_SWITCH_FLU 1 2393270631Sjfv#define I40E_AQ_CLUSTER_ID_TXSCHED 2 2394270631Sjfv#define I40E_AQ_CLUSTER_ID_HMC 3 2395270631Sjfv#define I40E_AQ_CLUSTER_ID_MAC0 4 2396270631Sjfv#define I40E_AQ_CLUSTER_ID_MAC1 5 2397270631Sjfv#define I40E_AQ_CLUSTER_ID_MAC2 6 2398270631Sjfv#define I40E_AQ_CLUSTER_ID_MAC3 7 2399270631Sjfv#define I40E_AQ_CLUSTER_ID_DCB 8 2400270631Sjfv#define I40E_AQ_CLUSTER_ID_EMP_MEM 9 2401270631Sjfv#define I40E_AQ_CLUSTER_ID_PKT_BUF 10 2402270631Sjfv#define I40E_AQ_CLUSTER_ID_ALTRAM 11 2403270631Sjfv 2404270631Sjfvstruct i40e_aqc_debug_dump_internals { 2405270631Sjfv u8 cluster_id; 2406270631Sjfv u8 table_id; 2407270631Sjfv __le16 data_size; 2408270631Sjfv __le32 idx; 2409270631Sjfv __le32 address_high; 2410270631Sjfv __le32 address_low; 2411270631Sjfv}; 2412270631Sjfv 2413270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_dump_internals); 2414270631Sjfv 2415270631Sjfvstruct i40e_aqc_debug_modify_internals { 2416270631Sjfv u8 cluster_id; 2417270631Sjfv u8 cluster_specific_params[7]; 2418270631Sjfv __le32 address_high; 2419270631Sjfv __le32 address_low; 2420270631Sjfv}; 2421270631Sjfv 2422270631SjfvI40E_CHECK_CMD_LENGTH(i40e_aqc_debug_modify_internals); 2423270631Sjfv 2424270631Sjfv#endif 2425