1270631Sjfv/****************************************************************************** 2270631Sjfv 3292100Ssmh Copyright (c) 2013-2015, Intel Corporation 4270631Sjfv All rights reserved. 5270631Sjfv 6270631Sjfv Redistribution and use in source and binary forms, with or without 7270631Sjfv modification, are permitted provided that the following conditions are met: 8270631Sjfv 9270631Sjfv 1. Redistributions of source code must retain the above copyright notice, 10270631Sjfv this list of conditions and the following disclaimer. 11270631Sjfv 12270631Sjfv 2. Redistributions in binary form must reproduce the above copyright 13270631Sjfv notice, this list of conditions and the following disclaimer in the 14270631Sjfv documentation and/or other materials provided with the distribution. 15270631Sjfv 16270631Sjfv 3. Neither the name of the Intel Corporation nor the names of its 17270631Sjfv contributors may be used to endorse or promote products derived from 18270631Sjfv this software without specific prior written permission. 19270631Sjfv 20270631Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21270631Sjfv AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22270631Sjfv IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23270631Sjfv ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24270631Sjfv LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25270631Sjfv CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26270631Sjfv SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27270631Sjfv INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28270631Sjfv CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29270631Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30270631Sjfv POSSIBILITY OF SUCH DAMAGE. 31270631Sjfv 32270631Sjfv******************************************************************************/ 33270631Sjfv/*$FreeBSD$*/ 34270631Sjfv 35270631Sjfv#ifndef _I40E_ADMINQ_H_ 36270631Sjfv#define _I40E_ADMINQ_H_ 37270631Sjfv 38270631Sjfv#include "i40e_osdep.h" 39291248Ssmh#include "i40e_status.h" 40270631Sjfv#include "i40e_adminq_cmd.h" 41270631Sjfv 42270631Sjfv#define I40E_ADMINQ_DESC(R, i) \ 43270631Sjfv (&(((struct i40e_aq_desc *)((R).desc_buf.va))[i])) 44270631Sjfv 45270631Sjfv#define I40E_ADMINQ_DESC_ALIGNMENT 4096 46270631Sjfv 47270631Sjfvstruct i40e_adminq_ring { 48270631Sjfv struct i40e_virt_mem dma_head; /* space for dma structures */ 49270631Sjfv struct i40e_dma_mem desc_buf; /* descriptor ring memory */ 50270631Sjfv struct i40e_virt_mem cmd_buf; /* command buffer memory */ 51270631Sjfv 52270631Sjfv union { 53270631Sjfv struct i40e_dma_mem *asq_bi; 54270631Sjfv struct i40e_dma_mem *arq_bi; 55270631Sjfv } r; 56270631Sjfv 57270631Sjfv u16 count; /* Number of descriptors */ 58270631Sjfv u16 rx_buf_len; /* Admin Receive Queue buffer length */ 59270631Sjfv 60270631Sjfv /* used for interrupt processing */ 61270631Sjfv u16 next_to_use; 62270631Sjfv u16 next_to_clean; 63270631Sjfv 64270631Sjfv /* used for queue tracking */ 65270631Sjfv u32 head; 66270631Sjfv u32 tail; 67270631Sjfv u32 len; 68270631Sjfv u32 bah; 69270631Sjfv u32 bal; 70270631Sjfv}; 71270631Sjfv 72270631Sjfv/* ASQ transaction details */ 73270631Sjfvstruct i40e_asq_cmd_details { 74270631Sjfv void *callback; /* cast from type I40E_ADMINQ_CALLBACK */ 75270631Sjfv u64 cookie; 76270631Sjfv u16 flags_ena; 77270631Sjfv u16 flags_dis; 78270631Sjfv bool async; 79270631Sjfv bool postpone; 80292100Ssmh struct i40e_aq_desc *wb_desc; 81270631Sjfv}; 82270631Sjfv 83270631Sjfv#define I40E_ADMINQ_DETAILS(R, i) \ 84270631Sjfv (&(((struct i40e_asq_cmd_details *)((R).cmd_buf.va))[i])) 85270631Sjfv 86270631Sjfv/* ARQ event information */ 87270631Sjfvstruct i40e_arq_event_info { 88270631Sjfv struct i40e_aq_desc desc; 89270631Sjfv u16 msg_len; 90270631Sjfv u16 buf_len; 91270631Sjfv u8 *msg_buf; 92270631Sjfv}; 93270631Sjfv 94270631Sjfv/* Admin Queue information */ 95270631Sjfvstruct i40e_adminq_info { 96270631Sjfv struct i40e_adminq_ring arq; /* receive queue */ 97270631Sjfv struct i40e_adminq_ring asq; /* send queue */ 98270631Sjfv u32 asq_cmd_timeout; /* send queue cmd write back timeout*/ 99270631Sjfv u16 num_arq_entries; /* receive queue depth */ 100270631Sjfv u16 num_asq_entries; /* send queue depth */ 101270631Sjfv u16 arq_buf_size; /* receive queue buffer size */ 102270631Sjfv u16 asq_buf_size; /* send queue buffer size */ 103270631Sjfv u16 fw_maj_ver; /* firmware major version */ 104270631Sjfv u16 fw_min_ver; /* firmware minor version */ 105291248Ssmh u32 fw_build; /* firmware build number */ 106270631Sjfv u16 api_maj_ver; /* api major version */ 107270631Sjfv u16 api_min_ver; /* api minor version */ 108270631Sjfv bool nvm_release_on_done; 109270631Sjfv 110270631Sjfv struct i40e_spinlock asq_spinlock; /* Send queue spinlock */ 111270631Sjfv struct i40e_spinlock arq_spinlock; /* Receive queue spinlock */ 112270631Sjfv 113270631Sjfv /* last status values on send and receive queues */ 114270631Sjfv enum i40e_admin_queue_err asq_last_status; 115270631Sjfv enum i40e_admin_queue_err arq_last_status; 116270631Sjfv}; 117270631Sjfv 118270631Sjfv/* general information */ 119270631Sjfv#define I40E_AQ_LARGE_BUF 512 120291248Ssmh#define I40E_ASQ_CMD_TIMEOUT 250 /* msecs */ 121270631Sjfv 122270631Sjfvvoid i40e_fill_default_direct_cmd_desc(struct i40e_aq_desc *desc, 123270631Sjfv u16 opcode); 124270631Sjfv 125270631Sjfv#endif /* _I40E_ADMINQ_H_ */ 126