1315333Serj/****************************************************************************** 2315333Serj 3315333Serj Copyright (c) 2001-2017, Intel Corporation 4315333Serj All rights reserved. 5315333Serj 6315333Serj Redistribution and use in source and binary forms, with or without 7315333Serj modification, are permitted provided that the following conditions are met: 8315333Serj 9315333Serj 1. Redistributions of source code must retain the above copyright notice, 10315333Serj this list of conditions and the following disclaimer. 11315333Serj 12315333Serj 2. Redistributions in binary form must reproduce the above copyright 13315333Serj notice, this list of conditions and the following disclaimer in the 14315333Serj documentation and/or other materials provided with the distribution. 15315333Serj 16315333Serj 3. Neither the name of the Intel Corporation nor the names of its 17315333Serj contributors may be used to endorse or promote products derived from 18315333Serj this software without specific prior written permission. 19315333Serj 20315333Serj THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21315333Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22315333Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23315333Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24315333Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25315333Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26315333Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27315333Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28315333Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29315333Serj ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30315333Serj POSSIBILITY OF SUCH DAMAGE. 31315333Serj 32315333Serj******************************************************************************/ 33315333Serj/*$FreeBSD: stable/10/sys/dev/ixgbe/ixv.h 315434 2017-03-16 23:18:57Z erj $*/ 34315333Serj 35315333Serj 36315333Serj#ifndef _IXGBE_H_ 37315333Serj#define _IXGBE_H_ 38315333Serj 39315333Serj 40315333Serj#include <sys/param.h> 41315333Serj#include <sys/systm.h> 42315333Serj#include <sys/buf_ring.h> 43315333Serj#include <sys/mbuf.h> 44315333Serj#include <sys/protosw.h> 45315333Serj#include <sys/socket.h> 46315333Serj#include <sys/malloc.h> 47315333Serj#include <sys/kernel.h> 48315333Serj#include <sys/module.h> 49315333Serj#include <sys/sockio.h> 50315333Serj#include <sys/eventhandler.h> 51315333Serj 52315333Serj#include <net/if.h> 53315333Serj#include <net/if_var.h> 54315333Serj#include <net/if_arp.h> 55315333Serj#include <net/bpf.h> 56315333Serj#include <net/ethernet.h> 57315333Serj#include <net/if_dl.h> 58315333Serj#include <net/if_media.h> 59315333Serj 60315333Serj#include <net/bpf.h> 61315333Serj#include <net/if_types.h> 62315333Serj#include <net/if_vlan_var.h> 63315333Serj 64315333Serj#include <netinet/in_systm.h> 65315333Serj#include <netinet/in.h> 66315333Serj#include <netinet/if_ether.h> 67315333Serj#include <netinet/ip.h> 68315333Serj#include <netinet/ip6.h> 69315333Serj#include <netinet/tcp.h> 70315333Serj#include <netinet/tcp_lro.h> 71315333Serj#include <netinet/udp.h> 72315333Serj 73315333Serj#include <machine/in_cksum.h> 74315333Serj 75315333Serj#include <sys/bus.h> 76315333Serj#include <machine/bus.h> 77315333Serj#include <sys/rman.h> 78315333Serj#include <machine/resource.h> 79315333Serj#include <vm/vm.h> 80315333Serj#include <vm/pmap.h> 81315333Serj#include <machine/clock.h> 82315333Serj#include <dev/pci/pcivar.h> 83315333Serj#include <dev/pci/pcireg.h> 84315333Serj#include <sys/proc.h> 85315333Serj#include <sys/sysctl.h> 86315333Serj#include <sys/endian.h> 87315333Serj#include <sys/taskqueue.h> 88315333Serj#include <sys/pcpu.h> 89315333Serj#include <sys/smp.h> 90315333Serj#include <machine/smp.h> 91315333Serj#include <sys/sbuf.h> 92315333Serj 93315333Serj#include "ixv_features.h" 94315333Serj#include "ixv_vf.h" 95315333Serj 96315333Serj/* Tunables */ 97315333Serj 98315333Serj/* 99315333Serj * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 100315333Serj * number of transmit descriptors allocated by the driver. Increasing this 101315333Serj * value allows the driver to queue more transmits. Each descriptor is 16 102315333Serj * bytes. Performance tests have show the 2K value to be optimal for top 103315333Serj * performance. 104315333Serj */ 105315333Serj#define DEFAULT_TXD 1024 106315333Serj#define PERFORM_TXD 2048 107315333Serj#define MAX_TXD 4096 108315333Serj#define MIN_TXD 64 109315333Serj 110315333Serj/* 111315333Serj * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 112315333Serj * number of receive descriptors allocated for each RX queue. Increasing this 113315333Serj * value allows the driver to buffer more incoming packets. Each descriptor 114315333Serj * is 16 bytes. A receive buffer is also allocated for each descriptor. 115315333Serj * 116315333Serj * Note: with 8 rings and a dual port card, it is possible to bump up 117315333Serj * against the system mbuf pool limit, you can tune nmbclusters 118315333Serj * to adjust for this. 119315333Serj */ 120315333Serj#define DEFAULT_RXD 1024 121315333Serj#define PERFORM_RXD 2048 122315333Serj#define MAX_RXD 4096 123315333Serj#define MIN_RXD 64 124315333Serj 125315333Serj/* Alignment for rings */ 126315333Serj#define DBA_ALIGN 128 127315333Serj 128315333Serj/* 129315333Serj * This is the max watchdog interval, ie. the time that can 130315333Serj * pass between any two TX clean operations, such only happening 131315333Serj * when the TX hardware is functioning. 132315333Serj */ 133315333Serj#define IXGBE_WATCHDOG (10 * hz) 134315333Serj 135315333Serj/* 136315333Serj * This parameters control when the driver calls the routine to reclaim 137315333Serj * transmit descriptors. 138315333Serj */ 139315333Serj#define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8) 140315333Serj#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) 141315333Serj 142315333Serj/* These defines are used in MTU calculations */ 143315333Serj#define IXGBE_MAX_FRAME_SIZE 9728 144315333Serj#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 145315333Serj#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 146315333Serj ETHER_VLAN_ENCAP_LEN) 147315333Serj#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 148315333Serj#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 149315333Serj 150315333Serj/* Flow control constants */ 151315333Serj#define IXGBE_FC_PAUSE 0xFFFF 152315333Serj#define IXGBE_FC_HI 0x20000 153315333Serj#define IXGBE_FC_LO 0x10000 154315333Serj 155315333Serj/* 156315333Serj * Used for optimizing small rx mbufs. Effort is made to keep the copy 157315333Serj * small and aligned for the CPU L1 cache. 158315333Serj * 159315333Serj * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 160315333Serj * 32 byte alignment needed for the fast bcopy results in 8 bytes being 161315333Serj * wasted. Getting 64 byte alignment, which _should_ be ideal for 162315333Serj * modern Intel CPUs, results in 40 bytes wasted and a significant drop 163315333Serj * in observed efficiency of the optimization, 97.9% -> 81.8%. 164315333Serj */ 165315333Serj#if __FreeBSD_version < 1002000 166315333Serj#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 167315333Serj#endif 168315333Serj#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 169315333Serj#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 170315333Serj#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 171315333Serj 172315333Serj/* Keep older OS drivers building... */ 173315333Serj#if !defined(SYSCTL_ADD_UQUAD) 174315333Serj#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 175315333Serj#endif 176315333Serj 177315333Serj/* Defines for printing debug information */ 178315333Serj#define DEBUG_INIT 0 179315333Serj#define DEBUG_IOCTL 0 180315333Serj#define DEBUG_HW 0 181315333Serj 182315333Serj#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 183315333Serj#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 184315333Serj#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 185315333Serj#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 186315333Serj#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 187315333Serj#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 188315333Serj#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 189315333Serj#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 190315333Serj#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 191315333Serj 192315333Serj#define MAX_NUM_MULTICAST_ADDRESSES 128 193315333Serj#define IXGBE_82598_SCATTER 100 194315333Serj#define IXGBE_82599_SCATTER 32 195315333Serj#define MSIX_82598_BAR 3 196315333Serj#define MSIX_82599_BAR 4 197315333Serj#define IXGBE_TSO_SIZE 262140 198315333Serj#define IXGBE_RX_HDR 128 199315333Serj#define IXGBE_VFTA_SIZE 128 200315333Serj#define IXGBE_BR_SIZE 4096 201315333Serj#define IXGBE_QUEUE_MIN_FREE 32 202315333Serj#define IXGBE_MAX_TX_BUSY 10 203315333Serj#define IXGBE_QUEUE_HUNG 0x80000000 204315333Serj 205315333Serj#define IXGBE_EITR_DEFAULT 128 206315333Serj 207315333Serj/* Supported offload bits in mbuf flag */ 208315333Serj#if __FreeBSD_version >= 1000000 209315333Serj#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 210315333Serj CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 211315333Serj CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 212315333Serj#elif __FreeBSD_version >= 800000 213315333Serj#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 214315333Serj#else 215315333Serj#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 216315333Serj#endif 217315333Serj 218315333Serj/* Backward compatibility items for very old versions */ 219315333Serj#ifndef pci_find_cap 220315333Serj#define pci_find_cap pci_find_extcap 221315333Serj#endif 222315333Serj 223315333Serj#ifndef DEVMETHOD_END 224315333Serj#define DEVMETHOD_END { NULL, NULL } 225315333Serj#endif 226315333Serj 227315333Serj/* 228315333Serj * Interrupt Moderation parameters 229315333Serj */ 230315333Serj#define IXGBE_LOW_LATENCY 128 231315333Serj#define IXGBE_AVE_LATENCY 400 232315333Serj#define IXGBE_BULK_LATENCY 1200 233315333Serj 234315333Serj/* Using 1FF (the max value), the interval is ~1.05ms */ 235315333Serj#define IXGBE_LINK_ITR_QUANTA 0x1FF 236315333Serj#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 237315333Serj IXGBE_EITR_ITR_INT_MASK) 238315333Serj 239315333Serj/* MAC type macros */ 240315333Serj#define IXGBE_IS_X550VF(_adapter) \ 241315333Serj ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ 242315333Serj (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf) || \ 243315333Serj (_adapter->hw.mac.type == ixgbe_mac_X550EM_a_vf)) 244315333Serj 245315333Serj#define IXGBE_IS_VF(_x) 1 246315333Serj 247315333Serj 248315333Serj/************************************************************************ 249315333Serj * vendor_info_array 250315333Serj * 251315333Serj * This array contains the list of Subvendor/Subdevice IDs on 252315333Serj * which the driver should load. 253315333Serj ************************************************************************/ 254315333Serjtypedef struct _ixgbe_vendor_info_t { 255315333Serj unsigned int vendor_id; 256315333Serj unsigned int device_id; 257315333Serj unsigned int subvendor_id; 258315333Serj unsigned int subdevice_id; 259315333Serj unsigned int index; 260315333Serj} ixgbe_vendor_info_t; 261315333Serj 262315333Serjstruct ixgbe_bp_data { 263315333Serj u32 low; 264315333Serj u32 high; 265315333Serj u32 log; 266315333Serj}; 267315333Serj 268315333Serjstruct ixgbe_tx_buf { 269315333Serj union ixgbe_adv_tx_desc *eop; 270315333Serj struct mbuf *m_head; 271315333Serj bus_dmamap_t map; 272315333Serj}; 273315333Serj 274315333Serjstruct ixgbe_rx_buf { 275315333Serj struct mbuf *buf; 276315333Serj struct mbuf *fmp; 277315333Serj bus_dmamap_t pmap; 278315333Serj u_int flags; 279315333Serj#define IXGBE_RX_COPY 0x01 280315333Serj uint64_t addr; 281315333Serj}; 282315333Serj 283315333Serj/* 284315333Serj * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free 285315333Serj */ 286315333Serjstruct ixgbe_dma_alloc { 287315333Serj bus_addr_t dma_paddr; 288315333Serj caddr_t dma_vaddr; 289315333Serj bus_dma_tag_t dma_tag; 290315333Serj bus_dmamap_t dma_map; 291315333Serj bus_dma_segment_t dma_seg; 292315333Serj bus_size_t dma_size; 293315333Serj int dma_nseg; 294315333Serj}; 295315333Serj 296315333Serjstruct ixgbe_mc_addr { 297315333Serj u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 298315333Serj u32 vmdq; 299315333Serj}; 300315333Serj 301315333Serj/* 302315333Serj * Driver queue struct: this is the interrupt container 303315333Serj * for the associated tx and rx ring. 304315333Serj */ 305315333Serjstruct ix_queue { 306315333Serj struct adapter *adapter; 307315333Serj u32 msix; /* This queue's MSI-X vector */ 308315333Serj u32 eims; /* This queue's EIMS bit */ 309315333Serj u32 eitr_setting; 310315333Serj u32 me; 311315333Serj struct resource *res; 312315333Serj void *tag; 313315333Serj int busy; 314315333Serj struct tx_ring *txr; 315315333Serj struct rx_ring *rxr; 316315333Serj struct task que_task; 317315333Serj struct taskqueue *tq; 318315333Serj u64 irqs; 319315333Serj}; 320315333Serj 321315333Serj/* 322315333Serj * The transmit ring, one per queue 323315333Serj */ 324315333Serjstruct tx_ring { 325315333Serj struct adapter *adapter; 326315333Serj struct mtx tx_mtx; 327315333Serj u32 me; 328315333Serj u32 tail; 329315333Serj int busy; 330315333Serj union ixgbe_adv_tx_desc *tx_base; 331315333Serj struct ixgbe_tx_buf *tx_buffers; 332315333Serj struct ixgbe_dma_alloc txdma; 333315333Serj volatile u16 tx_avail; 334315333Serj u16 next_avail_desc; 335315333Serj u16 next_to_clean; 336315333Serj u16 num_desc; 337315333Serj u32 txd_cmd; 338315333Serj bus_dma_tag_t txtag; 339315333Serj char mtx_name[16]; 340315333Serj struct buf_ring *br; 341315333Serj struct task txq_task; 342315333Serj 343315333Serj /* Flow Director */ 344315333Serj u16 atr_sample; 345315333Serj u16 atr_count; 346315333Serj 347315333Serj u32 bytes; /* used for AIM */ 348315333Serj u32 packets; 349315333Serj /* Soft Stats */ 350315434Serj u64 tso_tx; 351315434Serj u64 no_tx_map_avail; 352315434Serj u64 no_tx_dma_setup; 353315333Serj u64 no_desc_avail; 354315333Serj u64 total_packets; 355315333Serj}; 356315333Serj 357315333Serj 358315333Serj/* 359315333Serj * The Receive ring, one per rx queue 360315333Serj */ 361315333Serjstruct rx_ring { 362315333Serj struct adapter *adapter; 363315333Serj struct mtx rx_mtx; 364315333Serj u32 me; 365315333Serj u32 tail; 366315333Serj union ixgbe_adv_rx_desc *rx_base; 367315333Serj struct ixgbe_dma_alloc rxdma; 368315333Serj struct lro_ctrl lro; 369315333Serj bool lro_enabled; 370315333Serj bool hw_rsc; 371315333Serj bool vtag_strip; 372315333Serj u16 next_to_refresh; 373315333Serj u16 next_to_check; 374315333Serj u16 num_desc; 375315333Serj u16 mbuf_sz; 376315333Serj char mtx_name[16]; 377315333Serj struct ixgbe_rx_buf *rx_buffers; 378315333Serj bus_dma_tag_t ptag; 379315333Serj 380315333Serj u32 bytes; /* Used for AIM calc */ 381315333Serj u32 packets; 382315333Serj 383315333Serj /* Soft stats */ 384315333Serj u64 rx_irq; 385315333Serj u64 rx_copies; 386315333Serj u64 rx_packets; 387315333Serj u64 rx_bytes; 388315333Serj u64 rx_discarded; 389315333Serj u64 rsc_num; 390315333Serj 391315333Serj /* Flow Director */ 392315333Serj u64 flm; 393315333Serj}; 394315333Serj 395315333Serj#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 396315333Serj 397315333Serjstruct ixgbe_vf { 398315333Serj u_int pool; 399315333Serj u_int rar_index; 400315333Serj u_int max_frame_size; 401315333Serj uint32_t flags; 402315333Serj uint8_t ether_addr[ETHER_ADDR_LEN]; 403315333Serj uint16_t mc_hash[IXGBE_MAX_VF_MC]; 404315333Serj uint16_t num_mc_hashes; 405315333Serj uint16_t default_vlan; 406315333Serj uint16_t vlan_tag; 407315333Serj uint16_t api_ver; 408315333Serj}; 409315333Serj 410315333Serj/* Our adapter structure */ 411315333Serjstruct adapter { 412315333Serj struct ixgbe_hw hw; 413315333Serj struct ixgbe_osdep osdep; 414315333Serj 415315333Serj struct device *dev; 416315333Serj struct ifnet *ifp; 417315333Serj 418315333Serj struct resource *pci_mem; 419315333Serj struct resource *msix_mem; 420315333Serj 421315333Serj /* 422315333Serj * Interrupt resources: this set is 423315333Serj * either used for legacy, or for Link 424315333Serj * when doing MSI-X 425315333Serj */ 426315333Serj void *tag; 427315333Serj struct resource *res; 428315333Serj 429315333Serj struct ifmedia media; 430315333Serj struct callout timer; 431315333Serj int link_rid; 432315333Serj int if_flags; 433315333Serj 434315333Serj struct mtx core_mtx; 435315333Serj 436315333Serj eventhandler_tag vlan_attach; 437315333Serj eventhandler_tag vlan_detach; 438315333Serj 439315333Serj u16 num_vlans; 440315333Serj u16 num_queues; 441315333Serj 442315333Serj /* 443315333Serj * Shadow VFTA table, this is needed because 444315333Serj * the real vlan filter table gets cleared during 445315333Serj * a soft reset and the driver needs to be able 446315333Serj * to repopulate it. 447315333Serj */ 448315333Serj u32 shadow_vfta[IXGBE_VFTA_SIZE]; 449315333Serj 450315333Serj /* Info about the interface */ 451315333Serj int advertise; /* link speeds */ 452315333Serj bool enable_aim; /* adaptive interrupt moderation */ 453315333Serj bool link_active; 454315333Serj u16 max_frame_size; 455315333Serj u16 num_segs; 456315333Serj u32 link_speed; 457315333Serj bool link_up; 458315333Serj u32 vector; 459315333Serj u16 dmac; 460315333Serj u32 phy_layer; 461315333Serj 462315333Serj /* Power management-related */ 463315333Serj bool wol_support; 464315333Serj u32 wufc; 465315333Serj 466315333Serj /* Mbuf cluster size */ 467315333Serj u32 rx_mbuf_sz; 468315333Serj 469315333Serj /* Support for pluggable optics */ 470315333Serj bool sfp_probe; 471315333Serj struct task link_task; /* Link tasklet */ 472315333Serj struct task mod_task; /* SFP tasklet */ 473315333Serj struct task msf_task; /* Multispeed Fiber */ 474315333Serj struct task mbx_task; /* VF -> PF mailbox interrupt */ 475315333Serj 476315333Serj /* Flow Director */ 477315333Serj int fdir_reinit; 478315333Serj struct task fdir_task; 479315333Serj 480315333Serj struct task phy_task; /* PHY intr tasklet */ 481315333Serj struct taskqueue *tq; 482315333Serj 483315333Serj /* 484315333Serj * Queues: 485315333Serj * This is the irq holder, it has 486315333Serj * and RX/TX pair or rings associated 487315333Serj * with it. 488315333Serj */ 489315333Serj struct ix_queue *queues; 490315333Serj 491315333Serj /* 492315333Serj * Transmit rings 493315333Serj * Allocated at run time, an array of rings 494315333Serj */ 495315333Serj struct tx_ring *tx_rings; 496315333Serj u32 num_tx_desc; 497315333Serj u32 tx_process_limit; 498315333Serj 499315333Serj /* 500315333Serj * Receive rings 501315333Serj * Allocated at run time, an array of rings 502315333Serj */ 503315333Serj struct rx_ring *rx_rings; 504315333Serj u64 active_queues; 505315333Serj u32 num_rx_desc; 506315333Serj u32 rx_process_limit; 507315333Serj 508315333Serj /* Multicast array memory */ 509315333Serj struct ixgbe_mc_addr *mta; 510315333Serj 511315333Serj /* SR-IOV */ 512315333Serj int iov_mode; 513315333Serj int num_vfs; 514315333Serj int pool; 515315333Serj struct ixgbe_vf *vfs; 516315333Serj 517315333Serj /* Bypass */ 518315333Serj struct ixgbe_bp_data bypass; 519315333Serj 520315333Serj /* Netmap */ 521315333Serj void (*init_locked)(struct adapter *); 522315333Serj void (*stop_locked)(void *); 523315333Serj 524315333Serj /* Misc stats maintained by the driver */ 525315333Serj unsigned long dropped_pkts; 526315333Serj unsigned long mbuf_defrag_failed; 527315333Serj unsigned long mbuf_header_failed; 528315333Serj unsigned long mbuf_packet_failed; 529315333Serj unsigned long watchdog_events; 530315333Serj unsigned long link_irq; 531315333Serj struct ixgbevf_hw_stats stats_vf; 532315333Serj#if __FreeBSD_version >= 1100036 533315333Serj /* counter(9) stats */ 534315333Serj u64 ipackets; 535315333Serj u64 ierrors; 536315333Serj u64 opackets; 537315333Serj u64 oerrors; 538315333Serj u64 ibytes; 539315333Serj u64 obytes; 540315333Serj u64 imcasts; 541315333Serj u64 omcasts; 542315333Serj u64 iqdrops; 543315333Serj u64 noproto; 544315333Serj#endif 545315333Serj /* Feature capable/enabled flags. See ixgbe_features.h */ 546315333Serj u32 feat_cap; 547315333Serj u32 feat_en; 548315333Serj}; 549315333Serj 550315333Serj 551315333Serj/* Precision Time Sync (IEEE 1588) defines */ 552315333Serj#define ETHERTYPE_IEEE1588 0x88F7 553315333Serj#define PICOSECS_PER_TICK 20833 554315333Serj#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 555315333Serj#define IXGBE_ADVTXD_TSTAMP 0x00080000 556315333Serj 557315333Serj 558315333Serj#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 559315333Serj mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 560315333Serj#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 561315333Serj#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 562315333Serj#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 563315333Serj#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 564315333Serj#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 565315333Serj#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 566315333Serj#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 567315333Serj#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 568315333Serj#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 569315333Serj#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 570315333Serj#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 571315333Serj#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 572315333Serj 573315333Serj/* For backward compatibility */ 574315333Serj#if !defined(PCIER_LINK_STA) 575315333Serj#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 576315333Serj#endif 577315333Serj 578315333Serj/* Stats macros */ 579315333Serj#if __FreeBSD_version >= 1100036 580315333Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 581315333Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 582315333Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 583315333Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 584315333Serj#define IXGBE_SET_COLLISIONS(sc, count) 585315333Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 586315333Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 587315333Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 588315333Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 589315333Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 590315333Serj#else 591315333Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 592315333Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 593315333Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 594315333Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 595315333Serj#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 596315333Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 597315333Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 598315333Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 599315333Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 600315333Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 601315333Serj#endif 602315333Serj 603315333Serj/* External PHY register addresses */ 604315333Serj#define IXGBE_PHY_CURRENT_TEMP 0xC820 605315333Serj#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 606315333Serj 607315333Serj/* Sysctl help messages; displayed with sysctl -d */ 608315333Serj#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 609315333Serj "\nControl advertised link speed using these flags:\n" \ 610315333Serj "\t0x1 - advertise 100M\n" \ 611315333Serj "\t0x2 - advertise 1G\n" \ 612315333Serj "\t0x4 - advertise 10G\n" \ 613315333Serj "\t0x8 - advertise 10M\n\n" \ 614315333Serj "\t100M and 10M are only supported on certain adapters.\n" 615315333Serj 616315333Serj#define IXGBE_SYSCTL_DESC_SET_FC \ 617315333Serj "\nSet flow control mode using these values:\n" \ 618315333Serj "\t0 - off\n" \ 619315333Serj "\t1 - rx pause\n" \ 620315333Serj "\t2 - tx pause\n" \ 621315333Serj "\t3 - tx and rx pause" 622315333Serj 623315333Serj/* Workaround to make 8.0 buildable */ 624315333Serj#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 625315333Serjstatic __inline int 626315333Serjdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 627315333Serj{ 628315333Serj#ifdef ALTQ 629315333Serj if (ALTQ_IS_ENABLED(&ifp->if_snd)) 630315333Serj return (1); 631315333Serj#endif 632315333Serj return (!buf_ring_empty(br)); 633315333Serj} 634315333Serj#endif 635315333Serj 636315333Serj/* 637315333Serj * Find the number of unrefreshed RX descriptors 638315333Serj */ 639315333Serjstatic inline u16 640315333Serjixgbe_rx_unrefreshed(struct rx_ring *rxr) 641315333Serj{ 642315333Serj if (rxr->next_to_check > rxr->next_to_refresh) 643315333Serj return (rxr->next_to_check - rxr->next_to_refresh - 1); 644315333Serj else 645315333Serj return ((rxr->num_desc + rxr->next_to_check) - 646315333Serj rxr->next_to_refresh - 1); 647315333Serj} 648315333Serj 649315333Serjstatic inline int 650315333Serjixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy) 651315333Serj{ 652315333Serj UNREFERENCED_1PARAMETER(dummy); 653315333Serj 654315333Serj return IFQ_DRV_IS_EMPTY(&ifp->if_snd); 655315333Serj} 656315333Serj 657315333Serj/* 658315333Serj * This checks for a zero mac addr, something that will be likely 659315333Serj * unless the Admin on the Host has created one. 660315333Serj */ 661315333Serjstatic inline bool 662315333Serjixv_check_ether_addr(u8 *addr) 663315333Serj{ 664315333Serj bool status = TRUE; 665315333Serj 666315333Serj if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 667315333Serj addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 668315333Serj status = FALSE; 669315333Serj 670315333Serj return (status); 671315333Serj} 672315333Serj 673315333Serj/* Shared Prototypes */ 674315333Serjvoid ixv_legacy_start(struct ifnet *); 675315333Serjint ixv_legacy_start_locked(struct ifnet *, struct tx_ring *); 676315333Serjint ixv_mq_start(struct ifnet *, struct mbuf *); 677315333Serjint ixv_mq_start_locked(struct ifnet *, struct tx_ring *); 678315333Serjvoid ixv_qflush(struct ifnet *); 679315333Serjvoid ixv_deferred_mq_start(void *, int); 680315333Serjvoid ixv_init_locked(struct adapter *); 681315333Serj 682315333Serjint ixv_allocate_queues(struct adapter *); 683315333Serjint ixv_setup_transmit_structures(struct adapter *); 684315333Serjvoid ixv_free_transmit_structures(struct adapter *); 685315333Serjint ixv_setup_receive_structures(struct adapter *); 686315333Serjvoid ixv_free_receive_structures(struct adapter *); 687315333Serjvoid ixv_txeof(struct tx_ring *); 688315333Serjbool ixv_rxeof(struct ix_queue *); 689315333Serj 690315333Serj#include "ixv_rss.h" 691315333Serj#include "ixv_netmap.h" 692315333Serj 693315333Serj#endif /* _IXGBE_H_ */ 694