ixgbe_x550.c revision 283620
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_x550.c 283620 2015-05-27 17:44:11Z erj $*/ 34 35#include "ixgbe_x550.h" 36#include "ixgbe_x540.h" 37#include "ixgbe_type.h" 38#include "ixgbe_api.h" 39#include "ixgbe_common.h" 40#include "ixgbe_phy.h" 41 42static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed); 43 44/** 45 * ixgbe_init_ops_X550 - Inits func ptrs and MAC type 46 * @hw: pointer to hardware structure 47 * 48 * Initialize the function pointers and assign the MAC type for X550. 49 * Does not touch the hardware. 50 **/ 51s32 ixgbe_init_ops_X550(struct ixgbe_hw *hw) 52{ 53 struct ixgbe_mac_info *mac = &hw->mac; 54 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 55 s32 ret_val; 56 57 DEBUGFUNC("ixgbe_init_ops_X550"); 58 59 ret_val = ixgbe_init_ops_X540(hw); 60 mac->ops.dmac_config = ixgbe_dmac_config_X550; 61 mac->ops.dmac_config_tcs = ixgbe_dmac_config_tcs_X550; 62 mac->ops.dmac_update_tcs = ixgbe_dmac_update_tcs_X550; 63 mac->ops.setup_eee = ixgbe_setup_eee_X550; 64 mac->ops.set_source_address_pruning = 65 ixgbe_set_source_address_pruning_X550; 66 mac->ops.set_ethertype_anti_spoofing = 67 ixgbe_set_ethertype_anti_spoofing_X550; 68 69 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 70 eeprom->ops.init_params = ixgbe_init_eeprom_params_X550; 71 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 72 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 73 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 74 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 75 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 76 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 77 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 78 79 mac->ops.disable_mdd = ixgbe_disable_mdd_X550; 80 mac->ops.enable_mdd = ixgbe_enable_mdd_X550; 81 mac->ops.mdd_event = ixgbe_mdd_event_X550; 82 mac->ops.restore_mdd_vf = ixgbe_restore_mdd_vf_X550; 83 mac->ops.disable_rx = ixgbe_disable_rx_x550; 84 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 85 hw->mac.ops.led_on = ixgbe_led_on_t_X550em; 86 hw->mac.ops.led_off = ixgbe_led_off_t_X550em; 87 } 88 return ret_val; 89} 90 91/** 92 * ixgbe_read_cs4227 - Read CS4227 register 93 * @hw: pointer to hardware structure 94 * @reg: register number to write 95 * @value: pointer to receive value read 96 * 97 * Returns status code 98 **/ 99static s32 ixgbe_read_cs4227(struct ixgbe_hw *hw, u16 reg, u16 *value) 100{ 101 return ixgbe_read_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 102} 103 104/** 105 * ixgbe_write_cs4227 - Write CS4227 register 106 * @hw: pointer to hardware structure 107 * @reg: register number to write 108 * @value: value to write to register 109 * 110 * Returns status code 111 **/ 112static s32 ixgbe_write_cs4227(struct ixgbe_hw *hw, u16 reg, u16 value) 113{ 114 return ixgbe_write_i2c_combined_unlocked(hw, IXGBE_CS4227, reg, value); 115} 116 117/** 118 * ixgbe_get_cs4227_status - Return CS4227 status 119 * @hw: pointer to hardware structure 120 * 121 * Returns error if CS4227 not successfully initialized 122 **/ 123static s32 ixgbe_get_cs4227_status(struct ixgbe_hw *hw) 124{ 125 s32 status; 126 u16 value = 0; 127 u16 reg_slice, reg_val; 128 u8 retry; 129 130 for (retry = 0; retry < IXGBE_CS4227_RETRIES; ++retry) { 131 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_GLOBAL_ID_LSB, 132 &value); 133 if (status != IXGBE_SUCCESS) 134 return status; 135 if (value == IXGBE_CS4227_GLOBAL_ID_VALUE) 136 break; 137 msec_delay(IXGBE_CS4227_CHECK_DELAY); 138 } 139 if (value != IXGBE_CS4227_GLOBAL_ID_VALUE) 140 return IXGBE_ERR_PHY; 141 142 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 143 if (status != IXGBE_SUCCESS) 144 return status; 145 146 /* If this is the first time after power-on, check the ucode. 147 * Otherwise, this will disrupt link on all ports. Because we 148 * can only do this the first time, we must check all ports, 149 * not just our own. 150 */ 151 if (value != IXGBE_CS4227_SCRATCH_VALUE) { 152 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; 153 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 154 status = ixgbe_write_cs4227(hw, reg_slice, 155 reg_val); 156 if (status != IXGBE_SUCCESS) 157 return status; 158 159 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; 160 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 161 status = ixgbe_write_cs4227(hw, reg_slice, 162 reg_val); 163 if (status != IXGBE_SUCCESS) 164 return status; 165 166 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); 167 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 168 status = ixgbe_write_cs4227(hw, reg_slice, 169 reg_val); 170 if (status != IXGBE_SUCCESS) 171 return status; 172 173 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); 174 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 175 status = ixgbe_write_cs4227(hw, reg_slice, 176 reg_val); 177 if (status != IXGBE_SUCCESS) 178 return status; 179 180 msec_delay(10); 181 } 182 183 /* Verify that the ucode is operational on all ports. */ 184 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB; 185 reg_val = 0xFFFF; 186 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 187 if (status != IXGBE_SUCCESS) 188 return status; 189 if (reg_val != 0) 190 return IXGBE_ERR_PHY; 191 192 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB; 193 reg_val = 0xFFFF; 194 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 195 if (status != IXGBE_SUCCESS) 196 return status; 197 if (reg_val != 0) 198 return IXGBE_ERR_PHY; 199 200 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (1 << 12); 201 reg_val = 0xFFFF; 202 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 203 if (status != IXGBE_SUCCESS) 204 return status; 205 if (reg_val != 0) 206 return IXGBE_ERR_PHY; 207 208 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (1 << 12); 209 reg_val = 0xFFFF; 210 status = ixgbe_read_cs4227(hw, reg_slice, ®_val); 211 if (status != IXGBE_SUCCESS) 212 return status; 213 if (reg_val != 0) 214 return IXGBE_ERR_PHY; 215 216 /* Set scratch for next time. */ 217 status = ixgbe_write_cs4227(hw, IXGBE_CS4227_SCRATCH, 218 IXGBE_CS4227_SCRATCH_VALUE); 219 if (status != IXGBE_SUCCESS) 220 return status; 221 status = ixgbe_read_cs4227(hw, IXGBE_CS4227_SCRATCH, &value); 222 if (status != IXGBE_SUCCESS) 223 return status; 224 if (value != IXGBE_CS4227_SCRATCH_VALUE) 225 return IXGBE_ERR_PHY; 226 227 return IXGBE_SUCCESS; 228} 229 230/** 231 * ixgbe_read_pe - Read register from port expander 232 * @hw: pointer to hardware structure 233 * @reg: register number to read 234 * @value: pointer to receive read value 235 * 236 * Returns status code 237 **/ 238static s32 ixgbe_read_pe(struct ixgbe_hw *hw, u8 reg, u8 *value) 239{ 240 s32 status; 241 242 status = ixgbe_read_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 243 if (status != IXGBE_SUCCESS) 244 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 245 "port expander access failed with %d\n", status); 246 return status; 247} 248 249/** 250 * ixgbe_write_pe - Write register to port expander 251 * @hw: pointer to hardware structure 252 * @reg: register number to write 253 * @value: value to write 254 * 255 * Returns status code 256 **/ 257static s32 ixgbe_write_pe(struct ixgbe_hw *hw, u8 reg, u8 value) 258{ 259 s32 status; 260 261 status = ixgbe_write_i2c_byte_unlocked(hw, reg, IXGBE_PE, value); 262 if (status != IXGBE_SUCCESS) 263 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 264 "port expander access failed with %d\n", status); 265 return status; 266} 267 268/** 269 * ixgbe_reset_cs4227 - Reset CS4227 using port expander 270 * @hw: pointer to hardware structure 271 * 272 * Returns error code 273 **/ 274static s32 ixgbe_reset_cs4227(struct ixgbe_hw *hw) 275{ 276 s32 status; 277 u8 reg; 278 279 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 280 if (status != IXGBE_SUCCESS) 281 return status; 282 reg |= IXGBE_PE_BIT1; 283 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 284 if (status != IXGBE_SUCCESS) 285 return status; 286 287 status = ixgbe_read_pe(hw, IXGBE_PE_CONFIG, ®); 288 if (status != IXGBE_SUCCESS) 289 return status; 290 reg &= ~IXGBE_PE_BIT1; 291 status = ixgbe_write_pe(hw, IXGBE_PE_CONFIG, reg); 292 if (status != IXGBE_SUCCESS) 293 return status; 294 295 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 296 if (status != IXGBE_SUCCESS) 297 return status; 298 reg &= ~IXGBE_PE_BIT1; 299 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 300 if (status != IXGBE_SUCCESS) 301 return status; 302 303 usec_delay(IXGBE_CS4227_RESET_HOLD); 304 305 status = ixgbe_read_pe(hw, IXGBE_PE_OUTPUT, ®); 306 if (status != IXGBE_SUCCESS) 307 return status; 308 reg |= IXGBE_PE_BIT1; 309 status = ixgbe_write_pe(hw, IXGBE_PE_OUTPUT, reg); 310 if (status != IXGBE_SUCCESS) 311 return status; 312 313 msec_delay(IXGBE_CS4227_RESET_DELAY); 314 315 return IXGBE_SUCCESS; 316} 317 318/** 319 * ixgbe_check_cs4227 - Check CS4227 and reset as needed 320 * @hw: pointer to hardware structure 321 **/ 322static void ixgbe_check_cs4227(struct ixgbe_hw *hw) 323{ 324 u32 swfw_mask = hw->phy.phy_semaphore_mask; 325 s32 status; 326 u8 retry; 327 328 for (retry = 0; retry < IXGBE_CS4227_RETRIES; retry++) { 329 status = hw->mac.ops.acquire_swfw_sync(hw, swfw_mask); 330 if (status != IXGBE_SUCCESS) { 331 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 332 "semaphore failed with %d\n", status); 333 return; 334 } 335 status = ixgbe_get_cs4227_status(hw); 336 if (status == IXGBE_SUCCESS) { 337 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 338 msec_delay(hw->eeprom.semaphore_delay); 339 return; 340 } 341 ixgbe_reset_cs4227(hw); 342 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 343 msec_delay(hw->eeprom.semaphore_delay); 344 } 345 ERROR_REPORT2(IXGBE_ERROR_CAUTION, 346 "Unable to initialize CS4227, err=%d\n", status); 347} 348 349/** 350 * ixgbe_setup_mux_ctl - Setup ESDP register for I2C mux control 351 * @hw: pointer to hardware structure 352 **/ 353static void ixgbe_setup_mux_ctl(struct ixgbe_hw *hw) 354{ 355 u32 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 356 357 if (hw->bus.lan_id) { 358 esdp &= ~(IXGBE_ESDP_SDP1_NATIVE | IXGBE_ESDP_SDP1); 359 esdp |= IXGBE_ESDP_SDP1_DIR; 360 } 361 esdp &= ~(IXGBE_ESDP_SDP0_NATIVE | IXGBE_ESDP_SDP0_DIR); 362 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 363 IXGBE_WRITE_FLUSH(hw); 364} 365 366/** 367 * ixgbe_identify_phy_x550em - Get PHY type based on device id 368 * @hw: pointer to hardware structure 369 * 370 * Returns error code 371 */ 372static s32 ixgbe_identify_phy_x550em(struct ixgbe_hw *hw) 373{ 374 switch (hw->device_id) { 375 case IXGBE_DEV_ID_X550EM_X_SFP: 376 /* set up for CS4227 usage */ 377 hw->phy.phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 378 ixgbe_setup_mux_ctl(hw); 379 ixgbe_check_cs4227(hw); 380 381 return ixgbe_identify_module_generic(hw); 382 break; 383 case IXGBE_DEV_ID_X550EM_X_KX4: 384 hw->phy.type = ixgbe_phy_x550em_kx4; 385 break; 386 case IXGBE_DEV_ID_X550EM_X_KR: 387 hw->phy.type = ixgbe_phy_x550em_kr; 388 break; 389 case IXGBE_DEV_ID_X550EM_X_1G_T: 390 case IXGBE_DEV_ID_X550EM_X_10G_T: 391 return ixgbe_identify_phy_generic(hw); 392 default: 393 break; 394 } 395 return IXGBE_SUCCESS; 396} 397 398static s32 ixgbe_read_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 399 u32 device_type, u16 *phy_data) 400{ 401 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, *phy_data); 402 return IXGBE_NOT_IMPLEMENTED; 403} 404 405static s32 ixgbe_write_phy_reg_x550em(struct ixgbe_hw *hw, u32 reg_addr, 406 u32 device_type, u16 phy_data) 407{ 408 UNREFERENCED_4PARAMETER(*hw, reg_addr, device_type, phy_data); 409 return IXGBE_NOT_IMPLEMENTED; 410} 411 412/** 413* ixgbe_init_ops_X550EM - Inits func ptrs and MAC type 414* @hw: pointer to hardware structure 415* 416* Initialize the function pointers and for MAC type X550EM. 417* Does not touch the hardware. 418**/ 419s32 ixgbe_init_ops_X550EM(struct ixgbe_hw *hw) 420{ 421 struct ixgbe_mac_info *mac = &hw->mac; 422 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 423 struct ixgbe_phy_info *phy = &hw->phy; 424 s32 ret_val; 425 426 DEBUGFUNC("ixgbe_init_ops_X550EM"); 427 428 /* Similar to X550 so start there. */ 429 ret_val = ixgbe_init_ops_X550(hw); 430 431 /* Since this function eventually calls 432 * ixgbe_init_ops_540 by design, we are setting 433 * the pointers to NULL explicitly here to overwrite 434 * the values being set in the x540 function. 435 */ 436 437 /* FCOE not supported in x550EM */ 438 mac->ops.get_san_mac_addr = NULL; 439 mac->ops.set_san_mac_addr = NULL; 440 mac->ops.get_wwn_prefix = NULL; 441 mac->ops.get_fcoe_boot_status = NULL; 442 443 /* IPsec not supported in x550EM */ 444 mac->ops.disable_sec_rx_path = NULL; 445 mac->ops.enable_sec_rx_path = NULL; 446 447 /* AUTOC register is not present in x550EM. */ 448 mac->ops.prot_autoc_read = NULL; 449 mac->ops.prot_autoc_write = NULL; 450 451 /* X550EM bus type is internal*/ 452 hw->bus.type = ixgbe_bus_type_internal; 453 mac->ops.get_bus_info = ixgbe_get_bus_info_X550em; 454 455 mac->ops.read_iosf_sb_reg = ixgbe_read_iosf_sb_reg_x550; 456 mac->ops.write_iosf_sb_reg = ixgbe_write_iosf_sb_reg_x550; 457 mac->ops.get_media_type = ixgbe_get_media_type_X550em; 458 mac->ops.setup_sfp = ixgbe_setup_sfp_modules_X550em; 459 mac->ops.get_link_capabilities = ixgbe_get_link_capabilities_X550em; 460 mac->ops.reset_hw = ixgbe_reset_hw_X550em; 461 mac->ops.get_supported_physical_layer = 462 ixgbe_get_supported_physical_layer_X550em; 463 464 if (mac->ops.get_media_type(hw) == ixgbe_media_type_copper) 465 mac->ops.setup_fc = ixgbe_setup_fc_generic; 466 else 467 mac->ops.setup_fc = ixgbe_setup_fc_X550em; 468 469 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X550em; 470 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X550em; 471 472 if (hw->device_id != IXGBE_DEV_ID_X550EM_X_KR) 473 mac->ops.setup_eee = NULL; 474 475 /* PHY */ 476 phy->ops.init = ixgbe_init_phy_ops_X550em; 477 phy->ops.identify = ixgbe_identify_phy_x550em; 478 if (mac->ops.get_media_type(hw) != ixgbe_media_type_copper) 479 phy->ops.set_phy_power = NULL; 480 481 482 /* EEPROM */ 483 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 484 eeprom->ops.read = ixgbe_read_ee_hostif_X550; 485 eeprom->ops.read_buffer = ixgbe_read_ee_hostif_buffer_X550; 486 eeprom->ops.write = ixgbe_write_ee_hostif_X550; 487 eeprom->ops.write_buffer = ixgbe_write_ee_hostif_buffer_X550; 488 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X550; 489 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X550; 490 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X550; 491 492 return ret_val; 493} 494 495/** 496 * ixgbe_dmac_config_X550 497 * @hw: pointer to hardware structure 498 * 499 * Configure DMA coalescing. If enabling dmac, dmac is activated. 500 * When disabling dmac, dmac enable dmac bit is cleared. 501 **/ 502s32 ixgbe_dmac_config_X550(struct ixgbe_hw *hw) 503{ 504 u32 reg, high_pri_tc; 505 506 DEBUGFUNC("ixgbe_dmac_config_X550"); 507 508 /* Disable DMA coalescing before configuring */ 509 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 510 reg &= ~IXGBE_DMACR_DMAC_EN; 511 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 512 513 /* Disable DMA Coalescing if the watchdog timer is 0 */ 514 if (!hw->mac.dmac_config.watchdog_timer) 515 goto out; 516 517 ixgbe_dmac_config_tcs_X550(hw); 518 519 /* Configure DMA Coalescing Control Register */ 520 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 521 522 /* Set the watchdog timer in units of 40.96 usec */ 523 reg &= ~IXGBE_DMACR_DMACWT_MASK; 524 reg |= (hw->mac.dmac_config.watchdog_timer * 100) / 4096; 525 526 reg &= ~IXGBE_DMACR_HIGH_PRI_TC_MASK; 527 /* If fcoe is enabled, set high priority traffic class */ 528 if (hw->mac.dmac_config.fcoe_en) { 529 high_pri_tc = 1 << hw->mac.dmac_config.fcoe_tc; 530 reg |= ((high_pri_tc << IXGBE_DMACR_HIGH_PRI_TC_SHIFT) & 531 IXGBE_DMACR_HIGH_PRI_TC_MASK); 532 } 533 reg |= IXGBE_DMACR_EN_MNG_IND; 534 535 /* Enable DMA coalescing after configuration */ 536 reg |= IXGBE_DMACR_DMAC_EN; 537 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 538 539out: 540 return IXGBE_SUCCESS; 541} 542 543/** 544 * ixgbe_dmac_config_tcs_X550 545 * @hw: pointer to hardware structure 546 * 547 * Configure DMA coalescing threshold per TC. The dmac enable bit must 548 * be cleared before configuring. 549 **/ 550s32 ixgbe_dmac_config_tcs_X550(struct ixgbe_hw *hw) 551{ 552 u32 tc, reg, pb_headroom, rx_pb_size, maxframe_size_kb; 553 554 DEBUGFUNC("ixgbe_dmac_config_tcs_X550"); 555 556 /* Configure DMA coalescing enabled */ 557 switch (hw->mac.dmac_config.link_speed) { 558 case IXGBE_LINK_SPEED_100_FULL: 559 pb_headroom = IXGBE_DMACRXT_100M; 560 break; 561 case IXGBE_LINK_SPEED_1GB_FULL: 562 pb_headroom = IXGBE_DMACRXT_1G; 563 break; 564 default: 565 pb_headroom = IXGBE_DMACRXT_10G; 566 break; 567 } 568 569 maxframe_size_kb = ((IXGBE_READ_REG(hw, IXGBE_MAXFRS) >> 570 IXGBE_MHADD_MFS_SHIFT) / 1024); 571 572 /* Set the per Rx packet buffer receive threshold */ 573 for (tc = 0; tc < IXGBE_DCB_MAX_TRAFFIC_CLASS; tc++) { 574 reg = IXGBE_READ_REG(hw, IXGBE_DMCTH(tc)); 575 reg &= ~IXGBE_DMCTH_DMACRXT_MASK; 576 577 if (tc < hw->mac.dmac_config.num_tcs) { 578 /* Get Rx PB size */ 579 rx_pb_size = IXGBE_READ_REG(hw, IXGBE_RXPBSIZE(tc)); 580 rx_pb_size = (rx_pb_size & IXGBE_RXPBSIZE_MASK) >> 581 IXGBE_RXPBSIZE_SHIFT; 582 583 /* Calculate receive buffer threshold in kilobytes */ 584 if (rx_pb_size > pb_headroom) 585 rx_pb_size = rx_pb_size - pb_headroom; 586 else 587 rx_pb_size = 0; 588 589 /* Minimum of MFS shall be set for DMCTH */ 590 reg |= (rx_pb_size > maxframe_size_kb) ? 591 rx_pb_size : maxframe_size_kb; 592 } 593 IXGBE_WRITE_REG(hw, IXGBE_DMCTH(tc), reg); 594 } 595 return IXGBE_SUCCESS; 596} 597 598/** 599 * ixgbe_dmac_update_tcs_X550 600 * @hw: pointer to hardware structure 601 * 602 * Disables dmac, updates per TC settings, and then enables dmac. 603 **/ 604s32 ixgbe_dmac_update_tcs_X550(struct ixgbe_hw *hw) 605{ 606 u32 reg; 607 608 DEBUGFUNC("ixgbe_dmac_update_tcs_X550"); 609 610 /* Disable DMA coalescing before configuring */ 611 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 612 reg &= ~IXGBE_DMACR_DMAC_EN; 613 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 614 615 ixgbe_dmac_config_tcs_X550(hw); 616 617 /* Enable DMA coalescing after configuration */ 618 reg = IXGBE_READ_REG(hw, IXGBE_DMACR); 619 reg |= IXGBE_DMACR_DMAC_EN; 620 IXGBE_WRITE_REG(hw, IXGBE_DMACR, reg); 621 622 return IXGBE_SUCCESS; 623} 624 625/** 626 * ixgbe_init_eeprom_params_X550 - Initialize EEPROM params 627 * @hw: pointer to hardware structure 628 * 629 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 630 * ixgbe_hw struct in order to set up EEPROM access. 631 **/ 632s32 ixgbe_init_eeprom_params_X550(struct ixgbe_hw *hw) 633{ 634 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 635 u32 eec; 636 u16 eeprom_size; 637 638 DEBUGFUNC("ixgbe_init_eeprom_params_X550"); 639 640 if (eeprom->type == ixgbe_eeprom_uninitialized) { 641 eeprom->semaphore_delay = 10; 642 eeprom->type = ixgbe_flash; 643 644 eec = IXGBE_READ_REG(hw, IXGBE_EEC); 645 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 646 IXGBE_EEC_SIZE_SHIFT); 647 eeprom->word_size = 1 << (eeprom_size + 648 IXGBE_EEPROM_WORD_SIZE_SHIFT); 649 650 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 651 eeprom->type, eeprom->word_size); 652 } 653 654 return IXGBE_SUCCESS; 655} 656 657/** 658 * ixgbe_setup_eee_X550 - Enable/disable EEE support 659 * @hw: pointer to the HW structure 660 * @enable_eee: boolean flag to enable EEE 661 * 662 * Enable/disable EEE based on enable_eee flag. 663 * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 664 * are modified. 665 * 666 **/ 667s32 ixgbe_setup_eee_X550(struct ixgbe_hw *hw, bool enable_eee) 668{ 669 u32 eeer; 670 u16 autoneg_eee_reg; 671 u32 link_reg; 672 s32 status; 673 u32 fuse; 674 675 DEBUGFUNC("ixgbe_setup_eee_X550"); 676 677 eeer = IXGBE_READ_REG(hw, IXGBE_EEER); 678 /* Enable or disable EEE per flag */ 679 if (enable_eee) { 680 eeer |= (IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 681 682 if (hw->device_id == IXGBE_DEV_ID_X550T) { 683 /* Advertise EEE capability */ 684 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 685 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 686 687 autoneg_eee_reg |= (IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 688 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 689 IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 690 691 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 692 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 693 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 694 /* Not supported on first revision. */ 695 fuse = IXGBE_READ_REG(hw, IXGBE_FUSES0_GROUP(0)); 696 if (!(fuse & IXGBE_FUSES0_REV1)) 697 return IXGBE_SUCCESS; 698 699 status = ixgbe_read_iosf_sb_reg_x550(hw, 700 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 701 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 702 if (status != IXGBE_SUCCESS) 703 return status; 704 705 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 706 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX; 707 708 /* Don't advertise FEC capability when EEE enabled. */ 709 link_reg &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 710 711 status = ixgbe_write_iosf_sb_reg_x550(hw, 712 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 713 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 714 if (status != IXGBE_SUCCESS) 715 return status; 716 } 717 } else { 718 eeer &= ~(IXGBE_EEER_TX_LPI_EN | IXGBE_EEER_RX_LPI_EN); 719 720 if (hw->device_id == IXGBE_DEV_ID_X550T) { 721 /* Disable advertised EEE capability */ 722 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 723 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_eee_reg); 724 725 autoneg_eee_reg &= ~(IXGBE_AUTO_NEG_10GBASE_EEE_ADVT | 726 IXGBE_AUTO_NEG_1000BASE_EEE_ADVT | 727 IXGBE_AUTO_NEG_100BASE_EEE_ADVT); 728 729 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_EEE_ADVT, 730 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_eee_reg); 731 } else if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) { 732 status = ixgbe_read_iosf_sb_reg_x550(hw, 733 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 734 IXGBE_SB_IOSF_TARGET_KR_PHY, &link_reg); 735 if (status != IXGBE_SUCCESS) 736 return status; 737 738 link_reg &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR | 739 IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX); 740 741 /* Advertise FEC capability when EEE is disabled. */ 742 link_reg |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC; 743 744 status = ixgbe_write_iosf_sb_reg_x550(hw, 745 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 746 IXGBE_SB_IOSF_TARGET_KR_PHY, link_reg); 747 if (status != IXGBE_SUCCESS) 748 return status; 749 } 750 } 751 IXGBE_WRITE_REG(hw, IXGBE_EEER, eeer); 752 753 return IXGBE_SUCCESS; 754} 755 756/** 757 * ixgbe_set_source_address_pruning_X550 - Enable/Disbale source address pruning 758 * @hw: pointer to hardware structure 759 * @enable: enable or disable source address pruning 760 * @pool: Rx pool to set source address pruning for 761 **/ 762void ixgbe_set_source_address_pruning_X550(struct ixgbe_hw *hw, bool enable, 763 unsigned int pool) 764{ 765 u64 pfflp; 766 767 /* max rx pool is 63 */ 768 if (pool > 63) 769 return; 770 771 pfflp = (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPL); 772 pfflp |= (u64)IXGBE_READ_REG(hw, IXGBE_PFFLPH) << 32; 773 774 if (enable) 775 pfflp |= (1ULL << pool); 776 else 777 pfflp &= ~(1ULL << pool); 778 779 IXGBE_WRITE_REG(hw, IXGBE_PFFLPL, (u32)pfflp); 780 IXGBE_WRITE_REG(hw, IXGBE_PFFLPH, (u32)(pfflp >> 32)); 781} 782 783/** 784 * ixgbe_set_ethertype_anti_spoofing_X550 - Enable/Disable Ethertype anti-spoofing 785 * @hw: pointer to hardware structure 786 * @enable: enable or disable switch for Ethertype anti-spoofing 787 * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 788 * 789 **/ 790void ixgbe_set_ethertype_anti_spoofing_X550(struct ixgbe_hw *hw, 791 bool enable, int vf) 792{ 793 int vf_target_reg = vf >> 3; 794 int vf_target_shift = vf % 8 + IXGBE_SPOOF_ETHERTYPEAS_SHIFT; 795 u32 pfvfspoof; 796 797 DEBUGFUNC("ixgbe_set_ethertype_anti_spoofing_X550"); 798 799 pfvfspoof = IXGBE_READ_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg)); 800 if (enable) 801 pfvfspoof |= (1 << vf_target_shift); 802 else 803 pfvfspoof &= ~(1 << vf_target_shift); 804 805 IXGBE_WRITE_REG(hw, IXGBE_PFVFSPOOF(vf_target_reg), pfvfspoof); 806} 807 808/** 809 * ixgbe_iosf_wait - Wait for IOSF command completion 810 * @hw: pointer to hardware structure 811 * @ctrl: pointer to location to receive final IOSF control value 812 * 813 * Returns failing status on timeout 814 * 815 * Note: ctrl can be NULL if the IOSF control register value is not needed 816 **/ 817static s32 ixgbe_iosf_wait(struct ixgbe_hw *hw, u32 *ctrl) 818{ 819 u32 i, command; 820 821 /* Check every 10 usec to see if the address cycle completed. 822 * The SB IOSF BUSY bit will clear when the operation is 823 * complete 824 */ 825 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 826 command = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL); 827 if ((command & IXGBE_SB_IOSF_CTRL_BUSY) == 0) 828 break; 829 usec_delay(10); 830 } 831 if (ctrl) 832 *ctrl = command; 833 if (i == IXGBE_MDIO_COMMAND_TIMEOUT) { 834 ERROR_REPORT1(IXGBE_ERROR_POLLING, "Wait timed out\n"); 835 return IXGBE_ERR_PHY; 836 } 837 838 return IXGBE_SUCCESS; 839} 840 841/** 842 * ixgbe_write_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 843 * device 844 * @hw: pointer to hardware structure 845 * @reg_addr: 32 bit PHY register to write 846 * @device_type: 3 bit device type 847 * @data: Data to write to the register 848 **/ 849s32 ixgbe_write_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 850 u32 device_type, u32 data) 851{ 852 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 853 u32 command, error; 854 s32 ret; 855 856 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 857 if (ret != IXGBE_SUCCESS) 858 return ret; 859 860 ret = ixgbe_iosf_wait(hw, NULL); 861 if (ret != IXGBE_SUCCESS) 862 goto out; 863 864 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 865 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 866 867 /* Write IOSF control register */ 868 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 869 870 /* Write IOSF data register */ 871 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA, data); 872 873 ret = ixgbe_iosf_wait(hw, &command); 874 875 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 876 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 877 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 878 ERROR_REPORT2(IXGBE_ERROR_POLLING, 879 "Failed to write, error %x\n", error); 880 ret = IXGBE_ERR_PHY; 881 } 882 883out: 884 ixgbe_release_swfw_semaphore(hw, gssr); 885 return ret; 886} 887 888/** 889 * ixgbe_read_iosf_sb_reg_x550 - Writes a value to specified register of the IOSF 890 * device 891 * @hw: pointer to hardware structure 892 * @reg_addr: 32 bit PHY register to write 893 * @device_type: 3 bit device type 894 * @phy_data: Pointer to read data from the register 895 **/ 896s32 ixgbe_read_iosf_sb_reg_x550(struct ixgbe_hw *hw, u32 reg_addr, 897 u32 device_type, u32 *data) 898{ 899 u32 gssr = IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_PHY0_SM; 900 u32 command, error; 901 s32 ret; 902 903 ret = ixgbe_acquire_swfw_semaphore(hw, gssr); 904 if (ret != IXGBE_SUCCESS) 905 return ret; 906 907 ret = ixgbe_iosf_wait(hw, NULL); 908 if (ret != IXGBE_SUCCESS) 909 goto out; 910 911 command = ((reg_addr << IXGBE_SB_IOSF_CTRL_ADDR_SHIFT) | 912 (device_type << IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT)); 913 914 /* Write IOSF control register */ 915 IXGBE_WRITE_REG(hw, IXGBE_SB_IOSF_INDIRECT_CTRL, command); 916 917 ret = ixgbe_iosf_wait(hw, &command); 918 919 if ((command & IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK) != 0) { 920 error = (command & IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK) >> 921 IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT; 922 ERROR_REPORT2(IXGBE_ERROR_POLLING, 923 "Failed to read, error %x\n", error); 924 ret = IXGBE_ERR_PHY; 925 } 926 927 if (ret == IXGBE_SUCCESS) 928 *data = IXGBE_READ_REG(hw, IXGBE_SB_IOSF_INDIRECT_DATA); 929 930out: 931 ixgbe_release_swfw_semaphore(hw, gssr); 932 return ret; 933} 934 935/** 936 * ixgbe_disable_mdd_X550 937 * @hw: pointer to hardware structure 938 * 939 * Disable malicious driver detection 940 **/ 941void ixgbe_disable_mdd_X550(struct ixgbe_hw *hw) 942{ 943 u32 reg; 944 945 DEBUGFUNC("ixgbe_disable_mdd_X550"); 946 947 /* Disable MDD for TX DMA and interrupt */ 948 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 949 reg &= ~(IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 950 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 951 952 /* Disable MDD for RX and interrupt */ 953 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 954 reg &= ~(IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 955 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 956} 957 958/** 959 * ixgbe_enable_mdd_X550 960 * @hw: pointer to hardware structure 961 * 962 * Enable malicious driver detection 963 **/ 964void ixgbe_enable_mdd_X550(struct ixgbe_hw *hw) 965{ 966 u32 reg; 967 968 DEBUGFUNC("ixgbe_enable_mdd_X550"); 969 970 /* Enable MDD for TX DMA and interrupt */ 971 reg = IXGBE_READ_REG(hw, IXGBE_DMATXCTL); 972 reg |= (IXGBE_DMATXCTL_MDP_EN | IXGBE_DMATXCTL_MBINTEN); 973 IXGBE_WRITE_REG(hw, IXGBE_DMATXCTL, reg); 974 975 /* Enable MDD for RX and interrupt */ 976 reg = IXGBE_READ_REG(hw, IXGBE_RDRXCTL); 977 reg |= (IXGBE_RDRXCTL_MDP_EN | IXGBE_RDRXCTL_MBINTEN); 978 IXGBE_WRITE_REG(hw, IXGBE_RDRXCTL, reg); 979} 980 981/** 982 * ixgbe_restore_mdd_vf_X550 983 * @hw: pointer to hardware structure 984 * @vf: vf index 985 * 986 * Restore VF that was disabled during malicious driver detection event 987 **/ 988void ixgbe_restore_mdd_vf_X550(struct ixgbe_hw *hw, u32 vf) 989{ 990 u32 idx, reg, num_qs, start_q, bitmask; 991 992 DEBUGFUNC("ixgbe_restore_mdd_vf_X550"); 993 994 /* Map VF to queues */ 995 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 996 switch (reg & IXGBE_MRQC_MRQE_MASK) { 997 case IXGBE_MRQC_VMDQRT8TCEN: 998 num_qs = 8; /* 16 VFs / pools */ 999 bitmask = 0x000000FF; 1000 break; 1001 case IXGBE_MRQC_VMDQRSS32EN: 1002 case IXGBE_MRQC_VMDQRT4TCEN: 1003 num_qs = 4; /* 32 VFs / pools */ 1004 bitmask = 0x0000000F; 1005 break; 1006 default: /* 64 VFs / pools */ 1007 num_qs = 2; 1008 bitmask = 0x00000003; 1009 break; 1010 } 1011 start_q = vf * num_qs; 1012 1013 /* Release vf's queues by clearing WQBR_TX and WQBR_RX (RW1C) */ 1014 idx = start_q / 32; 1015 reg = 0; 1016 reg |= (bitmask << (start_q % 32)); 1017 IXGBE_WRITE_REG(hw, IXGBE_WQBR_TX(idx), reg); 1018 IXGBE_WRITE_REG(hw, IXGBE_WQBR_RX(idx), reg); 1019} 1020 1021/** 1022 * ixgbe_mdd_event_X550 1023 * @hw: pointer to hardware structure 1024 * @vf_bitmap: vf bitmap of malicious vfs 1025 * 1026 * Handle malicious driver detection event. 1027 **/ 1028void ixgbe_mdd_event_X550(struct ixgbe_hw *hw, u32 *vf_bitmap) 1029{ 1030 u32 wqbr; 1031 u32 i, j, reg, q, shift, vf, idx; 1032 1033 DEBUGFUNC("ixgbe_mdd_event_X550"); 1034 1035 /* figure out pool size for mapping to vf's */ 1036 reg = IXGBE_READ_REG(hw, IXGBE_MRQC); 1037 switch (reg & IXGBE_MRQC_MRQE_MASK) { 1038 case IXGBE_MRQC_VMDQRT8TCEN: 1039 shift = 3; /* 16 VFs / pools */ 1040 break; 1041 case IXGBE_MRQC_VMDQRSS32EN: 1042 case IXGBE_MRQC_VMDQRT4TCEN: 1043 shift = 2; /* 32 VFs / pools */ 1044 break; 1045 default: 1046 shift = 1; /* 64 VFs / pools */ 1047 break; 1048 } 1049 1050 /* Read WQBR_TX and WQBR_RX and check for malicious queues */ 1051 for (i = 0; i < 4; i++) { 1052 wqbr = IXGBE_READ_REG(hw, IXGBE_WQBR_TX(i)); 1053 wqbr |= IXGBE_READ_REG(hw, IXGBE_WQBR_RX(i)); 1054 1055 if (!wqbr) 1056 continue; 1057 1058 /* Get malicious queue */ 1059 for (j = 0; j < 32 && wqbr; j++) { 1060 1061 if (!(wqbr & (1 << j))) 1062 continue; 1063 1064 /* Get queue from bitmask */ 1065 q = j + (i * 32); 1066 1067 /* Map queue to vf */ 1068 vf = (q >> shift); 1069 1070 /* Set vf bit in vf_bitmap */ 1071 idx = vf / 32; 1072 vf_bitmap[idx] |= (1 << (vf % 32)); 1073 wqbr &= ~(1 << j); 1074 } 1075 } 1076} 1077 1078/** 1079 * ixgbe_get_media_type_X550em - Get media type 1080 * @hw: pointer to hardware structure 1081 * 1082 * Returns the media type (fiber, copper, backplane) 1083 */ 1084enum ixgbe_media_type ixgbe_get_media_type_X550em(struct ixgbe_hw *hw) 1085{ 1086 enum ixgbe_media_type media_type; 1087 1088 DEBUGFUNC("ixgbe_get_media_type_X550em"); 1089 1090 /* Detect if there is a copper PHY attached. */ 1091 switch (hw->device_id) { 1092 case IXGBE_DEV_ID_X550EM_X_KR: 1093 case IXGBE_DEV_ID_X550EM_X_KX4: 1094 media_type = ixgbe_media_type_backplane; 1095 break; 1096 case IXGBE_DEV_ID_X550EM_X_SFP: 1097 media_type = ixgbe_media_type_fiber; 1098 break; 1099 case IXGBE_DEV_ID_X550EM_X_1G_T: 1100 case IXGBE_DEV_ID_X550EM_X_10G_T: 1101 media_type = ixgbe_media_type_copper; 1102 break; 1103 default: 1104 media_type = ixgbe_media_type_unknown; 1105 break; 1106 } 1107 return media_type; 1108} 1109 1110/** 1111 * ixgbe_supported_sfp_modules_X550em - Check if SFP module type is supported 1112 * @hw: pointer to hardware structure 1113 * @linear: TRUE if SFP module is linear 1114 */ 1115static s32 ixgbe_supported_sfp_modules_X550em(struct ixgbe_hw *hw, bool *linear) 1116{ 1117 DEBUGFUNC("ixgbe_supported_sfp_modules_X550em"); 1118 1119 switch (hw->phy.sfp_type) { 1120 case ixgbe_sfp_type_not_present: 1121 return IXGBE_ERR_SFP_NOT_PRESENT; 1122 case ixgbe_sfp_type_da_cu_core0: 1123 case ixgbe_sfp_type_da_cu_core1: 1124 *linear = TRUE; 1125 break; 1126 case ixgbe_sfp_type_srlr_core0: 1127 case ixgbe_sfp_type_srlr_core1: 1128 case ixgbe_sfp_type_da_act_lmt_core0: 1129 case ixgbe_sfp_type_da_act_lmt_core1: 1130 case ixgbe_sfp_type_1g_sx_core0: 1131 case ixgbe_sfp_type_1g_sx_core1: 1132 case ixgbe_sfp_type_1g_lx_core0: 1133 case ixgbe_sfp_type_1g_lx_core1: 1134 *linear = FALSE; 1135 break; 1136 case ixgbe_sfp_type_unknown: 1137 case ixgbe_sfp_type_1g_cu_core0: 1138 case ixgbe_sfp_type_1g_cu_core1: 1139 default: 1140 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1141 } 1142 1143 return IXGBE_SUCCESS; 1144} 1145 1146/** 1147 * ixgbe_identify_sfp_module_X550em - Identifies SFP modules 1148 * @hw: pointer to hardware structure 1149 * 1150 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1151 **/ 1152s32 ixgbe_identify_sfp_module_X550em(struct ixgbe_hw *hw) 1153{ 1154 s32 status; 1155 bool linear; 1156 1157 DEBUGFUNC("ixgbe_identify_sfp_module_X550em"); 1158 1159 status = ixgbe_identify_module_generic(hw); 1160 1161 if (status != IXGBE_SUCCESS) 1162 return status; 1163 1164 /* Check if SFP module is supported */ 1165 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1166 1167 return status; 1168} 1169 1170/** 1171 * ixgbe_setup_sfp_modules_X550em - Setup MAC link ops 1172 * @hw: pointer to hardware structure 1173 */ 1174s32 ixgbe_setup_sfp_modules_X550em(struct ixgbe_hw *hw) 1175{ 1176 s32 status; 1177 bool linear; 1178 1179 DEBUGFUNC("ixgbe_setup_sfp_modules_X550em"); 1180 1181 /* Check if SFP module is supported */ 1182 status = ixgbe_supported_sfp_modules_X550em(hw, &linear); 1183 1184 if (status != IXGBE_SUCCESS) 1185 return status; 1186 1187 ixgbe_init_mac_link_ops_X550em(hw); 1188 hw->phy.ops.reset = NULL; 1189 1190 return IXGBE_SUCCESS; 1191} 1192 1193/** 1194 * ixgbe_init_mac_link_ops_X550em - init mac link function pointers 1195 * @hw: pointer to hardware structure 1196 */ 1197void ixgbe_init_mac_link_ops_X550em(struct ixgbe_hw *hw) 1198{ 1199 struct ixgbe_mac_info *mac = &hw->mac; 1200 1201 DEBUGFUNC("ixgbe_init_mac_link_ops_X550em"); 1202 1203 switch (hw->mac.ops.get_media_type(hw)) { 1204 case ixgbe_media_type_fiber: 1205 /* CS4227 does not support autoneg, so disable the laser control 1206 * functions for SFP+ fiber 1207 */ 1208 mac->ops.disable_tx_laser = NULL; 1209 mac->ops.enable_tx_laser = NULL; 1210 mac->ops.flap_tx_laser = NULL; 1211 mac->ops.setup_link = ixgbe_setup_mac_link_multispeed_fiber; 1212 mac->ops.setup_mac_link = ixgbe_setup_mac_link_sfp_x550em; 1213 mac->ops.set_rate_select_speed = 1214 ixgbe_set_soft_rate_select_speed; 1215 break; 1216 case ixgbe_media_type_copper: 1217 mac->ops.setup_link = ixgbe_setup_mac_link_t_X550em; 1218 mac->ops.check_link = ixgbe_check_link_t_X550em; 1219 break; 1220 default: 1221 break; 1222 } 1223} 1224 1225/** 1226 * ixgbe_get_link_capabilities_x550em - Determines link capabilities 1227 * @hw: pointer to hardware structure 1228 * @speed: pointer to link speed 1229 * @autoneg: TRUE when autoneg or autotry is enabled 1230 */ 1231s32 ixgbe_get_link_capabilities_X550em(struct ixgbe_hw *hw, 1232 ixgbe_link_speed *speed, 1233 bool *autoneg) 1234{ 1235 DEBUGFUNC("ixgbe_get_link_capabilities_X550em"); 1236 1237 /* SFP */ 1238 if (hw->phy.media_type == ixgbe_media_type_fiber) { 1239 1240 /* CS4227 SFP must not enable auto-negotiation */ 1241 *autoneg = FALSE; 1242 1243 /* Check if 1G SFP module. */ 1244 if (hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1245 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1 1246 || hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1247 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1) { 1248 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1249 return IXGBE_SUCCESS; 1250 } 1251 1252 /* Link capabilities are based on SFP */ 1253 if (hw->phy.multispeed_fiber) 1254 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1255 IXGBE_LINK_SPEED_1GB_FULL; 1256 else 1257 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1258 } else { 1259 *speed = IXGBE_LINK_SPEED_10GB_FULL | 1260 IXGBE_LINK_SPEED_1GB_FULL; 1261 *autoneg = TRUE; 1262 } 1263 1264 return IXGBE_SUCCESS; 1265} 1266 1267/** 1268 * ixgbe_get_lasi_ext_t_x550em - Determime external Base T PHY interrupt cause 1269 * @hw: pointer to hardware structure 1270 * @lsc: pointer to boolean flag which indicates whether external Base T 1271 * PHY interrupt is lsc 1272 * 1273 * Determime if external Base T PHY interrupt cause is high temperature 1274 * failure alarm or link status change. 1275 * 1276 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1277 * failure alarm, else return PHY access status. 1278 */ 1279static s32 ixgbe_get_lasi_ext_t_x550em(struct ixgbe_hw *hw, bool *lsc) 1280{ 1281 u32 status; 1282 u16 reg; 1283 1284 *lsc = FALSE; 1285 1286 /* Vendor alarm triggered */ 1287 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1288 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1289 ®); 1290 1291 if (status != IXGBE_SUCCESS || 1292 !(reg & IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN)) 1293 return status; 1294 1295 /* Vendor Auto-Neg alarm triggered or Global alarm 1 triggered */ 1296 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG, 1297 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1298 ®); 1299 1300 if (status != IXGBE_SUCCESS || 1301 !(reg & (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1302 IXGBE_MDIO_GLOBAL_ALARM_1_INT))) 1303 return status; 1304 1305 /* High temperature failure alarm triggered */ 1306 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_ALARM_1, 1307 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1308 ®); 1309 1310 if (status != IXGBE_SUCCESS) 1311 return status; 1312 1313 /* If high temperature failure, then return over temp error and exit */ 1314 if (reg & IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL) { 1315 /* power down the PHY in case the PHY FW didn't already */ 1316 ixgbe_set_copper_phy_power(hw, FALSE); 1317 return IXGBE_ERR_OVERTEMP; 1318 } 1319 1320 /* Vendor alarm 2 triggered */ 1321 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG, 1322 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1323 1324 if (status != IXGBE_SUCCESS || 1325 !(reg & IXGBE_MDIO_GLOBAL_STD_ALM2_INT)) 1326 return status; 1327 1328 /* link connect/disconnect event occurred */ 1329 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2, 1330 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1331 1332 if (status != IXGBE_SUCCESS) 1333 return status; 1334 1335 /* Indicate LSC */ 1336 if (reg & IXGBE_MDIO_AUTO_NEG_VEN_LSC) 1337 *lsc = TRUE; 1338 1339 return IXGBE_SUCCESS; 1340} 1341 1342/** 1343 * ixgbe_enable_lasi_ext_t_x550em - Enable external Base T PHY interrupts 1344 * @hw: pointer to hardware structure 1345 * 1346 * Enable link status change and temperature failure alarm for the external 1347 * Base T PHY 1348 * 1349 * Returns PHY access status 1350 */ 1351static s32 ixgbe_enable_lasi_ext_t_x550em(struct ixgbe_hw *hw) 1352{ 1353 u32 status; 1354 u16 reg; 1355 bool lsc; 1356 1357 /* Clear interrupt flags */ 1358 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 1359 1360 /* Enable link status change alarm */ 1361 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1362 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, ®); 1363 1364 if (status != IXGBE_SUCCESS) 1365 return status; 1366 1367 reg |= IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN; 1368 1369 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK, 1370 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, reg); 1371 1372 if (status != IXGBE_SUCCESS) 1373 return status; 1374 1375 /* Enables high temperature failure alarm */ 1376 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1377 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1378 ®); 1379 1380 if (status != IXGBE_SUCCESS) 1381 return status; 1382 1383 reg |= IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN; 1384 1385 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_MASK, 1386 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1387 reg); 1388 1389 if (status != IXGBE_SUCCESS) 1390 return status; 1391 1392 /* Enable vendor Auto-Neg alarm and Global Interrupt Mask 1 alarm */ 1393 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1394 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1395 ®); 1396 1397 if (status != IXGBE_SUCCESS) 1398 return status; 1399 1400 reg |= (IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN | 1401 IXGBE_MDIO_GLOBAL_ALARM_1_INT); 1402 1403 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK, 1404 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1405 reg); 1406 1407 if (status != IXGBE_SUCCESS) 1408 return status; 1409 1410 /* Enable chip-wide vendor alarm */ 1411 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1412 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1413 ®); 1414 1415 if (status != IXGBE_SUCCESS) 1416 return status; 1417 1418 reg |= IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN; 1419 1420 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK, 1421 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1422 reg); 1423 1424 return status; 1425} 1426 1427/** 1428 * ixgbe_setup_kr_speed_x550em - Configure the KR PHY for link speed. 1429 * @hw: pointer to hardware structure 1430 * @speed: link speed 1431 * 1432 * Configures the integrated KR PHY. 1433 **/ 1434static s32 ixgbe_setup_kr_speed_x550em(struct ixgbe_hw *hw, 1435 ixgbe_link_speed speed) 1436{ 1437 s32 status; 1438 u32 reg_val; 1439 1440 status = ixgbe_read_iosf_sb_reg_x550(hw, 1441 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1442 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1443 if (status) 1444 return status; 1445 1446 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1447 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ | 1448 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC); 1449 reg_val &= ~(IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR | 1450 IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX); 1451 1452 /* Advertise 10G support. */ 1453 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 1454 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR; 1455 1456 /* Advertise 1G support. */ 1457 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 1458 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX; 1459 1460 /* Restart auto-negotiation. */ 1461 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1462 status = ixgbe_write_iosf_sb_reg_x550(hw, 1463 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1464 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1465 1466 return status; 1467} 1468 1469/** 1470 * ixgbe_init_phy_ops_X550em - PHY/SFP specific init 1471 * @hw: pointer to hardware structure 1472 * 1473 * Initialize any function pointers that were not able to be 1474 * set during init_shared_code because the PHY/SFP type was 1475 * not known. Perform the SFP init if necessary. 1476 */ 1477s32 ixgbe_init_phy_ops_X550em(struct ixgbe_hw *hw) 1478{ 1479 struct ixgbe_phy_info *phy = &hw->phy; 1480 ixgbe_link_speed speed; 1481 s32 ret_val; 1482 1483 DEBUGFUNC("ixgbe_init_phy_ops_X550em"); 1484 1485 hw->mac.ops.set_lan_id(hw); 1486 1487 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) { 1488 phy->phy_semaphore_mask = IXGBE_GSSR_SHARED_I2C_SM; 1489 ixgbe_setup_mux_ctl(hw); 1490 1491 /* Save NW management interface connected on board. This is used 1492 * to determine internal PHY mode. 1493 */ 1494 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1495 1496 /* If internal PHY mode is KR, then initialize KR link */ 1497 if (phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE) { 1498 speed = IXGBE_LINK_SPEED_10GB_FULL | 1499 IXGBE_LINK_SPEED_1GB_FULL; 1500 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1501 } 1502 1503 phy->ops.identify_sfp = ixgbe_identify_sfp_module_X550em; 1504 } 1505 1506 /* Identify the PHY or SFP module */ 1507 ret_val = phy->ops.identify(hw); 1508 if (ret_val == IXGBE_ERR_SFP_NOT_SUPPORTED) 1509 return ret_val; 1510 1511 /* Setup function pointers based on detected hardware */ 1512 ixgbe_init_mac_link_ops_X550em(hw); 1513 if (phy->sfp_type != ixgbe_sfp_type_unknown) 1514 phy->ops.reset = NULL; 1515 1516 /* Set functions pointers based on phy type */ 1517 switch (hw->phy.type) { 1518 case ixgbe_phy_x550em_kx4: 1519 phy->ops.setup_link = ixgbe_setup_kx4_x550em; 1520 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1521 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1522 break; 1523 case ixgbe_phy_x550em_kr: 1524 phy->ops.setup_link = ixgbe_setup_kr_x550em; 1525 phy->ops.read_reg = ixgbe_read_phy_reg_x550em; 1526 phy->ops.write_reg = ixgbe_write_phy_reg_x550em; 1527 break; 1528 case ixgbe_phy_x550em_ext_t: 1529 /* Save NW management interface connected on board. This is used 1530 * to determine internal PHY mode 1531 */ 1532 phy->nw_mng_if_sel = IXGBE_READ_REG(hw, IXGBE_NW_MNG_IF_SEL); 1533 1534 /* If internal link mode is XFI, then setup iXFI internal link, 1535 * else setup KR now. 1536 */ 1537 if (!(phy->nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 1538 phy->ops.setup_internal_link = 1539 ixgbe_setup_internal_phy_t_x550em; 1540 } else { 1541 speed = IXGBE_LINK_SPEED_10GB_FULL | 1542 IXGBE_LINK_SPEED_1GB_FULL; 1543 ret_val = ixgbe_setup_kr_speed_x550em(hw, speed); 1544 } 1545 1546 phy->ops.enter_lplu = ixgbe_enter_lplu_t_x550em; 1547 phy->ops.handle_lasi = ixgbe_handle_lasi_ext_t_x550em; 1548 phy->ops.reset = ixgbe_reset_phy_t_X550em; 1549 break; 1550 default: 1551 break; 1552 } 1553 return ret_val; 1554} 1555 1556/** 1557 * ixgbe_reset_hw_X550em - Perform hardware reset 1558 * @hw: pointer to hardware structure 1559 * 1560 * Resets the hardware by resetting the transmit and receive units, masks 1561 * and clears all interrupts, perform a PHY reset, and perform a link (MAC) 1562 * reset. 1563 */ 1564s32 ixgbe_reset_hw_X550em(struct ixgbe_hw *hw) 1565{ 1566 ixgbe_link_speed link_speed; 1567 s32 status; 1568 u32 ctrl = 0; 1569 u32 i; 1570 u32 hlreg0; 1571 bool link_up = FALSE; 1572 1573 DEBUGFUNC("ixgbe_reset_hw_X550em"); 1574 1575 /* Call adapter stop to disable Tx/Rx and clear interrupts */ 1576 status = hw->mac.ops.stop_adapter(hw); 1577 if (status != IXGBE_SUCCESS) 1578 return status; 1579 1580 /* flush pending Tx transactions */ 1581 ixgbe_clear_tx_pending(hw); 1582 1583 /* PHY ops must be identified and initialized prior to reset */ 1584 1585 /* Identify PHY and related function pointers */ 1586 status = hw->phy.ops.init(hw); 1587 1588 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1589 return status; 1590 1591 /* start the external PHY */ 1592 if (hw->phy.type == ixgbe_phy_x550em_ext_t) { 1593 status = ixgbe_init_ext_t_x550em(hw); 1594 if (status) 1595 return status; 1596 } 1597 1598 /* Setup SFP module if there is one present. */ 1599 if (hw->phy.sfp_setup_needed) { 1600 status = hw->mac.ops.setup_sfp(hw); 1601 hw->phy.sfp_setup_needed = FALSE; 1602 } 1603 1604 if (status == IXGBE_ERR_SFP_NOT_SUPPORTED) 1605 return status; 1606 1607 /* Reset PHY */ 1608 if (!hw->phy.reset_disable && hw->phy.ops.reset) 1609 hw->phy.ops.reset(hw); 1610 1611mac_reset_top: 1612 /* Issue global reset to the MAC. Needs to be SW reset if link is up. 1613 * If link reset is used when link is up, it might reset the PHY when 1614 * mng is using it. If link is down or the flag to force full link 1615 * reset is set, then perform link reset. 1616 */ 1617 ctrl = IXGBE_CTRL_LNK_RST; 1618 if (!hw->force_full_reset) { 1619 hw->mac.ops.check_link(hw, &link_speed, &link_up, FALSE); 1620 if (link_up) 1621 ctrl = IXGBE_CTRL_RST; 1622 } 1623 1624 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 1625 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 1626 IXGBE_WRITE_FLUSH(hw); 1627 1628 /* Poll for reset bit to self-clear meaning reset is complete */ 1629 for (i = 0; i < 10; i++) { 1630 usec_delay(1); 1631 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 1632 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 1633 break; 1634 } 1635 1636 if (ctrl & IXGBE_CTRL_RST_MASK) { 1637 status = IXGBE_ERR_RESET_FAILED; 1638 DEBUGOUT("Reset polling failed to complete.\n"); 1639 } 1640 1641 msec_delay(50); 1642 1643 /* Double resets are required for recovery from certain error 1644 * conditions. Between resets, it is necessary to stall to 1645 * allow time for any pending HW events to complete. 1646 */ 1647 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 1648 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 1649 goto mac_reset_top; 1650 } 1651 1652 /* Store the permanent mac address */ 1653 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 1654 1655 /* Store MAC address from RAR0, clear receive address registers, and 1656 * clear the multicast table. Also reset num_rar_entries to 128, 1657 * since we modify this value when programming the SAN MAC address. 1658 */ 1659 hw->mac.num_rar_entries = 128; 1660 hw->mac.ops.init_rx_addrs(hw); 1661 1662 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_10G_T) { 1663 /* Config MDIO clock speed. */ 1664 hlreg0 = IXGBE_READ_REG(hw, IXGBE_HLREG0); 1665 hlreg0 &= ~IXGBE_HLREG0_MDCSPD; 1666 IXGBE_WRITE_REG(hw, IXGBE_HLREG0, hlreg0); 1667 } 1668 1669 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_SFP) 1670 ixgbe_setup_mux_ctl(hw); 1671 1672 return status; 1673} 1674 1675/** 1676 * ixgbe_init_ext_t_x550em - Start (unstall) the external Base T PHY. 1677 * @hw: pointer to hardware structure 1678 */ 1679s32 ixgbe_init_ext_t_x550em(struct ixgbe_hw *hw) 1680{ 1681 u32 status; 1682 u16 reg; 1683 1684 status = hw->phy.ops.read_reg(hw, 1685 IXGBE_MDIO_TX_VENDOR_ALARMS_3, 1686 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 1687 ®); 1688 1689 if (status != IXGBE_SUCCESS) 1690 return status; 1691 1692 /* If PHY FW reset completed bit is set then this is the first 1693 * SW instance after a power on so the PHY FW must be un-stalled. 1694 */ 1695 if (reg & IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK) { 1696 status = hw->phy.ops.read_reg(hw, 1697 IXGBE_MDIO_GLOBAL_RES_PR_10, 1698 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1699 ®); 1700 1701 if (status != IXGBE_SUCCESS) 1702 return status; 1703 1704 reg &= ~IXGBE_MDIO_POWER_UP_STALL; 1705 1706 status = hw->phy.ops.write_reg(hw, 1707 IXGBE_MDIO_GLOBAL_RES_PR_10, 1708 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1709 reg); 1710 1711 if (status != IXGBE_SUCCESS) 1712 return status; 1713 } 1714 1715 return status; 1716} 1717 1718/** 1719 * ixgbe_setup_kr_x550em - Configure the KR PHY. 1720 * @hw: pointer to hardware structure 1721 * 1722 * Configures the integrated KR PHY. 1723 **/ 1724s32 ixgbe_setup_kr_x550em(struct ixgbe_hw *hw) 1725{ 1726 return ixgbe_setup_kr_speed_x550em(hw, hw->phy.autoneg_advertised); 1727} 1728 1729/** 1730 * ixgbe_setup_kx4_x550em - Configure the KX4 PHY. 1731 * @hw: pointer to hardware structure 1732 * 1733 * Configures the integrated KX4 PHY. 1734 **/ 1735s32 ixgbe_setup_kx4_x550em(struct ixgbe_hw *hw) 1736{ 1737 s32 status; 1738 u32 reg_val; 1739 1740 status = ixgbe_read_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1741 IXGBE_SB_IOSF_TARGET_KX4_PCS, ®_val); 1742 if (status) 1743 return status; 1744 1745 reg_val &= ~(IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4 | 1746 IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX); 1747 1748 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_ENABLE; 1749 1750 /* Advertise 10G support. */ 1751 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1752 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX4; 1753 1754 /* Advertise 1G support. */ 1755 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1756 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_CAP_KX; 1757 1758 /* Restart auto-negotiation. */ 1759 reg_val |= IXGBE_KX4_LINK_CNTL_1_TETH_AN_RESTART; 1760 status = ixgbe_write_iosf_sb_reg_x550(hw, IXGBE_KX4_LINK_CNTL_1, 1761 IXGBE_SB_IOSF_TARGET_KX4_PCS, reg_val); 1762 1763 return status; 1764} 1765 1766/** 1767 * ixgbe_setup_mac_link_sfp_x550em - Setup internal/external the PHY for SFP 1768 * @hw: pointer to hardware structure 1769 * 1770 * Configure the external PHY and the integrated KR PHY for SFP support. 1771 **/ 1772s32 ixgbe_setup_mac_link_sfp_x550em(struct ixgbe_hw *hw, 1773 ixgbe_link_speed speed, 1774 bool autoneg_wait_to_complete) 1775{ 1776 s32 ret_val; 1777 u16 reg_slice, reg_val; 1778 bool setup_linear = FALSE; 1779 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 1780 1781 /* Check if SFP module is supported and linear */ 1782 ret_val = ixgbe_supported_sfp_modules_X550em(hw, &setup_linear); 1783 1784 /* If no SFP module present, then return success. Return success since 1785 * there is no reason to configure CS4227 and SFP not present error is 1786 * not excepted in the setup MAC link flow. 1787 */ 1788 if (ret_val == IXGBE_ERR_SFP_NOT_PRESENT) 1789 return IXGBE_SUCCESS; 1790 1791 if (ret_val != IXGBE_SUCCESS) 1792 return ret_val; 1793 1794 /* Configure CS4227 for LINE connection rate then type. */ 1795 reg_slice = IXGBE_CS4227_LINE_SPARE22_MSB + (hw->bus.lan_id << 12); 1796 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; 1797 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1798 reg_val); 1799 1800 reg_slice = IXGBE_CS4227_LINE_SPARE24_LSB + (hw->bus.lan_id << 12); 1801 if (setup_linear) 1802 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1803 else 1804 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1805 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1806 reg_val); 1807 1808 /* Configure CS4227 for HOST connection rate then type. */ 1809 reg_slice = IXGBE_CS4227_HOST_SPARE22_MSB + (hw->bus.lan_id << 12); 1810 reg_val = (speed & IXGBE_LINK_SPEED_10GB_FULL) ? 0 : 0x8000; 1811 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1812 reg_val); 1813 1814 reg_slice = IXGBE_CS4227_HOST_SPARE24_LSB + (hw->bus.lan_id << 12); 1815 if (setup_linear) 1816 reg_val = (IXGBE_CS4227_EDC_MODE_CX1 << 1) | 0x1; 1817 else 1818 reg_val = (IXGBE_CS4227_EDC_MODE_SR << 1) | 0x1; 1819 ret_val = ixgbe_write_i2c_combined(hw, IXGBE_CS4227, reg_slice, 1820 reg_val); 1821 1822 /* If internal link mode is XFI, then setup XFI internal link. */ 1823 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) 1824 ret_val = ixgbe_setup_ixfi_x550em(hw, &speed); 1825 1826 return ret_val; 1827} 1828 1829/** 1830 * ixgbe_setup_ixfi_x550em - Configure the KR PHY for iXFI mode. 1831 * @hw: pointer to hardware structure 1832 * @speed: the link speed to force 1833 * 1834 * Configures the integrated KR PHY to use iXFI mode. Used to connect an 1835 * internal and external PHY at a specific speed, without autonegotiation. 1836 **/ 1837static s32 ixgbe_setup_ixfi_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed) 1838{ 1839 s32 status; 1840 u32 reg_val; 1841 1842 /* Disable AN and force speed to 10G Serial. */ 1843 status = ixgbe_read_iosf_sb_reg_x550(hw, 1844 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1845 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1846 if (status != IXGBE_SUCCESS) 1847 return status; 1848 1849 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 1850 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 1851 1852 /* Select forced link speed for internal PHY. */ 1853 switch (*speed) { 1854 case IXGBE_LINK_SPEED_10GB_FULL: 1855 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 1856 break; 1857 case IXGBE_LINK_SPEED_1GB_FULL: 1858 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G; 1859 break; 1860 default: 1861 /* Other link speeds are not supported by internal KR PHY. */ 1862 return IXGBE_ERR_LINK_SETUP; 1863 } 1864 1865 status = ixgbe_write_iosf_sb_reg_x550(hw, 1866 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1867 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1868 if (status != IXGBE_SUCCESS) 1869 return status; 1870 1871 /* Disable training protocol FSM. */ 1872 status = ixgbe_read_iosf_sb_reg_x550(hw, 1873 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1874 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1875 if (status != IXGBE_SUCCESS) 1876 return status; 1877 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL; 1878 status = ixgbe_write_iosf_sb_reg_x550(hw, 1879 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 1880 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1881 if (status != IXGBE_SUCCESS) 1882 return status; 1883 1884 /* Disable Flex from training TXFFE. */ 1885 status = ixgbe_read_iosf_sb_reg_x550(hw, 1886 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1887 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1888 if (status != IXGBE_SUCCESS) 1889 return status; 1890 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1891 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1892 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1893 status = ixgbe_write_iosf_sb_reg_x550(hw, 1894 IXGBE_KRM_DSP_TXFFE_STATE_4(hw->bus.lan_id), 1895 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1896 if (status != IXGBE_SUCCESS) 1897 return status; 1898 status = ixgbe_read_iosf_sb_reg_x550(hw, 1899 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1900 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1901 if (status != IXGBE_SUCCESS) 1902 return status; 1903 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_C0_EN; 1904 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN; 1905 reg_val &= ~IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN; 1906 status = ixgbe_write_iosf_sb_reg_x550(hw, 1907 IXGBE_KRM_DSP_TXFFE_STATE_5(hw->bus.lan_id), 1908 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1909 if (status != IXGBE_SUCCESS) 1910 return status; 1911 1912 /* Enable override for coefficients. */ 1913 status = ixgbe_read_iosf_sb_reg_x550(hw, 1914 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1915 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1916 if (status != IXGBE_SUCCESS) 1917 return status; 1918 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN; 1919 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN; 1920 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN; 1921 reg_val |= IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN; 1922 status = ixgbe_write_iosf_sb_reg_x550(hw, 1923 IXGBE_KRM_TX_COEFF_CTRL_1(hw->bus.lan_id), 1924 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1925 if (status != IXGBE_SUCCESS) 1926 return status; 1927 1928 /* Toggle port SW reset by AN reset. */ 1929 status = ixgbe_read_iosf_sb_reg_x550(hw, 1930 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1931 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 1932 if (status != IXGBE_SUCCESS) 1933 return status; 1934 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART; 1935 status = ixgbe_write_iosf_sb_reg_x550(hw, 1936 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 1937 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 1938 1939 return status; 1940} 1941 1942/** 1943 * ixgbe_ext_phy_t_x550em_get_link - Get ext phy link status 1944 * @hw: address of hardware structure 1945 * @link_up: address of boolean to indicate link status 1946 * 1947 * Returns error code if unable to get link status. 1948 */ 1949static s32 ixgbe_ext_phy_t_x550em_get_link(struct ixgbe_hw *hw, bool *link_up) 1950{ 1951 u32 ret; 1952 u16 autoneg_status; 1953 1954 *link_up = FALSE; 1955 1956 /* read this twice back to back to indicate current status */ 1957 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1958 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1959 &autoneg_status); 1960 if (ret != IXGBE_SUCCESS) 1961 return ret; 1962 1963 ret = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 1964 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1965 &autoneg_status); 1966 if (ret != IXGBE_SUCCESS) 1967 return ret; 1968 1969 *link_up = !!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS); 1970 1971 return IXGBE_SUCCESS; 1972} 1973 1974/** 1975 * ixgbe_setup_internal_phy_t_x550em - Configure KR PHY to X557 link 1976 * @hw: point to hardware structure 1977 * 1978 * Configures the link between the integrated KR PHY and the external X557 PHY 1979 * The driver will call this function when it gets a link status change 1980 * interrupt from the X557 PHY. This function configures the link speed 1981 * between the PHYs to match the link speed of the BASE-T link. 1982 * 1983 * A return of a non-zero value indicates an error, and the base driver should 1984 * not report link up. 1985 */ 1986s32 ixgbe_setup_internal_phy_t_x550em(struct ixgbe_hw *hw) 1987{ 1988 ixgbe_link_speed force_speed; 1989 bool link_up; 1990 u32 status; 1991 u16 speed; 1992 1993 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 1994 return IXGBE_ERR_CONFIG; 1995 1996 /* If link is not up, then there is no setup necessary so return */ 1997 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 1998 if (status != IXGBE_SUCCESS) 1999 return status; 2000 2001 if (!link_up) 2002 return IXGBE_SUCCESS; 2003 2004 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2005 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2006 &speed); 2007 if (status != IXGBE_SUCCESS) 2008 return status; 2009 2010 /* If link is not still up, then no setup is necessary so return */ 2011 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2012 if (status != IXGBE_SUCCESS) 2013 return status; 2014 if (!link_up) 2015 return IXGBE_SUCCESS; 2016 2017 /* clear everything but the speed and duplex bits */ 2018 speed &= IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK; 2019 2020 switch (speed) { 2021 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL: 2022 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 2023 break; 2024 case IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL: 2025 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 2026 break; 2027 default: 2028 /* Internal PHY does not support anything else */ 2029 return IXGBE_ERR_INVALID_LINK_SETTINGS; 2030 } 2031 2032 return ixgbe_setup_ixfi_x550em(hw, &force_speed); 2033} 2034 2035/** 2036 * ixgbe_setup_phy_loopback_x550em - Configure the KR PHY for loopback. 2037 * @hw: pointer to hardware structure 2038 * 2039 * Configures the integrated KR PHY to use internal loopback mode. 2040 **/ 2041s32 ixgbe_setup_phy_loopback_x550em(struct ixgbe_hw *hw) 2042{ 2043 s32 status; 2044 u32 reg_val; 2045 2046 /* Disable AN and force speed to 10G Serial. */ 2047 status = ixgbe_read_iosf_sb_reg_x550(hw, 2048 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2049 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2050 if (status != IXGBE_SUCCESS) 2051 return status; 2052 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE; 2053 reg_val &= ~IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK; 2054 reg_val |= IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G; 2055 status = ixgbe_write_iosf_sb_reg_x550(hw, 2056 IXGBE_KRM_LINK_CTRL_1(hw->bus.lan_id), 2057 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2058 if (status != IXGBE_SUCCESS) 2059 return status; 2060 2061 /* Set near-end loopback clocks. */ 2062 status = ixgbe_read_iosf_sb_reg_x550(hw, 2063 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2064 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2065 if (status != IXGBE_SUCCESS) 2066 return status; 2067 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B; 2068 reg_val |= IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS; 2069 status = ixgbe_write_iosf_sb_reg_x550(hw, 2070 IXGBE_KRM_PORT_CAR_GEN_CTRL(hw->bus.lan_id), 2071 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2072 if (status != IXGBE_SUCCESS) 2073 return status; 2074 2075 /* Set loopback enable. */ 2076 status = ixgbe_read_iosf_sb_reg_x550(hw, 2077 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2078 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2079 if (status != IXGBE_SUCCESS) 2080 return status; 2081 reg_val |= IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK; 2082 status = ixgbe_write_iosf_sb_reg_x550(hw, 2083 IXGBE_KRM_PMD_DFX_BURNIN(hw->bus.lan_id), 2084 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2085 if (status != IXGBE_SUCCESS) 2086 return status; 2087 2088 /* Training bypass. */ 2089 status = ixgbe_read_iosf_sb_reg_x550(hw, 2090 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2091 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2092 if (status != IXGBE_SUCCESS) 2093 return status; 2094 reg_val |= IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS; 2095 status = ixgbe_write_iosf_sb_reg_x550(hw, 2096 IXGBE_KRM_RX_TRN_LINKUP_CTRL(hw->bus.lan_id), 2097 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2098 2099 return status; 2100} 2101 2102/** 2103 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2104 * assuming that the semaphore is already obtained. 2105 * @hw: pointer to hardware structure 2106 * @offset: offset of word in the EEPROM to read 2107 * @data: word read from the EEPROM 2108 * 2109 * Reads a 16 bit word from the EEPROM using the hostif. 2110 **/ 2111s32 ixgbe_read_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2112 u16 *data) 2113{ 2114 s32 status; 2115 struct ixgbe_hic_read_shadow_ram buffer; 2116 2117 DEBUGFUNC("ixgbe_read_ee_hostif_data_X550"); 2118 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2119 buffer.hdr.req.buf_lenh = 0; 2120 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2121 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2122 2123 /* convert offset from words to bytes */ 2124 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2125 /* one word */ 2126 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2127 2128 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2129 sizeof(buffer), 2130 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2131 2132 if (status) 2133 return status; 2134 2135 *data = (u16)IXGBE_READ_REG_ARRAY(hw, IXGBE_FLEX_MNG, 2136 FW_NVM_DATA_OFFSET); 2137 2138 return 0; 2139} 2140 2141/** 2142 * ixgbe_read_ee_hostif_X550 - Read EEPROM word using a host interface command 2143 * @hw: pointer to hardware structure 2144 * @offset: offset of word in the EEPROM to read 2145 * @data: word read from the EEPROM 2146 * 2147 * Reads a 16 bit word from the EEPROM using the hostif. 2148 **/ 2149s32 ixgbe_read_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2150 u16 *data) 2151{ 2152 s32 status = IXGBE_SUCCESS; 2153 2154 DEBUGFUNC("ixgbe_read_ee_hostif_X550"); 2155 2156 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2157 IXGBE_SUCCESS) { 2158 status = ixgbe_read_ee_hostif_data_X550(hw, offset, data); 2159 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2160 } else { 2161 status = IXGBE_ERR_SWFW_SYNC; 2162 } 2163 2164 return status; 2165} 2166 2167/** 2168 * ixgbe_read_ee_hostif_buffer_X550- Read EEPROM word(s) using hostif 2169 * @hw: pointer to hardware structure 2170 * @offset: offset of word in the EEPROM to read 2171 * @words: number of words 2172 * @data: word(s) read from the EEPROM 2173 * 2174 * Reads a 16 bit word(s) from the EEPROM using the hostif. 2175 **/ 2176s32 ixgbe_read_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2177 u16 offset, u16 words, u16 *data) 2178{ 2179 struct ixgbe_hic_read_shadow_ram buffer; 2180 u32 current_word = 0; 2181 u16 words_to_read; 2182 s32 status; 2183 u32 i; 2184 2185 DEBUGFUNC("ixgbe_read_ee_hostif_buffer_X550"); 2186 2187 /* Take semaphore for the entire operation. */ 2188 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2189 if (status) { 2190 DEBUGOUT("EEPROM read buffer - semaphore failed\n"); 2191 return status; 2192 } 2193 while (words) { 2194 if (words > FW_MAX_READ_BUFFER_SIZE / 2) 2195 words_to_read = FW_MAX_READ_BUFFER_SIZE / 2; 2196 else 2197 words_to_read = words; 2198 2199 buffer.hdr.req.cmd = FW_READ_SHADOW_RAM_CMD; 2200 buffer.hdr.req.buf_lenh = 0; 2201 buffer.hdr.req.buf_lenl = FW_READ_SHADOW_RAM_LEN; 2202 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2203 2204 /* convert offset from words to bytes */ 2205 buffer.address = IXGBE_CPU_TO_BE32((offset + current_word) * 2); 2206 buffer.length = IXGBE_CPU_TO_BE16(words_to_read * 2); 2207 2208 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2209 sizeof(buffer), 2210 IXGBE_HI_COMMAND_TIMEOUT, 2211 FALSE); 2212 2213 if (status) { 2214 DEBUGOUT("Host interface command failed\n"); 2215 goto out; 2216 } 2217 2218 for (i = 0; i < words_to_read; i++) { 2219 u32 reg = IXGBE_FLEX_MNG + (FW_NVM_DATA_OFFSET << 2) + 2220 2 * i; 2221 u32 value = IXGBE_READ_REG(hw, reg); 2222 2223 data[current_word] = (u16)(value & 0xffff); 2224 current_word++; 2225 i++; 2226 if (i < words_to_read) { 2227 value >>= 16; 2228 data[current_word] = (u16)(value & 0xffff); 2229 current_word++; 2230 } 2231 } 2232 words -= words_to_read; 2233 } 2234 2235out: 2236 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2237 return status; 2238} 2239 2240/** 2241 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2242 * @hw: pointer to hardware structure 2243 * @offset: offset of word in the EEPROM to write 2244 * @data: word write to the EEPROM 2245 * 2246 * Write a 16 bit word to the EEPROM using the hostif. 2247 **/ 2248s32 ixgbe_write_ee_hostif_data_X550(struct ixgbe_hw *hw, u16 offset, 2249 u16 data) 2250{ 2251 s32 status; 2252 struct ixgbe_hic_write_shadow_ram buffer; 2253 2254 DEBUGFUNC("ixgbe_write_ee_hostif_data_X550"); 2255 2256 buffer.hdr.req.cmd = FW_WRITE_SHADOW_RAM_CMD; 2257 buffer.hdr.req.buf_lenh = 0; 2258 buffer.hdr.req.buf_lenl = FW_WRITE_SHADOW_RAM_LEN; 2259 buffer.hdr.req.checksum = FW_DEFAULT_CHECKSUM; 2260 2261 /* one word */ 2262 buffer.length = IXGBE_CPU_TO_BE16(sizeof(u16)); 2263 buffer.data = data; 2264 buffer.address = IXGBE_CPU_TO_BE32(offset * 2); 2265 2266 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2267 sizeof(buffer), 2268 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2269 2270 return status; 2271} 2272 2273/** 2274 * ixgbe_write_ee_hostif_X550 - Write EEPROM word using hostif 2275 * @hw: pointer to hardware structure 2276 * @offset: offset of word in the EEPROM to write 2277 * @data: word write to the EEPROM 2278 * 2279 * Write a 16 bit word to the EEPROM using the hostif. 2280 **/ 2281s32 ixgbe_write_ee_hostif_X550(struct ixgbe_hw *hw, u16 offset, 2282 u16 data) 2283{ 2284 s32 status = IXGBE_SUCCESS; 2285 2286 DEBUGFUNC("ixgbe_write_ee_hostif_X550"); 2287 2288 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 2289 IXGBE_SUCCESS) { 2290 status = ixgbe_write_ee_hostif_data_X550(hw, offset, data); 2291 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2292 } else { 2293 DEBUGOUT("write ee hostif failed to get semaphore"); 2294 status = IXGBE_ERR_SWFW_SYNC; 2295 } 2296 2297 return status; 2298} 2299 2300/** 2301 * ixgbe_write_ee_hostif_buffer_X550 - Write EEPROM word(s) using hostif 2302 * @hw: pointer to hardware structure 2303 * @offset: offset of word in the EEPROM to write 2304 * @words: number of words 2305 * @data: word(s) write to the EEPROM 2306 * 2307 * Write a 16 bit word(s) to the EEPROM using the hostif. 2308 **/ 2309s32 ixgbe_write_ee_hostif_buffer_X550(struct ixgbe_hw *hw, 2310 u16 offset, u16 words, u16 *data) 2311{ 2312 s32 status = IXGBE_SUCCESS; 2313 u32 i = 0; 2314 2315 DEBUGFUNC("ixgbe_write_ee_hostif_buffer_X550"); 2316 2317 /* Take semaphore for the entire operation. */ 2318 status = hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2319 if (status != IXGBE_SUCCESS) { 2320 DEBUGOUT("EEPROM write buffer - semaphore failed\n"); 2321 goto out; 2322 } 2323 2324 for (i = 0; i < words; i++) { 2325 status = ixgbe_write_ee_hostif_data_X550(hw, offset + i, 2326 data[i]); 2327 2328 if (status != IXGBE_SUCCESS) { 2329 DEBUGOUT("Eeprom buffered write failed\n"); 2330 break; 2331 } 2332 } 2333 2334 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 2335out: 2336 2337 return status; 2338} 2339 2340/** 2341 * ixgbe_checksum_ptr_x550 - Checksum one pointer region 2342 * @hw: pointer to hardware structure 2343 * @ptr: pointer offset in eeprom 2344 * @size: size of section pointed by ptr, if 0 first word will be used as size 2345 * @csum: address of checksum to update 2346 * 2347 * Returns error status for any failure 2348 */ 2349static s32 ixgbe_checksum_ptr_x550(struct ixgbe_hw *hw, u16 ptr, 2350 u16 size, u16 *csum, u16 *buffer, 2351 u32 buffer_size) 2352{ 2353 u16 buf[256]; 2354 s32 status; 2355 u16 length, bufsz, i, start; 2356 u16 *local_buffer; 2357 2358 bufsz = sizeof(buf) / sizeof(buf[0]); 2359 2360 /* Read a chunk at the pointer location */ 2361 if (!buffer) { 2362 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, bufsz, buf); 2363 if (status) { 2364 DEBUGOUT("Failed to read EEPROM image\n"); 2365 return status; 2366 } 2367 local_buffer = buf; 2368 } else { 2369 if (buffer_size < ptr) 2370 return IXGBE_ERR_PARAM; 2371 local_buffer = &buffer[ptr]; 2372 } 2373 2374 if (size) { 2375 start = 0; 2376 length = size; 2377 } else { 2378 start = 1; 2379 length = local_buffer[0]; 2380 2381 /* Skip pointer section if length is invalid. */ 2382 if (length == 0xFFFF || length == 0 || 2383 (ptr + length) >= hw->eeprom.word_size) 2384 return IXGBE_SUCCESS; 2385 } 2386 2387 if (buffer && ((u32)start + (u32)length > buffer_size)) 2388 return IXGBE_ERR_PARAM; 2389 2390 for (i = start; length; i++, length--) { 2391 if (i == bufsz && !buffer) { 2392 ptr += bufsz; 2393 i = 0; 2394 if (length < bufsz) 2395 bufsz = length; 2396 2397 /* Read a chunk at the pointer location */ 2398 status = ixgbe_read_ee_hostif_buffer_X550(hw, ptr, 2399 bufsz, buf); 2400 if (status) { 2401 DEBUGOUT("Failed to read EEPROM image\n"); 2402 return status; 2403 } 2404 } 2405 *csum += local_buffer[i]; 2406 } 2407 return IXGBE_SUCCESS; 2408} 2409 2410/** 2411 * ixgbe_calc_checksum_X550 - Calculates and returns the checksum 2412 * @hw: pointer to hardware structure 2413 * @buffer: pointer to buffer containing calculated checksum 2414 * @buffer_size: size of buffer 2415 * 2416 * Returns a negative error code on error, or the 16-bit checksum 2417 **/ 2418s32 ixgbe_calc_checksum_X550(struct ixgbe_hw *hw, u16 *buffer, u32 buffer_size) 2419{ 2420 u16 eeprom_ptrs[IXGBE_EEPROM_LAST_WORD + 1]; 2421 u16 *local_buffer; 2422 s32 status; 2423 u16 checksum = 0; 2424 u16 pointer, i, size; 2425 2426 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X550"); 2427 2428 hw->eeprom.ops.init_params(hw); 2429 2430 if (!buffer) { 2431 /* Read pointer area */ 2432 status = ixgbe_read_ee_hostif_buffer_X550(hw, 0, 2433 IXGBE_EEPROM_LAST_WORD + 1, 2434 eeprom_ptrs); 2435 if (status) { 2436 DEBUGOUT("Failed to read EEPROM image\n"); 2437 return status; 2438 } 2439 local_buffer = eeprom_ptrs; 2440 } else { 2441 if (buffer_size < IXGBE_EEPROM_LAST_WORD) 2442 return IXGBE_ERR_PARAM; 2443 local_buffer = buffer; 2444 } 2445 2446 /* 2447 * For X550 hardware include 0x0-0x41 in the checksum, skip the 2448 * checksum word itself 2449 */ 2450 for (i = 0; i <= IXGBE_EEPROM_LAST_WORD; i++) 2451 if (i != IXGBE_EEPROM_CHECKSUM) 2452 checksum += local_buffer[i]; 2453 2454 /* 2455 * Include all data from pointers 0x3, 0x6-0xE. This excludes the 2456 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 2457 */ 2458 for (i = IXGBE_PCIE_ANALOG_PTR_X550; i < IXGBE_FW_PTR; i++) { 2459 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 2460 continue; 2461 2462 pointer = local_buffer[i]; 2463 2464 /* Skip pointer section if the pointer is invalid. */ 2465 if (pointer == 0xFFFF || pointer == 0 || 2466 pointer >= hw->eeprom.word_size) 2467 continue; 2468 2469 switch (i) { 2470 case IXGBE_PCIE_GENERAL_PTR: 2471 size = IXGBE_IXGBE_PCIE_GENERAL_SIZE; 2472 break; 2473 case IXGBE_PCIE_CONFIG0_PTR: 2474 case IXGBE_PCIE_CONFIG1_PTR: 2475 size = IXGBE_PCIE_CONFIG_SIZE; 2476 break; 2477 default: 2478 size = 0; 2479 break; 2480 } 2481 2482 status = ixgbe_checksum_ptr_x550(hw, pointer, size, &checksum, 2483 buffer, buffer_size); 2484 if (status) 2485 return status; 2486 } 2487 2488 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 2489 2490 return (s32)checksum; 2491} 2492 2493/** 2494 * ixgbe_calc_eeprom_checksum_X550 - Calculates and returns the checksum 2495 * @hw: pointer to hardware structure 2496 * 2497 * Returns a negative error code on error, or the 16-bit checksum 2498 **/ 2499s32 ixgbe_calc_eeprom_checksum_X550(struct ixgbe_hw *hw) 2500{ 2501 return ixgbe_calc_checksum_X550(hw, NULL, 0); 2502} 2503 2504/** 2505 * ixgbe_validate_eeprom_checksum_X550 - Validate EEPROM checksum 2506 * @hw: pointer to hardware structure 2507 * @checksum_val: calculated checksum 2508 * 2509 * Performs checksum calculation and validates the EEPROM checksum. If the 2510 * caller does not need checksum_val, the value can be NULL. 2511 **/ 2512s32 ixgbe_validate_eeprom_checksum_X550(struct ixgbe_hw *hw, u16 *checksum_val) 2513{ 2514 s32 status; 2515 u16 checksum; 2516 u16 read_checksum = 0; 2517 2518 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X550"); 2519 2520 /* Read the first word from the EEPROM. If this times out or fails, do 2521 * not continue or we could be in for a very long wait while every 2522 * EEPROM read fails 2523 */ 2524 status = hw->eeprom.ops.read(hw, 0, &checksum); 2525 if (status) { 2526 DEBUGOUT("EEPROM read failed\n"); 2527 return status; 2528 } 2529 2530 status = hw->eeprom.ops.calc_checksum(hw); 2531 if (status < 0) 2532 return status; 2533 2534 checksum = (u16)(status & 0xffff); 2535 2536 status = ixgbe_read_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2537 &read_checksum); 2538 if (status) 2539 return status; 2540 2541 /* Verify read checksum from EEPROM is the same as 2542 * calculated checksum 2543 */ 2544 if (read_checksum != checksum) { 2545 status = IXGBE_ERR_EEPROM_CHECKSUM; 2546 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 2547 "Invalid EEPROM checksum"); 2548 } 2549 2550 /* If the user cares, return the calculated checksum */ 2551 if (checksum_val) 2552 *checksum_val = checksum; 2553 2554 return status; 2555} 2556 2557/** 2558 * ixgbe_update_eeprom_checksum_X550 - Updates the EEPROM checksum and flash 2559 * @hw: pointer to hardware structure 2560 * 2561 * After writing EEPROM to shadow RAM using EEWR register, software calculates 2562 * checksum and updates the EEPROM and instructs the hardware to update 2563 * the flash. 2564 **/ 2565s32 ixgbe_update_eeprom_checksum_X550(struct ixgbe_hw *hw) 2566{ 2567 s32 status; 2568 u16 checksum = 0; 2569 2570 DEBUGFUNC("ixgbe_update_eeprom_checksum_X550"); 2571 2572 /* Read the first word from the EEPROM. If this times out or fails, do 2573 * not continue or we could be in for a very long wait while every 2574 * EEPROM read fails 2575 */ 2576 status = ixgbe_read_ee_hostif_X550(hw, 0, &checksum); 2577 if (status) { 2578 DEBUGOUT("EEPROM read failed\n"); 2579 return status; 2580 } 2581 2582 status = ixgbe_calc_eeprom_checksum_X550(hw); 2583 if (status < 0) 2584 return status; 2585 2586 checksum = (u16)(status & 0xffff); 2587 2588 status = ixgbe_write_ee_hostif_X550(hw, IXGBE_EEPROM_CHECKSUM, 2589 checksum); 2590 if (status) 2591 return status; 2592 2593 status = ixgbe_update_flash_X550(hw); 2594 2595 return status; 2596} 2597 2598/** 2599 * ixgbe_update_flash_X550 - Instruct HW to copy EEPROM to Flash device 2600 * @hw: pointer to hardware structure 2601 * 2602 * Issue a shadow RAM dump to FW to copy EEPROM from shadow RAM to the flash. 2603 **/ 2604s32 ixgbe_update_flash_X550(struct ixgbe_hw *hw) 2605{ 2606 s32 status = IXGBE_SUCCESS; 2607 union ixgbe_hic_hdr2 buffer; 2608 2609 DEBUGFUNC("ixgbe_update_flash_X550"); 2610 2611 buffer.req.cmd = FW_SHADOW_RAM_DUMP_CMD; 2612 buffer.req.buf_lenh = 0; 2613 buffer.req.buf_lenl = FW_SHADOW_RAM_DUMP_LEN; 2614 buffer.req.checksum = FW_DEFAULT_CHECKSUM; 2615 2616 status = ixgbe_host_interface_command(hw, (u32 *)&buffer, 2617 sizeof(buffer), 2618 IXGBE_HI_COMMAND_TIMEOUT, FALSE); 2619 2620 return status; 2621} 2622 2623/** 2624 * ixgbe_get_supported_physical_layer_X550em - Returns physical layer type 2625 * @hw: pointer to hardware structure 2626 * 2627 * Determines physical layer capabilities of the current configuration. 2628 **/ 2629u32 ixgbe_get_supported_physical_layer_X550em(struct ixgbe_hw *hw) 2630{ 2631 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 2632 u16 ext_ability = 0; 2633 2634 DEBUGFUNC("ixgbe_get_supported_physical_layer_X550em"); 2635 2636 hw->phy.ops.identify(hw); 2637 2638 switch (hw->phy.type) { 2639 case ixgbe_phy_x550em_kr: 2640 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KR | 2641 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2642 break; 2643 case ixgbe_phy_x550em_kx4: 2644 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_KX4 | 2645 IXGBE_PHYSICAL_LAYER_1000BASE_KX; 2646 break; 2647 case ixgbe_phy_x550em_ext_t: 2648 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 2649 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 2650 &ext_ability); 2651 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 2652 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 2653 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 2654 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 2655 break; 2656 default: 2657 break; 2658 } 2659 2660 if (hw->mac.ops.get_media_type(hw) == ixgbe_media_type_fiber) 2661 physical_layer = ixgbe_get_supported_phy_sfp_layer_generic(hw); 2662 2663 return physical_layer; 2664} 2665 2666/** 2667 * ixgbe_get_bus_info_x550em - Set PCI bus info 2668 * @hw: pointer to hardware structure 2669 * 2670 * Sets bus link width and speed to unknown because X550em is 2671 * not a PCI device. 2672 **/ 2673s32 ixgbe_get_bus_info_X550em(struct ixgbe_hw *hw) 2674{ 2675 2676 DEBUGFUNC("ixgbe_get_bus_info_x550em"); 2677 2678 hw->bus.width = ixgbe_bus_width_unknown; 2679 hw->bus.speed = ixgbe_bus_speed_unknown; 2680 2681 hw->mac.ops.set_lan_id(hw); 2682 2683 return IXGBE_SUCCESS; 2684} 2685 2686/** 2687 * ixgbe_disable_rx_x550 - Disable RX unit 2688 * 2689 * Enables the Rx DMA unit for x550 2690 **/ 2691void ixgbe_disable_rx_x550(struct ixgbe_hw *hw) 2692{ 2693 u32 rxctrl, pfdtxgswc; 2694 s32 status; 2695 struct ixgbe_hic_disable_rxen fw_cmd; 2696 2697 DEBUGFUNC("ixgbe_enable_rx_dma_x550"); 2698 2699 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2700 if (rxctrl & IXGBE_RXCTRL_RXEN) { 2701 pfdtxgswc = IXGBE_READ_REG(hw, IXGBE_PFDTXGSWC); 2702 if (pfdtxgswc & IXGBE_PFDTXGSWC_VT_LBEN) { 2703 pfdtxgswc &= ~IXGBE_PFDTXGSWC_VT_LBEN; 2704 IXGBE_WRITE_REG(hw, IXGBE_PFDTXGSWC, pfdtxgswc); 2705 hw->mac.set_lben = TRUE; 2706 } else { 2707 hw->mac.set_lben = FALSE; 2708 } 2709 2710 fw_cmd.hdr.cmd = FW_DISABLE_RXEN_CMD; 2711 fw_cmd.hdr.buf_len = FW_DISABLE_RXEN_LEN; 2712 fw_cmd.hdr.checksum = FW_DEFAULT_CHECKSUM; 2713 fw_cmd.port_number = (u8)hw->bus.lan_id; 2714 2715 status = ixgbe_host_interface_command(hw, (u32 *)&fw_cmd, 2716 sizeof(struct ixgbe_hic_disable_rxen), 2717 IXGBE_HI_COMMAND_TIMEOUT, TRUE); 2718 2719 /* If we fail - disable RX using register write */ 2720 if (status) { 2721 rxctrl = IXGBE_READ_REG(hw, IXGBE_RXCTRL); 2722 if (rxctrl & IXGBE_RXCTRL_RXEN) { 2723 rxctrl &= ~IXGBE_RXCTRL_RXEN; 2724 IXGBE_WRITE_REG(hw, IXGBE_RXCTRL, rxctrl); 2725 } 2726 } 2727 } 2728} 2729 2730/** 2731 * ixgbe_enter_lplu_x550em - Transition to low power states 2732 * @hw: pointer to hardware structure 2733 * 2734 * Configures Low Power Link Up on transition to low power states 2735 * (from D0 to non-D0). Link is required to enter LPLU so avoid resetting the 2736 * X557 PHY immediately prior to entering LPLU. 2737 **/ 2738s32 ixgbe_enter_lplu_t_x550em(struct ixgbe_hw *hw) 2739{ 2740 u16 an_10g_cntl_reg, autoneg_reg, speed; 2741 s32 status; 2742 ixgbe_link_speed lcd_speed; 2743 u32 save_autoneg; 2744 bool link_up; 2745 2746 /* If blocked by MNG FW, then don't restart AN */ 2747 if (ixgbe_check_reset_blocked(hw)) 2748 return IXGBE_SUCCESS; 2749 2750 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2751 if (status != IXGBE_SUCCESS) 2752 return status; 2753 2754 status = ixgbe_read_eeprom(hw, NVM_INIT_CTRL_3, &hw->eeprom.ctrl_word_3); 2755 2756 if (status != IXGBE_SUCCESS) 2757 return status; 2758 2759 /* If link is down, LPLU disabled in NVM, WoL disabled, or manageability 2760 * disabled, then force link down by entering low power mode. 2761 */ 2762 if (!link_up || !(hw->eeprom.ctrl_word_3 & NVM_INIT_CTRL_3_LPLU) || 2763 !(hw->wol_enabled || ixgbe_mng_present(hw))) 2764 return ixgbe_set_copper_phy_power(hw, FALSE); 2765 2766 /* Determine LCD */ 2767 status = ixgbe_get_lcd_t_x550em(hw, &lcd_speed); 2768 2769 if (status != IXGBE_SUCCESS) 2770 return status; 2771 2772 /* If no valid LCD link speed, then force link down and exit. */ 2773 if (lcd_speed == IXGBE_LINK_SPEED_UNKNOWN) 2774 return ixgbe_set_copper_phy_power(hw, FALSE); 2775 2776 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_STAT, 2777 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2778 &speed); 2779 2780 if (status != IXGBE_SUCCESS) 2781 return status; 2782 2783 /* If no link now, speed is invalid so take link down */ 2784 status = ixgbe_ext_phy_t_x550em_get_link(hw, &link_up); 2785 if (status != IXGBE_SUCCESS) 2786 return ixgbe_set_copper_phy_power(hw, FALSE); 2787 2788 /* clear everything but the speed bits */ 2789 speed &= IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK; 2790 2791 /* If current speed is already LCD, then exit. */ 2792 if (((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB) && 2793 (lcd_speed == IXGBE_LINK_SPEED_1GB_FULL)) || 2794 ((speed == IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB) && 2795 (lcd_speed == IXGBE_LINK_SPEED_10GB_FULL))) 2796 return status; 2797 2798 /* Clear AN completed indication */ 2799 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM, 2800 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2801 &autoneg_reg); 2802 2803 if (status != IXGBE_SUCCESS) 2804 return status; 2805 2806 status = hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 2807 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2808 &an_10g_cntl_reg); 2809 2810 if (status != IXGBE_SUCCESS) 2811 return status; 2812 2813 status = hw->phy.ops.read_reg(hw, 2814 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 2815 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2816 &autoneg_reg); 2817 2818 if (status != IXGBE_SUCCESS) 2819 return status; 2820 2821 save_autoneg = hw->phy.autoneg_advertised; 2822 2823 /* Setup link at least common link speed */ 2824 status = hw->mac.ops.setup_link(hw, lcd_speed, FALSE); 2825 2826 /* restore autoneg from before setting lplu speed */ 2827 hw->phy.autoneg_advertised = save_autoneg; 2828 2829 return status; 2830} 2831 2832/** 2833 * ixgbe_get_lcd_x550em - Determine lowest common denominator 2834 * @hw: pointer to hardware structure 2835 * @lcd_speed: pointer to lowest common link speed 2836 * 2837 * Determine lowest common link speed with link partner. 2838 **/ 2839s32 ixgbe_get_lcd_t_x550em(struct ixgbe_hw *hw, ixgbe_link_speed *lcd_speed) 2840{ 2841 u16 an_lp_status; 2842 s32 status; 2843 u16 word = hw->eeprom.ctrl_word_3; 2844 2845 *lcd_speed = IXGBE_LINK_SPEED_UNKNOWN; 2846 2847 status = hw->phy.ops.read_reg(hw, IXGBE_AUTO_NEG_LP_STATUS, 2848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 2849 &an_lp_status); 2850 2851 if (status != IXGBE_SUCCESS) 2852 return status; 2853 2854 /* If link partner advertised 1G, return 1G */ 2855 if (an_lp_status & IXGBE_AUTO_NEG_LP_1000BASE_CAP) { 2856 *lcd_speed = IXGBE_LINK_SPEED_1GB_FULL; 2857 return status; 2858 } 2859 2860 /* If 10G disabled for LPLU via NVM D10GMP, then return no valid LCD */ 2861 if ((hw->bus.lan_id && (word & NVM_INIT_CTRL_3_D10GMP_PORT1)) || 2862 (word & NVM_INIT_CTRL_3_D10GMP_PORT0)) 2863 return status; 2864 2865 /* Link partner not capable of lower speeds, return 10G */ 2866 *lcd_speed = IXGBE_LINK_SPEED_10GB_FULL; 2867 return status; 2868} 2869 2870/** 2871 * ixgbe_setup_fc_X550em - Set up flow control 2872 * @hw: pointer to hardware structure 2873 * 2874 * Called at init time to set up flow control. 2875 **/ 2876s32 ixgbe_setup_fc_X550em(struct ixgbe_hw *hw) 2877{ 2878 s32 ret_val = IXGBE_SUCCESS; 2879 u32 pause, asm_dir, reg_val; 2880 2881 DEBUGFUNC("ixgbe_setup_fc_X550em"); 2882 2883 /* Validate the requested mode */ 2884 if (hw->fc.strict_ieee && hw->fc.requested_mode == ixgbe_fc_rx_pause) { 2885 ERROR_REPORT1(IXGBE_ERROR_UNSUPPORTED, 2886 "ixgbe_fc_rx_pause not valid in strict IEEE mode\n"); 2887 ret_val = IXGBE_ERR_INVALID_LINK_SETTINGS; 2888 goto out; 2889 } 2890 2891 /* 10gig parts do not have a word in the EEPROM to determine the 2892 * default flow control setting, so we explicitly set it to full. 2893 */ 2894 if (hw->fc.requested_mode == ixgbe_fc_default) 2895 hw->fc.requested_mode = ixgbe_fc_full; 2896 2897 /* Determine PAUSE and ASM_DIR bits. */ 2898 switch (hw->fc.requested_mode) { 2899 case ixgbe_fc_none: 2900 pause = 0; 2901 asm_dir = 0; 2902 break; 2903 case ixgbe_fc_tx_pause: 2904 pause = 0; 2905 asm_dir = 1; 2906 break; 2907 case ixgbe_fc_rx_pause: 2908 /* Rx Flow control is enabled and Tx Flow control is 2909 * disabled by software override. Since there really 2910 * isn't a way to advertise that we are capable of RX 2911 * Pause ONLY, we will advertise that we support both 2912 * symmetric and asymmetric Rx PAUSE, as such we fall 2913 * through to the fc_full statement. Later, we will 2914 * disable the adapter's ability to send PAUSE frames. 2915 */ 2916 case ixgbe_fc_full: 2917 pause = 1; 2918 asm_dir = 1; 2919 break; 2920 default: 2921 ERROR_REPORT1(IXGBE_ERROR_ARGUMENT, 2922 "Flow control param set incorrectly\n"); 2923 ret_val = IXGBE_ERR_CONFIG; 2924 goto out; 2925 } 2926 2927 if (hw->phy.media_type == ixgbe_media_type_backplane) { 2928 ret_val = ixgbe_read_iosf_sb_reg_x550(hw, 2929 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2930 IXGBE_SB_IOSF_TARGET_KR_PHY, ®_val); 2931 if (ret_val != IXGBE_SUCCESS) 2932 goto out; 2933 reg_val &= ~(IXGBE_KRM_AN_CNTL_1_SYM_PAUSE | 2934 IXGBE_KRM_AN_CNTL_1_ASM_PAUSE); 2935 if (pause) 2936 reg_val |= IXGBE_KRM_AN_CNTL_1_SYM_PAUSE; 2937 if (asm_dir) 2938 reg_val |= IXGBE_KRM_AN_CNTL_1_ASM_PAUSE; 2939 ret_val = ixgbe_write_iosf_sb_reg_x550(hw, 2940 IXGBE_KRM_AN_CNTL_1(hw->bus.lan_id), 2941 IXGBE_SB_IOSF_TARGET_KR_PHY, reg_val); 2942 2943 /* Not all devices fully support AN. */ 2944 if (hw->device_id == IXGBE_DEV_ID_X550EM_X_KR) 2945 hw->fc.disable_fc_autoneg = TRUE; 2946 } 2947 2948out: 2949 return ret_val; 2950} 2951 2952/** 2953 * ixgbe_set_mux - Set mux for port 1 access with CS4227 2954 * @hw: pointer to hardware structure 2955 * @state: set mux if 1, clear if 0 2956 */ 2957static void ixgbe_set_mux(struct ixgbe_hw *hw, u8 state) 2958{ 2959 u32 esdp; 2960 2961 if (!hw->bus.lan_id) 2962 return; 2963 esdp = IXGBE_READ_REG(hw, IXGBE_ESDP); 2964 if (state) 2965 esdp |= IXGBE_ESDP_SDP1; 2966 else 2967 esdp &= ~IXGBE_ESDP_SDP1; 2968 IXGBE_WRITE_REG(hw, IXGBE_ESDP, esdp); 2969 IXGBE_WRITE_FLUSH(hw); 2970} 2971 2972/** 2973 * ixgbe_acquire_swfw_sync_X550em - Acquire SWFW semaphore 2974 * @hw: pointer to hardware structure 2975 * @mask: Mask to specify which semaphore to acquire 2976 * 2977 * Acquires the SWFW semaphore and sets the I2C MUX 2978 **/ 2979s32 ixgbe_acquire_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 2980{ 2981 s32 status; 2982 2983 DEBUGFUNC("ixgbe_acquire_swfw_sync_X550em"); 2984 2985 status = ixgbe_acquire_swfw_sync_X540(hw, mask); 2986 if (status) 2987 return status; 2988 2989 if (mask & IXGBE_GSSR_I2C_MASK) 2990 ixgbe_set_mux(hw, 1); 2991 2992 return IXGBE_SUCCESS; 2993} 2994 2995/** 2996 * ixgbe_release_swfw_sync_X550em - Release SWFW semaphore 2997 * @hw: pointer to hardware structure 2998 * @mask: Mask to specify which semaphore to release 2999 * 3000 * Releases the SWFW semaphore and sets the I2C MUX 3001 **/ 3002void ixgbe_release_swfw_sync_X550em(struct ixgbe_hw *hw, u32 mask) 3003{ 3004 DEBUGFUNC("ixgbe_release_swfw_sync_X550em"); 3005 3006 if (mask & IXGBE_GSSR_I2C_MASK) 3007 ixgbe_set_mux(hw, 0); 3008 3009 ixgbe_release_swfw_sync_X540(hw, mask); 3010} 3011 3012/** 3013 * ixgbe_handle_lasi_ext_t_x550em - Handle external Base T PHY interrupt 3014 * @hw: pointer to hardware structure 3015 * 3016 * Handle external Base T PHY interrupt. If high temperature 3017 * failure alarm then return error, else if link status change 3018 * then setup internal/external PHY link 3019 * 3020 * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 3021 * failure alarm, else return PHY access status. 3022 */ 3023s32 ixgbe_handle_lasi_ext_t_x550em(struct ixgbe_hw *hw) 3024{ 3025 bool lsc; 3026 u32 status; 3027 3028 status = ixgbe_get_lasi_ext_t_x550em(hw, &lsc); 3029 3030 if (status != IXGBE_SUCCESS) 3031 return status; 3032 3033 if (lsc) 3034 return ixgbe_setup_internal_phy(hw); 3035 3036 return IXGBE_SUCCESS; 3037} 3038 3039/** 3040 * ixgbe_setup_mac_link_t_X550em - Sets the auto advertised link speed 3041 * @hw: pointer to hardware structure 3042 * @speed: new link speed 3043 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 3044 * 3045 * Setup internal/external PHY link speed based on link speed, then set 3046 * external PHY auto advertised link speed. 3047 * 3048 * Returns error status for any failure 3049 **/ 3050s32 ixgbe_setup_mac_link_t_X550em(struct ixgbe_hw *hw, 3051 ixgbe_link_speed speed, 3052 bool autoneg_wait_to_complete) 3053{ 3054 s32 status; 3055 ixgbe_link_speed force_speed; 3056 3057 DEBUGFUNC("ixgbe_setup_mac_link_t_X550em"); 3058 3059 /* Setup internal/external PHY link speed to iXFI (10G), unless 3060 * only 1G is auto advertised then setup KX link. 3061 */ 3062 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 3063 force_speed = IXGBE_LINK_SPEED_10GB_FULL; 3064 else 3065 force_speed = IXGBE_LINK_SPEED_1GB_FULL; 3066 3067 /* If internal link mode is XFI, then setup XFI internal link. */ 3068 if (!(hw->phy.nw_mng_if_sel & IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE)) { 3069 status = ixgbe_setup_ixfi_x550em(hw, &force_speed); 3070 3071 if (status != IXGBE_SUCCESS) 3072 return status; 3073 } 3074 3075 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 3076} 3077 3078/** 3079 * ixgbe_check_link_t_X550em - Determine link and speed status 3080 * @hw: pointer to hardware structure 3081 * @speed: pointer to link speed 3082 * @link_up: TRUE when link is up 3083 * @link_up_wait_to_complete: bool used to wait for link up or not 3084 * 3085 * Check that both the MAC and X557 external PHY have link. 3086 **/ 3087s32 ixgbe_check_link_t_X550em(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 3088 bool *link_up, bool link_up_wait_to_complete) 3089{ 3090 u32 status; 3091 u16 autoneg_status; 3092 3093 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_copper) 3094 return IXGBE_ERR_CONFIG; 3095 3096 status = ixgbe_check_mac_link_generic(hw, speed, link_up, 3097 link_up_wait_to_complete); 3098 3099 /* If check link fails or MAC link is not up, then return */ 3100 if (status != IXGBE_SUCCESS || !(*link_up)) 3101 return status; 3102 3103 /* MAC link is up, so check external PHY link. 3104 * Read this twice back to back to indicate current status. 3105 */ 3106 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3107 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3108 &autoneg_status); 3109 3110 if (status != IXGBE_SUCCESS) 3111 return status; 3112 3113 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_STATUS, 3114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 3115 &autoneg_status); 3116 3117 if (status != IXGBE_SUCCESS) 3118 return status; 3119 3120 /* If external PHY link is not up, then indicate link not up */ 3121 if (!(autoneg_status & IXGBE_MDIO_AUTO_NEG_LINK_STATUS)) 3122 *link_up = FALSE; 3123 3124 return IXGBE_SUCCESS; 3125} 3126 3127/** 3128 * ixgbe_reset_phy_t_X550em - Performs X557 PHY reset and enables LASI 3129 * @hw: pointer to hardware structure 3130 **/ 3131s32 ixgbe_reset_phy_t_X550em(struct ixgbe_hw *hw) 3132{ 3133 s32 status; 3134 3135 status = ixgbe_reset_phy_generic(hw); 3136 3137 if (status != IXGBE_SUCCESS) 3138 return status; 3139 3140 /* Configure Link Status Alarm and Temperature Threshold interrupts */ 3141 return ixgbe_enable_lasi_ext_t_x550em(hw); 3142} 3143 3144/** 3145 * ixgbe_led_on_t_X550em - Turns on the software controllable LEDs. 3146 * @hw: pointer to hardware structure 3147 * @led_idx: led number to turn on 3148 **/ 3149s32 ixgbe_led_on_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3150{ 3151 u16 phy_data; 3152 3153 DEBUGFUNC("ixgbe_led_on_t_X550em"); 3154 3155 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3156 return IXGBE_ERR_PARAM; 3157 3158 /* To turn on the LED, set mode to ON. */ 3159 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3160 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3161 phy_data |= IXGBE_X557_LED_MANUAL_SET_MASK; 3162 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3163 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3164 3165 return IXGBE_SUCCESS; 3166} 3167 3168/** 3169 * ixgbe_led_off_t_X550em - Turns off the software controllable LEDs. 3170 * @hw: pointer to hardware structure 3171 * @led_idx: led number to turn off 3172 **/ 3173s32 ixgbe_led_off_t_X550em(struct ixgbe_hw *hw, u32 led_idx) 3174{ 3175 u16 phy_data; 3176 3177 DEBUGFUNC("ixgbe_led_off_t_X550em"); 3178 3179 if (led_idx >= IXGBE_X557_MAX_LED_INDEX) 3180 return IXGBE_ERR_PARAM; 3181 3182 /* To turn on the LED, set mode to ON. */ 3183 ixgbe_read_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3184 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, &phy_data); 3185 phy_data &= ~IXGBE_X557_LED_MANUAL_SET_MASK; 3186 ixgbe_write_phy_reg(hw, IXGBE_X557_LED_PROVISIONING + led_idx, 3187 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, phy_data); 3188 3189 return IXGBE_SUCCESS; 3190} 3191 3192