ixgbe_x540.c revision 315333
1/****************************************************************************** 2 3 Copyright (c) 2001-2017, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_x540.c 315333 2017-03-15 21:20:17Z erj $*/ 34 35#include "ixgbe_x540.h" 36#include "ixgbe_type.h" 37#include "ixgbe_api.h" 38#include "ixgbe_common.h" 39#include "ixgbe_phy.h" 40 41#define IXGBE_X540_MAX_TX_QUEUES 128 42#define IXGBE_X540_MAX_RX_QUEUES 128 43#define IXGBE_X540_RAR_ENTRIES 128 44#define IXGBE_X540_MC_TBL_SIZE 128 45#define IXGBE_X540_VFT_TBL_SIZE 128 46#define IXGBE_X540_RX_PB_SIZE 384 47 48static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw); 49static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw); 50static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw); 51 52/** 53 * ixgbe_init_ops_X540 - Inits func ptrs and MAC type 54 * @hw: pointer to hardware structure 55 * 56 * Initialize the function pointers and assign the MAC type for X540. 57 * Does not touch the hardware. 58 **/ 59s32 ixgbe_init_ops_X540(struct ixgbe_hw *hw) 60{ 61 struct ixgbe_mac_info *mac = &hw->mac; 62 struct ixgbe_phy_info *phy = &hw->phy; 63 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 64 s32 ret_val; 65 66 DEBUGFUNC("ixgbe_init_ops_X540"); 67 68 ret_val = ixgbe_init_phy_ops_generic(hw); 69 ret_val = ixgbe_init_ops_generic(hw); 70 71 72 /* EEPROM */ 73 eeprom->ops.init_params = ixgbe_init_eeprom_params_X540; 74 eeprom->ops.read = ixgbe_read_eerd_X540; 75 eeprom->ops.read_buffer = ixgbe_read_eerd_buffer_X540; 76 eeprom->ops.write = ixgbe_write_eewr_X540; 77 eeprom->ops.write_buffer = ixgbe_write_eewr_buffer_X540; 78 eeprom->ops.update_checksum = ixgbe_update_eeprom_checksum_X540; 79 eeprom->ops.validate_checksum = ixgbe_validate_eeprom_checksum_X540; 80 eeprom->ops.calc_checksum = ixgbe_calc_eeprom_checksum_X540; 81 82 /* PHY */ 83 phy->ops.init = ixgbe_init_phy_ops_generic; 84 phy->ops.reset = NULL; 85 phy->ops.set_phy_power = ixgbe_set_copper_phy_power; 86 87 /* MAC */ 88 mac->ops.reset_hw = ixgbe_reset_hw_X540; 89 mac->ops.enable_relaxed_ordering = ixgbe_enable_relaxed_ordering_gen2; 90 mac->ops.get_media_type = ixgbe_get_media_type_X540; 91 mac->ops.get_supported_physical_layer = 92 ixgbe_get_supported_physical_layer_X540; 93 mac->ops.read_analog_reg8 = NULL; 94 mac->ops.write_analog_reg8 = NULL; 95 mac->ops.start_hw = ixgbe_start_hw_X540; 96 mac->ops.get_san_mac_addr = ixgbe_get_san_mac_addr_generic; 97 mac->ops.set_san_mac_addr = ixgbe_set_san_mac_addr_generic; 98 mac->ops.get_device_caps = ixgbe_get_device_caps_generic; 99 mac->ops.get_wwn_prefix = ixgbe_get_wwn_prefix_generic; 100 mac->ops.get_fcoe_boot_status = ixgbe_get_fcoe_boot_status_generic; 101 mac->ops.acquire_swfw_sync = ixgbe_acquire_swfw_sync_X540; 102 mac->ops.release_swfw_sync = ixgbe_release_swfw_sync_X540; 103 mac->ops.init_swfw_sync = ixgbe_init_swfw_sync_X540; 104 mac->ops.disable_sec_rx_path = ixgbe_disable_sec_rx_path_generic; 105 mac->ops.enable_sec_rx_path = ixgbe_enable_sec_rx_path_generic; 106 107 /* RAR, Multicast, VLAN */ 108 mac->ops.set_vmdq = ixgbe_set_vmdq_generic; 109 mac->ops.set_vmdq_san_mac = ixgbe_set_vmdq_san_mac_generic; 110 mac->ops.clear_vmdq = ixgbe_clear_vmdq_generic; 111 mac->ops.insert_mac_addr = ixgbe_insert_mac_addr_generic; 112 mac->rar_highwater = 1; 113 mac->ops.set_vfta = ixgbe_set_vfta_generic; 114 mac->ops.set_vlvf = ixgbe_set_vlvf_generic; 115 mac->ops.clear_vfta = ixgbe_clear_vfta_generic; 116 mac->ops.init_uta_tables = ixgbe_init_uta_tables_generic; 117 mac->ops.set_mac_anti_spoofing = ixgbe_set_mac_anti_spoofing; 118 mac->ops.set_vlan_anti_spoofing = ixgbe_set_vlan_anti_spoofing; 119 120 /* Link */ 121 mac->ops.get_link_capabilities = 122 ixgbe_get_copper_link_capabilities_generic; 123 mac->ops.setup_link = ixgbe_setup_mac_link_X540; 124 mac->ops.setup_rxpba = ixgbe_set_rxpba_generic; 125 mac->ops.check_link = ixgbe_check_mac_link_generic; 126 mac->ops.bypass_rw = ixgbe_bypass_rw_generic; 127 mac->ops.bypass_valid_rd = ixgbe_bypass_valid_rd_generic; 128 mac->ops.bypass_set = ixgbe_bypass_set_generic; 129 mac->ops.bypass_rd_eep = ixgbe_bypass_rd_eep_generic; 130 131 132 mac->mcft_size = IXGBE_X540_MC_TBL_SIZE; 133 mac->vft_size = IXGBE_X540_VFT_TBL_SIZE; 134 mac->num_rar_entries = IXGBE_X540_RAR_ENTRIES; 135 mac->rx_pb_size = IXGBE_X540_RX_PB_SIZE; 136 mac->max_rx_queues = IXGBE_X540_MAX_RX_QUEUES; 137 mac->max_tx_queues = IXGBE_X540_MAX_TX_QUEUES; 138 mac->max_msix_vectors = ixgbe_get_pcie_msix_count_generic(hw); 139 140 /* 141 * FWSM register 142 * ARC supported; valid only if manageability features are 143 * enabled. 144 */ 145 mac->arc_subsystem_valid = !!(IXGBE_READ_REG(hw, IXGBE_FWSM_BY_MAC(hw)) 146 & IXGBE_FWSM_MODE_MASK); 147 148 hw->mbx.ops.init_params = ixgbe_init_mbx_params_pf; 149 150 /* LEDs */ 151 mac->ops.blink_led_start = ixgbe_blink_led_start_X540; 152 mac->ops.blink_led_stop = ixgbe_blink_led_stop_X540; 153 154 /* Manageability interface */ 155 mac->ops.set_fw_drv_ver = ixgbe_set_fw_drv_ver_generic; 156 157 mac->ops.get_rtrup2tc = ixgbe_dcb_get_rtrup2tc_generic; 158 159 return ret_val; 160} 161 162/** 163 * ixgbe_get_link_capabilities_X540 - Determines link capabilities 164 * @hw: pointer to hardware structure 165 * @speed: pointer to link speed 166 * @autoneg: TRUE when autoneg or autotry is enabled 167 * 168 * Determines the link capabilities by reading the AUTOC register. 169 **/ 170s32 ixgbe_get_link_capabilities_X540(struct ixgbe_hw *hw, 171 ixgbe_link_speed *speed, 172 bool *autoneg) 173{ 174 ixgbe_get_copper_link_capabilities_generic(hw, speed, autoneg); 175 176 return IXGBE_SUCCESS; 177} 178 179/** 180 * ixgbe_get_media_type_X540 - Get media type 181 * @hw: pointer to hardware structure 182 * 183 * Returns the media type (fiber, copper, backplane) 184 **/ 185enum ixgbe_media_type ixgbe_get_media_type_X540(struct ixgbe_hw *hw) 186{ 187 UNREFERENCED_1PARAMETER(hw); 188 return ixgbe_media_type_copper; 189} 190 191/** 192 * ixgbe_setup_mac_link_X540 - Sets the auto advertised capabilities 193 * @hw: pointer to hardware structure 194 * @speed: new link speed 195 * @autoneg_wait_to_complete: TRUE when waiting for completion is needed 196 **/ 197s32 ixgbe_setup_mac_link_X540(struct ixgbe_hw *hw, 198 ixgbe_link_speed speed, 199 bool autoneg_wait_to_complete) 200{ 201 DEBUGFUNC("ixgbe_setup_mac_link_X540"); 202 return hw->phy.ops.setup_link_speed(hw, speed, autoneg_wait_to_complete); 203} 204 205/** 206 * ixgbe_reset_hw_X540 - Perform hardware reset 207 * @hw: pointer to hardware structure 208 * 209 * Resets the hardware by resetting the transmit and receive units, masks 210 * and clears all interrupts, and perform a reset. 211 **/ 212s32 ixgbe_reset_hw_X540(struct ixgbe_hw *hw) 213{ 214 s32 status; 215 u32 ctrl, i; 216 217 DEBUGFUNC("ixgbe_reset_hw_X540"); 218 219 /* Call adapter stop to disable tx/rx and clear interrupts */ 220 status = hw->mac.ops.stop_adapter(hw); 221 if (status != IXGBE_SUCCESS) 222 goto reset_hw_out; 223 224 /* flush pending Tx transactions */ 225 ixgbe_clear_tx_pending(hw); 226 227mac_reset_top: 228 ctrl = IXGBE_CTRL_RST; 229 ctrl |= IXGBE_READ_REG(hw, IXGBE_CTRL); 230 IXGBE_WRITE_REG(hw, IXGBE_CTRL, ctrl); 231 IXGBE_WRITE_FLUSH(hw); 232 233 /* Poll for reset bit to self-clear indicating reset is complete */ 234 for (i = 0; i < 10; i++) { 235 usec_delay(1); 236 ctrl = IXGBE_READ_REG(hw, IXGBE_CTRL); 237 if (!(ctrl & IXGBE_CTRL_RST_MASK)) 238 break; 239 } 240 241 if (ctrl & IXGBE_CTRL_RST_MASK) { 242 status = IXGBE_ERR_RESET_FAILED; 243 ERROR_REPORT1(IXGBE_ERROR_POLLING, 244 "Reset polling failed to complete.\n"); 245 } 246 msec_delay(100); 247 248 /* 249 * Double resets are required for recovery from certain error 250 * conditions. Between resets, it is necessary to stall to allow time 251 * for any pending HW events to complete. 252 */ 253 if (hw->mac.flags & IXGBE_FLAGS_DOUBLE_RESET_REQUIRED) { 254 hw->mac.flags &= ~IXGBE_FLAGS_DOUBLE_RESET_REQUIRED; 255 goto mac_reset_top; 256 } 257 258 /* Set the Rx packet buffer size. */ 259 IXGBE_WRITE_REG(hw, IXGBE_RXPBSIZE(0), 384 << IXGBE_RXPBSIZE_SHIFT); 260 261 /* Store the permanent mac address */ 262 hw->mac.ops.get_mac_addr(hw, hw->mac.perm_addr); 263 264 /* 265 * Store MAC address from RAR0, clear receive address registers, and 266 * clear the multicast table. Also reset num_rar_entries to 128, 267 * since we modify this value when programming the SAN MAC address. 268 */ 269 hw->mac.num_rar_entries = 128; 270 hw->mac.ops.init_rx_addrs(hw); 271 272 /* Store the permanent SAN mac address */ 273 hw->mac.ops.get_san_mac_addr(hw, hw->mac.san_addr); 274 275 /* Add the SAN MAC address to the RAR only if it's a valid address */ 276 if (ixgbe_validate_mac_addr(hw->mac.san_addr) == 0) { 277 /* Save the SAN MAC RAR index */ 278 hw->mac.san_mac_rar_index = hw->mac.num_rar_entries - 1; 279 280 hw->mac.ops.set_rar(hw, hw->mac.san_mac_rar_index, 281 hw->mac.san_addr, 0, IXGBE_RAH_AV); 282 283 /* clear VMDq pool/queue selection for this RAR */ 284 hw->mac.ops.clear_vmdq(hw, hw->mac.san_mac_rar_index, 285 IXGBE_CLEAR_VMDQ_ALL); 286 287 /* Reserve the last RAR for the SAN MAC address */ 288 hw->mac.num_rar_entries--; 289 } 290 291 /* Store the alternative WWNN/WWPN prefix */ 292 hw->mac.ops.get_wwn_prefix(hw, &hw->mac.wwnn_prefix, 293 &hw->mac.wwpn_prefix); 294 295reset_hw_out: 296 return status; 297} 298 299/** 300 * ixgbe_start_hw_X540 - Prepare hardware for Tx/Rx 301 * @hw: pointer to hardware structure 302 * 303 * Starts the hardware using the generic start_hw function 304 * and the generation start_hw function. 305 * Then performs revision-specific operations, if any. 306 **/ 307s32 ixgbe_start_hw_X540(struct ixgbe_hw *hw) 308{ 309 s32 ret_val = IXGBE_SUCCESS; 310 311 DEBUGFUNC("ixgbe_start_hw_X540"); 312 313 ret_val = ixgbe_start_hw_generic(hw); 314 if (ret_val != IXGBE_SUCCESS) 315 goto out; 316 317 ret_val = ixgbe_start_hw_gen2(hw); 318 319out: 320 return ret_val; 321} 322 323/** 324 * ixgbe_get_supported_physical_layer_X540 - Returns physical layer type 325 * @hw: pointer to hardware structure 326 * 327 * Determines physical layer capabilities of the current configuration. 328 **/ 329u32 ixgbe_get_supported_physical_layer_X540(struct ixgbe_hw *hw) 330{ 331 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 332 u16 ext_ability = 0; 333 334 DEBUGFUNC("ixgbe_get_supported_physical_layer_X540"); 335 336 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_EXT_ABILITY, 337 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &ext_ability); 338 if (ext_ability & IXGBE_MDIO_PHY_10GBASET_ABILITY) 339 physical_layer |= IXGBE_PHYSICAL_LAYER_10GBASE_T; 340 if (ext_ability & IXGBE_MDIO_PHY_1000BASET_ABILITY) 341 physical_layer |= IXGBE_PHYSICAL_LAYER_1000BASE_T; 342 if (ext_ability & IXGBE_MDIO_PHY_100BASETX_ABILITY) 343 physical_layer |= IXGBE_PHYSICAL_LAYER_100BASE_TX; 344 345 return physical_layer; 346} 347 348/** 349 * ixgbe_init_eeprom_params_X540 - Initialize EEPROM params 350 * @hw: pointer to hardware structure 351 * 352 * Initializes the EEPROM parameters ixgbe_eeprom_info within the 353 * ixgbe_hw struct in order to set up EEPROM access. 354 **/ 355s32 ixgbe_init_eeprom_params_X540(struct ixgbe_hw *hw) 356{ 357 struct ixgbe_eeprom_info *eeprom = &hw->eeprom; 358 u32 eec; 359 u16 eeprom_size; 360 361 DEBUGFUNC("ixgbe_init_eeprom_params_X540"); 362 363 if (eeprom->type == ixgbe_eeprom_uninitialized) { 364 eeprom->semaphore_delay = 10; 365 eeprom->type = ixgbe_flash; 366 367 eec = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 368 eeprom_size = (u16)((eec & IXGBE_EEC_SIZE) >> 369 IXGBE_EEC_SIZE_SHIFT); 370 eeprom->word_size = 1 << (eeprom_size + 371 IXGBE_EEPROM_WORD_SIZE_SHIFT); 372 373 DEBUGOUT2("Eeprom params: type = %d, size = %d\n", 374 eeprom->type, eeprom->word_size); 375 } 376 377 return IXGBE_SUCCESS; 378} 379 380/** 381 * ixgbe_read_eerd_X540- Read EEPROM word using EERD 382 * @hw: pointer to hardware structure 383 * @offset: offset of word in the EEPROM to read 384 * @data: word read from the EEPROM 385 * 386 * Reads a 16 bit word from the EEPROM using the EERD register. 387 **/ 388s32 ixgbe_read_eerd_X540(struct ixgbe_hw *hw, u16 offset, u16 *data) 389{ 390 s32 status = IXGBE_SUCCESS; 391 392 DEBUGFUNC("ixgbe_read_eerd_X540"); 393 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 394 IXGBE_SUCCESS) { 395 status = ixgbe_read_eerd_generic(hw, offset, data); 396 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 397 } else { 398 status = IXGBE_ERR_SWFW_SYNC; 399 } 400 401 return status; 402} 403 404/** 405 * ixgbe_read_eerd_buffer_X540- Read EEPROM word(s) using EERD 406 * @hw: pointer to hardware structure 407 * @offset: offset of word in the EEPROM to read 408 * @words: number of words 409 * @data: word(s) read from the EEPROM 410 * 411 * Reads a 16 bit word(s) from the EEPROM using the EERD register. 412 **/ 413s32 ixgbe_read_eerd_buffer_X540(struct ixgbe_hw *hw, 414 u16 offset, u16 words, u16 *data) 415{ 416 s32 status = IXGBE_SUCCESS; 417 418 DEBUGFUNC("ixgbe_read_eerd_buffer_X540"); 419 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 420 IXGBE_SUCCESS) { 421 status = ixgbe_read_eerd_buffer_generic(hw, offset, 422 words, data); 423 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 424 } else { 425 status = IXGBE_ERR_SWFW_SYNC; 426 } 427 428 return status; 429} 430 431/** 432 * ixgbe_write_eewr_X540 - Write EEPROM word using EEWR 433 * @hw: pointer to hardware structure 434 * @offset: offset of word in the EEPROM to write 435 * @data: word write to the EEPROM 436 * 437 * Write a 16 bit word to the EEPROM using the EEWR register. 438 **/ 439s32 ixgbe_write_eewr_X540(struct ixgbe_hw *hw, u16 offset, u16 data) 440{ 441 s32 status = IXGBE_SUCCESS; 442 443 DEBUGFUNC("ixgbe_write_eewr_X540"); 444 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 445 IXGBE_SUCCESS) { 446 status = ixgbe_write_eewr_generic(hw, offset, data); 447 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 448 } else { 449 status = IXGBE_ERR_SWFW_SYNC; 450 } 451 452 return status; 453} 454 455/** 456 * ixgbe_write_eewr_buffer_X540 - Write EEPROM word(s) using EEWR 457 * @hw: pointer to hardware structure 458 * @offset: offset of word in the EEPROM to write 459 * @words: number of words 460 * @data: word(s) write to the EEPROM 461 * 462 * Write a 16 bit word(s) to the EEPROM using the EEWR register. 463 **/ 464s32 ixgbe_write_eewr_buffer_X540(struct ixgbe_hw *hw, 465 u16 offset, u16 words, u16 *data) 466{ 467 s32 status = IXGBE_SUCCESS; 468 469 DEBUGFUNC("ixgbe_write_eewr_buffer_X540"); 470 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM) == 471 IXGBE_SUCCESS) { 472 status = ixgbe_write_eewr_buffer_generic(hw, offset, 473 words, data); 474 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 475 } else { 476 status = IXGBE_ERR_SWFW_SYNC; 477 } 478 479 return status; 480} 481 482/** 483 * ixgbe_calc_eeprom_checksum_X540 - Calculates and returns the checksum 484 * 485 * This function does not use synchronization for EERD and EEWR. It can 486 * be used internally by function which utilize ixgbe_acquire_swfw_sync_X540. 487 * 488 * @hw: pointer to hardware structure 489 * 490 * Returns a negative error code on error, or the 16-bit checksum 491 **/ 492s32 ixgbe_calc_eeprom_checksum_X540(struct ixgbe_hw *hw) 493{ 494 u16 i, j; 495 u16 checksum = 0; 496 u16 length = 0; 497 u16 pointer = 0; 498 u16 word = 0; 499 u16 ptr_start = IXGBE_PCIE_ANALOG_PTR; 500 501 /* Do not use hw->eeprom.ops.read because we do not want to take 502 * the synchronization semaphores here. Instead use 503 * ixgbe_read_eerd_generic 504 */ 505 506 DEBUGFUNC("ixgbe_calc_eeprom_checksum_X540"); 507 508 /* Include 0x0 up to IXGBE_EEPROM_CHECKSUM; do not include the 509 * checksum itself 510 */ 511 for (i = 0; i < IXGBE_EEPROM_CHECKSUM; i++) { 512 if (ixgbe_read_eerd_generic(hw, i, &word)) { 513 DEBUGOUT("EEPROM read failed\n"); 514 return IXGBE_ERR_EEPROM; 515 } 516 checksum += word; 517 } 518 519 /* Include all data from pointers 0x3, 0x6-0xE. This excludes the 520 * FW, PHY module, and PCIe Expansion/Option ROM pointers. 521 */ 522 for (i = ptr_start; i < IXGBE_FW_PTR; i++) { 523 if (i == IXGBE_PHY_PTR || i == IXGBE_OPTION_ROM_PTR) 524 continue; 525 526 if (ixgbe_read_eerd_generic(hw, i, &pointer)) { 527 DEBUGOUT("EEPROM read failed\n"); 528 return IXGBE_ERR_EEPROM; 529 } 530 531 /* Skip pointer section if the pointer is invalid. */ 532 if (pointer == 0xFFFF || pointer == 0 || 533 pointer >= hw->eeprom.word_size) 534 continue; 535 536 if (ixgbe_read_eerd_generic(hw, pointer, &length)) { 537 DEBUGOUT("EEPROM read failed\n"); 538 return IXGBE_ERR_EEPROM; 539 } 540 541 /* Skip pointer section if length is invalid. */ 542 if (length == 0xFFFF || length == 0 || 543 (pointer + length) >= hw->eeprom.word_size) 544 continue; 545 546 for (j = pointer + 1; j <= pointer + length; j++) { 547 if (ixgbe_read_eerd_generic(hw, j, &word)) { 548 DEBUGOUT("EEPROM read failed\n"); 549 return IXGBE_ERR_EEPROM; 550 } 551 checksum += word; 552 } 553 } 554 555 checksum = (u16)IXGBE_EEPROM_SUM - checksum; 556 557 return (s32)checksum; 558} 559 560/** 561 * ixgbe_validate_eeprom_checksum_X540 - Validate EEPROM checksum 562 * @hw: pointer to hardware structure 563 * @checksum_val: calculated checksum 564 * 565 * Performs checksum calculation and validates the EEPROM checksum. If the 566 * caller does not need checksum_val, the value can be NULL. 567 **/ 568s32 ixgbe_validate_eeprom_checksum_X540(struct ixgbe_hw *hw, 569 u16 *checksum_val) 570{ 571 s32 status; 572 u16 checksum; 573 u16 read_checksum = 0; 574 575 DEBUGFUNC("ixgbe_validate_eeprom_checksum_X540"); 576 577 /* Read the first word from the EEPROM. If this times out or fails, do 578 * not continue or we could be in for a very long wait while every 579 * EEPROM read fails 580 */ 581 status = hw->eeprom.ops.read(hw, 0, &checksum); 582 if (status) { 583 DEBUGOUT("EEPROM read failed\n"); 584 return status; 585 } 586 587 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 588 return IXGBE_ERR_SWFW_SYNC; 589 590 status = hw->eeprom.ops.calc_checksum(hw); 591 if (status < 0) 592 goto out; 593 594 checksum = (u16)(status & 0xffff); 595 596 /* Do not use hw->eeprom.ops.read because we do not want to take 597 * the synchronization semaphores twice here. 598 */ 599 status = ixgbe_read_eerd_generic(hw, IXGBE_EEPROM_CHECKSUM, 600 &read_checksum); 601 if (status) 602 goto out; 603 604 /* Verify read checksum from EEPROM is the same as 605 * calculated checksum 606 */ 607 if (read_checksum != checksum) { 608 ERROR_REPORT1(IXGBE_ERROR_INVALID_STATE, 609 "Invalid EEPROM checksum"); 610 status = IXGBE_ERR_EEPROM_CHECKSUM; 611 } 612 613 /* If the user cares, return the calculated checksum */ 614 if (checksum_val) 615 *checksum_val = checksum; 616 617out: 618 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 619 620 return status; 621} 622 623/** 624 * ixgbe_update_eeprom_checksum_X540 - Updates the EEPROM checksum and flash 625 * @hw: pointer to hardware structure 626 * 627 * After writing EEPROM to shadow RAM using EEWR register, software calculates 628 * checksum and updates the EEPROM and instructs the hardware to update 629 * the flash. 630 **/ 631s32 ixgbe_update_eeprom_checksum_X540(struct ixgbe_hw *hw) 632{ 633 s32 status; 634 u16 checksum; 635 636 DEBUGFUNC("ixgbe_update_eeprom_checksum_X540"); 637 638 /* Read the first word from the EEPROM. If this times out or fails, do 639 * not continue or we could be in for a very long wait while every 640 * EEPROM read fails 641 */ 642 status = hw->eeprom.ops.read(hw, 0, &checksum); 643 if (status) { 644 DEBUGOUT("EEPROM read failed\n"); 645 return status; 646 } 647 648 if (hw->mac.ops.acquire_swfw_sync(hw, IXGBE_GSSR_EEP_SM)) 649 return IXGBE_ERR_SWFW_SYNC; 650 651 status = hw->eeprom.ops.calc_checksum(hw); 652 if (status < 0) 653 goto out; 654 655 checksum = (u16)(status & 0xffff); 656 657 /* Do not use hw->eeprom.ops.write because we do not want to 658 * take the synchronization semaphores twice here. 659 */ 660 status = ixgbe_write_eewr_generic(hw, IXGBE_EEPROM_CHECKSUM, checksum); 661 if (status) 662 goto out; 663 664 status = ixgbe_update_flash_X540(hw); 665 666out: 667 hw->mac.ops.release_swfw_sync(hw, IXGBE_GSSR_EEP_SM); 668 669 return status; 670} 671 672/** 673 * ixgbe_update_flash_X540 - Instruct HW to copy EEPROM to Flash device 674 * @hw: pointer to hardware structure 675 * 676 * Set FLUP (bit 23) of the EEC register to instruct Hardware to copy 677 * EEPROM from shadow RAM to the flash device. 678 **/ 679s32 ixgbe_update_flash_X540(struct ixgbe_hw *hw) 680{ 681 u32 flup; 682 s32 status; 683 684 DEBUGFUNC("ixgbe_update_flash_X540"); 685 686 status = ixgbe_poll_flash_update_done_X540(hw); 687 if (status == IXGBE_ERR_EEPROM) { 688 DEBUGOUT("Flash update time out\n"); 689 goto out; 690 } 691 692 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)) | IXGBE_EEC_FLUP; 693 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 694 695 status = ixgbe_poll_flash_update_done_X540(hw); 696 if (status == IXGBE_SUCCESS) 697 DEBUGOUT("Flash update complete\n"); 698 else 699 DEBUGOUT("Flash update time out\n"); 700 701 if (hw->mac.type == ixgbe_mac_X540 && hw->revision_id == 0) { 702 flup = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 703 704 if (flup & IXGBE_EEC_SEC1VAL) { 705 flup |= IXGBE_EEC_FLUP; 706 IXGBE_WRITE_REG(hw, IXGBE_EEC_BY_MAC(hw), flup); 707 } 708 709 status = ixgbe_poll_flash_update_done_X540(hw); 710 if (status == IXGBE_SUCCESS) 711 DEBUGOUT("Flash update complete\n"); 712 else 713 DEBUGOUT("Flash update time out\n"); 714 } 715out: 716 return status; 717} 718 719/** 720 * ixgbe_poll_flash_update_done_X540 - Poll flash update status 721 * @hw: pointer to hardware structure 722 * 723 * Polls the FLUDONE (bit 26) of the EEC Register to determine when the 724 * flash update is done. 725 **/ 726static s32 ixgbe_poll_flash_update_done_X540(struct ixgbe_hw *hw) 727{ 728 u32 i; 729 u32 reg; 730 s32 status = IXGBE_ERR_EEPROM; 731 732 DEBUGFUNC("ixgbe_poll_flash_update_done_X540"); 733 734 for (i = 0; i < IXGBE_FLUDONE_ATTEMPTS; i++) { 735 reg = IXGBE_READ_REG(hw, IXGBE_EEC_BY_MAC(hw)); 736 if (reg & IXGBE_EEC_FLUDONE) { 737 status = IXGBE_SUCCESS; 738 break; 739 } 740 msec_delay(5); 741 } 742 743 if (i == IXGBE_FLUDONE_ATTEMPTS) 744 ERROR_REPORT1(IXGBE_ERROR_POLLING, 745 "Flash update status polling timed out"); 746 747 return status; 748} 749 750/** 751 * ixgbe_acquire_swfw_sync_X540 - Acquire SWFW semaphore 752 * @hw: pointer to hardware structure 753 * @mask: Mask to specify which semaphore to acquire 754 * 755 * Acquires the SWFW semaphore thought the SW_FW_SYNC register for 756 * the specified function (CSR, PHY0, PHY1, NVM, Flash) 757 **/ 758s32 ixgbe_acquire_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 759{ 760 u32 swmask = mask & IXGBE_GSSR_NVM_PHY_MASK; 761 u32 fwmask = swmask << 5; 762 u32 swi2c_mask = mask & IXGBE_GSSR_I2C_MASK; 763 u32 timeout = 200; 764 u32 hwmask = 0; 765 u32 swfw_sync; 766 u32 i; 767 768 DEBUGFUNC("ixgbe_acquire_swfw_sync_X540"); 769 770 if (swmask & IXGBE_GSSR_EEP_SM) 771 hwmask |= IXGBE_GSSR_FLASH_SM; 772 773 /* SW only mask doesn't have FW bit pair */ 774 if (mask & IXGBE_GSSR_SW_MNG_SM) 775 swmask |= IXGBE_GSSR_SW_MNG_SM; 776 777 swmask |= swi2c_mask; 778 fwmask |= swi2c_mask << 2; 779 for (i = 0; i < timeout; i++) { 780 /* SW NVM semaphore bit is used for access to all 781 * SW_FW_SYNC bits (not just NVM) 782 */ 783 if (ixgbe_get_swfw_sync_semaphore(hw)) { 784 DEBUGOUT("Failed to get NVM access and register semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 785 return IXGBE_ERR_SWFW_SYNC; 786 } 787 788 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 789 if (!(swfw_sync & (fwmask | swmask | hwmask))) { 790 swfw_sync |= swmask; 791 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), 792 swfw_sync); 793 ixgbe_release_swfw_sync_semaphore(hw); 794 return IXGBE_SUCCESS; 795 } 796 /* Firmware currently using resource (fwmask), hardware 797 * currently using resource (hwmask), or other software 798 * thread currently using resource (swmask) 799 */ 800 ixgbe_release_swfw_sync_semaphore(hw); 801 msec_delay(5); 802 } 803 804 /* Failed to get SW only semaphore */ 805 if (swmask == IXGBE_GSSR_SW_MNG_SM) { 806 ERROR_REPORT1(IXGBE_ERROR_POLLING, 807 "Failed to get SW only semaphore"); 808 DEBUGOUT("Failed to get SW only semaphore, returning IXGBE_ERR_SWFW_SYNC\n"); 809 return IXGBE_ERR_SWFW_SYNC; 810 } 811 812 /* If the resource is not released by the FW/HW the SW can assume that 813 * the FW/HW malfunctions. In that case the SW should set the SW bit(s) 814 * of the requested resource(s) while ignoring the corresponding FW/HW 815 * bits in the SW_FW_SYNC register. 816 */ 817 if (ixgbe_get_swfw_sync_semaphore(hw)) { 818 DEBUGOUT("Failed to get NVM sempahore and register semaphore while forcefully ignoring FW sempahore bit(s) and setting SW semaphore bit(s), returning IXGBE_ERR_SWFW_SYNC\n"); 819 return IXGBE_ERR_SWFW_SYNC; 820 } 821 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 822 if (swfw_sync & (fwmask | hwmask)) { 823 swfw_sync |= swmask; 824 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 825 ixgbe_release_swfw_sync_semaphore(hw); 826 msec_delay(5); 827 return IXGBE_SUCCESS; 828 } 829 /* If the resource is not released by other SW the SW can assume that 830 * the other SW malfunctions. In that case the SW should clear all SW 831 * flags that it does not own and then repeat the whole process once 832 * again. 833 */ 834 if (swfw_sync & swmask) { 835 u32 rmask = IXGBE_GSSR_EEP_SM | IXGBE_GSSR_PHY0_SM | 836 IXGBE_GSSR_PHY1_SM | IXGBE_GSSR_MAC_CSR_SM; 837 838 if (swi2c_mask) 839 rmask |= IXGBE_GSSR_I2C_MASK; 840 ixgbe_release_swfw_sync_X540(hw, rmask); 841 ixgbe_release_swfw_sync_semaphore(hw); 842 DEBUGOUT("Resource not released by other SW, returning IXGBE_ERR_SWFW_SYNC\n"); 843 return IXGBE_ERR_SWFW_SYNC; 844 } 845 ixgbe_release_swfw_sync_semaphore(hw); 846 DEBUGOUT("Returning error IXGBE_ERR_SWFW_SYNC\n"); 847 848 return IXGBE_ERR_SWFW_SYNC; 849} 850 851/** 852 * ixgbe_release_swfw_sync_X540 - Release SWFW semaphore 853 * @hw: pointer to hardware structure 854 * @mask: Mask to specify which semaphore to release 855 * 856 * Releases the SWFW semaphore through the SW_FW_SYNC register 857 * for the specified function (CSR, PHY0, PHY1, EVM, Flash) 858 **/ 859void ixgbe_release_swfw_sync_X540(struct ixgbe_hw *hw, u32 mask) 860{ 861 u32 swmask = mask & (IXGBE_GSSR_NVM_PHY_MASK | IXGBE_GSSR_SW_MNG_SM); 862 u32 swfw_sync; 863 864 DEBUGFUNC("ixgbe_release_swfw_sync_X540"); 865 866 if (mask & IXGBE_GSSR_I2C_MASK) 867 swmask |= mask & IXGBE_GSSR_I2C_MASK; 868 ixgbe_get_swfw_sync_semaphore(hw); 869 870 swfw_sync = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 871 swfw_sync &= ~swmask; 872 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swfw_sync); 873 874 ixgbe_release_swfw_sync_semaphore(hw); 875 msec_delay(2); 876} 877 878/** 879 * ixgbe_get_swfw_sync_semaphore - Get hardware semaphore 880 * @hw: pointer to hardware structure 881 * 882 * Sets the hardware semaphores so SW/FW can gain control of shared resources 883 **/ 884static s32 ixgbe_get_swfw_sync_semaphore(struct ixgbe_hw *hw) 885{ 886 s32 status = IXGBE_ERR_EEPROM; 887 u32 timeout = 2000; 888 u32 i; 889 u32 swsm; 890 891 DEBUGFUNC("ixgbe_get_swfw_sync_semaphore"); 892 893 /* Get SMBI software semaphore between device drivers first */ 894 for (i = 0; i < timeout; i++) { 895 /* 896 * If the SMBI bit is 0 when we read it, then the bit will be 897 * set and we have the semaphore 898 */ 899 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 900 if (!(swsm & IXGBE_SWSM_SMBI)) { 901 status = IXGBE_SUCCESS; 902 break; 903 } 904 usec_delay(50); 905 } 906 907 /* Now get the semaphore between SW/FW through the REGSMP bit */ 908 if (status == IXGBE_SUCCESS) { 909 for (i = 0; i < timeout; i++) { 910 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 911 if (!(swsm & IXGBE_SWFW_REGSMP)) 912 break; 913 914 usec_delay(50); 915 } 916 917 /* 918 * Release semaphores and return error if SW NVM semaphore 919 * was not granted because we don't have access to the EEPROM 920 */ 921 if (i >= timeout) { 922 ERROR_REPORT1(IXGBE_ERROR_POLLING, 923 "REGSMP Software NVM semaphore not granted.\n"); 924 ixgbe_release_swfw_sync_semaphore(hw); 925 status = IXGBE_ERR_EEPROM; 926 } 927 } else { 928 ERROR_REPORT1(IXGBE_ERROR_POLLING, 929 "Software semaphore SMBI between device drivers " 930 "not granted.\n"); 931 } 932 933 return status; 934} 935 936/** 937 * ixgbe_release_swfw_sync_semaphore - Release hardware semaphore 938 * @hw: pointer to hardware structure 939 * 940 * This function clears hardware semaphore bits. 941 **/ 942static void ixgbe_release_swfw_sync_semaphore(struct ixgbe_hw *hw) 943{ 944 u32 swsm; 945 946 DEBUGFUNC("ixgbe_release_swfw_sync_semaphore"); 947 948 /* Release both semaphores by writing 0 to the bits REGSMP and SMBI */ 949 950 swsm = IXGBE_READ_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw)); 951 swsm &= ~IXGBE_SWFW_REGSMP; 952 IXGBE_WRITE_REG(hw, IXGBE_SWFW_SYNC_BY_MAC(hw), swsm); 953 954 swsm = IXGBE_READ_REG(hw, IXGBE_SWSM_BY_MAC(hw)); 955 swsm &= ~IXGBE_SWSM_SMBI; 956 IXGBE_WRITE_REG(hw, IXGBE_SWSM_BY_MAC(hw), swsm); 957 958 IXGBE_WRITE_FLUSH(hw); 959} 960 961/** 962 * ixgbe_init_swfw_sync_X540 - Release hardware semaphore 963 * @hw: pointer to hardware structure 964 * 965 * This function reset hardware semaphore bits for a semaphore that may 966 * have be left locked due to a catastrophic failure. 967 **/ 968void ixgbe_init_swfw_sync_X540(struct ixgbe_hw *hw) 969{ 970 /* First try to grab the semaphore but we don't need to bother 971 * looking to see whether we got the lock or not since we do 972 * the same thing regardless of whether we got the lock or not. 973 * We got the lock - we release it. 974 * We timeout trying to get the lock - we force its release. 975 */ 976 ixgbe_get_swfw_sync_semaphore(hw); 977 ixgbe_release_swfw_sync_semaphore(hw); 978} 979 980/** 981 * ixgbe_blink_led_start_X540 - Blink LED based on index. 982 * @hw: pointer to hardware structure 983 * @index: led number to blink 984 * 985 * Devices that implement the version 2 interface: 986 * X540 987 **/ 988s32 ixgbe_blink_led_start_X540(struct ixgbe_hw *hw, u32 index) 989{ 990 u32 macc_reg; 991 u32 ledctl_reg; 992 ixgbe_link_speed speed; 993 bool link_up; 994 995 DEBUGFUNC("ixgbe_blink_led_start_X540"); 996 997 if (index > 3) 998 return IXGBE_ERR_PARAM; 999 1000 /* 1001 * Link should be up in order for the blink bit in the LED control 1002 * register to work. Force link and speed in the MAC if link is down. 1003 * This will be reversed when we stop the blinking. 1004 */ 1005 hw->mac.ops.check_link(hw, &speed, &link_up, FALSE); 1006 if (link_up == FALSE) { 1007 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1008 macc_reg |= IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS; 1009 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1010 } 1011 /* Set the LED to LINK_UP + BLINK. */ 1012 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1013 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1014 ledctl_reg |= IXGBE_LED_BLINK(index); 1015 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1016 IXGBE_WRITE_FLUSH(hw); 1017 1018 return IXGBE_SUCCESS; 1019} 1020 1021/** 1022 * ixgbe_blink_led_stop_X540 - Stop blinking LED based on index. 1023 * @hw: pointer to hardware structure 1024 * @index: led number to stop blinking 1025 * 1026 * Devices that implement the version 2 interface: 1027 * X540 1028 **/ 1029s32 ixgbe_blink_led_stop_X540(struct ixgbe_hw *hw, u32 index) 1030{ 1031 u32 macc_reg; 1032 u32 ledctl_reg; 1033 1034 if (index > 3) 1035 return IXGBE_ERR_PARAM; 1036 1037 DEBUGFUNC("ixgbe_blink_led_stop_X540"); 1038 1039 /* Restore the LED to its default value. */ 1040 ledctl_reg = IXGBE_READ_REG(hw, IXGBE_LEDCTL); 1041 ledctl_reg &= ~IXGBE_LED_MODE_MASK(index); 1042 ledctl_reg |= IXGBE_LED_LINK_ACTIVE << IXGBE_LED_MODE_SHIFT(index); 1043 ledctl_reg &= ~IXGBE_LED_BLINK(index); 1044 IXGBE_WRITE_REG(hw, IXGBE_LEDCTL, ledctl_reg); 1045 1046 /* Unforce link and speed in the MAC. */ 1047 macc_reg = IXGBE_READ_REG(hw, IXGBE_MACC); 1048 macc_reg &= ~(IXGBE_MACC_FLU | IXGBE_MACC_FSV_10G | IXGBE_MACC_FS); 1049 IXGBE_WRITE_REG(hw, IXGBE_MACC, macc_reg); 1050 IXGBE_WRITE_FLUSH(hw); 1051 1052 return IXGBE_SUCCESS; 1053} 1054