1179055Sjfv/****************************************************************************** 2171384Sjfv 3315333Serj Copyright (c) 2001-2017, Intel Corporation 4171384Sjfv All rights reserved. 5315333Serj 6315333Serj Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8315333Serj 9315333Serj 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11315333Serj 12315333Serj 2. Redistributions in binary form must reproduce the above copyright 13315333Serj notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15315333Serj 16315333Serj 3. Neither the name of the Intel Corporation nor the names of its 17315333Serj contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19315333Serj 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21315333Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22315333Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23315333Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24315333Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25315333Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26315333Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27315333Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28315333Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_type.h 315333 2017-03-15 21:20:17Z erj $*/ 34171384Sjfv 35171384Sjfv#ifndef _IXGBE_TYPE_H_ 36171384Sjfv#define _IXGBE_TYPE_H_ 37171384Sjfv 38251964Sjfv/* 39251964Sjfv * The following is a brief description of the error categories used by the 40251964Sjfv * ERROR_REPORT* macros. 41251964Sjfv * 42251964Sjfv * - IXGBE_ERROR_INVALID_STATE 43251964Sjfv * This category is for errors which represent a serious failure state that is 44251964Sjfv * unexpected, and could be potentially harmful to device operation. It should 45251964Sjfv * not be used for errors relating to issues that can be worked around or 46251964Sjfv * ignored. 47251964Sjfv * 48251964Sjfv * - IXGBE_ERROR_POLLING 49251964Sjfv * This category is for errors related to polling/timeout issues and should be 50251964Sjfv * used in any case where the timeout occured, or a failure to obtain a lock, or 51251964Sjfv * failure to receive data within the time limit. 52251964Sjfv * 53251964Sjfv * - IXGBE_ERROR_CAUTION 54251964Sjfv * This category should be used for reporting issues that may be the cause of 55251964Sjfv * other errors, such as temperature warnings. It should indicate an event which 56251964Sjfv * could be serious, but hasn't necessarily caused problems yet. 57251964Sjfv * 58251964Sjfv * - IXGBE_ERROR_SOFTWARE 59251964Sjfv * This category is intended for errors due to software state preventing 60251964Sjfv * something. The category is not intended for errors due to bad arguments, or 61251964Sjfv * due to unsupported features. It should be used when a state occurs which 62251964Sjfv * prevents action but is not a serious issue. 63251964Sjfv * 64251964Sjfv * - IXGBE_ERROR_ARGUMENT 65251964Sjfv * This category is for when a bad or invalid argument is passed. It should be 66251964Sjfv * used whenever a function is called and error checking has detected the 67251964Sjfv * argument is wrong or incorrect. 68251964Sjfv * 69251964Sjfv * - IXGBE_ERROR_UNSUPPORTED 70251964Sjfv * This category is for errors which are due to unsupported circumstances or 71251964Sjfv * configuration issues. It should not be used when the issue is due to an 72251964Sjfv * invalid argument, but for when something has occurred that is unsupported 73251964Sjfv * (Ex: Flow control autonegotiation or an unsupported SFP+ module.) 74251964Sjfv */ 75251964Sjfv 76171384Sjfv#include "ixgbe_osdep.h" 77171384Sjfv 78283620Serj/* Override this by setting IOMEM in your ixgbe_osdep.h header */ 79283620Serj#define IOMEM 80194875Sjfv 81251964Sjfv/* Vendor ID */ 82251964Sjfv#define IXGBE_INTEL_VENDOR_ID 0x8086 83251964Sjfv 84171384Sjfv/* Device IDs */ 85230775Sjfv#define IXGBE_DEV_ID_82598 0x10B6 86230775Sjfv#define IXGBE_DEV_ID_82598_BX 0x1508 87230775Sjfv#define IXGBE_DEV_ID_82598AF_DUAL_PORT 0x10C6 88230775Sjfv#define IXGBE_DEV_ID_82598AF_SINGLE_PORT 0x10C7 89230775Sjfv#define IXGBE_DEV_ID_82598AT 0x10C8 90230775Sjfv#define IXGBE_DEV_ID_82598AT2 0x150B 91230775Sjfv#define IXGBE_DEV_ID_82598EB_SFP_LOM 0x10DB 92230775Sjfv#define IXGBE_DEV_ID_82598EB_CX4 0x10DD 93230775Sjfv#define IXGBE_DEV_ID_82598_CX4_DUAL_PORT 0x10EC 94230775Sjfv#define IXGBE_DEV_ID_82598_DA_DUAL_PORT 0x10F1 95230775Sjfv#define IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM 0x10E1 96230775Sjfv#define IXGBE_DEV_ID_82598EB_XF_LR 0x10F4 97230775Sjfv#define IXGBE_DEV_ID_82599_KX4 0x10F7 98230775Sjfv#define IXGBE_DEV_ID_82599_KX4_MEZZ 0x1514 99230775Sjfv#define IXGBE_DEV_ID_82599_KR 0x1517 100230775Sjfv#define IXGBE_DEV_ID_82599_COMBO_BACKPLANE 0x10F8 101230775Sjfv#define IXGBE_SUBDEV_ID_82599_KX4_KR_MEZZ 0x000C 102230775Sjfv#define IXGBE_DEV_ID_82599_CX4 0x10F9 103230775Sjfv#define IXGBE_DEV_ID_82599_SFP 0x10FB 104230775Sjfv#define IXGBE_SUBDEV_ID_82599_SFP 0x11A9 105283620Serj#define IXGBE_SUBDEV_ID_82599_SFP_WOL0 0x1071 106247822Sjfv#define IXGBE_SUBDEV_ID_82599_RNDC 0x1F72 107230775Sjfv#define IXGBE_SUBDEV_ID_82599_560FLR 0x17D0 108247822Sjfv#define IXGBE_SUBDEV_ID_82599_ECNA_DP 0x0470 109251964Sjfv#define IXGBE_SUBDEV_ID_82599_SP_560FLR 0x211B 110283620Serj#define IXGBE_SUBDEV_ID_82599_LOM_SNAP6 0x2159 111283620Serj#define IXGBE_SUBDEV_ID_82599_SFP_1OCP 0x000D 112283620Serj#define IXGBE_SUBDEV_ID_82599_SFP_2OCP 0x0008 113315333Serj#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM1 0x8976 114315333Serj#define IXGBE_SUBDEV_ID_82599_SFP_LOM_OEM2 0x06EE 115230775Sjfv#define IXGBE_DEV_ID_82599_BACKPLANE_FCOE 0x152A 116230775Sjfv#define IXGBE_DEV_ID_82599_SFP_FCOE 0x1529 117230775Sjfv#define IXGBE_DEV_ID_82599_SFP_EM 0x1507 118238149Sjfv#define IXGBE_DEV_ID_82599_SFP_SF2 0x154D 119247822Sjfv#define IXGBE_DEV_ID_82599_SFP_SF_QP 0x154A 120283620Serj#define IXGBE_DEV_ID_82599_QSFP_SF_QP 0x1558 121230775Sjfv#define IXGBE_DEV_ID_82599EN_SFP 0x1557 122251964Sjfv#define IXGBE_SUBDEV_ID_82599EN_SFP_OCP1 0x0001 123230775Sjfv#define IXGBE_DEV_ID_82599_XAUI_LOM 0x10FC 124230775Sjfv#define IXGBE_DEV_ID_82599_T3_LOM 0x151C 125247822Sjfv#define IXGBE_DEV_ID_82599_BYPASS 0x155D 126247822Sjfv#define IXGBE_DEV_ID_X540T 0x1528 127247822Sjfv#define IXGBE_DEV_ID_X540_BYPASS 0x155C 128283620Serj#define IXGBE_DEV_ID_X540T1 0x1560 129283620Serj#define IXGBE_DEV_ID_X550T 0x1563 130295524Ssbruno#define IXGBE_DEV_ID_X550T1 0x15D1 131315333Serj/* Placeholder value, pending official value. */ 132315333Serj#define IXGBE_DEV_ID_X550EM_A_KR 0x15C2 133315333Serj#define IXGBE_DEV_ID_X550EM_A_KR_L 0x15C3 134315333Serj#define IXGBE_DEV_ID_X550EM_A_SFP_N 0x15C4 135315333Serj#define IXGBE_DEV_ID_X550EM_A_SGMII 0x15C6 136315333Serj#define IXGBE_DEV_ID_X550EM_A_SGMII_L 0x15C7 137315333Serj#define IXGBE_DEV_ID_X550EM_A_10G_T 0x15C8 138315333Serj#define IXGBE_DEV_ID_X550EM_A_QSFP 0x15CA 139315333Serj#define IXGBE_DEV_ID_X550EM_A_QSFP_N 0x15CC 140315333Serj#define IXGBE_DEV_ID_X550EM_A_SFP 0x15CE 141315333Serj#define IXGBE_DEV_ID_X550EM_A_1G_T 0x15E4 142315333Serj#define IXGBE_DEV_ID_X550EM_A_1G_T_L 0x15E5 143283620Serj#define IXGBE_DEV_ID_X550EM_X_KX4 0x15AA 144283620Serj#define IXGBE_DEV_ID_X550EM_X_KR 0x15AB 145283620Serj#define IXGBE_DEV_ID_X550EM_X_SFP 0x15AC 146283620Serj#define IXGBE_DEV_ID_X550EM_X_10G_T 0x15AD 147283620Serj#define IXGBE_DEV_ID_X550EM_X_1G_T 0x15AE 148315333Serj#define IXGBE_DEV_ID_X550EM_X_XFI 0x15B0 149171384Sjfv 150283620Serj#define IXGBE_CAT(r,m) IXGBE_##r##m 151283620Serj 152283620Serj#define IXGBE_BY_MAC(_hw, r) ((_hw)->mvals[IXGBE_CAT(r, _IDX)]) 153283620Serj 154171384Sjfv/* General Registers */ 155230775Sjfv#define IXGBE_CTRL 0x00000 156230775Sjfv#define IXGBE_STATUS 0x00008 157230775Sjfv#define IXGBE_CTRL_EXT 0x00018 158230775Sjfv#define IXGBE_ESDP 0x00020 159230775Sjfv#define IXGBE_EODSDP 0x00028 160283620Serj#define IXGBE_I2CCTL_82599 0x00028 161283620Serj#define IXGBE_I2CCTL IXGBE_I2CCTL_82599 162283620Serj#define IXGBE_I2CCTL_X540 IXGBE_I2CCTL_82599 163283620Serj#define IXGBE_I2CCTL_X550 0x15F5C 164283620Serj#define IXGBE_I2CCTL_X550EM_x IXGBE_I2CCTL_X550 165315333Serj#define IXGBE_I2CCTL_X550EM_a IXGBE_I2CCTL_X550 166283620Serj#define IXGBE_I2CCTL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2CCTL) 167230775Sjfv#define IXGBE_PHY_GPIO 0x00028 168230775Sjfv#define IXGBE_MAC_GPIO 0x00030 169230775Sjfv#define IXGBE_PHYINT_STATUS0 0x00100 170230775Sjfv#define IXGBE_PHYINT_STATUS1 0x00104 171230775Sjfv#define IXGBE_PHYINT_STATUS2 0x00108 172230775Sjfv#define IXGBE_LEDCTL 0x00200 173230775Sjfv#define IXGBE_FRTIMER 0x00048 174230775Sjfv#define IXGBE_TCPTIMER 0x0004C 175230775Sjfv#define IXGBE_CORESPARE 0x00600 176230775Sjfv#define IXGBE_EXVET 0x05078 177171384Sjfv 178171384Sjfv/* NVM Registers */ 179283620Serj#define IXGBE_EEC 0x10010 180283620Serj#define IXGBE_EEC_X540 IXGBE_EEC 181283620Serj#define IXGBE_EEC_X550 IXGBE_EEC 182283620Serj#define IXGBE_EEC_X550EM_x IXGBE_EEC 183315333Serj#define IXGBE_EEC_X550EM_a 0x15FF8 184315333Serj#define IXGBE_EEC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EEC) 185283620Serj 186283620Serj#define IXGBE_EERD 0x10014 187283620Serj#define IXGBE_EEWR 0x10018 188283620Serj 189283620Serj#define IXGBE_FLA 0x1001C 190283620Serj#define IXGBE_FLA_X540 IXGBE_FLA 191283620Serj#define IXGBE_FLA_X550 IXGBE_FLA 192283620Serj#define IXGBE_FLA_X550EM_x IXGBE_FLA 193315333Serj#define IXGBE_FLA_X550EM_a 0x15F68 194315333Serj#define IXGBE_FLA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FLA) 195283620Serj 196230775Sjfv#define IXGBE_EEMNGCTL 0x10110 197230775Sjfv#define IXGBE_EEMNGDATA 0x10114 198230775Sjfv#define IXGBE_FLMNGCTL 0x10118 199230775Sjfv#define IXGBE_FLMNGDATA 0x1011C 200230775Sjfv#define IXGBE_FLMNGCNT 0x10120 201230775Sjfv#define IXGBE_FLOP 0x1013C 202283620Serj 203283620Serj#define IXGBE_GRC 0x10200 204283620Serj#define IXGBE_GRC_X540 IXGBE_GRC 205283620Serj#define IXGBE_GRC_X550 IXGBE_GRC 206283620Serj#define IXGBE_GRC_X550EM_x IXGBE_GRC 207315333Serj#define IXGBE_GRC_X550EM_a 0x15F64 208315333Serj#define IXGBE_GRC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), GRC) 209283620Serj 210283620Serj#define IXGBE_SRAMREL 0x10210 211283620Serj#define IXGBE_SRAMREL_X540 IXGBE_SRAMREL 212283620Serj#define IXGBE_SRAMREL_X550 IXGBE_SRAMREL 213283620Serj#define IXGBE_SRAMREL_X550EM_x IXGBE_SRAMREL 214315333Serj#define IXGBE_SRAMREL_X550EM_a 0x15F6C 215315333Serj#define IXGBE_SRAMREL_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SRAMREL) 216283620Serj 217230775Sjfv#define IXGBE_PHYDBG 0x10218 218171384Sjfv 219190873Sjfv/* General Receive Control */ 220230775Sjfv#define IXGBE_GRC_MNG 0x00000001 /* Manageability Enable */ 221230775Sjfv#define IXGBE_GRC_APME 0x00000002 /* APM enabled in EEPROM */ 222190873Sjfv 223230775Sjfv#define IXGBE_VPDDIAG0 0x10204 224230775Sjfv#define IXGBE_VPDDIAG1 0x10208 225190873Sjfv 226190873Sjfv/* I2CCTL Bit Masks */ 227283620Serj#define IXGBE_I2C_CLK_IN 0x00000001 228283620Serj#define IXGBE_I2C_CLK_IN_X540 IXGBE_I2C_CLK_IN 229283620Serj#define IXGBE_I2C_CLK_IN_X550 0x00004000 230283620Serj#define IXGBE_I2C_CLK_IN_X550EM_x IXGBE_I2C_CLK_IN_X550 231315333Serj#define IXGBE_I2C_CLK_IN_X550EM_a IXGBE_I2C_CLK_IN_X550 232283620Serj#define IXGBE_I2C_CLK_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_IN) 233283620Serj 234283620Serj#define IXGBE_I2C_CLK_OUT 0x00000002 235283620Serj#define IXGBE_I2C_CLK_OUT_X540 IXGBE_I2C_CLK_OUT 236283620Serj#define IXGBE_I2C_CLK_OUT_X550 0x00000200 237283620Serj#define IXGBE_I2C_CLK_OUT_X550EM_x IXGBE_I2C_CLK_OUT_X550 238315333Serj#define IXGBE_I2C_CLK_OUT_X550EM_a IXGBE_I2C_CLK_OUT_X550 239283620Serj#define IXGBE_I2C_CLK_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OUT) 240283620Serj 241283620Serj#define IXGBE_I2C_DATA_IN 0x00000004 242283620Serj#define IXGBE_I2C_DATA_IN_X540 IXGBE_I2C_DATA_IN 243283620Serj#define IXGBE_I2C_DATA_IN_X550 0x00001000 244283620Serj#define IXGBE_I2C_DATA_IN_X550EM_x IXGBE_I2C_DATA_IN_X550 245315333Serj#define IXGBE_I2C_DATA_IN_X550EM_a IXGBE_I2C_DATA_IN_X550 246283620Serj#define IXGBE_I2C_DATA_IN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_IN) 247283620Serj 248283620Serj#define IXGBE_I2C_DATA_OUT 0x00000008 249283620Serj#define IXGBE_I2C_DATA_OUT_X540 IXGBE_I2C_DATA_OUT 250283620Serj#define IXGBE_I2C_DATA_OUT_X550 0x00000400 251283620Serj#define IXGBE_I2C_DATA_OUT_X550EM_x IXGBE_I2C_DATA_OUT_X550 252315333Serj#define IXGBE_I2C_DATA_OUT_X550EM_a IXGBE_I2C_DATA_OUT_X550 253283620Serj#define IXGBE_I2C_DATA_OUT_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OUT) 254283620Serj 255283620Serj#define IXGBE_I2C_DATA_OE_N_EN 0 256283620Serj#define IXGBE_I2C_DATA_OE_N_EN_X540 IXGBE_I2C_DATA_OE_N_EN 257283620Serj#define IXGBE_I2C_DATA_OE_N_EN_X550 0x00000800 258283620Serj#define IXGBE_I2C_DATA_OE_N_EN_X550EM_x IXGBE_I2C_DATA_OE_N_EN_X550 259315333Serj#define IXGBE_I2C_DATA_OE_N_EN_X550EM_a IXGBE_I2C_DATA_OE_N_EN_X550 260283620Serj#define IXGBE_I2C_DATA_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_DATA_OE_N_EN) 261283620Serj 262283620Serj#define IXGBE_I2C_BB_EN 0 263283620Serj#define IXGBE_I2C_BB_EN_X540 IXGBE_I2C_BB_EN 264283620Serj#define IXGBE_I2C_BB_EN_X550 0x00000100 265283620Serj#define IXGBE_I2C_BB_EN_X550EM_x IXGBE_I2C_BB_EN_X550 266315333Serj#define IXGBE_I2C_BB_EN_X550EM_a IXGBE_I2C_BB_EN_X550 267283620Serj 268283620Serj#define IXGBE_I2C_BB_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_BB_EN) 269283620Serj 270283620Serj#define IXGBE_I2C_CLK_OE_N_EN 0 271283620Serj#define IXGBE_I2C_CLK_OE_N_EN_X540 IXGBE_I2C_CLK_OE_N_EN 272283620Serj#define IXGBE_I2C_CLK_OE_N_EN_X550 0x00002000 273283620Serj#define IXGBE_I2C_CLK_OE_N_EN_X550EM_x IXGBE_I2C_CLK_OE_N_EN_X550 274315333Serj#define IXGBE_I2C_CLK_OE_N_EN_X550EM_a IXGBE_I2C_CLK_OE_N_EN_X550 275283620Serj#define IXGBE_I2C_CLK_OE_N_EN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), I2C_CLK_OE_N_EN) 276238149Sjfv#define IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT 500 277190873Sjfv 278238149Sjfv 279171384Sjfv/* Interrupt Registers */ 280230775Sjfv#define IXGBE_EICR 0x00800 281230775Sjfv#define IXGBE_EICS 0x00808 282230775Sjfv#define IXGBE_EIMS 0x00880 283230775Sjfv#define IXGBE_EIMC 0x00888 284230775Sjfv#define IXGBE_EIAC 0x00810 285230775Sjfv#define IXGBE_EIAM 0x00890 286230775Sjfv#define IXGBE_EICS_EX(_i) (0x00A90 + (_i) * 4) 287230775Sjfv#define IXGBE_EIMS_EX(_i) (0x00AA0 + (_i) * 4) 288230775Sjfv#define IXGBE_EIMC_EX(_i) (0x00AB0 + (_i) * 4) 289230775Sjfv#define IXGBE_EIAM_EX(_i) (0x00AD0 + (_i) * 4) 290190873Sjfv/* 82599 EITR is only 12 bits, with the lower 3 always zero */ 291190873Sjfv/* 292190873Sjfv * 82598 EITR is 16 bits but set the limits based on the max 293190873Sjfv * supported by all ixgbe hardware 294190873Sjfv */ 295230775Sjfv#define IXGBE_MAX_INT_RATE 488281 296230775Sjfv#define IXGBE_MIN_INT_RATE 956 297230775Sjfv#define IXGBE_MAX_EITR 0x00000FF8 298230775Sjfv#define IXGBE_MIN_EITR 8 299230775Sjfv#define IXGBE_EITR(_i) (((_i) <= 23) ? (0x00820 + ((_i) * 4)) : \ 300230775Sjfv (0x012300 + (((_i) - 24) * 4))) 301230775Sjfv#define IXGBE_EITR_ITR_INT_MASK 0x00000FF8 302230775Sjfv#define IXGBE_EITR_LLI_MOD 0x00008000 303230775Sjfv#define IXGBE_EITR_CNT_WDIS 0x80000000 304230775Sjfv#define IXGBE_IVAR(_i) (0x00900 + ((_i) * 4)) /* 24 at 0x900-0x960 */ 305230775Sjfv#define IXGBE_IVAR_MISC 0x00A00 /* misc MSI-X interrupt causes */ 306230775Sjfv#define IXGBE_EITRSEL 0x00894 307230775Sjfv#define IXGBE_MSIXT 0x00000 /* MSI-X Table. 0x0000 - 0x01C */ 308230775Sjfv#define IXGBE_MSIXPBA 0x02000 /* MSI-X Pending bit array */ 309230775Sjfv#define IXGBE_PBACL(_i) (((_i) == 0) ? (0x11068) : (0x110C0 + ((_i) * 4))) 310230775Sjfv#define IXGBE_GPIE 0x00898 311171384Sjfv 312171384Sjfv/* Flow Control Registers */ 313230775Sjfv#define IXGBE_FCADBUL 0x03210 314230775Sjfv#define IXGBE_FCADBUH 0x03214 315230775Sjfv#define IXGBE_FCAMACL 0x04328 316230775Sjfv#define IXGBE_FCAMACH 0x0432C 317230775Sjfv#define IXGBE_FCRTH_82599(_i) (0x03260 + ((_i) * 4)) /* 8 of these (0-7) */ 318230775Sjfv#define IXGBE_FCRTL_82599(_i) (0x03220 + ((_i) * 4)) /* 8 of these (0-7) */ 319230775Sjfv#define IXGBE_PFCTOP 0x03008 320230775Sjfv#define IXGBE_FCTTV(_i) (0x03200 + ((_i) * 4)) /* 4 of these (0-3) */ 321230775Sjfv#define IXGBE_FCRTL(_i) (0x03220 + ((_i) * 8)) /* 8 of these (0-7) */ 322230775Sjfv#define IXGBE_FCRTH(_i) (0x03260 + ((_i) * 8)) /* 8 of these (0-7) */ 323230775Sjfv#define IXGBE_FCRTV 0x032A0 324230775Sjfv#define IXGBE_FCCFG 0x03D00 325230775Sjfv#define IXGBE_TFCS 0x0CE00 326171384Sjfv 327171384Sjfv/* Receive DMA Registers */ 328230775Sjfv#define IXGBE_RDBAL(_i) (((_i) < 64) ? (0x01000 + ((_i) * 0x40)) : \ 329230775Sjfv (0x0D000 + (((_i) - 64) * 0x40))) 330230775Sjfv#define IXGBE_RDBAH(_i) (((_i) < 64) ? (0x01004 + ((_i) * 0x40)) : \ 331230775Sjfv (0x0D004 + (((_i) - 64) * 0x40))) 332230775Sjfv#define IXGBE_RDLEN(_i) (((_i) < 64) ? (0x01008 + ((_i) * 0x40)) : \ 333230775Sjfv (0x0D008 + (((_i) - 64) * 0x40))) 334230775Sjfv#define IXGBE_RDH(_i) (((_i) < 64) ? (0x01010 + ((_i) * 0x40)) : \ 335230775Sjfv (0x0D010 + (((_i) - 64) * 0x40))) 336230775Sjfv#define IXGBE_RDT(_i) (((_i) < 64) ? (0x01018 + ((_i) * 0x40)) : \ 337230775Sjfv (0x0D018 + (((_i) - 64) * 0x40))) 338230775Sjfv#define IXGBE_RXDCTL(_i) (((_i) < 64) ? (0x01028 + ((_i) * 0x40)) : \ 339230775Sjfv (0x0D028 + (((_i) - 64) * 0x40))) 340230775Sjfv#define IXGBE_RSCCTL(_i) (((_i) < 64) ? (0x0102C + ((_i) * 0x40)) : \ 341230775Sjfv (0x0D02C + (((_i) - 64) * 0x40))) 342230775Sjfv#define IXGBE_RSCDBU 0x03028 343230775Sjfv#define IXGBE_RDDCC 0x02F20 344230775Sjfv#define IXGBE_RXMEMWRAP 0x03190 345230775Sjfv#define IXGBE_STARCTRL 0x03024 346179055Sjfv/* 347179055Sjfv * Split and Replication Receive Control Registers 348179055Sjfv * 00-15 : 0x02100 + n*4 349179055Sjfv * 16-64 : 0x01014 + n*0x40 350179055Sjfv * 64-127: 0x0D014 + (n-64)*0x40 351179055Sjfv */ 352230775Sjfv#define IXGBE_SRRCTL(_i) (((_i) <= 15) ? (0x02100 + ((_i) * 4)) : \ 353230775Sjfv (((_i) < 64) ? (0x01014 + ((_i) * 0x40)) : \ 354230775Sjfv (0x0D014 + (((_i) - 64) * 0x40)))) 355179055Sjfv/* 356179055Sjfv * Rx DCA Control Register: 357179055Sjfv * 00-15 : 0x02200 + n*4 358179055Sjfv * 16-64 : 0x0100C + n*0x40 359179055Sjfv * 64-127: 0x0D00C + (n-64)*0x40 360179055Sjfv */ 361230775Sjfv#define IXGBE_DCA_RXCTRL(_i) (((_i) <= 15) ? (0x02200 + ((_i) * 4)) : \ 362230775Sjfv (((_i) < 64) ? (0x0100C + ((_i) * 0x40)) : \ 363230775Sjfv (0x0D00C + (((_i) - 64) * 0x40)))) 364230775Sjfv#define IXGBE_RDRXCTL 0x02F00 365230775Sjfv/* 8 of these 0x03C00 - 0x03C1C */ 366230775Sjfv#define IXGBE_RXPBSIZE(_i) (0x03C00 + ((_i) * 4)) 367230775Sjfv#define IXGBE_RXCTRL 0x03000 368230775Sjfv#define IXGBE_DROPEN 0x03D04 369230775Sjfv#define IXGBE_RXPBSIZE_SHIFT 10 370251964Sjfv#define IXGBE_RXPBSIZE_MASK 0x000FFC00 371171384Sjfv 372171384Sjfv/* Receive Registers */ 373230775Sjfv#define IXGBE_RXCSUM 0x05000 374230775Sjfv#define IXGBE_RFCTL 0x05008 375230775Sjfv#define IXGBE_DRECCCTL 0x02F08 376230775Sjfv#define IXGBE_DRECCCTL_DISABLE 0 377230775Sjfv#define IXGBE_DRECCCTL2 0x02F8C 378205720Sjfv 379179055Sjfv/* Multicast Table Array - 128 entries */ 380230775Sjfv#define IXGBE_MTA(_i) (0x05200 + ((_i) * 4)) 381230775Sjfv#define IXGBE_RAL(_i) (((_i) <= 15) ? (0x05400 + ((_i) * 8)) : \ 382230775Sjfv (0x0A200 + ((_i) * 8))) 383230775Sjfv#define IXGBE_RAH(_i) (((_i) <= 15) ? (0x05404 + ((_i) * 8)) : \ 384230775Sjfv (0x0A204 + ((_i) * 8))) 385230775Sjfv#define IXGBE_MPSAR_LO(_i) (0x0A600 + ((_i) * 8)) 386230775Sjfv#define IXGBE_MPSAR_HI(_i) (0x0A604 + ((_i) * 8)) 387179055Sjfv/* Packet split receive type */ 388230775Sjfv#define IXGBE_PSRTYPE(_i) (((_i) <= 15) ? (0x05480 + ((_i) * 4)) : \ 389230775Sjfv (0x0EA00 + ((_i) * 4))) 390179055Sjfv/* array of 4096 1-bit vlan filters */ 391230775Sjfv#define IXGBE_VFTA(_i) (0x0A000 + ((_i) * 4)) 392179055Sjfv/*array of 4096 4-bit vlan vmdq indices */ 393230775Sjfv#define IXGBE_VFTAVIND(_j, _i) (0x0A200 + ((_j) * 0x200) + ((_i) * 4)) 394230775Sjfv#define IXGBE_FCTRL 0x05080 395230775Sjfv#define IXGBE_VLNCTRL 0x05088 396230775Sjfv#define IXGBE_MCSTCTRL 0x05090 397230775Sjfv#define IXGBE_MRQC 0x05818 398230775Sjfv#define IXGBE_SAQF(_i) (0x0E000 + ((_i) * 4)) /* Source Address Queue Filter */ 399230775Sjfv#define IXGBE_DAQF(_i) (0x0E200 + ((_i) * 4)) /* Dest. Address Queue Filter */ 400230775Sjfv#define IXGBE_SDPQF(_i) (0x0E400 + ((_i) * 4)) /* Src Dest. Addr Queue Filter */ 401230775Sjfv#define IXGBE_FTQF(_i) (0x0E600 + ((_i) * 4)) /* Five Tuple Queue Filter */ 402230775Sjfv#define IXGBE_ETQF(_i) (0x05128 + ((_i) * 4)) /* EType Queue Filter */ 403230775Sjfv#define IXGBE_ETQS(_i) (0x0EC00 + ((_i) * 4)) /* EType Queue Select */ 404230775Sjfv#define IXGBE_SYNQF 0x0EC30 /* SYN Packet Queue Filter */ 405230775Sjfv#define IXGBE_RQTC 0x0EC70 406230775Sjfv#define IXGBE_MTQC 0x08120 407230775Sjfv#define IXGBE_VLVF(_i) (0x0F100 + ((_i) * 4)) /* 64 of these (0-63) */ 408230775Sjfv#define IXGBE_VLVFB(_i) (0x0F200 + ((_i) * 4)) /* 128 of these (0-127) */ 409230775Sjfv#define IXGBE_VMVIR(_i) (0x08000 + ((_i) * 4)) /* 64 of these (0-63) */ 410283620Serj#define IXGBE_PFFLPL 0x050B0 411283620Serj#define IXGBE_PFFLPH 0x050B4 412230775Sjfv#define IXGBE_VT_CTL 0x051B0 413230775Sjfv#define IXGBE_PFMAILBOX(_i) (0x04B00 + (4 * (_i))) /* 64 total */ 414230775Sjfv/* 64 Mailboxes, 16 DW each */ 415230775Sjfv#define IXGBE_PFMBMEM(_i) (0x13000 + (64 * (_i))) 416230775Sjfv#define IXGBE_PFMBICR(_i) (0x00710 + (4 * (_i))) /* 4 total */ 417230775Sjfv#define IXGBE_PFMBIMR(_i) (0x00720 + (4 * (_i))) /* 4 total */ 418230775Sjfv#define IXGBE_VFRE(_i) (0x051E0 + ((_i) * 4)) 419230775Sjfv#define IXGBE_VFTE(_i) (0x08110 + ((_i) * 4)) 420230775Sjfv#define IXGBE_VMECM(_i) (0x08790 + ((_i) * 4)) 421230775Sjfv#define IXGBE_QDE 0x2F04 422230775Sjfv#define IXGBE_VMTXSW(_i) (0x05180 + ((_i) * 4)) /* 2 total */ 423230775Sjfv#define IXGBE_VMOLR(_i) (0x0F000 + ((_i) * 4)) /* 64 total */ 424230775Sjfv#define IXGBE_UTA(_i) (0x0F400 + ((_i) * 4)) 425230775Sjfv#define IXGBE_MRCTL(_i) (0x0F600 + ((_i) * 4)) 426230775Sjfv#define IXGBE_VMRVLAN(_i) (0x0F610 + ((_i) * 4)) 427230775Sjfv#define IXGBE_VMRVM(_i) (0x0F630 + ((_i) * 4)) 428283620Serj#define IXGBE_LVMMC_RX 0x2FA8 429283620Serj#define IXGBE_LVMMC_TX 0x8108 430283620Serj#define IXGBE_LMVM_RX 0x2FA4 431283620Serj#define IXGBE_LMVM_TX 0x8124 432283620Serj#define IXGBE_WQBR_RX(_i) (0x2FB0 + ((_i) * 4)) /* 4 total */ 433283620Serj#define IXGBE_WQBR_TX(_i) (0x8130 + ((_i) * 4)) /* 4 total */ 434230775Sjfv#define IXGBE_L34T_IMIR(_i) (0x0E800 + ((_i) * 4)) /*128 of these (0-127)*/ 435230775Sjfv#define IXGBE_RXFECCERR0 0x051B8 436230775Sjfv#define IXGBE_LLITHRESH 0x0EC90 437230775Sjfv#define IXGBE_IMIR(_i) (0x05A80 + ((_i) * 4)) /* 8 of these (0-7) */ 438230775Sjfv#define IXGBE_IMIREXT(_i) (0x05AA0 + ((_i) * 4)) /* 8 of these (0-7) */ 439230775Sjfv#define IXGBE_IMIRVP 0x05AC0 440230775Sjfv#define IXGBE_VMD_CTL 0x0581C 441230775Sjfv#define IXGBE_RETA(_i) (0x05C00 + ((_i) * 4)) /* 32 of these (0-31) */ 442283620Serj#define IXGBE_ERETA(_i) (0x0EE80 + ((_i) * 4)) /* 96 of these (0-95) */ 443230775Sjfv#define IXGBE_RSSRK(_i) (0x05C80 + ((_i) * 4)) /* 10 of these (0-9) */ 444171384Sjfv 445283620Serj/* Registers for setting up RSS on X550 with SRIOV 446283620Serj * _p - pool number (0..63) 447283620Serj * _i - index (0..10 for PFVFRSSRK, 0..15 for PFVFRETA) 448283620Serj */ 449283620Serj#define IXGBE_PFVFMRQC(_p) (0x03400 + ((_p) * 4)) 450283620Serj#define IXGBE_PFVFRSSRK(_i, _p) (0x018000 + ((_i) * 4) + ((_p) * 0x40)) 451283620Serj#define IXGBE_PFVFRETA(_i, _p) (0x019000 + ((_i) * 4) + ((_p) * 0x40)) 452247822Sjfv 453190873Sjfv/* Flow Director registers */ 454230775Sjfv#define IXGBE_FDIRCTRL 0x0EE00 455230775Sjfv#define IXGBE_FDIRHKEY 0x0EE68 456230775Sjfv#define IXGBE_FDIRSKEY 0x0EE6C 457230775Sjfv#define IXGBE_FDIRDIP4M 0x0EE3C 458230775Sjfv#define IXGBE_FDIRSIP4M 0x0EE40 459230775Sjfv#define IXGBE_FDIRTCPM 0x0EE44 460230775Sjfv#define IXGBE_FDIRUDPM 0x0EE48 461283620Serj#define IXGBE_FDIRSCTPM 0x0EE78 462230775Sjfv#define IXGBE_FDIRIP6M 0x0EE74 463230775Sjfv#define IXGBE_FDIRM 0x0EE70 464179055Sjfv 465190873Sjfv/* Flow Director Stats registers */ 466230775Sjfv#define IXGBE_FDIRFREE 0x0EE38 467230775Sjfv#define IXGBE_FDIRLEN 0x0EE4C 468230775Sjfv#define IXGBE_FDIRUSTAT 0x0EE50 469230775Sjfv#define IXGBE_FDIRFSTAT 0x0EE54 470230775Sjfv#define IXGBE_FDIRMATCH 0x0EE58 471230775Sjfv#define IXGBE_FDIRMISS 0x0EE5C 472190873Sjfv 473190873Sjfv/* Flow Director Programming registers */ 474190873Sjfv#define IXGBE_FDIRSIPv6(_i) (0x0EE0C + ((_i) * 4)) /* 3 of these (0-2) */ 475230775Sjfv#define IXGBE_FDIRIPSA 0x0EE18 476230775Sjfv#define IXGBE_FDIRIPDA 0x0EE1C 477230775Sjfv#define IXGBE_FDIRPORT 0x0EE20 478230775Sjfv#define IXGBE_FDIRVLAN 0x0EE24 479230775Sjfv#define IXGBE_FDIRHASH 0x0EE28 480230775Sjfv#define IXGBE_FDIRCMD 0x0EE2C 481190873Sjfv 482171384Sjfv/* Transmit DMA registers */ 483230775Sjfv#define IXGBE_TDBAL(_i) (0x06000 + ((_i) * 0x40)) /* 32 of them (0-31)*/ 484230775Sjfv#define IXGBE_TDBAH(_i) (0x06004 + ((_i) * 0x40)) 485230775Sjfv#define IXGBE_TDLEN(_i) (0x06008 + ((_i) * 0x40)) 486230775Sjfv#define IXGBE_TDH(_i) (0x06010 + ((_i) * 0x40)) 487230775Sjfv#define IXGBE_TDT(_i) (0x06018 + ((_i) * 0x40)) 488230775Sjfv#define IXGBE_TXDCTL(_i) (0x06028 + ((_i) * 0x40)) 489230775Sjfv#define IXGBE_TDWBAL(_i) (0x06038 + ((_i) * 0x40)) 490230775Sjfv#define IXGBE_TDWBAH(_i) (0x0603C + ((_i) * 0x40)) 491230775Sjfv#define IXGBE_DTXCTL 0x07E00 492179055Sjfv 493230775Sjfv#define IXGBE_DMATXCTL 0x04A80 494230775Sjfv#define IXGBE_PFVFSPOOF(_i) (0x08200 + ((_i) * 4)) /* 8 of these 0 - 7 */ 495230775Sjfv#define IXGBE_PFDTXGSWC 0x08220 496230775Sjfv#define IXGBE_DTXMXSZRQ 0x08100 497230775Sjfv#define IXGBE_DTXTCPFLGL 0x04A88 498230775Sjfv#define IXGBE_DTXTCPFLGH 0x04A8C 499230775Sjfv#define IXGBE_LBDRPEN 0x0CA00 500230775Sjfv#define IXGBE_TXPBTHRESH(_i) (0x04950 + ((_i) * 4)) /* 8 of these 0 - 7 */ 501190873Sjfv 502230775Sjfv#define IXGBE_DMATXCTL_TE 0x1 /* Transmit Enable */ 503230775Sjfv#define IXGBE_DMATXCTL_NS 0x2 /* No Snoop LSO hdr buffer */ 504230775Sjfv#define IXGBE_DMATXCTL_GDV 0x8 /* Global Double VLAN */ 505283620Serj#define IXGBE_DMATXCTL_MDP_EN 0x20 /* Bit 5 */ 506283620Serj#define IXGBE_DMATXCTL_MBINTEN 0x40 /* Bit 6 */ 507230775Sjfv#define IXGBE_DMATXCTL_VT_SHIFT 16 /* VLAN EtherType */ 508194875Sjfv 509230775Sjfv#define IXGBE_PFDTXGSWC_VT_LBEN 0x1 /* Local L2 VT switch enable */ 510215911Sjfv 511215911Sjfv/* Anti-spoofing defines */ 512230775Sjfv#define IXGBE_SPOOF_MACAS_MASK 0xFF 513230775Sjfv#define IXGBE_SPOOF_VLANAS_MASK 0xFF00 514230775Sjfv#define IXGBE_SPOOF_VLANAS_SHIFT 8 515283620Serj#define IXGBE_SPOOF_ETHERTYPEAS 0xFF000000 516283620Serj#define IXGBE_SPOOF_ETHERTYPEAS_SHIFT 16 517230775Sjfv#define IXGBE_PFVFSPOOF_REG_COUNT 8 518230775Sjfv/* 16 of these (0-15) */ 519230775Sjfv#define IXGBE_DCA_TXCTRL(_i) (0x07200 + ((_i) * 4)) 520190873Sjfv/* Tx DCA Control register : 128 of these (0-127) */ 521230775Sjfv#define IXGBE_DCA_TXCTRL_82599(_i) (0x0600C + ((_i) * 0x40)) 522230775Sjfv#define IXGBE_TIPG 0x0CB00 523230775Sjfv#define IXGBE_TXPBSIZE(_i) (0x0CC00 + ((_i) * 4)) /* 8 of these */ 524230775Sjfv#define IXGBE_MNGTXMAP 0x0CD10 525230775Sjfv#define IXGBE_TIPG_FIBER_DEFAULT 3 526230775Sjfv#define IXGBE_TXPBSIZE_SHIFT 10 527171384Sjfv 528171384Sjfv/* Wake up registers */ 529230775Sjfv#define IXGBE_WUC 0x05800 530230775Sjfv#define IXGBE_WUFC 0x05808 531230775Sjfv#define IXGBE_WUS 0x05810 532230775Sjfv#define IXGBE_IPAV 0x05838 533230775Sjfv#define IXGBE_IP4AT 0x05840 /* IPv4 table 0x5840-0x5858 */ 534230775Sjfv#define IXGBE_IP6AT 0x05880 /* IPv6 table 0x5880-0x588F */ 535185352Sjfv 536230775Sjfv#define IXGBE_WUPL 0x05900 537230775Sjfv#define IXGBE_WUPM 0x05A00 /* wake up pkt memory 0x5A00-0x5A7C */ 538283620Serj#define IXGBE_PROXYS 0x05F60 /* Proxying Status Register */ 539283620Serj#define IXGBE_PROXYFC 0x05F64 /* Proxying Filter Control Register */ 540283620Serj#define IXGBE_VXLANCTRL 0x0000507C /* Rx filter VXLAN UDPPORT Register */ 541247822Sjfv 542315333Serj/* masks for accessing VXLAN and GENEVE UDP ports */ 543315333Serj#define IXGBE_VXLANCTRL_VXLAN_UDPPORT_MASK 0x0000ffff /* VXLAN port */ 544315333Serj#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_MASK 0xffff0000 /* GENEVE port */ 545315333Serj#define IXGBE_VXLANCTRL_ALL_UDPPORT_MASK 0xffffffff /* GENEVE/VXLAN */ 546315333Serj 547315333Serj#define IXGBE_VXLANCTRL_GENEVE_UDPPORT_SHIFT 16 548315333Serj 549283620Serj#define IXGBE_FHFT(_n) (0x09000 + ((_n) * 0x100)) /* Flex host filter table */ 550230775Sjfv/* Ext Flexible Host Filter Table */ 551283620Serj#define IXGBE_FHFT_EXT(_n) (0x09800 + ((_n) * 0x100)) 552283620Serj#define IXGBE_FHFT_EXT_X550(_n) (0x09600 + ((_n) * 0x100)) 553171384Sjfv 554247822Sjfv/* Four Flexible Filters are supported */ 555230775Sjfv#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX 4 556247822Sjfv 557247822Sjfv/* Six Flexible Filters are supported */ 558247822Sjfv#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_6 6 559283620Serj/* Eight Flexible Filters are supported */ 560283620Serj#define IXGBE_FLEXIBLE_FILTER_COUNT_MAX_8 8 561230775Sjfv#define IXGBE_EXT_FLEXIBLE_FILTER_COUNT_MAX 2 562185352Sjfv 563185352Sjfv/* Each Flexible Filter is at most 128 (0x80) bytes in length */ 564230775Sjfv#define IXGBE_FLEXIBLE_FILTER_SIZE_MAX 128 565230775Sjfv#define IXGBE_FHFT_LENGTH_OFFSET 0xFC /* Length byte in FHFT */ 566230775Sjfv#define IXGBE_FHFT_LENGTH_MASK 0x0FF /* Length in lower byte */ 567185352Sjfv 568185352Sjfv/* Definitions for power management and wakeup registers */ 569185352Sjfv/* Wake Up Control */ 570230775Sjfv#define IXGBE_WUC_PME_EN 0x00000002 /* PME Enable */ 571230775Sjfv#define IXGBE_WUC_PME_STATUS 0x00000004 /* PME Status */ 572230775Sjfv#define IXGBE_WUC_WKEN 0x00000010 /* Enable PE_WAKE_N pin assertion */ 573185352Sjfv 574185352Sjfv/* Wake Up Filter Control */ 575230775Sjfv#define IXGBE_WUFC_LNKC 0x00000001 /* Link Status Change Wakeup Enable */ 576230775Sjfv#define IXGBE_WUFC_MAG 0x00000002 /* Magic Packet Wakeup Enable */ 577230775Sjfv#define IXGBE_WUFC_EX 0x00000004 /* Directed Exact Wakeup Enable */ 578230775Sjfv#define IXGBE_WUFC_MC 0x00000008 /* Directed Multicast Wakeup Enable */ 579230775Sjfv#define IXGBE_WUFC_BC 0x00000010 /* Broadcast Wakeup Enable */ 580230775Sjfv#define IXGBE_WUFC_ARP 0x00000020 /* ARP Request Packet Wakeup Enable */ 581230775Sjfv#define IXGBE_WUFC_IPV4 0x00000040 /* Directed IPv4 Packet Wakeup Enable */ 582230775Sjfv#define IXGBE_WUFC_IPV6 0x00000080 /* Directed IPv6 Packet Wakeup Enable */ 583230775Sjfv#define IXGBE_WUFC_MNG 0x00000100 /* Directed Mgmt Packet Wakeup Enable */ 584185352Sjfv 585230775Sjfv#define IXGBE_WUFC_IGNORE_TCO 0x00008000 /* Ignore WakeOn TCO packets */ 586230775Sjfv#define IXGBE_WUFC_FLX0 0x00010000 /* Flexible Filter 0 Enable */ 587230775Sjfv#define IXGBE_WUFC_FLX1 0x00020000 /* Flexible Filter 1 Enable */ 588230775Sjfv#define IXGBE_WUFC_FLX2 0x00040000 /* Flexible Filter 2 Enable */ 589230775Sjfv#define IXGBE_WUFC_FLX3 0x00080000 /* Flexible Filter 3 Enable */ 590230775Sjfv#define IXGBE_WUFC_FLX4 0x00100000 /* Flexible Filter 4 Enable */ 591230775Sjfv#define IXGBE_WUFC_FLX5 0x00200000 /* Flexible Filter 5 Enable */ 592247822Sjfv#define IXGBE_WUFC_FLX_FILTERS 0x000F0000 /* Mask for 4 flex filters */ 593283620Serj#define IXGBE_WUFC_FLX_FILTERS_6 0x003F0000 /* Mask for 6 flex filters */ 594283620Serj#define IXGBE_WUFC_FLX_FILTERS_8 0x00FF0000 /* Mask for 8 flex filters */ 595283620Serj#define IXGBE_WUFC_FW_RST_WK 0x80000000 /* Ena wake on FW reset assertion */ 596230775Sjfv/* Mask for Ext. flex filters */ 597230775Sjfv#define IXGBE_WUFC_EXT_FLX_FILTERS 0x00300000 598247822Sjfv#define IXGBE_WUFC_ALL_FILTERS 0x000F00FF /* Mask all 4 flex filters */ 599247822Sjfv#define IXGBE_WUFC_ALL_FILTERS_6 0x003F00FF /* Mask all 6 flex filters */ 600283620Serj#define IXGBE_WUFC_ALL_FILTERS_8 0x00FF00FF /* Mask all 8 flex filters */ 601230775Sjfv#define IXGBE_WUFC_FLX_OFFSET 16 /* Offset to the Flexible Filters bits */ 602185352Sjfv 603185352Sjfv/* Wake Up Status */ 604230775Sjfv#define IXGBE_WUS_LNKC IXGBE_WUFC_LNKC 605230775Sjfv#define IXGBE_WUS_MAG IXGBE_WUFC_MAG 606230775Sjfv#define IXGBE_WUS_EX IXGBE_WUFC_EX 607230775Sjfv#define IXGBE_WUS_MC IXGBE_WUFC_MC 608230775Sjfv#define IXGBE_WUS_BC IXGBE_WUFC_BC 609230775Sjfv#define IXGBE_WUS_ARP IXGBE_WUFC_ARP 610230775Sjfv#define IXGBE_WUS_IPV4 IXGBE_WUFC_IPV4 611230775Sjfv#define IXGBE_WUS_IPV6 IXGBE_WUFC_IPV6 612230775Sjfv#define IXGBE_WUS_MNG IXGBE_WUFC_MNG 613230775Sjfv#define IXGBE_WUS_FLX0 IXGBE_WUFC_FLX0 614230775Sjfv#define IXGBE_WUS_FLX1 IXGBE_WUFC_FLX1 615230775Sjfv#define IXGBE_WUS_FLX2 IXGBE_WUFC_FLX2 616230775Sjfv#define IXGBE_WUS_FLX3 IXGBE_WUFC_FLX3 617230775Sjfv#define IXGBE_WUS_FLX4 IXGBE_WUFC_FLX4 618230775Sjfv#define IXGBE_WUS_FLX5 IXGBE_WUFC_FLX5 619230775Sjfv#define IXGBE_WUS_FLX_FILTERS IXGBE_WUFC_FLX_FILTERS 620283620Serj#define IXGBE_WUS_FW_RST_WK IXGBE_WUFC_FW_RST_WK 621283620Serj/* Proxy Status */ 622283620Serj#define IXGBE_PROXYS_EX 0x00000004 /* Exact packet received */ 623283620Serj#define IXGBE_PROXYS_ARP_DIR 0x00000020 /* ARP w/filter match received */ 624283620Serj#define IXGBE_PROXYS_NS 0x00000200 /* IPV6 NS received */ 625283620Serj#define IXGBE_PROXYS_NS_DIR 0x00000400 /* IPV6 NS w/DA match received */ 626283620Serj#define IXGBE_PROXYS_ARP 0x00000800 /* ARP request packet received */ 627283620Serj#define IXGBE_PROXYS_MLD 0x00001000 /* IPv6 MLD packet received */ 628185352Sjfv 629283620Serj/* Proxying Filter Control */ 630283620Serj#define IXGBE_PROXYFC_ENABLE 0x00000001 /* Port Proxying Enable */ 631283620Serj#define IXGBE_PROXYFC_EX 0x00000004 /* Directed Exact Proxy Enable */ 632283620Serj#define IXGBE_PROXYFC_ARP_DIR 0x00000020 /* Directed ARP Proxy Enable */ 633283620Serj#define IXGBE_PROXYFC_NS 0x00000200 /* IPv6 Neighbor Solicitation */ 634283620Serj#define IXGBE_PROXYFC_ARP 0x00000800 /* ARP Request Proxy Enable */ 635283620Serj#define IXGBE_PROXYFC_MLD 0x00000800 /* IPv6 MLD Proxy Enable */ 636283620Serj#define IXGBE_PROXYFC_NO_TCO 0x00008000 /* Ignore TCO packets */ 637283620Serj 638230775Sjfv#define IXGBE_WUPL_LENGTH_MASK 0xFFFF 639185352Sjfv 640185352Sjfv/* DCB registers */ 641230775Sjfv#define IXGBE_DCB_MAX_TRAFFIC_CLASS 8 642230775Sjfv#define IXGBE_RMCS 0x03D00 643230775Sjfv#define IXGBE_DPMCS 0x07F40 644230775Sjfv#define IXGBE_PDPMCS 0x0CD00 645230775Sjfv#define IXGBE_RUPPBMR 0x050A0 646230775Sjfv#define IXGBE_RT2CR(_i) (0x03C20 + ((_i) * 4)) /* 8 of these (0-7) */ 647230775Sjfv#define IXGBE_RT2SR(_i) (0x03C40 + ((_i) * 4)) /* 8 of these (0-7) */ 648230775Sjfv#define IXGBE_TDTQ2TCCR(_i) (0x0602C + ((_i) * 0x40)) /* 8 of these (0-7) */ 649230775Sjfv#define IXGBE_TDTQ2TCSR(_i) (0x0622C + ((_i) * 0x40)) /* 8 of these (0-7) */ 650230775Sjfv#define IXGBE_TDPT2TCCR(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 651230775Sjfv#define IXGBE_TDPT2TCSR(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 652171384Sjfv 653283620Serj/* Power Management */ 654283620Serj/* DMA Coalescing configuration */ 655283620Serjstruct ixgbe_dmac_config { 656283620Serj u16 watchdog_timer; /* usec units */ 657283620Serj bool fcoe_en; 658283620Serj u32 link_speed; 659283620Serj u8 fcoe_tc; 660283620Serj u8 num_tcs; 661283620Serj}; 662179055Sjfv 663283620Serj/* 664283620Serj * DMA Coalescing threshold Rx PB TC[n] value in Kilobyte by link speed. 665283620Serj * DMACRXT = 10Gbps = 10,000 bits / usec = 1250 bytes / usec 70 * 1250 == 666283620Serj * 87500 bytes [85KB] 667283620Serj */ 668283620Serj#define IXGBE_DMACRXT_10G 0x55 669283620Serj#define IXGBE_DMACRXT_1G 0x09 670283620Serj#define IXGBE_DMACRXT_100M 0x01 671251964Sjfv 672283620Serj/* DMA Coalescing registers */ 673283620Serj#define IXGBE_DMCMNGTH 0x15F20 /* Management Threshold */ 674283620Serj#define IXGBE_DMACR 0x02400 /* Control register */ 675283620Serj#define IXGBE_DMCTH(_i) (0x03300 + ((_i) * 4)) /* 8 of these */ 676283620Serj#define IXGBE_DMCTLX 0x02404 /* Time to Lx request */ 677283620Serj/* DMA Coalescing register fields */ 678283620Serj#define IXGBE_DMCMNGTH_DMCMNGTH_MASK 0x000FFFF0 /* Mng Threshold mask */ 679283620Serj#define IXGBE_DMCMNGTH_DMCMNGTH_SHIFT 4 /* Management Threshold shift */ 680283620Serj#define IXGBE_DMACR_DMACWT_MASK 0x0000FFFF /* Watchdog Timer mask */ 681283620Serj#define IXGBE_DMACR_HIGH_PRI_TC_MASK 0x00FF0000 682283620Serj#define IXGBE_DMACR_HIGH_PRI_TC_SHIFT 16 683283620Serj#define IXGBE_DMACR_EN_MNG_IND 0x10000000 /* Enable Mng Indications */ 684283620Serj#define IXGBE_DMACR_LX_COAL_IND 0x40000000 /* Lx Coalescing indicate */ 685283620Serj#define IXGBE_DMACR_DMAC_EN 0x80000000 /* DMA Coalescing Enable */ 686283620Serj#define IXGBE_DMCTH_DMACRXT_MASK 0x000001FF /* Receive Threshold mask */ 687283620Serj#define IXGBE_DMCTLX_TTLX_MASK 0x00000FFF /* Time to Lx request mask */ 688283620Serj 689283620Serj/* EEE registers */ 690283620Serj#define IXGBE_EEER 0x043A0 /* EEE register */ 691283620Serj#define IXGBE_EEE_STAT 0x04398 /* EEE Status */ 692283620Serj#define IXGBE_EEE_SU 0x04380 /* EEE Set up */ 693283620Serj#define IXGBE_EEE_SU_TEEE_DLY_SHIFT 26 694283620Serj#define IXGBE_TLPIC 0x041F4 /* EEE Tx LPI count */ 695283620Serj#define IXGBE_RLPIC 0x041F8 /* EEE Rx LPI count */ 696283620Serj 697283620Serj/* EEE register fields */ 698283620Serj#define IXGBE_EEER_TX_LPI_EN 0x00010000 /* Enable EEE LPI TX path */ 699283620Serj#define IXGBE_EEER_RX_LPI_EN 0x00020000 /* Enable EEE LPI RX path */ 700283620Serj#define IXGBE_EEE_STAT_NEG 0x20000000 /* EEE support neg on link */ 701283620Serj#define IXGBE_EEE_RX_LPI_STATUS 0x40000000 /* RX Link in LPI status */ 702283620Serj#define IXGBE_EEE_TX_LPI_STATUS 0x80000000 /* TX Link in LPI status */ 703283620Serj 704283620Serj 705283620Serj 706190873Sjfv/* Security Control Registers */ 707230775Sjfv#define IXGBE_SECTXCTRL 0x08800 708230775Sjfv#define IXGBE_SECTXSTAT 0x08804 709230775Sjfv#define IXGBE_SECTXBUFFAF 0x08808 710230775Sjfv#define IXGBE_SECTXMINIFG 0x08810 711230775Sjfv#define IXGBE_SECRXCTRL 0x08D00 712230775Sjfv#define IXGBE_SECRXSTAT 0x08D04 713179055Sjfv 714190873Sjfv/* Security Bit Fields and Masks */ 715230775Sjfv#define IXGBE_SECTXCTRL_SECTX_DIS 0x00000001 716230775Sjfv#define IXGBE_SECTXCTRL_TX_DIS 0x00000002 717230775Sjfv#define IXGBE_SECTXCTRL_STORE_FORWARD 0x00000004 718190873Sjfv 719230775Sjfv#define IXGBE_SECTXSTAT_SECTX_RDY 0x00000001 720230775Sjfv#define IXGBE_SECTXSTAT_ECC_TXERR 0x00000002 721190873Sjfv 722230775Sjfv#define IXGBE_SECRXCTRL_SECRX_DIS 0x00000001 723230775Sjfv#define IXGBE_SECRXCTRL_RX_DIS 0x00000002 724190873Sjfv 725230775Sjfv#define IXGBE_SECRXSTAT_SECRX_RDY 0x00000001 726230775Sjfv#define IXGBE_SECRXSTAT_ECC_RXERR 0x00000002 727190873Sjfv 728190873Sjfv/* LinkSec (MacSec) Registers */ 729230775Sjfv#define IXGBE_LSECTXCAP 0x08A00 730230775Sjfv#define IXGBE_LSECRXCAP 0x08F00 731230775Sjfv#define IXGBE_LSECTXCTRL 0x08A04 732230775Sjfv#define IXGBE_LSECTXSCL 0x08A08 /* SCI Low */ 733230775Sjfv#define IXGBE_LSECTXSCH 0x08A0C /* SCI High */ 734230775Sjfv#define IXGBE_LSECTXSA 0x08A10 735230775Sjfv#define IXGBE_LSECTXPN0 0x08A14 736230775Sjfv#define IXGBE_LSECTXPN1 0x08A18 737230775Sjfv#define IXGBE_LSECTXKEY0(_n) (0x08A1C + (4 * (_n))) /* 4 of these (0-3) */ 738230775Sjfv#define IXGBE_LSECTXKEY1(_n) (0x08A2C + (4 * (_n))) /* 4 of these (0-3) */ 739230775Sjfv#define IXGBE_LSECRXCTRL 0x08F04 740230775Sjfv#define IXGBE_LSECRXSCL 0x08F08 741230775Sjfv#define IXGBE_LSECRXSCH 0x08F0C 742230775Sjfv#define IXGBE_LSECRXSA(_i) (0x08F10 + (4 * (_i))) /* 2 of these (0-1) */ 743230775Sjfv#define IXGBE_LSECRXPN(_i) (0x08F18 + (4 * (_i))) /* 2 of these (0-1) */ 744230775Sjfv#define IXGBE_LSECRXKEY(_n, _m) (0x08F20 + ((0x10 * (_n)) + (4 * (_m)))) 745230775Sjfv#define IXGBE_LSECTXUT 0x08A3C /* OutPktsUntagged */ 746230775Sjfv#define IXGBE_LSECTXPKTE 0x08A40 /* OutPktsEncrypted */ 747230775Sjfv#define IXGBE_LSECTXPKTP 0x08A44 /* OutPktsProtected */ 748230775Sjfv#define IXGBE_LSECTXOCTE 0x08A48 /* OutOctetsEncrypted */ 749230775Sjfv#define IXGBE_LSECTXOCTP 0x08A4C /* OutOctetsProtected */ 750230775Sjfv#define IXGBE_LSECRXUT 0x08F40 /* InPktsUntagged/InPktsNoTag */ 751230775Sjfv#define IXGBE_LSECRXOCTD 0x08F44 /* InOctetsDecrypted */ 752230775Sjfv#define IXGBE_LSECRXOCTV 0x08F48 /* InOctetsValidated */ 753230775Sjfv#define IXGBE_LSECRXBAD 0x08F4C /* InPktsBadTag */ 754230775Sjfv#define IXGBE_LSECRXNOSCI 0x08F50 /* InPktsNoSci */ 755230775Sjfv#define IXGBE_LSECRXUNSCI 0x08F54 /* InPktsUnknownSci */ 756230775Sjfv#define IXGBE_LSECRXUNCH 0x08F58 /* InPktsUnchecked */ 757230775Sjfv#define IXGBE_LSECRXDELAY 0x08F5C /* InPktsDelayed */ 758230775Sjfv#define IXGBE_LSECRXLATE 0x08F60 /* InPktsLate */ 759230775Sjfv#define IXGBE_LSECRXOK(_n) (0x08F64 + (0x04 * (_n))) /* InPktsOk */ 760230775Sjfv#define IXGBE_LSECRXINV(_n) (0x08F6C + (0x04 * (_n))) /* InPktsInvalid */ 761230775Sjfv#define IXGBE_LSECRXNV(_n) (0x08F74 + (0x04 * (_n))) /* InPktsNotValid */ 762230775Sjfv#define IXGBE_LSECRXUNSA 0x08F7C /* InPktsUnusedSa */ 763230775Sjfv#define IXGBE_LSECRXNUSA 0x08F80 /* InPktsNotUsingSa */ 764190873Sjfv 765190873Sjfv/* LinkSec (MacSec) Bit Fields and Masks */ 766230775Sjfv#define IXGBE_LSECTXCAP_SUM_MASK 0x00FF0000 767230775Sjfv#define IXGBE_LSECTXCAP_SUM_SHIFT 16 768230775Sjfv#define IXGBE_LSECRXCAP_SUM_MASK 0x00FF0000 769230775Sjfv#define IXGBE_LSECRXCAP_SUM_SHIFT 16 770190873Sjfv 771230775Sjfv#define IXGBE_LSECTXCTRL_EN_MASK 0x00000003 772230775Sjfv#define IXGBE_LSECTXCTRL_DISABLE 0x0 773230775Sjfv#define IXGBE_LSECTXCTRL_AUTH 0x1 774230775Sjfv#define IXGBE_LSECTXCTRL_AUTH_ENCRYPT 0x2 775230775Sjfv#define IXGBE_LSECTXCTRL_AISCI 0x00000020 776230775Sjfv#define IXGBE_LSECTXCTRL_PNTHRSH_MASK 0xFFFFFF00 777230775Sjfv#define IXGBE_LSECTXCTRL_RSV_MASK 0x000000D8 778190873Sjfv 779230775Sjfv#define IXGBE_LSECRXCTRL_EN_MASK 0x0000000C 780230775Sjfv#define IXGBE_LSECRXCTRL_EN_SHIFT 2 781230775Sjfv#define IXGBE_LSECRXCTRL_DISABLE 0x0 782230775Sjfv#define IXGBE_LSECRXCTRL_CHECK 0x1 783230775Sjfv#define IXGBE_LSECRXCTRL_STRICT 0x2 784230775Sjfv#define IXGBE_LSECRXCTRL_DROP 0x3 785230775Sjfv#define IXGBE_LSECRXCTRL_PLSH 0x00000040 786230775Sjfv#define IXGBE_LSECRXCTRL_RP 0x00000080 787230775Sjfv#define IXGBE_LSECRXCTRL_RSV_MASK 0xFFFFFF33 788190873Sjfv 789190873Sjfv/* IpSec Registers */ 790230775Sjfv#define IXGBE_IPSTXIDX 0x08900 791230775Sjfv#define IXGBE_IPSTXSALT 0x08904 792230775Sjfv#define IXGBE_IPSTXKEY(_i) (0x08908 + (4 * (_i))) /* 4 of these (0-3) */ 793230775Sjfv#define IXGBE_IPSRXIDX 0x08E00 794230775Sjfv#define IXGBE_IPSRXIPADDR(_i) (0x08E04 + (4 * (_i))) /* 4 of these (0-3) */ 795230775Sjfv#define IXGBE_IPSRXSPI 0x08E14 796230775Sjfv#define IXGBE_IPSRXIPIDX 0x08E18 797230775Sjfv#define IXGBE_IPSRXKEY(_i) (0x08E1C + (4 * (_i))) /* 4 of these (0-3) */ 798230775Sjfv#define IXGBE_IPSRXSALT 0x08E2C 799230775Sjfv#define IXGBE_IPSRXMOD 0x08E30 800190873Sjfv 801230775Sjfv#define IXGBE_SECTXCTRL_STORE_FORWARD_ENABLE 0x4 802190873Sjfv 803190873Sjfv/* DCB registers */ 804230775Sjfv#define IXGBE_RTRPCS 0x02430 805230775Sjfv#define IXGBE_RTTDCS 0x04900 806230775Sjfv#define IXGBE_RTTDCS_ARBDIS 0x00000040 /* DCB arbiter disable */ 807230775Sjfv#define IXGBE_RTTPCS 0x0CD00 808230775Sjfv#define IXGBE_RTRUP2TC 0x03020 809230775Sjfv#define IXGBE_RTTUP2TC 0x0C800 810230775Sjfv#define IXGBE_RTRPT4C(_i) (0x02140 + ((_i) * 4)) /* 8 of these (0-7) */ 811230775Sjfv#define IXGBE_TXLLQ(_i) (0x082E0 + ((_i) * 4)) /* 4 of these (0-3) */ 812230775Sjfv#define IXGBE_RTRPT4S(_i) (0x02160 + ((_i) * 4)) /* 8 of these (0-7) */ 813230775Sjfv#define IXGBE_RTTDT2C(_i) (0x04910 + ((_i) * 4)) /* 8 of these (0-7) */ 814230775Sjfv#define IXGBE_RTTDT2S(_i) (0x04930 + ((_i) * 4)) /* 8 of these (0-7) */ 815230775Sjfv#define IXGBE_RTTPT2C(_i) (0x0CD20 + ((_i) * 4)) /* 8 of these (0-7) */ 816230775Sjfv#define IXGBE_RTTPT2S(_i) (0x0CD40 + ((_i) * 4)) /* 8 of these (0-7) */ 817230775Sjfv#define IXGBE_RTTDQSEL 0x04904 818230775Sjfv#define IXGBE_RTTDT1C 0x04908 819230775Sjfv#define IXGBE_RTTDT1S 0x0490C 820230775Sjfv#define IXGBE_RTTDTECC 0x04990 821230775Sjfv#define IXGBE_RTTDTECC_NO_BCN 0x00000100 822190873Sjfv 823230775Sjfv#define IXGBE_RTTBCNRC 0x04984 824230775Sjfv#define IXGBE_RTTBCNRC_RS_ENA 0x80000000 825230775Sjfv#define IXGBE_RTTBCNRC_RF_DEC_MASK 0x00003FFF 826230775Sjfv#define IXGBE_RTTBCNRC_RF_INT_SHIFT 14 827217593Sjfv#define IXGBE_RTTBCNRC_RF_INT_MASK \ 828217593Sjfv (IXGBE_RTTBCNRC_RF_DEC_MASK << IXGBE_RTTBCNRC_RF_INT_SHIFT) 829230775Sjfv#define IXGBE_RTTBCNRM 0x04980 830190873Sjfv 831190873Sjfv/* BCN (for DCB) Registers */ 832230775Sjfv#define IXGBE_RTTBCNRS 0x04988 833230775Sjfv#define IXGBE_RTTBCNCR 0x08B00 834230775Sjfv#define IXGBE_RTTBCNACH 0x08B04 835230775Sjfv#define IXGBE_RTTBCNACL 0x08B08 836230775Sjfv#define IXGBE_RTTBCNTG 0x04A90 837230775Sjfv#define IXGBE_RTTBCNIDX 0x08B0C 838230775Sjfv#define IXGBE_RTTBCNCP 0x08B10 839230775Sjfv#define IXGBE_RTFRTIMER 0x08B14 840230775Sjfv#define IXGBE_RTTBCNRTT 0x05150 841230775Sjfv#define IXGBE_RTTBCNRD 0x0498C 842190873Sjfv 843247822Sjfv 844190873Sjfv/* FCoE DMA Context Registers */ 845283620Serj/* FCoE Direct DMA Context */ 846283620Serj#define IXGBE_FCDDC(_i, _j) (0x20000 + ((_i) * 0x4) + ((_j) * 0x10)) 847230775Sjfv#define IXGBE_FCPTRL 0x02410 /* FC User Desc. PTR Low */ 848230775Sjfv#define IXGBE_FCPTRH 0x02414 /* FC USer Desc. PTR High */ 849230775Sjfv#define IXGBE_FCBUFF 0x02418 /* FC Buffer Control */ 850230775Sjfv#define IXGBE_FCDMARW 0x02420 /* FC Receive DMA RW */ 851230775Sjfv#define IXGBE_FCBUFF_VALID (1 << 0) /* DMA Context Valid */ 852230775Sjfv#define IXGBE_FCBUFF_BUFFSIZE (3 << 3) /* User Buffer Size */ 853230775Sjfv#define IXGBE_FCBUFF_WRCONTX (1 << 7) /* 0: Initiator, 1: Target */ 854230775Sjfv#define IXGBE_FCBUFF_BUFFCNT 0x0000ff00 /* Number of User Buffers */ 855230775Sjfv#define IXGBE_FCBUFF_OFFSET 0xffff0000 /* User Buffer Offset */ 856230775Sjfv#define IXGBE_FCBUFF_BUFFSIZE_SHIFT 3 857230775Sjfv#define IXGBE_FCBUFF_BUFFCNT_SHIFT 8 858230775Sjfv#define IXGBE_FCBUFF_OFFSET_SHIFT 16 859230775Sjfv#define IXGBE_FCDMARW_WE (1 << 14) /* Write enable */ 860230775Sjfv#define IXGBE_FCDMARW_RE (1 << 15) /* Read enable */ 861230775Sjfv#define IXGBE_FCDMARW_FCOESEL 0x000001ff /* FC X_ID: 11 bits */ 862230775Sjfv#define IXGBE_FCDMARW_LASTSIZE 0xffff0000 /* Last User Buffer Size */ 863230775Sjfv#define IXGBE_FCDMARW_LASTSIZE_SHIFT 16 864190873Sjfv/* FCoE SOF/EOF */ 865230775Sjfv#define IXGBE_TEOFF 0x04A94 /* Tx FC EOF */ 866230775Sjfv#define IXGBE_TSOFF 0x04A98 /* Tx FC SOF */ 867230775Sjfv#define IXGBE_REOFF 0x05158 /* Rx FC EOF */ 868230775Sjfv#define IXGBE_RSOFF 0x051F8 /* Rx FC SOF */ 869190873Sjfv/* FCoE Filter Context Registers */ 870283620Serj#define IXGBE_FCD_ID 0x05114 /* FCoE D_ID */ 871283620Serj#define IXGBE_FCSMAC 0x0510C /* FCoE Source MAC */ 872283620Serj#define IXGBE_FCFLTRW_SMAC_HIGH_SHIFT 16 873283620Serj/* FCoE Direct Filter Context */ 874283620Serj#define IXGBE_FCDFC(_i, _j) (0x28000 + ((_i) * 0x4) + ((_j) * 0x10)) 875283620Serj#define IXGBE_FCDFCD(_i) (0x30000 + ((_i) * 0x4)) 876230775Sjfv#define IXGBE_FCFLT 0x05108 /* FC FLT Context */ 877230775Sjfv#define IXGBE_FCFLTRW 0x05110 /* FC Filter RW Control */ 878230775Sjfv#define IXGBE_FCPARAM 0x051d8 /* FC Offset Parameter */ 879230775Sjfv#define IXGBE_FCFLT_VALID (1 << 0) /* Filter Context Valid */ 880230775Sjfv#define IXGBE_FCFLT_FIRST (1 << 1) /* Filter First */ 881230775Sjfv#define IXGBE_FCFLT_SEQID 0x00ff0000 /* Sequence ID */ 882230775Sjfv#define IXGBE_FCFLT_SEQCNT 0xff000000 /* Sequence Count */ 883230775Sjfv#define IXGBE_FCFLTRW_RVALDT (1 << 13) /* Fast Re-Validation */ 884230775Sjfv#define IXGBE_FCFLTRW_WE (1 << 14) /* Write Enable */ 885230775Sjfv#define IXGBE_FCFLTRW_RE (1 << 15) /* Read Enable */ 886190873Sjfv/* FCoE Receive Control */ 887230775Sjfv#define IXGBE_FCRXCTRL 0x05100 /* FC Receive Control */ 888230775Sjfv#define IXGBE_FCRXCTRL_FCOELLI (1 << 0) /* Low latency interrupt */ 889230775Sjfv#define IXGBE_FCRXCTRL_SAVBAD (1 << 1) /* Save Bad Frames */ 890230775Sjfv#define IXGBE_FCRXCTRL_FRSTRDH (1 << 2) /* EN 1st Read Header */ 891230775Sjfv#define IXGBE_FCRXCTRL_LASTSEQH (1 << 3) /* EN Last Header in Seq */ 892230775Sjfv#define IXGBE_FCRXCTRL_ALLH (1 << 4) /* EN All Headers */ 893230775Sjfv#define IXGBE_FCRXCTRL_FRSTSEQH (1 << 5) /* EN 1st Seq. Header */ 894230775Sjfv#define IXGBE_FCRXCTRL_ICRC (1 << 6) /* Ignore Bad FC CRC */ 895230775Sjfv#define IXGBE_FCRXCTRL_FCCRCBO (1 << 7) /* FC CRC Byte Ordering */ 896230775Sjfv#define IXGBE_FCRXCTRL_FCOEVER 0x00000f00 /* FCoE Version: 4 bits */ 897230775Sjfv#define IXGBE_FCRXCTRL_FCOEVER_SHIFT 8 898190873Sjfv/* FCoE Redirection */ 899230775Sjfv#define IXGBE_FCRECTL 0x0ED00 /* FC Redirection Control */ 900230775Sjfv#define IXGBE_FCRETA0 0x0ED10 /* FC Redirection Table 0 */ 901230775Sjfv#define IXGBE_FCRETA(_i) (IXGBE_FCRETA0 + ((_i) * 4)) /* FCoE Redir */ 902230775Sjfv#define IXGBE_FCRECTL_ENA 0x1 /* FCoE Redir Table Enable */ 903230775Sjfv#define IXGBE_FCRETASEL_ENA 0x2 /* FCoE FCRETASEL bit */ 904230775Sjfv#define IXGBE_FCRETA_SIZE 8 /* Max entries in FCRETA */ 905230775Sjfv#define IXGBE_FCRETA_ENTRY_MASK 0x0000007f /* 7 bits for the queue index */ 906283620Serj#define IXGBE_FCRETA_SIZE_X550 32 /* Max entries in FCRETA */ 907283620Serj/* Higher 7 bits for the queue index */ 908283620Serj#define IXGBE_FCRETA_ENTRY_HIGH_MASK 0x007F0000 909283620Serj#define IXGBE_FCRETA_ENTRY_HIGH_SHIFT 16 910190873Sjfv 911171384Sjfv/* Stats registers */ 912230775Sjfv#define IXGBE_CRCERRS 0x04000 913230775Sjfv#define IXGBE_ILLERRC 0x04004 914230775Sjfv#define IXGBE_ERRBC 0x04008 915230775Sjfv#define IXGBE_MSPDC 0x04010 916230775Sjfv#define IXGBE_MPC(_i) (0x03FA0 + ((_i) * 4)) /* 8 of these 3FA0-3FBC*/ 917230775Sjfv#define IXGBE_MLFC 0x04034 918230775Sjfv#define IXGBE_MRFC 0x04038 919230775Sjfv#define IXGBE_RLEC 0x04040 920230775Sjfv#define IXGBE_LXONTXC 0x03F60 921230775Sjfv#define IXGBE_LXONRXC 0x0CF60 922230775Sjfv#define IXGBE_LXOFFTXC 0x03F68 923230775Sjfv#define IXGBE_LXOFFRXC 0x0CF68 924230775Sjfv#define IXGBE_LXONRXCNT 0x041A4 925230775Sjfv#define IXGBE_LXOFFRXCNT 0x041A8 926230775Sjfv#define IXGBE_PXONRXCNT(_i) (0x04140 + ((_i) * 4)) /* 8 of these */ 927230775Sjfv#define IXGBE_PXOFFRXCNT(_i) (0x04160 + ((_i) * 4)) /* 8 of these */ 928230775Sjfv#define IXGBE_PXON2OFFCNT(_i) (0x03240 + ((_i) * 4)) /* 8 of these */ 929230775Sjfv#define IXGBE_PXONTXC(_i) (0x03F00 + ((_i) * 4)) /* 8 of these 3F00-3F1C*/ 930230775Sjfv#define IXGBE_PXONRXC(_i) (0x0CF00 + ((_i) * 4)) /* 8 of these CF00-CF1C*/ 931230775Sjfv#define IXGBE_PXOFFTXC(_i) (0x03F20 + ((_i) * 4)) /* 8 of these 3F20-3F3C*/ 932230775Sjfv#define IXGBE_PXOFFRXC(_i) (0x0CF20 + ((_i) * 4)) /* 8 of these CF20-CF3C*/ 933230775Sjfv#define IXGBE_PRC64 0x0405C 934230775Sjfv#define IXGBE_PRC127 0x04060 935230775Sjfv#define IXGBE_PRC255 0x04064 936230775Sjfv#define IXGBE_PRC511 0x04068 937230775Sjfv#define IXGBE_PRC1023 0x0406C 938230775Sjfv#define IXGBE_PRC1522 0x04070 939230775Sjfv#define IXGBE_GPRC 0x04074 940230775Sjfv#define IXGBE_BPRC 0x04078 941230775Sjfv#define IXGBE_MPRC 0x0407C 942230775Sjfv#define IXGBE_GPTC 0x04080 943230775Sjfv#define IXGBE_GORCL 0x04088 944230775Sjfv#define IXGBE_GORCH 0x0408C 945230775Sjfv#define IXGBE_GOTCL 0x04090 946230775Sjfv#define IXGBE_GOTCH 0x04094 947230775Sjfv#define IXGBE_RNBC(_i) (0x03FC0 + ((_i) * 4)) /* 8 of these 3FC0-3FDC*/ 948230775Sjfv#define IXGBE_RUC 0x040A4 949230775Sjfv#define IXGBE_RFC 0x040A8 950230775Sjfv#define IXGBE_ROC 0x040AC 951230775Sjfv#define IXGBE_RJC 0x040B0 952230775Sjfv#define IXGBE_MNGPRC 0x040B4 953230775Sjfv#define IXGBE_MNGPDC 0x040B8 954230775Sjfv#define IXGBE_MNGPTC 0x0CF90 955230775Sjfv#define IXGBE_TORL 0x040C0 956230775Sjfv#define IXGBE_TORH 0x040C4 957230775Sjfv#define IXGBE_TPR 0x040D0 958230775Sjfv#define IXGBE_TPT 0x040D4 959230775Sjfv#define IXGBE_PTC64 0x040D8 960230775Sjfv#define IXGBE_PTC127 0x040DC 961230775Sjfv#define IXGBE_PTC255 0x040E0 962230775Sjfv#define IXGBE_PTC511 0x040E4 963230775Sjfv#define IXGBE_PTC1023 0x040E8 964230775Sjfv#define IXGBE_PTC1522 0x040EC 965230775Sjfv#define IXGBE_MPTC 0x040F0 966230775Sjfv#define IXGBE_BPTC 0x040F4 967230775Sjfv#define IXGBE_XEC 0x04120 968230775Sjfv#define IXGBE_SSVPC 0x08780 969171384Sjfv 970230775Sjfv#define IXGBE_RQSMR(_i) (0x02300 + ((_i) * 4)) 971230775Sjfv#define IXGBE_TQSMR(_i) (((_i) <= 7) ? (0x07300 + ((_i) * 4)) : \ 972230775Sjfv (0x08600 + ((_i) * 4))) 973230775Sjfv#define IXGBE_TQSM(_i) (0x08600 + ((_i) * 4)) 974171384Sjfv 975230775Sjfv#define IXGBE_QPRC(_i) (0x01030 + ((_i) * 0x40)) /* 16 of these */ 976230775Sjfv#define IXGBE_QPTC(_i) (0x06030 + ((_i) * 0x40)) /* 16 of these */ 977230775Sjfv#define IXGBE_QBRC(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 978230775Sjfv#define IXGBE_QBTC(_i) (0x06034 + ((_i) * 0x40)) /* 16 of these */ 979230775Sjfv#define IXGBE_QBRC_L(_i) (0x01034 + ((_i) * 0x40)) /* 16 of these */ 980230775Sjfv#define IXGBE_QBRC_H(_i) (0x01038 + ((_i) * 0x40)) /* 16 of these */ 981230775Sjfv#define IXGBE_QPRDC(_i) (0x01430 + ((_i) * 0x40)) /* 16 of these */ 982230775Sjfv#define IXGBE_QBTC_L(_i) (0x08700 + ((_i) * 0x8)) /* 16 of these */ 983230775Sjfv#define IXGBE_QBTC_H(_i) (0x08704 + ((_i) * 0x8)) /* 16 of these */ 984230775Sjfv#define IXGBE_FCCRC 0x05118 /* Num of Good Eth CRC w/ Bad FC CRC */ 985230775Sjfv#define IXGBE_FCOERPDC 0x0241C /* FCoE Rx Packets Dropped Count */ 986230775Sjfv#define IXGBE_FCLAST 0x02424 /* FCoE Last Error Count */ 987230775Sjfv#define IXGBE_FCOEPRC 0x02428 /* Number of FCoE Packets Received */ 988230775Sjfv#define IXGBE_FCOEDWRC 0x0242C /* Number of FCoE DWords Received */ 989230775Sjfv#define IXGBE_FCOEPTC 0x08784 /* Number of FCoE Packets Transmitted */ 990230775Sjfv#define IXGBE_FCOEDWTC 0x08788 /* Number of FCoE DWords Transmitted */ 991230775Sjfv#define IXGBE_FCCRC_CNT_MASK 0x0000FFFF /* CRC_CNT: bit 0 - 15 */ 992230775Sjfv#define IXGBE_FCLAST_CNT_MASK 0x0000FFFF /* Last_CNT: bit 0 - 15 */ 993230775Sjfv#define IXGBE_O2BGPTC 0x041C4 994230775Sjfv#define IXGBE_O2BSPC 0x087B0 995230775Sjfv#define IXGBE_B2OSPC 0x041C0 996230775Sjfv#define IXGBE_B2OGPRC 0x02F90 997230775Sjfv#define IXGBE_BUPRC 0x04180 998230775Sjfv#define IXGBE_BMPRC 0x04184 999230775Sjfv#define IXGBE_BBPRC 0x04188 1000230775Sjfv#define IXGBE_BUPTC 0x0418C 1001230775Sjfv#define IXGBE_BMPTC 0x04190 1002230775Sjfv#define IXGBE_BBPTC 0x04194 1003230775Sjfv#define IXGBE_BCRCERRS 0x04198 1004230775Sjfv#define IXGBE_BXONRXC 0x0419C 1005230775Sjfv#define IXGBE_BXOFFRXC 0x041E0 1006230775Sjfv#define IXGBE_BXONTXC 0x041E4 1007230775Sjfv#define IXGBE_BXOFFTXC 0x041E8 1008171384Sjfv 1009171384Sjfv/* Management */ 1010230775Sjfv#define IXGBE_MAVTV(_i) (0x05010 + ((_i) * 4)) /* 8 of these (0-7) */ 1011230775Sjfv#define IXGBE_MFUTP(_i) (0x05030 + ((_i) * 4)) /* 8 of these (0-7) */ 1012230775Sjfv#define IXGBE_MANC 0x05820 1013230775Sjfv#define IXGBE_MFVAL 0x05824 1014230775Sjfv#define IXGBE_MANC2H 0x05860 1015230775Sjfv#define IXGBE_MDEF(_i) (0x05890 + ((_i) * 4)) /* 8 of these (0-7) */ 1016230775Sjfv#define IXGBE_MIPAF 0x058B0 1017230775Sjfv#define IXGBE_MMAL(_i) (0x05910 + ((_i) * 8)) /* 4 of these (0-3) */ 1018230775Sjfv#define IXGBE_MMAH(_i) (0x05914 + ((_i) * 8)) /* 4 of these (0-3) */ 1019230775Sjfv#define IXGBE_FTFT 0x09400 /* 0x9400-0x97FC */ 1020230775Sjfv#define IXGBE_METF(_i) (0x05190 + ((_i) * 4)) /* 4 of these (0-3) */ 1021230775Sjfv#define IXGBE_MDEF_EXT(_i) (0x05160 + ((_i) * 4)) /* 8 of these (0-7) */ 1022315333Serj#define IXGBE_LSWFW 0x15F14 1023230775Sjfv#define IXGBE_BMCIP(_i) (0x05050 + ((_i) * 4)) /* 0x5050-0x505C */ 1024230775Sjfv#define IXGBE_BMCIPVAL 0x05060 1025230775Sjfv#define IXGBE_BMCIP_IPADDR_TYPE 0x00000001 1026230775Sjfv#define IXGBE_BMCIP_IPADDR_VALID 0x00000002 1027171384Sjfv 1028230775Sjfv/* Management Bit Fields and Masks */ 1029283620Serj#define IXGBE_MANC_MPROXYE 0x40000000 /* Management Proxy Enable */ 1030247822Sjfv#define IXGBE_MANC_RCV_TCO_EN 0x00020000 /* Rcv TCO packet enable */ 1031230775Sjfv#define IXGBE_MANC_EN_BMC2OS 0x10000000 /* Ena BMC2OS and OS2BMC traffic */ 1032230775Sjfv#define IXGBE_MANC_EN_BMC2OS_SHIFT 28 1033230775Sjfv 1034230775Sjfv/* Firmware Semaphore Register */ 1035230775Sjfv#define IXGBE_FWSM_MODE_MASK 0xE 1036247822Sjfv#define IXGBE_FWSM_TS_ENABLED 0x1 1037247822Sjfv#define IXGBE_FWSM_FW_MODE_PT 0x4 1038230775Sjfv 1039171384Sjfv/* ARC Subsystem registers */ 1040230775Sjfv#define IXGBE_HICR 0x15F00 1041230775Sjfv#define IXGBE_FWSTS 0x15F0C 1042230775Sjfv#define IXGBE_HSMC0R 0x15F04 1043230775Sjfv#define IXGBE_HSMC1R 0x15F08 1044230775Sjfv#define IXGBE_SWSR 0x15F10 1045230775Sjfv#define IXGBE_HFDR 0x15FE8 1046230775Sjfv#define IXGBE_FLEX_MNG 0x15800 /* 0x15800 - 0x15EFC */ 1047171384Sjfv 1048230775Sjfv#define IXGBE_HICR_EN 0x01 /* Enable bit - RO */ 1049230775Sjfv/* Driver sets this bit when done to put command in RAM */ 1050230775Sjfv#define IXGBE_HICR_C 0x02 1051230775Sjfv#define IXGBE_HICR_SV 0x04 /* Status Validity */ 1052230775Sjfv#define IXGBE_HICR_FW_RESET_ENABLE 0x40 1053230775Sjfv#define IXGBE_HICR_FW_RESET 0x80 1054230775Sjfv 1055171384Sjfv/* PCI-E registers */ 1056230775Sjfv#define IXGBE_GCR 0x11000 1057230775Sjfv#define IXGBE_GTV 0x11004 1058230775Sjfv#define IXGBE_FUNCTAG 0x11008 1059230775Sjfv#define IXGBE_GLT 0x1100C 1060230775Sjfv#define IXGBE_PCIEPIPEADR 0x11004 1061230775Sjfv#define IXGBE_PCIEPIPEDAT 0x11008 1062230775Sjfv#define IXGBE_GSCL_1 0x11010 1063230775Sjfv#define IXGBE_GSCL_2 0x11014 1064315333Serj#define IXGBE_GSCL_1_X540 IXGBE_GSCL_1 1065315333Serj#define IXGBE_GSCL_2_X540 IXGBE_GSCL_2 1066230775Sjfv#define IXGBE_GSCL_3 0x11018 1067230775Sjfv#define IXGBE_GSCL_4 0x1101C 1068230775Sjfv#define IXGBE_GSCN_0 0x11020 1069230775Sjfv#define IXGBE_GSCN_1 0x11024 1070230775Sjfv#define IXGBE_GSCN_2 0x11028 1071230775Sjfv#define IXGBE_GSCN_3 0x1102C 1072315333Serj#define IXGBE_GSCN_0_X540 IXGBE_GSCN_0 1073315333Serj#define IXGBE_GSCN_1_X540 IXGBE_GSCN_1 1074315333Serj#define IXGBE_GSCN_2_X540 IXGBE_GSCN_2 1075315333Serj#define IXGBE_GSCN_3_X540 IXGBE_GSCN_3 1076230775Sjfv#define IXGBE_FACTPS 0x10150 1077283620Serj#define IXGBE_FACTPS_X540 IXGBE_FACTPS 1078315333Serj#define IXGBE_GSCL_1_X550 0x11800 1079315333Serj#define IXGBE_GSCL_2_X550 0x11804 1080315333Serj#define IXGBE_GSCL_1_X550EM_x IXGBE_GSCL_1_X550 1081315333Serj#define IXGBE_GSCL_2_X550EM_x IXGBE_GSCL_2_X550 1082315333Serj#define IXGBE_GSCN_0_X550 0x11820 1083315333Serj#define IXGBE_GSCN_1_X550 0x11824 1084315333Serj#define IXGBE_GSCN_2_X550 0x11828 1085315333Serj#define IXGBE_GSCN_3_X550 0x1182C 1086315333Serj#define IXGBE_GSCN_0_X550EM_x IXGBE_GSCN_0_X550 1087315333Serj#define IXGBE_GSCN_1_X550EM_x IXGBE_GSCN_1_X550 1088315333Serj#define IXGBE_GSCN_2_X550EM_x IXGBE_GSCN_2_X550 1089315333Serj#define IXGBE_GSCN_3_X550EM_x IXGBE_GSCN_3_X550 1090283620Serj#define IXGBE_FACTPS_X550 IXGBE_FACTPS 1091283620Serj#define IXGBE_FACTPS_X550EM_x IXGBE_FACTPS 1092315333Serj#define IXGBE_GSCL_1_X550EM_a IXGBE_GSCL_1_X550 1093315333Serj#define IXGBE_GSCL_2_X550EM_a IXGBE_GSCL_2_X550 1094315333Serj#define IXGBE_GSCN_0_X550EM_a IXGBE_GSCN_0_X550 1095315333Serj#define IXGBE_GSCN_1_X550EM_a IXGBE_GSCN_1_X550 1096315333Serj#define IXGBE_GSCN_2_X550EM_a IXGBE_GSCN_2_X550 1097315333Serj#define IXGBE_GSCN_3_X550EM_a IXGBE_GSCN_3_X550 1098315333Serj#define IXGBE_FACTPS_X550EM_a 0x15FEC 1099315333Serj#define IXGBE_FACTPS_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FACTPS) 1100283620Serj 1101230775Sjfv#define IXGBE_PCIEANACTL 0x11040 1102230775Sjfv#define IXGBE_SWSM 0x10140 1103283620Serj#define IXGBE_SWSM_X540 IXGBE_SWSM 1104283620Serj#define IXGBE_SWSM_X550 IXGBE_SWSM 1105283620Serj#define IXGBE_SWSM_X550EM_x IXGBE_SWSM 1106315333Serj#define IXGBE_SWSM_X550EM_a 0x15F70 1107315333Serj#define IXGBE_SWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWSM) 1108283620Serj 1109230775Sjfv#define IXGBE_FWSM 0x10148 1110283620Serj#define IXGBE_FWSM_X540 IXGBE_FWSM 1111283620Serj#define IXGBE_FWSM_X550 IXGBE_FWSM 1112283620Serj#define IXGBE_FWSM_X550EM_x IXGBE_FWSM 1113315333Serj#define IXGBE_FWSM_X550EM_a 0x15F74 1114315333Serj#define IXGBE_FWSM_BY_MAC(_hw) IXGBE_BY_MAC((_hw), FWSM) 1115283620Serj 1116283620Serj#define IXGBE_SWFW_SYNC IXGBE_GSSR 1117283620Serj#define IXGBE_SWFW_SYNC_X540 IXGBE_SWFW_SYNC 1118283620Serj#define IXGBE_SWFW_SYNC_X550 IXGBE_SWFW_SYNC 1119283620Serj#define IXGBE_SWFW_SYNC_X550EM_x IXGBE_SWFW_SYNC 1120315333Serj#define IXGBE_SWFW_SYNC_X550EM_a 0x15F78 1121315333Serj#define IXGBE_SWFW_SYNC_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SWFW_SYNC) 1122283620Serj 1123230775Sjfv#define IXGBE_GSSR 0x10160 1124230775Sjfv#define IXGBE_MREVID 0x11064 1125230775Sjfv#define IXGBE_DCA_ID 0x11070 1126230775Sjfv#define IXGBE_DCA_CTRL 0x11074 1127171384Sjfv 1128190873Sjfv/* PCI-E registers 82599-Specific */ 1129230775Sjfv#define IXGBE_GCR_EXT 0x11050 1130230775Sjfv#define IXGBE_GSCL_5_82599 0x11030 1131230775Sjfv#define IXGBE_GSCL_6_82599 0x11034 1132230775Sjfv#define IXGBE_GSCL_7_82599 0x11038 1133230775Sjfv#define IXGBE_GSCL_8_82599 0x1103C 1134315333Serj#define IXGBE_GSCL_5_X540 IXGBE_GSCL_5_82599 1135315333Serj#define IXGBE_GSCL_6_X540 IXGBE_GSCL_6_82599 1136315333Serj#define IXGBE_GSCL_7_X540 IXGBE_GSCL_7_82599 1137315333Serj#define IXGBE_GSCL_8_X540 IXGBE_GSCL_8_82599 1138230775Sjfv#define IXGBE_PHYADR_82599 0x11040 1139230775Sjfv#define IXGBE_PHYDAT_82599 0x11044 1140230775Sjfv#define IXGBE_PHYCTL_82599 0x11048 1141230775Sjfv#define IXGBE_PBACLR_82599 0x11068 1142283620Serj#define IXGBE_CIAA 0x11088 1143283620Serj#define IXGBE_CIAD 0x1108C 1144283620Serj#define IXGBE_CIAA_82599 IXGBE_CIAA 1145283620Serj#define IXGBE_CIAD_82599 IXGBE_CIAD 1146283620Serj#define IXGBE_CIAA_X540 IXGBE_CIAA 1147283620Serj#define IXGBE_CIAD_X540 IXGBE_CIAD 1148315333Serj#define IXGBE_GSCL_5_X550 0x11810 1149315333Serj#define IXGBE_GSCL_6_X550 0x11814 1150315333Serj#define IXGBE_GSCL_7_X550 0x11818 1151315333Serj#define IXGBE_GSCL_8_X550 0x1181C 1152315333Serj#define IXGBE_GSCL_5_X550EM_x IXGBE_GSCL_5_X550 1153315333Serj#define IXGBE_GSCL_6_X550EM_x IXGBE_GSCL_6_X550 1154315333Serj#define IXGBE_GSCL_7_X550EM_x IXGBE_GSCL_7_X550 1155315333Serj#define IXGBE_GSCL_8_X550EM_x IXGBE_GSCL_8_X550 1156283620Serj#define IXGBE_CIAA_X550 0x11508 1157283620Serj#define IXGBE_CIAD_X550 0x11510 1158283620Serj#define IXGBE_CIAA_X550EM_x IXGBE_CIAA_X550 1159283620Serj#define IXGBE_CIAD_X550EM_x IXGBE_CIAD_X550 1160315333Serj#define IXGBE_GSCL_5_X550EM_a IXGBE_GSCL_5_X550 1161315333Serj#define IXGBE_GSCL_6_X550EM_a IXGBE_GSCL_6_X550 1162315333Serj#define IXGBE_GSCL_7_X550EM_a IXGBE_GSCL_7_X550 1163315333Serj#define IXGBE_GSCL_8_X550EM_a IXGBE_GSCL_8_X550 1164315333Serj#define IXGBE_CIAA_X550EM_a IXGBE_CIAA_X550 1165315333Serj#define IXGBE_CIAD_X550EM_a IXGBE_CIAD_X550 1166283620Serj#define IXGBE_CIAA_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAA) 1167283620Serj#define IXGBE_CIAD_BY_MAC(_hw) IXGBE_BY_MAC((_hw), CIAD) 1168230775Sjfv#define IXGBE_PICAUSE 0x110B0 1169230775Sjfv#define IXGBE_PIENA 0x110B8 1170230775Sjfv#define IXGBE_CDQ_MBR_82599 0x110B4 1171230775Sjfv#define IXGBE_PCIESPARE 0x110BC 1172230775Sjfv#define IXGBE_MISC_REG_82599 0x110F0 1173230775Sjfv#define IXGBE_ECC_CTRL_0_82599 0x11100 1174230775Sjfv#define IXGBE_ECC_CTRL_1_82599 0x11104 1175230775Sjfv#define IXGBE_ECC_STATUS_82599 0x110E0 1176230775Sjfv#define IXGBE_BAR_CTRL_82599 0x110F4 1177190873Sjfv 1178200239Sjfv/* PCI Express Control */ 1179230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_MASK 0x0000F000 1180230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_10ms 0x00001000 1181230775Sjfv#define IXGBE_GCR_CMPL_TMOUT_RESEND 0x00010000 1182230775Sjfv#define IXGBE_GCR_CAP_VER2 0x00040000 1183200239Sjfv 1184230775Sjfv#define IXGBE_GCR_EXT_MSIX_EN 0x80000000 1185230775Sjfv#define IXGBE_GCR_EXT_BUFFERS_CLEAR 0x40000000 1186230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_16 0x00000001 1187230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_32 0x00000002 1188230775Sjfv#define IXGBE_GCR_EXT_VT_MODE_64 0x00000003 1189230775Sjfv#define IXGBE_GCR_EXT_SRIOV (IXGBE_GCR_EXT_MSIX_EN | \ 1190230775Sjfv IXGBE_GCR_EXT_VT_MODE_64) 1191238149Sjfv#define IXGBE_GCR_EXT_VT_MODE_MASK 0x00000003 1192190873Sjfv/* Time Sync Registers */ 1193230775Sjfv#define IXGBE_TSYNCRXCTL 0x05188 /* Rx Time Sync Control register - RW */ 1194230775Sjfv#define IXGBE_TSYNCTXCTL 0x08C00 /* Tx Time Sync Control register - RW */ 1195230775Sjfv#define IXGBE_RXSTMPL 0x051E8 /* Rx timestamp Low - RO */ 1196230775Sjfv#define IXGBE_RXSTMPH 0x051A4 /* Rx timestamp High - RO */ 1197230775Sjfv#define IXGBE_RXSATRL 0x051A0 /* Rx timestamp attribute low - RO */ 1198230775Sjfv#define IXGBE_RXSATRH 0x051A8 /* Rx timestamp attribute high - RO */ 1199230775Sjfv#define IXGBE_RXMTRL 0x05120 /* RX message type register low - RW */ 1200230775Sjfv#define IXGBE_TXSTMPL 0x08C04 /* Tx timestamp value Low - RO */ 1201230775Sjfv#define IXGBE_TXSTMPH 0x08C08 /* Tx timestamp value High - RO */ 1202230775Sjfv#define IXGBE_SYSTIML 0x08C0C /* System time register Low - RO */ 1203230775Sjfv#define IXGBE_SYSTIMH 0x08C10 /* System time register High - RO */ 1204283620Serj#define IXGBE_SYSTIMR 0x08C58 /* System time register Residue - RO */ 1205230775Sjfv#define IXGBE_TIMINCA 0x08C14 /* Increment attributes register - RW */ 1206230775Sjfv#define IXGBE_TIMADJL 0x08C18 /* Time Adjustment Offset register Low - RW */ 1207230775Sjfv#define IXGBE_TIMADJH 0x08C1C /* Time Adjustment Offset register High - RW */ 1208230775Sjfv#define IXGBE_TSAUXC 0x08C20 /* TimeSync Auxiliary Control register - RW */ 1209230775Sjfv#define IXGBE_TRGTTIML0 0x08C24 /* Target Time Register 0 Low - RW */ 1210230775Sjfv#define IXGBE_TRGTTIMH0 0x08C28 /* Target Time Register 0 High - RW */ 1211230775Sjfv#define IXGBE_TRGTTIML1 0x08C2C /* Target Time Register 1 Low - RW */ 1212230775Sjfv#define IXGBE_TRGTTIMH1 0x08C30 /* Target Time Register 1 High - RW */ 1213238149Sjfv#define IXGBE_CLKTIML 0x08C34 /* Clock Out Time Register Low - RW */ 1214238149Sjfv#define IXGBE_CLKTIMH 0x08C38 /* Clock Out Time Register High - RW */ 1215230775Sjfv#define IXGBE_FREQOUT0 0x08C34 /* Frequency Out 0 Control register - RW */ 1216230775Sjfv#define IXGBE_FREQOUT1 0x08C38 /* Frequency Out 1 Control register - RW */ 1217230775Sjfv#define IXGBE_AUXSTMPL0 0x08C3C /* Auxiliary Time Stamp 0 register Low - RO */ 1218230775Sjfv#define IXGBE_AUXSTMPH0 0x08C40 /* Auxiliary Time Stamp 0 register High - RO */ 1219230775Sjfv#define IXGBE_AUXSTMPL1 0x08C44 /* Auxiliary Time Stamp 1 register Low - RO */ 1220230775Sjfv#define IXGBE_AUXSTMPH1 0x08C48 /* Auxiliary Time Stamp 1 register High - RO */ 1221283620Serj#define IXGBE_TSIM 0x08C68 /* TimeSync Interrupt Mask Register - RW */ 1222283620Serj#define IXGBE_TSICR 0x08C60 /* TimeSync Interrupt Cause Register - WO */ 1223283620Serj#define IXGBE_TSSDP 0x0003C /* TimeSync SDP Configuration Register - RW */ 1224190873Sjfv 1225171384Sjfv/* Diagnostic Registers */ 1226230775Sjfv#define IXGBE_RDSTATCTL 0x02C20 1227230775Sjfv#define IXGBE_RDSTAT(_i) (0x02C00 + ((_i) * 4)) /* 0x02C00-0x02C1C */ 1228230775Sjfv#define IXGBE_RDHMPN 0x02F08 1229230775Sjfv#define IXGBE_RIC_DW(_i) (0x02F10 + ((_i) * 4)) 1230230775Sjfv#define IXGBE_RDPROBE 0x02F20 1231230775Sjfv#define IXGBE_RDMAM 0x02F30 1232230775Sjfv#define IXGBE_RDMAD 0x02F34 1233230775Sjfv#define IXGBE_TDHMPN 0x07F08 1234230775Sjfv#define IXGBE_TDHMPN2 0x082FC 1235230775Sjfv#define IXGBE_TXDESCIC 0x082CC 1236230775Sjfv#define IXGBE_TIC_DW(_i) (0x07F10 + ((_i) * 4)) 1237230775Sjfv#define IXGBE_TIC_DW2(_i) (0x082B0 + ((_i) * 4)) 1238230775Sjfv#define IXGBE_TDPROBE 0x07F20 1239230775Sjfv#define IXGBE_TXBUFCTRL 0x0C600 1240230775Sjfv#define IXGBE_TXBUFDATA0 0x0C610 1241230775Sjfv#define IXGBE_TXBUFDATA1 0x0C614 1242230775Sjfv#define IXGBE_TXBUFDATA2 0x0C618 1243230775Sjfv#define IXGBE_TXBUFDATA3 0x0C61C 1244230775Sjfv#define IXGBE_RXBUFCTRL 0x03600 1245230775Sjfv#define IXGBE_RXBUFDATA0 0x03610 1246230775Sjfv#define IXGBE_RXBUFDATA1 0x03614 1247230775Sjfv#define IXGBE_RXBUFDATA2 0x03618 1248230775Sjfv#define IXGBE_RXBUFDATA3 0x0361C 1249230775Sjfv#define IXGBE_PCIE_DIAG(_i) (0x11090 + ((_i) * 4)) /* 8 of these */ 1250230775Sjfv#define IXGBE_RFVAL 0x050A4 1251230775Sjfv#define IXGBE_MDFTC1 0x042B8 1252230775Sjfv#define IXGBE_MDFTC2 0x042C0 1253230775Sjfv#define IXGBE_MDFTFIFO1 0x042C4 1254230775Sjfv#define IXGBE_MDFTFIFO2 0x042C8 1255230775Sjfv#define IXGBE_MDFTS 0x042CC 1256230775Sjfv#define IXGBE_RXDATAWRPTR(_i) (0x03700 + ((_i) * 4)) /* 8 of these 3700-370C*/ 1257230775Sjfv#define IXGBE_RXDESCWRPTR(_i) (0x03710 + ((_i) * 4)) /* 8 of these 3710-371C*/ 1258230775Sjfv#define IXGBE_RXDATARDPTR(_i) (0x03720 + ((_i) * 4)) /* 8 of these 3720-372C*/ 1259230775Sjfv#define IXGBE_RXDESCRDPTR(_i) (0x03730 + ((_i) * 4)) /* 8 of these 3730-373C*/ 1260230775Sjfv#define IXGBE_TXDATAWRPTR(_i) (0x0C700 + ((_i) * 4)) /* 8 of these C700-C70C*/ 1261230775Sjfv#define IXGBE_TXDESCWRPTR(_i) (0x0C710 + ((_i) * 4)) /* 8 of these C710-C71C*/ 1262230775Sjfv#define IXGBE_TXDATARDPTR(_i) (0x0C720 + ((_i) * 4)) /* 8 of these C720-C72C*/ 1263230775Sjfv#define IXGBE_TXDESCRDPTR(_i) (0x0C730 + ((_i) * 4)) /* 8 of these C730-C73C*/ 1264230775Sjfv#define IXGBE_PCIEECCCTL 0x1106C 1265230775Sjfv#define IXGBE_RXWRPTR(_i) (0x03100 + ((_i) * 4)) /* 8 of these 3100-310C*/ 1266230775Sjfv#define IXGBE_RXUSED(_i) (0x03120 + ((_i) * 4)) /* 8 of these 3120-312C*/ 1267230775Sjfv#define IXGBE_RXRDPTR(_i) (0x03140 + ((_i) * 4)) /* 8 of these 3140-314C*/ 1268230775Sjfv#define IXGBE_RXRDWRPTR(_i) (0x03160 + ((_i) * 4)) /* 8 of these 3160-310C*/ 1269230775Sjfv#define IXGBE_TXWRPTR(_i) (0x0C100 + ((_i) * 4)) /* 8 of these C100-C10C*/ 1270230775Sjfv#define IXGBE_TXUSED(_i) (0x0C120 + ((_i) * 4)) /* 8 of these C120-C12C*/ 1271230775Sjfv#define IXGBE_TXRDPTR(_i) (0x0C140 + ((_i) * 4)) /* 8 of these C140-C14C*/ 1272230775Sjfv#define IXGBE_TXRDWRPTR(_i) (0x0C160 + ((_i) * 4)) /* 8 of these C160-C10C*/ 1273230775Sjfv#define IXGBE_PCIEECCCTL0 0x11100 1274230775Sjfv#define IXGBE_PCIEECCCTL1 0x11104 1275230775Sjfv#define IXGBE_RXDBUECC 0x03F70 1276230775Sjfv#define IXGBE_TXDBUECC 0x0CF70 1277230775Sjfv#define IXGBE_RXDBUEST 0x03F74 1278230775Sjfv#define IXGBE_TXDBUEST 0x0CF74 1279230775Sjfv#define IXGBE_PBTXECC 0x0C300 1280230775Sjfv#define IXGBE_PBRXECC 0x03300 1281230775Sjfv#define IXGBE_GHECCR 0x110B0 1282171384Sjfv 1283171384Sjfv/* MAC Registers */ 1284230775Sjfv#define IXGBE_PCS1GCFIG 0x04200 1285230775Sjfv#define IXGBE_PCS1GLCTL 0x04208 1286230775Sjfv#define IXGBE_PCS1GLSTA 0x0420C 1287230775Sjfv#define IXGBE_PCS1GDBG0 0x04210 1288230775Sjfv#define IXGBE_PCS1GDBG1 0x04214 1289230775Sjfv#define IXGBE_PCS1GANA 0x04218 1290230775Sjfv#define IXGBE_PCS1GANLP 0x0421C 1291230775Sjfv#define IXGBE_PCS1GANNP 0x04220 1292230775Sjfv#define IXGBE_PCS1GANLPNP 0x04224 1293230775Sjfv#define IXGBE_HLREG0 0x04240 1294230775Sjfv#define IXGBE_HLREG1 0x04244 1295230775Sjfv#define IXGBE_PAP 0x04248 1296230775Sjfv#define IXGBE_MACA 0x0424C 1297230775Sjfv#define IXGBE_APAE 0x04250 1298230775Sjfv#define IXGBE_ARD 0x04254 1299230775Sjfv#define IXGBE_AIS 0x04258 1300230775Sjfv#define IXGBE_MSCA 0x0425C 1301230775Sjfv#define IXGBE_MSRWD 0x04260 1302230775Sjfv#define IXGBE_MLADD 0x04264 1303230775Sjfv#define IXGBE_MHADD 0x04268 1304230775Sjfv#define IXGBE_MAXFRS 0x04268 1305230775Sjfv#define IXGBE_TREG 0x0426C 1306230775Sjfv#define IXGBE_PCSS1 0x04288 1307230775Sjfv#define IXGBE_PCSS2 0x0428C 1308230775Sjfv#define IXGBE_XPCSS 0x04290 1309230775Sjfv#define IXGBE_MFLCN 0x04294 1310230775Sjfv#define IXGBE_SERDESC 0x04298 1311315333Serj#define IXGBE_MAC_SGMII_BUSY 0x04298 1312230775Sjfv#define IXGBE_MACS 0x0429C 1313230775Sjfv#define IXGBE_AUTOC 0x042A0 1314230775Sjfv#define IXGBE_LINKS 0x042A4 1315230775Sjfv#define IXGBE_LINKS2 0x04324 1316230775Sjfv#define IXGBE_AUTOC2 0x042A8 1317230775Sjfv#define IXGBE_AUTOC3 0x042AC 1318230775Sjfv#define IXGBE_ANLP1 0x042B0 1319230775Sjfv#define IXGBE_ANLP2 0x042B4 1320230775Sjfv#define IXGBE_MACC 0x04330 1321230775Sjfv#define IXGBE_ATLASCTL 0x04800 1322230775Sjfv#define IXGBE_MMNGC 0x042D0 1323230775Sjfv#define IXGBE_ANLPNP1 0x042D4 1324230775Sjfv#define IXGBE_ANLPNP2 0x042D8 1325230775Sjfv#define IXGBE_KRPCSFC 0x042E0 1326230775Sjfv#define IXGBE_KRPCSS 0x042E4 1327230775Sjfv#define IXGBE_FECS1 0x042E8 1328230775Sjfv#define IXGBE_FECS2 0x042EC 1329230775Sjfv#define IXGBE_SMADARCTL 0x14F10 1330230775Sjfv#define IXGBE_MPVC 0x04318 1331230775Sjfv#define IXGBE_SGMIIC 0x04314 1332171384Sjfv 1333230775Sjfv/* Statistics Registers */ 1334230775Sjfv#define IXGBE_RXNFGPC 0x041B0 1335230775Sjfv#define IXGBE_RXNFGBCL 0x041B4 1336230775Sjfv#define IXGBE_RXNFGBCH 0x041B8 1337230775Sjfv#define IXGBE_RXDGPC 0x02F50 1338230775Sjfv#define IXGBE_RXDGBCL 0x02F54 1339230775Sjfv#define IXGBE_RXDGBCH 0x02F58 1340230775Sjfv#define IXGBE_RXDDGPC 0x02F5C 1341230775Sjfv#define IXGBE_RXDDGBCL 0x02F60 1342230775Sjfv#define IXGBE_RXDDGBCH 0x02F64 1343230775Sjfv#define IXGBE_RXLPBKGPC 0x02F68 1344230775Sjfv#define IXGBE_RXLPBKGBCL 0x02F6C 1345230775Sjfv#define IXGBE_RXLPBKGBCH 0x02F70 1346230775Sjfv#define IXGBE_RXDLPBKGPC 0x02F74 1347230775Sjfv#define IXGBE_RXDLPBKGBCL 0x02F78 1348230775Sjfv#define IXGBE_RXDLPBKGBCH 0x02F7C 1349230775Sjfv#define IXGBE_TXDGPC 0x087A0 1350230775Sjfv#define IXGBE_TXDGBCL 0x087A4 1351230775Sjfv#define IXGBE_TXDGBCH 0x087A8 1352230775Sjfv 1353230775Sjfv#define IXGBE_RXDSTATCTRL 0x02F40 1354230775Sjfv 1355200239Sjfv/* Copper Pond 2 link timeout */ 1356200239Sjfv#define IXGBE_VALIDATE_LINK_READY_TIMEOUT 50 1357200239Sjfv 1358190873Sjfv/* Omer CORECTL */ 1359230775Sjfv#define IXGBE_CORECTL 0x014F00 1360190873Sjfv/* BARCTRL */ 1361230775Sjfv#define IXGBE_BARCTRL 0x110F4 1362230775Sjfv#define IXGBE_BARCTRL_FLSIZE 0x0700 1363230775Sjfv#define IXGBE_BARCTRL_FLSIZE_SHIFT 8 1364230775Sjfv#define IXGBE_BARCTRL_CSRSIZE 0x2000 1365190873Sjfv 1366190873Sjfv/* RSCCTL Bit Masks */ 1367230775Sjfv#define IXGBE_RSCCTL_RSCEN 0x01 1368230775Sjfv#define IXGBE_RSCCTL_MAXDESC_1 0x00 1369230775Sjfv#define IXGBE_RSCCTL_MAXDESC_4 0x04 1370230775Sjfv#define IXGBE_RSCCTL_MAXDESC_8 0x08 1371230775Sjfv#define IXGBE_RSCCTL_MAXDESC_16 0x0C 1372247822Sjfv#define IXGBE_RSCCTL_TS_DIS 0x02 1373190873Sjfv 1374190873Sjfv/* RSCDBU Bit Masks */ 1375230775Sjfv#define IXGBE_RSCDBU_RSCSMALDIS_MASK 0x0000007F 1376230775Sjfv#define IXGBE_RSCDBU_RSCACKDIS 0x00000080 1377190873Sjfv 1378181003Sjfv/* RDRXCTL Bit Masks */ 1379230775Sjfv#define IXGBE_RDRXCTL_RDMTS_1_2 0x00000000 /* Rx Desc Min THLD Size */ 1380230775Sjfv#define IXGBE_RDRXCTL_CRCSTRIP 0x00000002 /* CRC Strip */ 1381283620Serj#define IXGBE_RDRXCTL_PSP 0x00000004 /* Pad Small Packet */ 1382230775Sjfv#define IXGBE_RDRXCTL_MVMEN 0x00000020 1383251964Sjfv#define IXGBE_RDRXCTL_RSC_PUSH_DIS 0x00000020 1384230775Sjfv#define IXGBE_RDRXCTL_DMAIDONE 0x00000008 /* DMA init cycle done */ 1385251964Sjfv#define IXGBE_RDRXCTL_RSC_PUSH 0x00000080 1386230775Sjfv#define IXGBE_RDRXCTL_AGGDIS 0x00010000 /* Aggregation disable */ 1387230775Sjfv#define IXGBE_RDRXCTL_RSCFRSTSIZE 0x003E0000 /* RSC First packet size */ 1388247822Sjfv#define IXGBE_RDRXCTL_RSCLLIDIS 0x00800000 /* Disable RSC compl on LLI*/ 1389230775Sjfv#define IXGBE_RDRXCTL_RSCACKC 0x02000000 /* must set 1 when RSC ena */ 1390230775Sjfv#define IXGBE_RDRXCTL_FCOE_WRFIX 0x04000000 /* must set 1 when RSC ena */ 1391283620Serj#define IXGBE_RDRXCTL_MBINTEN 0x10000000 1392283620Serj#define IXGBE_RDRXCTL_MDP_EN 0x20000000 1393171384Sjfv 1394190873Sjfv/* RQTC Bit Masks and Shifts */ 1395230775Sjfv#define IXGBE_RQTC_SHIFT_TC(_i) ((_i) * 4) 1396230775Sjfv#define IXGBE_RQTC_TC0_MASK (0x7 << 0) 1397230775Sjfv#define IXGBE_RQTC_TC1_MASK (0x7 << 4) 1398230775Sjfv#define IXGBE_RQTC_TC2_MASK (0x7 << 8) 1399230775Sjfv#define IXGBE_RQTC_TC3_MASK (0x7 << 12) 1400230775Sjfv#define IXGBE_RQTC_TC4_MASK (0x7 << 16) 1401230775Sjfv#define IXGBE_RQTC_TC5_MASK (0x7 << 20) 1402230775Sjfv#define IXGBE_RQTC_TC6_MASK (0x7 << 24) 1403230775Sjfv#define IXGBE_RQTC_TC7_MASK (0x7 << 28) 1404190873Sjfv 1405190873Sjfv/* PSRTYPE.RQPL Bit masks and shift */ 1406230775Sjfv#define IXGBE_PSRTYPE_RQPL_MASK 0x7 1407230775Sjfv#define IXGBE_PSRTYPE_RQPL_SHIFT 29 1408190873Sjfv 1409171384Sjfv/* CTRL Bit Masks */ 1410230775Sjfv#define IXGBE_CTRL_GIO_DIS 0x00000004 /* Global IO Master Disable bit */ 1411230775Sjfv#define IXGBE_CTRL_LNK_RST 0x00000008 /* Link Reset. Resets everything. */ 1412230775Sjfv#define IXGBE_CTRL_RST 0x04000000 /* Reset (SW) */ 1413230775Sjfv#define IXGBE_CTRL_RST_MASK (IXGBE_CTRL_LNK_RST | IXGBE_CTRL_RST) 1414171384Sjfv 1415171384Sjfv/* FACTPS */ 1416247822Sjfv#define IXGBE_FACTPS_MNGCG 0x20000000 /* Manageblility Clock Gated */ 1417230775Sjfv#define IXGBE_FACTPS_LFS 0x40000000 /* LAN Function Select */ 1418171384Sjfv 1419171384Sjfv/* MHADD Bit Masks */ 1420230775Sjfv#define IXGBE_MHADD_MFS_MASK 0xFFFF0000 1421230775Sjfv#define IXGBE_MHADD_MFS_SHIFT 16 1422171384Sjfv 1423171384Sjfv/* Extended Device Control */ 1424230775Sjfv#define IXGBE_CTRL_EXT_PFRSTD 0x00004000 /* Physical Function Reset Done */ 1425230775Sjfv#define IXGBE_CTRL_EXT_NS_DIS 0x00010000 /* No Snoop disable */ 1426230775Sjfv#define IXGBE_CTRL_EXT_RO_DIS 0x00020000 /* Relaxed Ordering disable */ 1427230775Sjfv#define IXGBE_CTRL_EXT_DRV_LOAD 0x10000000 /* Driver loaded bit for FW */ 1428171384Sjfv 1429171384Sjfv/* Direct Cache Access (DCA) definitions */ 1430230775Sjfv#define IXGBE_DCA_CTRL_DCA_ENABLE 0x00000000 /* DCA Enable */ 1431230775Sjfv#define IXGBE_DCA_CTRL_DCA_DISABLE 0x00000001 /* DCA Disable */ 1432171384Sjfv 1433230775Sjfv#define IXGBE_DCA_CTRL_DCA_MODE_CB1 0x00 /* DCA Mode CB1 */ 1434230775Sjfv#define IXGBE_DCA_CTRL_DCA_MODE_CB2 0x02 /* DCA Mode CB2 */ 1435171384Sjfv 1436230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_MASK 0x0000001F /* Rx CPUID Mask */ 1437230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_MASK_82599 0xFF000000 /* Rx CPUID Mask */ 1438230775Sjfv#define IXGBE_DCA_RXCTRL_CPUID_SHIFT_82599 24 /* Rx CPUID Shift */ 1439230775Sjfv#define IXGBE_DCA_RXCTRL_DESC_DCA_EN (1 << 5) /* Rx Desc enable */ 1440230775Sjfv#define IXGBE_DCA_RXCTRL_HEAD_DCA_EN (1 << 6) /* Rx Desc header ena */ 1441230775Sjfv#define IXGBE_DCA_RXCTRL_DATA_DCA_EN (1 << 7) /* Rx Desc payload ena */ 1442230775Sjfv#define IXGBE_DCA_RXCTRL_DESC_RRO_EN (1 << 9) /* Rx rd Desc Relax Order */ 1443238149Sjfv#define IXGBE_DCA_RXCTRL_DATA_WRO_EN (1 << 13) /* Rx wr data Relax Order */ 1444238149Sjfv#define IXGBE_DCA_RXCTRL_HEAD_WRO_EN (1 << 15) /* Rx wr header RO */ 1445171384Sjfv 1446230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_MASK 0x0000001F /* Tx CPUID Mask */ 1447230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_MASK_82599 0xFF000000 /* Tx CPUID Mask */ 1448230775Sjfv#define IXGBE_DCA_TXCTRL_CPUID_SHIFT_82599 24 /* Tx CPUID Shift */ 1449230775Sjfv#define IXGBE_DCA_TXCTRL_DESC_DCA_EN (1 << 5) /* DCA Tx Desc enable */ 1450238149Sjfv#define IXGBE_DCA_TXCTRL_DESC_RRO_EN (1 << 9) /* Tx rd Desc Relax Order */ 1451238149Sjfv#define IXGBE_DCA_TXCTRL_DESC_WRO_EN (1 << 11) /* Tx Desc writeback RO bit */ 1452238149Sjfv#define IXGBE_DCA_TXCTRL_DATA_RRO_EN (1 << 13) /* Tx rd data Relax Order */ 1453230775Sjfv#define IXGBE_DCA_MAX_QUEUES_82598 16 /* DCA regs only on 16 queues */ 1454171384Sjfv 1455171384Sjfv/* MSCA Bit Masks */ 1456230775Sjfv#define IXGBE_MSCA_NP_ADDR_MASK 0x0000FFFF /* MDI Addr (new prot) */ 1457230775Sjfv#define IXGBE_MSCA_NP_ADDR_SHIFT 0 1458230775Sjfv#define IXGBE_MSCA_DEV_TYPE_MASK 0x001F0000 /* Dev Type (new prot) */ 1459230775Sjfv#define IXGBE_MSCA_DEV_TYPE_SHIFT 16 /* Register Address (old prot */ 1460230775Sjfv#define IXGBE_MSCA_PHY_ADDR_MASK 0x03E00000 /* PHY Address mask */ 1461230775Sjfv#define IXGBE_MSCA_PHY_ADDR_SHIFT 21 /* PHY Address shift*/ 1462230775Sjfv#define IXGBE_MSCA_OP_CODE_MASK 0x0C000000 /* OP CODE mask */ 1463230775Sjfv#define IXGBE_MSCA_OP_CODE_SHIFT 26 /* OP CODE shift */ 1464230775Sjfv#define IXGBE_MSCA_ADDR_CYCLE 0x00000000 /* OP CODE 00 (addr cycle) */ 1465230775Sjfv#define IXGBE_MSCA_WRITE 0x04000000 /* OP CODE 01 (wr) */ 1466230775Sjfv#define IXGBE_MSCA_READ 0x0C000000 /* OP CODE 11 (rd) */ 1467230775Sjfv#define IXGBE_MSCA_READ_AUTOINC 0x08000000 /* OP CODE 10 (rd auto inc)*/ 1468230775Sjfv#define IXGBE_MSCA_ST_CODE_MASK 0x30000000 /* ST Code mask */ 1469230775Sjfv#define IXGBE_MSCA_ST_CODE_SHIFT 28 /* ST Code shift */ 1470230775Sjfv#define IXGBE_MSCA_NEW_PROTOCOL 0x00000000 /* ST CODE 00 (new prot) */ 1471230775Sjfv#define IXGBE_MSCA_OLD_PROTOCOL 0x10000000 /* ST CODE 01 (old prot) */ 1472230775Sjfv#define IXGBE_MSCA_MDI_COMMAND 0x40000000 /* Initiate MDI command */ 1473230775Sjfv#define IXGBE_MSCA_MDI_IN_PROG_EN 0x80000000 /* MDI in progress ena */ 1474171384Sjfv 1475171384Sjfv/* MSRWD bit masks */ 1476230775Sjfv#define IXGBE_MSRWD_WRITE_DATA_MASK 0x0000FFFF 1477230775Sjfv#define IXGBE_MSRWD_WRITE_DATA_SHIFT 0 1478230775Sjfv#define IXGBE_MSRWD_READ_DATA_MASK 0xFFFF0000 1479230775Sjfv#define IXGBE_MSRWD_READ_DATA_SHIFT 16 1480171384Sjfv 1481172043Sjfv/* Atlas registers */ 1482230775Sjfv#define IXGBE_ATLAS_PDN_LPBK 0x24 1483230775Sjfv#define IXGBE_ATLAS_PDN_10G 0xB 1484230775Sjfv#define IXGBE_ATLAS_PDN_1G 0xC 1485230775Sjfv#define IXGBE_ATLAS_PDN_AN 0xD 1486172043Sjfv 1487172043Sjfv/* Atlas bit masks */ 1488230775Sjfv#define IXGBE_ATLASCTL_WRITE_CMD 0x00010000 1489230775Sjfv#define IXGBE_ATLAS_PDN_TX_REG_EN 0x10 1490230775Sjfv#define IXGBE_ATLAS_PDN_TX_10G_QL_ALL 0xF0 1491230775Sjfv#define IXGBE_ATLAS_PDN_TX_1G_QL_ALL 0xF0 1492230775Sjfv#define IXGBE_ATLAS_PDN_TX_AN_QL_ALL 0xF0 1493172043Sjfv 1494190873Sjfv/* Omer bit masks */ 1495230775Sjfv#define IXGBE_CORECTL_WRITE_CMD 0x00010000 1496185352Sjfv 1497171384Sjfv/* Device Type definitions for new protocol MDIO commands */ 1498315333Serj#define IXGBE_MDIO_ZERO_DEV_TYPE 0x0 1499230775Sjfv#define IXGBE_MDIO_PMA_PMD_DEV_TYPE 0x1 1500230775Sjfv#define IXGBE_MDIO_PCS_DEV_TYPE 0x3 1501230775Sjfv#define IXGBE_MDIO_PHY_XS_DEV_TYPE 0x4 1502230775Sjfv#define IXGBE_MDIO_AUTO_NEG_DEV_TYPE 0x7 1503230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE 0x1E /* Device 30 */ 1504230775Sjfv#define IXGBE_TWINAX_DEV 1 1505171384Sjfv 1506230775Sjfv#define IXGBE_MDIO_COMMAND_TIMEOUT 100 /* PHY Timeout for 1 GB mode */ 1507172043Sjfv 1508230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL 0x0 /* VS1 Ctrl Reg */ 1509230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS 0x1 /* VS1 Status Reg */ 1510230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS 0x0008 /* 1 = Link Up */ 1511230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS 0x0010 /* 0-10G, 1-1G */ 1512230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_10G_SPEED 0x0018 1513230775Sjfv#define IXGBE_MDIO_VENDOR_SPECIFIC_1_1G_SPEED 0x0010 1514171384Sjfv 1515230775Sjfv#define IXGBE_MDIO_AUTO_NEG_CONTROL 0x0 /* AUTO_NEG Control Reg */ 1516230775Sjfv#define IXGBE_MDIO_AUTO_NEG_STATUS 0x1 /* AUTO_NEG Status Reg */ 1517283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STAT 0xC800 /* AUTO_NEG Vendor Status Reg */ 1518283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM 0xCC00 /* AUTO_NEG Vendor TX Reg */ 1519283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_TX_ALARM2 0xCC01 /* AUTO_NEG Vendor Tx Reg */ 1520283620Serj#define IXGBE_MDIO_AUTO_NEG_VEN_LSC 0x1 /* AUTO_NEG Vendor Tx LSC */ 1521230775Sjfv#define IXGBE_MDIO_AUTO_NEG_ADVT 0x10 /* AUTO_NEG Advt Reg */ 1522230775Sjfv#define IXGBE_MDIO_AUTO_NEG_LP 0x13 /* AUTO_NEG LP Status Reg */ 1523283620Serj#define IXGBE_MDIO_AUTO_NEG_EEE_ADVT 0x3C /* AUTO_NEG EEE Advt Reg */ 1524283620Serj#define IXGBE_AUTO_NEG_10GBASE_EEE_ADVT 0x8 /* AUTO NEG EEE 10GBaseT Advt */ 1525283620Serj#define IXGBE_AUTO_NEG_1000BASE_EEE_ADVT 0x4 /* AUTO NEG EEE 1000BaseT Advt */ 1526283620Serj#define IXGBE_AUTO_NEG_100BASE_EEE_ADVT 0x2 /* AUTO NEG EEE 100BaseT Advt */ 1527230775Sjfv#define IXGBE_MDIO_PHY_XS_CONTROL 0x0 /* PHY_XS Control Reg */ 1528230775Sjfv#define IXGBE_MDIO_PHY_XS_RESET 0x8000 /* PHY_XS Reset */ 1529230775Sjfv#define IXGBE_MDIO_PHY_ID_HIGH 0x2 /* PHY ID High Reg*/ 1530230775Sjfv#define IXGBE_MDIO_PHY_ID_LOW 0x3 /* PHY ID Low Reg*/ 1531230775Sjfv#define IXGBE_MDIO_PHY_SPEED_ABILITY 0x4 /* Speed Ability Reg */ 1532230775Sjfv#define IXGBE_MDIO_PHY_SPEED_10G 0x0001 /* 10G capable */ 1533230775Sjfv#define IXGBE_MDIO_PHY_SPEED_1G 0x0010 /* 1G capable */ 1534230775Sjfv#define IXGBE_MDIO_PHY_SPEED_100M 0x0020 /* 100M capable */ 1535230775Sjfv#define IXGBE_MDIO_PHY_EXT_ABILITY 0xB /* Ext Ability Reg */ 1536230775Sjfv#define IXGBE_MDIO_PHY_10GBASET_ABILITY 0x0004 /* 10GBaseT capable */ 1537230775Sjfv#define IXGBE_MDIO_PHY_1000BASET_ABILITY 0x0020 /* 1000BaseT capable */ 1538230775Sjfv#define IXGBE_MDIO_PHY_100BASETX_ABILITY 0x0080 /* 100BaseTX capable */ 1539230775Sjfv#define IXGBE_MDIO_PHY_SET_LOW_POWER_MODE 0x0800 /* Set low power mode */ 1540283620Serj#define IXGBE_AUTO_NEG_LP_STATUS 0xE820 /* AUTO NEG Rx LP Status Reg */ 1541283620Serj#define IXGBE_AUTO_NEG_LP_1000BASE_CAP 0x8000 /* AUTO NEG Rx LP 1000BaseT Cap */ 1542283620Serj#define IXGBE_AUTO_NEG_LP_10GBASE_CAP 0x0800 /* AUTO NEG Rx LP 10GBaseT Cap */ 1543283620Serj#define IXGBE_AUTO_NEG_10GBASET_STAT 0x0021 /* AUTO NEG 10G BaseT Stat */ 1544171384Sjfv 1545283620Serj#define IXGBE_MDIO_TX_VENDOR_ALARMS_3 0xCC02 /* Vendor Alarms 3 Reg */ 1546283620Serj#define IXGBE_MDIO_TX_VENDOR_ALARMS_3_RST_MASK 0x3 /* PHY Reset Complete Mask */ 1547283620Serj#define IXGBE_MDIO_GLOBAL_RES_PR_10 0xC479 /* Global Resv Provisioning 10 Reg */ 1548283620Serj#define IXGBE_MDIO_POWER_UP_STALL 0x8000 /* Power Up Stall */ 1549283620Serj#define IXGBE_MDIO_GLOBAL_INT_CHIP_STD_MASK 0xFF00 /* int std mask */ 1550283620Serj#define IXGBE_MDIO_GLOBAL_CHIP_STD_INT_FLAG 0xFC00 /* chip std int flag */ 1551283620Serj#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_MASK 0xFF01 /* int chip-wide mask */ 1552283620Serj#define IXGBE_MDIO_GLOBAL_INT_CHIP_VEN_FLAG 0xFC01 /* int chip-wide mask */ 1553283620Serj#define IXGBE_MDIO_GLOBAL_ALARM_1 0xCC00 /* Global alarm 1 */ 1554295528Ssmh#define IXGBE_MDIO_GLOBAL_ALM_1_DEV_FAULT 0x0010 /* device fault */ 1555283620Serj#define IXGBE_MDIO_GLOBAL_ALM_1_HI_TMP_FAIL 0x4000 /* high temp failure */ 1556315333Serj#define IXGBE_MDIO_GLOBAL_FAULT_MSG 0xC850 /* Global Fault Message */ 1557295528Ssmh#define IXGBE_MDIO_GLOBAL_FAULT_MSG_HI_TMP 0x8007 /* high temp failure */ 1558283620Serj#define IXGBE_MDIO_GLOBAL_INT_MASK 0xD400 /* Global int mask */ 1559283620Serj#define IXGBE_MDIO_GLOBAL_AN_VEN_ALM_INT_EN 0x1000 /* autoneg vendor alarm int enable */ 1560283620Serj#define IXGBE_MDIO_GLOBAL_ALARM_1_INT 0x4 /* int in Global alarm 1 */ 1561283620Serj#define IXGBE_MDIO_GLOBAL_VEN_ALM_INT_EN 0x1 /* vendor alarm int enable */ 1562283620Serj#define IXGBE_MDIO_GLOBAL_STD_ALM2_INT 0x200 /* vendor alarm2 int mask */ 1563283620Serj#define IXGBE_MDIO_GLOBAL_INT_HI_TEMP_EN 0x4000 /* int high temp enable */ 1564315333Serj#define IXGBE_MDIO_GLOBAL_INT_DEV_FAULT_EN 0x0010 /* int dev fault enable */ 1565230775Sjfv#define IXGBE_MDIO_PMA_PMD_CONTROL_ADDR 0x0000 /* PMA/PMD Control Reg */ 1566230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_ADDR 0xC30A /* PHY_XS SDA/SCL Addr Reg */ 1567230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_DATA 0xC30B /* PHY_XS SDA/SCL Data Reg */ 1568230775Sjfv#define IXGBE_MDIO_PMA_PMD_SDA_SCL_STAT 0xC30C /* PHY_XS SDA/SCL Status Reg */ 1569283620Serj#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_MASK 0xD401 /* PHY TX Vendor LASI */ 1570283620Serj#define IXGBE_MDIO_PMA_TX_VEN_LASI_INT_EN 0x1 /* PHY TX Vendor LASI enable */ 1571283620Serj#define IXGBE_MDIO_PMD_STD_TX_DISABLE_CNTR 0x9 /* Standard Transmit Dis Reg */ 1572283620Serj#define IXGBE_MDIO_PMD_GLOBAL_TX_DISABLE 0x0001 /* PMD Global Transmit Dis */ 1573185352Sjfv 1574283620Serj#define IXGBE_PCRC8ECL 0x0E810 /* PCR CRC-8 Error Count Lo */ 1575283620Serj#define IXGBE_PCRC8ECH 0x0E811 /* PCR CRC-8 Error Count Hi */ 1576283620Serj#define IXGBE_PCRC8ECH_MASK 0x1F 1577283620Serj#define IXGBE_LDPCECL 0x0E820 /* PCR Uncorrected Error Count Lo */ 1578283620Serj#define IXGBE_LDPCECH 0x0E821 /* PCR Uncorrected Error Count Hi */ 1579283620Serj 1580179055Sjfv/* MII clause 22/28 definitions */ 1581230775Sjfv#define IXGBE_MDIO_PHY_LOW_POWER_MODE 0x0800 1582179055Sjfv 1583283620Serj#define IXGBE_MDIO_XENPAK_LASI_STATUS 0x9005 /* XENPAK LASI Status register*/ 1584283620Serj#define IXGBE_XENPAK_LASI_LINK_STATUS_ALARM 0x1 /* Link Status Alarm change */ 1585283620Serj 1586283620Serj#define IXGBE_MDIO_AUTO_NEG_LINK_STATUS 0x4 /* Indicates if link is up */ 1587283620Serj 1588283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_MASK 0x7 /* Speed/Duplex Mask */ 1589283620Serj#define IXGBE_MDIO_AUTO_NEG_VEN_STAT_SPEED_MASK 0x6 /* Speed Mask */ 1590283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_HALF 0x0 /* 10Mb/s Half Duplex */ 1591283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10M_FULL 0x1 /* 10Mb/s Full Duplex */ 1592283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_HALF 0x2 /* 100Mb/s Half Duplex */ 1593283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_100M_FULL 0x3 /* 100Mb/s Full Duplex */ 1594283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_HALF 0x4 /* 1Gb/s Half Duplex */ 1595283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB_FULL 0x5 /* 1Gb/s Full Duplex */ 1596283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_HALF 0x6 /* 10Gb/s Half Duplex */ 1597283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB_FULL 0x7 /* 10Gb/s Full Duplex */ 1598283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_1GB 0x4 /* 1Gb/s */ 1599283620Serj#define IXGBE_MDIO_AUTO_NEG_VENDOR_STATUS_10GB 0x6 /* 10Gb/s */ 1600283620Serj 1601230775Sjfv#define IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG 0x20 /* 10G Control Reg */ 1602200239Sjfv#define IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG 0xC400 /* 1G Provisioning 1 */ 1603230775Sjfv#define IXGBE_MII_AUTONEG_XNP_TX_REG 0x17 /* 1G XNP Transmit */ 1604230775Sjfv#define IXGBE_MII_AUTONEG_ADVERTISE_REG 0x10 /* 100M Advertisement */ 1605230775Sjfv#define IXGBE_MII_10GBASE_T_ADVERTISE 0x1000 /* full duplex, bit:12*/ 1606230775Sjfv#define IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX 0x4000 /* full duplex, bit:14*/ 1607230775Sjfv#define IXGBE_MII_1GBASE_T_ADVERTISE 0x8000 /* full duplex, bit:15*/ 1608283620Serj#define IXGBE_MII_2_5GBASE_T_ADVERTISE 0x0400 1609283620Serj#define IXGBE_MII_5GBASE_T_ADVERTISE 0x0800 1610230775Sjfv#define IXGBE_MII_100BASE_T_ADVERTISE 0x0100 /* full duplex, bit:8 */ 1611230775Sjfv#define IXGBE_MII_100BASE_T_ADVERTISE_HALF 0x0080 /* half duplex, bit:7 */ 1612230775Sjfv#define IXGBE_MII_RESTART 0x200 1613230775Sjfv#define IXGBE_MII_AUTONEG_COMPLETE 0x20 1614230775Sjfv#define IXGBE_MII_AUTONEG_LINK_UP 0x04 1615230775Sjfv#define IXGBE_MII_AUTONEG_REG 0x0 1616179055Sjfv 1617230775Sjfv#define IXGBE_PHY_REVISION_MASK 0xFFFFFFF0 1618230775Sjfv#define IXGBE_MAX_PHY_ADDR 32 1619171384Sjfv 1620171384Sjfv/* PHY IDs*/ 1621230775Sjfv#define TN1010_PHY_ID 0x00A19410 1622230775Sjfv#define TNX_FW_REV 0xB 1623230775Sjfv#define X540_PHY_ID 0x01540200 1624295524Ssbruno#define X550_PHY_ID2 0x01540223 1625295524Ssbruno#define X550_PHY_ID3 0x01540221 1626283620Serj#define X557_PHY_ID 0x01540240 1627315333Serj#define X557_PHY_ID2 0x01540250 1628230775Sjfv#define AQ_FW_REV 0x20 1629230775Sjfv#define QT2022_PHY_ID 0x0043A400 1630230775Sjfv#define ATH_PHY_ID 0x03429050 1631171384Sjfv 1632179055Sjfv/* PHY Types */ 1633315333Serj#define IXGBE_M88E1500_E_PHY_ID 0x01410DD0 1634315333Serj#define IXGBE_M88E1543_E_PHY_ID 0x01410EA0 1635179055Sjfv 1636185352Sjfv/* Special PHY Init Routine */ 1637230775Sjfv#define IXGBE_PHY_INIT_OFFSET_NL 0x002B 1638230775Sjfv#define IXGBE_PHY_INIT_END_NL 0xFFFF 1639230775Sjfv#define IXGBE_CONTROL_MASK_NL 0xF000 1640230775Sjfv#define IXGBE_DATA_MASK_NL 0x0FFF 1641230775Sjfv#define IXGBE_CONTROL_SHIFT_NL 12 1642230775Sjfv#define IXGBE_DELAY_NL 0 1643230775Sjfv#define IXGBE_DATA_NL 1 1644230775Sjfv#define IXGBE_CONTROL_NL 0x000F 1645230775Sjfv#define IXGBE_CONTROL_EOL_NL 0x0FFF 1646230775Sjfv#define IXGBE_CONTROL_SOL_NL 0x0000 1647185352Sjfv 1648171384Sjfv/* General purpose Interrupt Enable */ 1649230775Sjfv#define IXGBE_SDP0_GPIEN 0x00000001 /* SDP0 */ 1650230775Sjfv#define IXGBE_SDP1_GPIEN 0x00000002 /* SDP1 */ 1651230775Sjfv#define IXGBE_SDP2_GPIEN 0x00000004 /* SDP2 */ 1652283620Serj#define IXGBE_SDP0_GPIEN_X540 0x00000002 /* SDP0 on X540 and X550 */ 1653283620Serj#define IXGBE_SDP1_GPIEN_X540 0x00000004 /* SDP1 on X540 and X550 */ 1654283620Serj#define IXGBE_SDP2_GPIEN_X540 0x00000008 /* SDP2 on X540 and X550 */ 1655283620Serj#define IXGBE_SDP0_GPIEN_X550 IXGBE_SDP0_GPIEN_X540 1656283620Serj#define IXGBE_SDP1_GPIEN_X550 IXGBE_SDP1_GPIEN_X540 1657283620Serj#define IXGBE_SDP2_GPIEN_X550 IXGBE_SDP2_GPIEN_X540 1658283620Serj#define IXGBE_SDP0_GPIEN_X550EM_x IXGBE_SDP0_GPIEN_X540 1659283620Serj#define IXGBE_SDP1_GPIEN_X550EM_x IXGBE_SDP1_GPIEN_X540 1660283620Serj#define IXGBE_SDP2_GPIEN_X550EM_x IXGBE_SDP2_GPIEN_X540 1661315333Serj#define IXGBE_SDP0_GPIEN_X550EM_a IXGBE_SDP0_GPIEN_X540 1662315333Serj#define IXGBE_SDP1_GPIEN_X550EM_a IXGBE_SDP1_GPIEN_X540 1663315333Serj#define IXGBE_SDP2_GPIEN_X550EM_a IXGBE_SDP2_GPIEN_X540 1664283620Serj#define IXGBE_SDP0_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP0_GPIEN) 1665283620Serj#define IXGBE_SDP1_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP1_GPIEN) 1666283620Serj#define IXGBE_SDP2_GPIEN_BY_MAC(_hw) IXGBE_BY_MAC((_hw), SDP2_GPIEN) 1667283620Serj 1668230775Sjfv#define IXGBE_GPIE_MSIX_MODE 0x00000010 /* MSI-X mode */ 1669230775Sjfv#define IXGBE_GPIE_OCD 0x00000020 /* Other Clear Disable */ 1670230775Sjfv#define IXGBE_GPIE_EIMEN 0x00000040 /* Immediate Interrupt Enable */ 1671230775Sjfv#define IXGBE_GPIE_EIAME 0x40000000 1672230775Sjfv#define IXGBE_GPIE_PBA_SUPPORT 0x80000000 1673230775Sjfv#define IXGBE_GPIE_RSC_DELAY_SHIFT 11 1674230775Sjfv#define IXGBE_GPIE_VTMODE_MASK 0x0000C000 /* VT Mode Mask */ 1675230775Sjfv#define IXGBE_GPIE_VTMODE_16 0x00004000 /* 16 VFs 8 queues per VF */ 1676230775Sjfv#define IXGBE_GPIE_VTMODE_32 0x00008000 /* 32 VFs 4 queues per VF */ 1677230775Sjfv#define IXGBE_GPIE_VTMODE_64 0x0000C000 /* 64 VFs 2 queues per VF */ 1678171384Sjfv 1679230775Sjfv/* Packet Buffer Initialization */ 1680230775Sjfv#define IXGBE_MAX_PACKET_BUFFERS 8 1681230775Sjfv 1682230775Sjfv#define IXGBE_TXPBSIZE_20KB 0x00005000 /* 20KB Packet Buffer */ 1683230775Sjfv#define IXGBE_TXPBSIZE_40KB 0x0000A000 /* 40KB Packet Buffer */ 1684230775Sjfv#define IXGBE_RXPBSIZE_48KB 0x0000C000 /* 48KB Packet Buffer */ 1685230775Sjfv#define IXGBE_RXPBSIZE_64KB 0x00010000 /* 64KB Packet Buffer */ 1686230775Sjfv#define IXGBE_RXPBSIZE_80KB 0x00014000 /* 80KB Packet Buffer */ 1687230775Sjfv#define IXGBE_RXPBSIZE_128KB 0x00020000 /* 128KB Packet Buffer */ 1688230775Sjfv#define IXGBE_RXPBSIZE_MAX 0x00080000 /* 512KB Packet Buffer */ 1689230775Sjfv#define IXGBE_TXPBSIZE_MAX 0x00028000 /* 160KB Packet Buffer */ 1690230775Sjfv 1691230775Sjfv#define IXGBE_TXPKT_SIZE_MAX 0xA /* Max Tx Packet size */ 1692230775Sjfv#define IXGBE_MAX_PB 8 1693230775Sjfv 1694230775Sjfv/* Packet buffer allocation strategies */ 1695230775Sjfvenum { 1696230775Sjfv PBA_STRATEGY_EQUAL = 0, /* Distribute PB space equally */ 1697230775Sjfv#define PBA_STRATEGY_EQUAL PBA_STRATEGY_EQUAL 1698230775Sjfv PBA_STRATEGY_WEIGHTED = 1, /* Weight front half of TCs */ 1699230775Sjfv#define PBA_STRATEGY_WEIGHTED PBA_STRATEGY_WEIGHTED 1700230775Sjfv}; 1701230775Sjfv 1702171384Sjfv/* Transmit Flow Control status */ 1703230775Sjfv#define IXGBE_TFCS_TXOFF 0x00000001 1704230775Sjfv#define IXGBE_TFCS_TXOFF0 0x00000100 1705230775Sjfv#define IXGBE_TFCS_TXOFF1 0x00000200 1706230775Sjfv#define IXGBE_TFCS_TXOFF2 0x00000400 1707230775Sjfv#define IXGBE_TFCS_TXOFF3 0x00000800 1708230775Sjfv#define IXGBE_TFCS_TXOFF4 0x00001000 1709230775Sjfv#define IXGBE_TFCS_TXOFF5 0x00002000 1710230775Sjfv#define IXGBE_TFCS_TXOFF6 0x00004000 1711230775Sjfv#define IXGBE_TFCS_TXOFF7 0x00008000 1712171384Sjfv 1713171384Sjfv/* TCP Timer */ 1714230775Sjfv#define IXGBE_TCPTIMER_KS 0x00000100 1715230775Sjfv#define IXGBE_TCPTIMER_COUNT_ENABLE 0x00000200 1716230775Sjfv#define IXGBE_TCPTIMER_COUNT_FINISH 0x00000400 1717230775Sjfv#define IXGBE_TCPTIMER_LOOP 0x00000800 1718230775Sjfv#define IXGBE_TCPTIMER_DURATION_MASK 0x000000FF 1719171384Sjfv 1720171384Sjfv/* HLREG0 Bit Masks */ 1721230775Sjfv#define IXGBE_HLREG0_TXCRCEN 0x00000001 /* bit 0 */ 1722230775Sjfv#define IXGBE_HLREG0_RXCRCSTRP 0x00000002 /* bit 1 */ 1723230775Sjfv#define IXGBE_HLREG0_JUMBOEN 0x00000004 /* bit 2 */ 1724230775Sjfv#define IXGBE_HLREG0_TXPADEN 0x00000400 /* bit 10 */ 1725230775Sjfv#define IXGBE_HLREG0_TXPAUSEEN 0x00001000 /* bit 12 */ 1726230775Sjfv#define IXGBE_HLREG0_RXPAUSEEN 0x00004000 /* bit 14 */ 1727230775Sjfv#define IXGBE_HLREG0_LPBK 0x00008000 /* bit 15 */ 1728230775Sjfv#define IXGBE_HLREG0_MDCSPD 0x00010000 /* bit 16 */ 1729230775Sjfv#define IXGBE_HLREG0_CONTMDC 0x00020000 /* bit 17 */ 1730230775Sjfv#define IXGBE_HLREG0_CTRLFLTR 0x00040000 /* bit 18 */ 1731230775Sjfv#define IXGBE_HLREG0_PREPEND 0x00F00000 /* bits 20-23 */ 1732230775Sjfv#define IXGBE_HLREG0_PRIPAUSEEN 0x01000000 /* bit 24 */ 1733230775Sjfv#define IXGBE_HLREG0_RXPAUSERECDA 0x06000000 /* bits 25-26 */ 1734230775Sjfv#define IXGBE_HLREG0_RXLNGTHERREN 0x08000000 /* bit 27 */ 1735230775Sjfv#define IXGBE_HLREG0_RXPADSTRIPEN 0x10000000 /* bit 28 */ 1736171384Sjfv 1737171384Sjfv/* VMD_CTL bitmasks */ 1738230775Sjfv#define IXGBE_VMD_CTL_VMDQ_EN 0x00000001 1739230775Sjfv#define IXGBE_VMD_CTL_VMDQ_FILTER 0x00000002 1740171384Sjfv 1741190873Sjfv/* VT_CTL bitmasks */ 1742230775Sjfv#define IXGBE_VT_CTL_DIS_DEFPL 0x20000000 /* disable default pool */ 1743230775Sjfv#define IXGBE_VT_CTL_REPLEN 0x40000000 /* replication enabled */ 1744230775Sjfv#define IXGBE_VT_CTL_VT_ENABLE 0x00000001 /* Enable VT Mode */ 1745230775Sjfv#define IXGBE_VT_CTL_POOL_SHIFT 7 1746230775Sjfv#define IXGBE_VT_CTL_POOL_MASK (0x3F << IXGBE_VT_CTL_POOL_SHIFT) 1747190873Sjfv 1748190873Sjfv/* VMOLR bitmasks */ 1749315333Serj#define IXGBE_VMOLR_UPE 0x00400000 /* unicast promiscuous */ 1750315333Serj#define IXGBE_VMOLR_VPE 0x00800000 /* VLAN promiscuous */ 1751230775Sjfv#define IXGBE_VMOLR_AUPE 0x01000000 /* accept untagged packets */ 1752230775Sjfv#define IXGBE_VMOLR_ROMPE 0x02000000 /* accept packets in MTA tbl */ 1753230775Sjfv#define IXGBE_VMOLR_ROPE 0x04000000 /* accept packets in UC tbl */ 1754230775Sjfv#define IXGBE_VMOLR_BAM 0x08000000 /* accept broadcast packets */ 1755230775Sjfv#define IXGBE_VMOLR_MPE 0x10000000 /* multicast promiscuous */ 1756190873Sjfv 1757190873Sjfv/* VFRE bitmask */ 1758230775Sjfv#define IXGBE_VFRE_ENABLE_ALL 0xFFFFFFFF 1759190873Sjfv 1760230775Sjfv#define IXGBE_VF_INIT_TIMEOUT 200 /* Number of retries to clear RSTI */ 1761194875Sjfv 1762171384Sjfv/* RDHMPN and TDHMPN bitmasks */ 1763230775Sjfv#define IXGBE_RDHMPN_RDICADDR 0x007FF800 1764230775Sjfv#define IXGBE_RDHMPN_RDICRDREQ 0x00800000 1765230775Sjfv#define IXGBE_RDHMPN_RDICADDR_SHIFT 11 1766230775Sjfv#define IXGBE_TDHMPN_TDICADDR 0x003FF800 1767230775Sjfv#define IXGBE_TDHMPN_TDICRDREQ 0x00800000 1768230775Sjfv#define IXGBE_TDHMPN_TDICADDR_SHIFT 11 1769171384Sjfv 1770230775Sjfv#define IXGBE_RDMAM_MEM_SEL_SHIFT 13 1771230775Sjfv#define IXGBE_RDMAM_DWORD_SHIFT 9 1772230775Sjfv#define IXGBE_RDMAM_DESC_COMP_FIFO 1 1773230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO 2 1774230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR 3 1775230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM 4 1776230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO 5 1777230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM 6 1778230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM 7 1779230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT 8 1780230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM 0xA 1781230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM 0xB 1782230775Sjfv#define IXGBE_RDMAM_DESC_COM_FIFO_RANGE 135 1783230775Sjfv#define IXGBE_RDMAM_DESC_COM_FIFO_COUNT 4 1784230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO_RANGE 48 1785230775Sjfv#define IXGBE_RDMAM_DFC_CMD_FIFO_COUNT 7 1786230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR_RANGE 32 1787230775Sjfv#define IXGBE_RDMAM_RSC_HEADER_ADDR_COUNT 4 1788230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM_RANGE 256 1789230775Sjfv#define IXGBE_RDMAM_TCN_STATUS_RAM_COUNT 9 1790230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO_RANGE 8 1791230775Sjfv#define IXGBE_RDMAM_WB_COLL_FIFO_COUNT 4 1792230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM_RANGE 64 1793230775Sjfv#define IXGBE_RDMAM_QSC_CNT_RAM_COUNT 4 1794230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM_RANGE 512 1795230775Sjfv#define IXGBE_RDMAM_QSC_FCOE_RAM_COUNT 5 1796230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT_RANGE 32 1797230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_CNT_COUNT 4 1798230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM_RANGE 128 1799230775Sjfv#define IXGBE_RDMAM_QSC_QUEUE_RAM_COUNT 8 1800230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM_RANGE 32 1801230775Sjfv#define IXGBE_RDMAM_QSC_RSC_RAM_COUNT 8 1802190873Sjfv 1803230775Sjfv#define IXGBE_TXDESCIC_READY 0x80000000 1804190873Sjfv 1805171384Sjfv/* Receive Checksum Control */ 1806230775Sjfv#define IXGBE_RXCSUM_IPPCSE 0x00001000 /* IP payload checksum enable */ 1807230775Sjfv#define IXGBE_RXCSUM_PCSD 0x00002000 /* packet checksum disabled */ 1808171384Sjfv 1809171384Sjfv/* FCRTL Bit Masks */ 1810230775Sjfv#define IXGBE_FCRTL_XONE 0x80000000 /* XON enable */ 1811230775Sjfv#define IXGBE_FCRTH_FCEN 0x80000000 /* Packet buffer fc enable */ 1812171384Sjfv 1813171384Sjfv/* PAP bit masks*/ 1814230775Sjfv#define IXGBE_PAP_TXPAUSECNT_MASK 0x0000FFFF /* Pause counter mask */ 1815171384Sjfv 1816171384Sjfv/* RMCS Bit Masks */ 1817230775Sjfv#define IXGBE_RMCS_RRM 0x00000002 /* Rx Recycle Mode enable */ 1818171384Sjfv/* Receive Arbitration Control: 0 Round Robin, 1 DFP */ 1819230775Sjfv#define IXGBE_RMCS_RAC 0x00000004 1820230775Sjfv/* Deficit Fixed Prio ena */ 1821230775Sjfv#define IXGBE_RMCS_DFP IXGBE_RMCS_RAC 1822230775Sjfv#define IXGBE_RMCS_TFCE_802_3X 0x00000008 /* Tx Priority FC ena */ 1823230775Sjfv#define IXGBE_RMCS_TFCE_PRIORITY 0x00000010 /* Tx Priority FC ena */ 1824230775Sjfv#define IXGBE_RMCS_ARBDIS 0x00000040 /* Arbitration disable bit */ 1825171384Sjfv 1826190873Sjfv/* FCCFG Bit Masks */ 1827230775Sjfv#define IXGBE_FCCFG_TFCE_802_3X 0x00000008 /* Tx link FC enable */ 1828230775Sjfv#define IXGBE_FCCFG_TFCE_PRIORITY 0x00000010 /* Tx priority FC enable */ 1829179055Sjfv 1830171384Sjfv/* Interrupt register bitmasks */ 1831171384Sjfv 1832171384Sjfv/* Extended Interrupt Cause Read */ 1833230775Sjfv#define IXGBE_EICR_RTX_QUEUE 0x0000FFFF /* RTx Queue Interrupt */ 1834230775Sjfv#define IXGBE_EICR_FLOW_DIR 0x00010000 /* FDir Exception */ 1835230775Sjfv#define IXGBE_EICR_RX_MISS 0x00020000 /* Packet Buffer Overrun */ 1836230775Sjfv#define IXGBE_EICR_PCI 0x00040000 /* PCI Exception */ 1837230775Sjfv#define IXGBE_EICR_MAILBOX 0x00080000 /* VF to PF Mailbox Interrupt */ 1838230775Sjfv#define IXGBE_EICR_LSC 0x00100000 /* Link Status Change */ 1839230775Sjfv#define IXGBE_EICR_LINKSEC 0x00200000 /* PN Threshold */ 1840230775Sjfv#define IXGBE_EICR_MNG 0x00400000 /* Manageability Event Interrupt */ 1841230775Sjfv#define IXGBE_EICR_TS 0x00800000 /* Thermal Sensor Event */ 1842238149Sjfv#define IXGBE_EICR_TIMESYNC 0x01000000 /* Timesync Event */ 1843230775Sjfv#define IXGBE_EICR_GPI_SDP0 0x01000000 /* Gen Purpose Interrupt on SDP0 */ 1844230775Sjfv#define IXGBE_EICR_GPI_SDP1 0x02000000 /* Gen Purpose Interrupt on SDP1 */ 1845230775Sjfv#define IXGBE_EICR_GPI_SDP2 0x04000000 /* Gen Purpose Interrupt on SDP2 */ 1846230775Sjfv#define IXGBE_EICR_ECC 0x10000000 /* ECC Error */ 1847283620Serj#define IXGBE_EICR_GPI_SDP0_X540 0x02000000 /* Gen Purpose Interrupt on SDP0 */ 1848283620Serj#define IXGBE_EICR_GPI_SDP1_X540 0x04000000 /* Gen Purpose Interrupt on SDP1 */ 1849283620Serj#define IXGBE_EICR_GPI_SDP2_X540 0x08000000 /* Gen Purpose Interrupt on SDP2 */ 1850283620Serj#define IXGBE_EICR_GPI_SDP0_X550 IXGBE_EICR_GPI_SDP0_X540 1851283620Serj#define IXGBE_EICR_GPI_SDP1_X550 IXGBE_EICR_GPI_SDP1_X540 1852283620Serj#define IXGBE_EICR_GPI_SDP2_X550 IXGBE_EICR_GPI_SDP2_X540 1853283620Serj#define IXGBE_EICR_GPI_SDP0_X550EM_x IXGBE_EICR_GPI_SDP0_X540 1854283620Serj#define IXGBE_EICR_GPI_SDP1_X550EM_x IXGBE_EICR_GPI_SDP1_X540 1855283620Serj#define IXGBE_EICR_GPI_SDP2_X550EM_x IXGBE_EICR_GPI_SDP2_X540 1856315333Serj#define IXGBE_EICR_GPI_SDP0_X550EM_a IXGBE_EICR_GPI_SDP0_X540 1857315333Serj#define IXGBE_EICR_GPI_SDP1_X550EM_a IXGBE_EICR_GPI_SDP1_X540 1858315333Serj#define IXGBE_EICR_GPI_SDP2_X550EM_a IXGBE_EICR_GPI_SDP2_X540 1859283620Serj#define IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP0) 1860283620Serj#define IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP1) 1861283620Serj#define IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) IXGBE_BY_MAC((_hw), EICR_GPI_SDP2) 1862283620Serj 1863230775Sjfv#define IXGBE_EICR_PBUR 0x10000000 /* Packet Buffer Handler Error */ 1864230775Sjfv#define IXGBE_EICR_DHER 0x20000000 /* Descriptor Handler Error */ 1865230775Sjfv#define IXGBE_EICR_TCP_TIMER 0x40000000 /* TCP Timer */ 1866230775Sjfv#define IXGBE_EICR_OTHER 0x80000000 /* Interrupt Cause Active */ 1867171384Sjfv 1868171384Sjfv/* Extended Interrupt Cause Set */ 1869230775Sjfv#define IXGBE_EICS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1870230775Sjfv#define IXGBE_EICS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1871230775Sjfv#define IXGBE_EICS_RX_MISS IXGBE_EICR_RX_MISS /* Pkt Buffer Overrun */ 1872230775Sjfv#define IXGBE_EICS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1873230775Sjfv#define IXGBE_EICS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1874230775Sjfv#define IXGBE_EICS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1875230775Sjfv#define IXGBE_EICS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1876238149Sjfv#define IXGBE_EICS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1877230775Sjfv#define IXGBE_EICS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1878230775Sjfv#define IXGBE_EICS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1879230775Sjfv#define IXGBE_EICS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1880230775Sjfv#define IXGBE_EICS_ECC IXGBE_EICR_ECC /* ECC Error */ 1881283620Serj#define IXGBE_EICS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1882283620Serj#define IXGBE_EICS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1883283620Serj#define IXGBE_EICS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 1884230775Sjfv#define IXGBE_EICS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1885230775Sjfv#define IXGBE_EICS_DHER IXGBE_EICR_DHER /* Desc Handler Error */ 1886230775Sjfv#define IXGBE_EICS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1887230775Sjfv#define IXGBE_EICS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1888171384Sjfv 1889171384Sjfv/* Extended Interrupt Mask Set */ 1890230775Sjfv#define IXGBE_EIMS_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1891230775Sjfv#define IXGBE_EIMS_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1892230775Sjfv#define IXGBE_EIMS_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1893230775Sjfv#define IXGBE_EIMS_PCI IXGBE_EICR_PCI /* PCI Exception */ 1894230775Sjfv#define IXGBE_EIMS_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1895230775Sjfv#define IXGBE_EIMS_LSC IXGBE_EICR_LSC /* Link Status Change */ 1896230775Sjfv#define IXGBE_EIMS_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1897230775Sjfv#define IXGBE_EIMS_TS IXGBE_EICR_TS /* Thermal Sensor Event */ 1898238149Sjfv#define IXGBE_EIMS_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1899230775Sjfv#define IXGBE_EIMS_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1900230775Sjfv#define IXGBE_EIMS_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1901230775Sjfv#define IXGBE_EIMS_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1902230775Sjfv#define IXGBE_EIMS_ECC IXGBE_EICR_ECC /* ECC Error */ 1903283620Serj#define IXGBE_EIMS_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1904283620Serj#define IXGBE_EIMS_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1905283620Serj#define IXGBE_EIMS_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 1906230775Sjfv#define IXGBE_EIMS_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1907230775Sjfv#define IXGBE_EIMS_DHER IXGBE_EICR_DHER /* Descr Handler Error */ 1908230775Sjfv#define IXGBE_EIMS_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1909230775Sjfv#define IXGBE_EIMS_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1910171384Sjfv 1911171384Sjfv/* Extended Interrupt Mask Clear */ 1912230775Sjfv#define IXGBE_EIMC_RTX_QUEUE IXGBE_EICR_RTX_QUEUE /* RTx Queue Interrupt */ 1913230775Sjfv#define IXGBE_EIMC_FLOW_DIR IXGBE_EICR_FLOW_DIR /* FDir Exception */ 1914230775Sjfv#define IXGBE_EIMC_RX_MISS IXGBE_EICR_RX_MISS /* Packet Buffer Overrun */ 1915230775Sjfv#define IXGBE_EIMC_PCI IXGBE_EICR_PCI /* PCI Exception */ 1916230775Sjfv#define IXGBE_EIMC_MAILBOX IXGBE_EICR_MAILBOX /* VF to PF Mailbox Int */ 1917230775Sjfv#define IXGBE_EIMC_LSC IXGBE_EICR_LSC /* Link Status Change */ 1918230775Sjfv#define IXGBE_EIMC_MNG IXGBE_EICR_MNG /* MNG Event Interrupt */ 1919238149Sjfv#define IXGBE_EIMC_TIMESYNC IXGBE_EICR_TIMESYNC /* Timesync Event */ 1920230775Sjfv#define IXGBE_EIMC_GPI_SDP0 IXGBE_EICR_GPI_SDP0 /* SDP0 Gen Purpose Int */ 1921230775Sjfv#define IXGBE_EIMC_GPI_SDP1 IXGBE_EICR_GPI_SDP1 /* SDP1 Gen Purpose Int */ 1922230775Sjfv#define IXGBE_EIMC_GPI_SDP2 IXGBE_EICR_GPI_SDP2 /* SDP2 Gen Purpose Int */ 1923230775Sjfv#define IXGBE_EIMC_ECC IXGBE_EICR_ECC /* ECC Error */ 1924283620Serj#define IXGBE_EIMC_GPI_SDP0_BY_MAC(_hw) IXGBE_EICR_GPI_SDP0_BY_MAC(_hw) 1925283620Serj#define IXGBE_EIMC_GPI_SDP1_BY_MAC(_hw) IXGBE_EICR_GPI_SDP1_BY_MAC(_hw) 1926283620Serj#define IXGBE_EIMC_GPI_SDP2_BY_MAC(_hw) IXGBE_EICR_GPI_SDP2_BY_MAC(_hw) 1927230775Sjfv#define IXGBE_EIMC_PBUR IXGBE_EICR_PBUR /* Pkt Buf Handler Err */ 1928230775Sjfv#define IXGBE_EIMC_DHER IXGBE_EICR_DHER /* Desc Handler Err */ 1929230775Sjfv#define IXGBE_EIMC_TCP_TIMER IXGBE_EICR_TCP_TIMER /* TCP Timer */ 1930230775Sjfv#define IXGBE_EIMC_OTHER IXGBE_EICR_OTHER /* INT Cause Active */ 1931171384Sjfv 1932171384Sjfv#define IXGBE_EIMS_ENABLE_MASK ( \ 1933230775Sjfv IXGBE_EIMS_RTX_QUEUE | \ 1934230775Sjfv IXGBE_EIMS_LSC | \ 1935230775Sjfv IXGBE_EIMS_TCP_TIMER | \ 1936230775Sjfv IXGBE_EIMS_OTHER) 1937171384Sjfv 1938179055Sjfv/* Immediate Interrupt Rx (A.K.A. Low Latency Interrupt) */ 1939230775Sjfv#define IXGBE_IMIR_PORT_IM_EN 0x00010000 /* TCP port enable */ 1940230775Sjfv#define IXGBE_IMIR_PORT_BP 0x00020000 /* TCP port check bypass */ 1941230775Sjfv#define IXGBE_IMIREXT_SIZE_BP 0x00001000 /* Packet size bypass */ 1942230775Sjfv#define IXGBE_IMIREXT_CTRL_URG 0x00002000 /* Check URG bit in header */ 1943230775Sjfv#define IXGBE_IMIREXT_CTRL_ACK 0x00004000 /* Check ACK bit in header */ 1944230775Sjfv#define IXGBE_IMIREXT_CTRL_PSH 0x00008000 /* Check PSH bit in header */ 1945230775Sjfv#define IXGBE_IMIREXT_CTRL_RST 0x00010000 /* Check RST bit in header */ 1946230775Sjfv#define IXGBE_IMIREXT_CTRL_SYN 0x00020000 /* Check SYN bit in header */ 1947230775Sjfv#define IXGBE_IMIREXT_CTRL_FIN 0x00040000 /* Check FIN bit in header */ 1948230775Sjfv#define IXGBE_IMIREXT_CTRL_BP 0x00080000 /* Bypass check of control bits */ 1949230775Sjfv#define IXGBE_IMIR_SIZE_BP_82599 0x00001000 /* Packet size bypass */ 1950230775Sjfv#define IXGBE_IMIR_CTRL_URG_82599 0x00002000 /* Check URG bit in header */ 1951230775Sjfv#define IXGBE_IMIR_CTRL_ACK_82599 0x00004000 /* Check ACK bit in header */ 1952230775Sjfv#define IXGBE_IMIR_CTRL_PSH_82599 0x00008000 /* Check PSH bit in header */ 1953230775Sjfv#define IXGBE_IMIR_CTRL_RST_82599 0x00010000 /* Check RST bit in header */ 1954230775Sjfv#define IXGBE_IMIR_CTRL_SYN_82599 0x00020000 /* Check SYN bit in header */ 1955230775Sjfv#define IXGBE_IMIR_CTRL_FIN_82599 0x00040000 /* Check FIN bit in header */ 1956230775Sjfv#define IXGBE_IMIR_CTRL_BP_82599 0x00080000 /* Bypass chk of ctrl bits */ 1957230775Sjfv#define IXGBE_IMIR_LLI_EN_82599 0x00100000 /* Enables low latency Int */ 1958230775Sjfv#define IXGBE_IMIR_RX_QUEUE_MASK_82599 0x0000007F /* Rx Queue Mask */ 1959230775Sjfv#define IXGBE_IMIR_RX_QUEUE_SHIFT_82599 21 /* Rx Queue Shift */ 1960230775Sjfv#define IXGBE_IMIRVP_PRIORITY_MASK 0x00000007 /* VLAN priority mask */ 1961230775Sjfv#define IXGBE_IMIRVP_PRIORITY_EN 0x00000008 /* VLAN priority enable */ 1962171384Sjfv 1963230775Sjfv#define IXGBE_MAX_FTQF_FILTERS 128 1964230775Sjfv#define IXGBE_FTQF_PROTOCOL_MASK 0x00000003 1965230775Sjfv#define IXGBE_FTQF_PROTOCOL_TCP 0x00000000 1966230775Sjfv#define IXGBE_FTQF_PROTOCOL_UDP 0x00000001 1967230775Sjfv#define IXGBE_FTQF_PROTOCOL_SCTP 2 1968230775Sjfv#define IXGBE_FTQF_PRIORITY_MASK 0x00000007 1969230775Sjfv#define IXGBE_FTQF_PRIORITY_SHIFT 2 1970230775Sjfv#define IXGBE_FTQF_POOL_MASK 0x0000003F 1971230775Sjfv#define IXGBE_FTQF_POOL_SHIFT 8 1972230775Sjfv#define IXGBE_FTQF_5TUPLE_MASK_MASK 0x0000001F 1973230775Sjfv#define IXGBE_FTQF_5TUPLE_MASK_SHIFT 25 1974230775Sjfv#define IXGBE_FTQF_SOURCE_ADDR_MASK 0x1E 1975230775Sjfv#define IXGBE_FTQF_DEST_ADDR_MASK 0x1D 1976230775Sjfv#define IXGBE_FTQF_SOURCE_PORT_MASK 0x1B 1977230775Sjfv#define IXGBE_FTQF_DEST_PORT_MASK 0x17 1978230775Sjfv#define IXGBE_FTQF_PROTOCOL_COMP_MASK 0x0F 1979230775Sjfv#define IXGBE_FTQF_POOL_MASK_EN 0x40000000 1980230775Sjfv#define IXGBE_FTQF_QUEUE_ENABLE 0x80000000 1981190873Sjfv 1982171384Sjfv/* Interrupt clear mask */ 1983230775Sjfv#define IXGBE_IRQ_CLEAR_MASK 0xFFFFFFFF 1984171384Sjfv 1985171384Sjfv/* Interrupt Vector Allocation Registers */ 1986230775Sjfv#define IXGBE_IVAR_REG_NUM 25 1987230775Sjfv#define IXGBE_IVAR_REG_NUM_82599 64 1988230775Sjfv#define IXGBE_IVAR_TXRX_ENTRY 96 1989230775Sjfv#define IXGBE_IVAR_RX_ENTRY 64 1990230775Sjfv#define IXGBE_IVAR_RX_QUEUE(_i) (0 + (_i)) 1991230775Sjfv#define IXGBE_IVAR_TX_QUEUE(_i) (64 + (_i)) 1992230775Sjfv#define IXGBE_IVAR_TX_ENTRY 32 1993171384Sjfv 1994230775Sjfv#define IXGBE_IVAR_TCP_TIMER_INDEX 96 /* 0 based index */ 1995230775Sjfv#define IXGBE_IVAR_OTHER_CAUSES_INDEX 97 /* 0 based index */ 1996171384Sjfv 1997230775Sjfv#define IXGBE_MSIX_VECTOR(_i) (0 + (_i)) 1998171384Sjfv 1999230775Sjfv#define IXGBE_IVAR_ALLOC_VAL 0x80 /* Interrupt Allocation valid */ 2000171384Sjfv 2001190873Sjfv/* ETYPE Queue Filter/Select Bit Masks */ 2002230775Sjfv#define IXGBE_MAX_ETQF_FILTERS 8 2003230775Sjfv#define IXGBE_ETQF_FCOE 0x08000000 /* bit 27 */ 2004230775Sjfv#define IXGBE_ETQF_BCN 0x10000000 /* bit 28 */ 2005283620Serj#define IXGBE_ETQF_TX_ANTISPOOF 0x20000000 /* bit 29 */ 2006230775Sjfv#define IXGBE_ETQF_1588 0x40000000 /* bit 30 */ 2007230775Sjfv#define IXGBE_ETQF_FILTER_EN 0x80000000 /* bit 31 */ 2008230775Sjfv#define IXGBE_ETQF_POOL_ENABLE (1 << 26) /* bit 26 */ 2009238149Sjfv#define IXGBE_ETQF_POOL_SHIFT 20 2010190873Sjfv 2011230775Sjfv#define IXGBE_ETQS_RX_QUEUE 0x007F0000 /* bits 22:16 */ 2012230775Sjfv#define IXGBE_ETQS_RX_QUEUE_SHIFT 16 2013230775Sjfv#define IXGBE_ETQS_LLI 0x20000000 /* bit 29 */ 2014230775Sjfv#define IXGBE_ETQS_QUEUE_EN 0x80000000 /* bit 31 */ 2015190873Sjfv 2016190873Sjfv/* 2017190873Sjfv * ETQF filter list: one static filter per filter consumer. This is 2018230775Sjfv * to avoid filter collisions later. Add new filters 2019230775Sjfv * here!! 2020190873Sjfv * 2021190873Sjfv * Current filters: 2022230775Sjfv * EAPOL 802.1x (0x888e): Filter 0 2023230775Sjfv * FCoE (0x8906): Filter 2 2024230775Sjfv * 1588 (0x88f7): Filter 3 2025230775Sjfv * FIP (0x8914): Filter 4 2026283620Serj * LLDP (0x88CC): Filter 5 2027283620Serj * LACP (0x8809): Filter 6 2028295524Ssbruno * FC (0x8808): Filter 7 2029190873Sjfv */ 2030230775Sjfv#define IXGBE_ETQF_FILTER_EAPOL 0 2031230775Sjfv#define IXGBE_ETQF_FILTER_FCOE 2 2032230775Sjfv#define IXGBE_ETQF_FILTER_1588 3 2033230775Sjfv#define IXGBE_ETQF_FILTER_FIP 4 2034283620Serj#define IXGBE_ETQF_FILTER_LLDP 5 2035283620Serj#define IXGBE_ETQF_FILTER_LACP 6 2036295524Ssbruno#define IXGBE_ETQF_FILTER_FC 7 2037171384Sjfv/* VLAN Control Bit Masks */ 2038230775Sjfv#define IXGBE_VLNCTRL_VET 0x0000FFFF /* bits 0-15 */ 2039230775Sjfv#define IXGBE_VLNCTRL_CFI 0x10000000 /* bit 28 */ 2040230775Sjfv#define IXGBE_VLNCTRL_CFIEN 0x20000000 /* bit 29 */ 2041230775Sjfv#define IXGBE_VLNCTRL_VFE 0x40000000 /* bit 30 */ 2042230775Sjfv#define IXGBE_VLNCTRL_VME 0x80000000 /* bit 31 */ 2043171384Sjfv 2044190873Sjfv/* VLAN pool filtering masks */ 2045230775Sjfv#define IXGBE_VLVF_VIEN 0x80000000 /* filter is valid */ 2046230775Sjfv#define IXGBE_VLVF_ENTRIES 64 2047230775Sjfv#define IXGBE_VLVF_VLANID_MASK 0x00000FFF 2048215911Sjfv/* Per VF Port VLAN insertion rules */ 2049230775Sjfv#define IXGBE_VMVIR_VLANA_DEFAULT 0x40000000 /* Always use default VLAN */ 2050230775Sjfv#define IXGBE_VMVIR_VLANA_NEVER 0x80000000 /* Never insert VLAN tag */ 2051179055Sjfv 2052230775Sjfv#define IXGBE_ETHERNET_IEEE_VLAN_TYPE 0x8100 /* 802.1q protocol */ 2053171384Sjfv 2054171384Sjfv/* STATUS Bit Masks */ 2055230775Sjfv#define IXGBE_STATUS_LAN_ID 0x0000000C /* LAN ID */ 2056230775Sjfv#define IXGBE_STATUS_LAN_ID_SHIFT 2 /* LAN ID Shift*/ 2057230775Sjfv#define IXGBE_STATUS_GIO 0x00080000 /* GIO Master Ena Status */ 2058171384Sjfv 2059230775Sjfv#define IXGBE_STATUS_LAN_ID_0 0x00000000 /* LAN ID 0 */ 2060230775Sjfv#define IXGBE_STATUS_LAN_ID_1 0x00000004 /* LAN ID 1 */ 2061171384Sjfv 2062171384Sjfv/* ESDP Bit Masks */ 2063230775Sjfv#define IXGBE_ESDP_SDP0 0x00000001 /* SDP0 Data Value */ 2064230775Sjfv#define IXGBE_ESDP_SDP1 0x00000002 /* SDP1 Data Value */ 2065230775Sjfv#define IXGBE_ESDP_SDP2 0x00000004 /* SDP2 Data Value */ 2066230775Sjfv#define IXGBE_ESDP_SDP3 0x00000008 /* SDP3 Data Value */ 2067230775Sjfv#define IXGBE_ESDP_SDP4 0x00000010 /* SDP4 Data Value */ 2068230775Sjfv#define IXGBE_ESDP_SDP5 0x00000020 /* SDP5 Data Value */ 2069230775Sjfv#define IXGBE_ESDP_SDP6 0x00000040 /* SDP6 Data Value */ 2070238149Sjfv#define IXGBE_ESDP_SDP7 0x00000080 /* SDP7 Data Value */ 2071238149Sjfv#define IXGBE_ESDP_SDP0_DIR 0x00000100 /* SDP0 IO direction */ 2072238149Sjfv#define IXGBE_ESDP_SDP1_DIR 0x00000200 /* SDP1 IO direction */ 2073247822Sjfv#define IXGBE_ESDP_SDP2_DIR 0x00000400 /* SDP1 IO direction */ 2074238149Sjfv#define IXGBE_ESDP_SDP3_DIR 0x00000800 /* SDP3 IO direction */ 2075238149Sjfv#define IXGBE_ESDP_SDP4_DIR 0x00001000 /* SDP4 IO direction */ 2076230775Sjfv#define IXGBE_ESDP_SDP5_DIR 0x00002000 /* SDP5 IO direction */ 2077238149Sjfv#define IXGBE_ESDP_SDP6_DIR 0x00004000 /* SDP6 IO direction */ 2078238149Sjfv#define IXGBE_ESDP_SDP7_DIR 0x00008000 /* SDP7 IO direction */ 2079238149Sjfv#define IXGBE_ESDP_SDP0_NATIVE 0x00010000 /* SDP0 IO mode */ 2080238149Sjfv#define IXGBE_ESDP_SDP1_NATIVE 0x00020000 /* SDP1 IO mode */ 2081171384Sjfv 2082238149Sjfv 2083171384Sjfv/* LEDCTL Bit Masks */ 2084230775Sjfv#define IXGBE_LED_IVRT_BASE 0x00000040 2085230775Sjfv#define IXGBE_LED_BLINK_BASE 0x00000080 2086230775Sjfv#define IXGBE_LED_MODE_MASK_BASE 0x0000000F 2087230775Sjfv#define IXGBE_LED_OFFSET(_base, _i) (_base << (8 * (_i))) 2088230775Sjfv#define IXGBE_LED_MODE_SHIFT(_i) (8*(_i)) 2089230775Sjfv#define IXGBE_LED_IVRT(_i) IXGBE_LED_OFFSET(IXGBE_LED_IVRT_BASE, _i) 2090230775Sjfv#define IXGBE_LED_BLINK(_i) IXGBE_LED_OFFSET(IXGBE_LED_BLINK_BASE, _i) 2091230775Sjfv#define IXGBE_LED_MODE_MASK(_i) IXGBE_LED_OFFSET(IXGBE_LED_MODE_MASK_BASE, _i) 2092283620Serj#define IXGBE_X557_LED_MANUAL_SET_MASK (1 << 8) 2093283620Serj#define IXGBE_X557_MAX_LED_INDEX 3 2094283620Serj#define IXGBE_X557_LED_PROVISIONING 0xC430 2095171384Sjfv 2096171384Sjfv/* LED modes */ 2097230775Sjfv#define IXGBE_LED_LINK_UP 0x0 2098230775Sjfv#define IXGBE_LED_LINK_10G 0x1 2099230775Sjfv#define IXGBE_LED_MAC 0x2 2100230775Sjfv#define IXGBE_LED_FILTER 0x3 2101230775Sjfv#define IXGBE_LED_LINK_ACTIVE 0x4 2102230775Sjfv#define IXGBE_LED_LINK_1G 0x5 2103230775Sjfv#define IXGBE_LED_ON 0xE 2104230775Sjfv#define IXGBE_LED_OFF 0xF 2105171384Sjfv 2106171384Sjfv/* AUTOC Bit Masks */ 2107190873Sjfv#define IXGBE_AUTOC_KX4_KX_SUPP_MASK 0xC0000000 2108230775Sjfv#define IXGBE_AUTOC_KX4_SUPP 0x80000000 2109230775Sjfv#define IXGBE_AUTOC_KX_SUPP 0x40000000 2110230775Sjfv#define IXGBE_AUTOC_PAUSE 0x30000000 2111230775Sjfv#define IXGBE_AUTOC_ASM_PAUSE 0x20000000 2112230775Sjfv#define IXGBE_AUTOC_SYM_PAUSE 0x10000000 2113230775Sjfv#define IXGBE_AUTOC_RF 0x08000000 2114230775Sjfv#define IXGBE_AUTOC_PD_TMR 0x06000000 2115230775Sjfv#define IXGBE_AUTOC_AN_RX_LOOSE 0x01000000 2116230775Sjfv#define IXGBE_AUTOC_AN_RX_DRIFT 0x00800000 2117230775Sjfv#define IXGBE_AUTOC_AN_RX_ALIGN 0x007C0000 2118230775Sjfv#define IXGBE_AUTOC_FECA 0x00040000 2119230775Sjfv#define IXGBE_AUTOC_FECR 0x00020000 2120230775Sjfv#define IXGBE_AUTOC_KR_SUPP 0x00010000 2121230775Sjfv#define IXGBE_AUTOC_AN_RESTART 0x00001000 2122230775Sjfv#define IXGBE_AUTOC_FLU 0x00000001 2123230775Sjfv#define IXGBE_AUTOC_LMS_SHIFT 13 2124230775Sjfv#define IXGBE_AUTOC_LMS_10G_SERIAL (0x3 << IXGBE_AUTOC_LMS_SHIFT) 2125230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR (0x4 << IXGBE_AUTOC_LMS_SHIFT) 2126230775Sjfv#define IXGBE_AUTOC_LMS_SGMII_1G_100M (0x5 << IXGBE_AUTOC_LMS_SHIFT) 2127230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 2128230775Sjfv#define IXGBE_AUTOC_LMS_KX4_KX_KR_SGMII (0x7 << IXGBE_AUTOC_LMS_SHIFT) 2129230775Sjfv#define IXGBE_AUTOC_LMS_MASK (0x7 << IXGBE_AUTOC_LMS_SHIFT) 2130230775Sjfv#define IXGBE_AUTOC_LMS_1G_LINK_NO_AN (0x0 << IXGBE_AUTOC_LMS_SHIFT) 2131230775Sjfv#define IXGBE_AUTOC_LMS_10G_LINK_NO_AN (0x1 << IXGBE_AUTOC_LMS_SHIFT) 2132230775Sjfv#define IXGBE_AUTOC_LMS_1G_AN (0x2 << IXGBE_AUTOC_LMS_SHIFT) 2133230775Sjfv#define IXGBE_AUTOC_LMS_KX4_AN (0x4 << IXGBE_AUTOC_LMS_SHIFT) 2134230775Sjfv#define IXGBE_AUTOC_LMS_KX4_AN_1G_AN (0x6 << IXGBE_AUTOC_LMS_SHIFT) 2135230775Sjfv#define IXGBE_AUTOC_LMS_ATTACH_TYPE (0x7 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2136171384Sjfv 2137230775Sjfv#define IXGBE_AUTOC_1G_PMA_PMD_MASK 0x00000200 2138230775Sjfv#define IXGBE_AUTOC_1G_PMA_PMD_SHIFT 9 2139230775Sjfv#define IXGBE_AUTOC_10G_PMA_PMD_MASK 0x00000180 2140230775Sjfv#define IXGBE_AUTOC_10G_PMA_PMD_SHIFT 7 2141230775Sjfv#define IXGBE_AUTOC_10G_XAUI (0x0 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2142230775Sjfv#define IXGBE_AUTOC_10G_KX4 (0x1 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2143230775Sjfv#define IXGBE_AUTOC_10G_CX4 (0x2 << IXGBE_AUTOC_10G_PMA_PMD_SHIFT) 2144230775Sjfv#define IXGBE_AUTOC_1G_BX (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2145230775Sjfv#define IXGBE_AUTOC_1G_KX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2146230775Sjfv#define IXGBE_AUTOC_1G_SFI (0x0 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2147230775Sjfv#define IXGBE_AUTOC_1G_KX_BX (0x1 << IXGBE_AUTOC_1G_PMA_PMD_SHIFT) 2148171384Sjfv 2149230775Sjfv#define IXGBE_AUTOC2_UPPER_MASK 0xFFFF0000 2150230775Sjfv#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_MASK 0x00030000 2151230775Sjfv#define IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT 16 2152230775Sjfv#define IXGBE_AUTOC2_10G_KR (0x0 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2153230775Sjfv#define IXGBE_AUTOC2_10G_XFI (0x1 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2154230775Sjfv#define IXGBE_AUTOC2_10G_SFI (0x2 << IXGBE_AUTOC2_10G_SERIAL_PMA_PMD_SHIFT) 2155251964Sjfv#define IXGBE_AUTOC2_LINK_DISABLE_ON_D3_MASK 0x50000000 2156251964Sjfv#define IXGBE_AUTOC2_LINK_DISABLE_MASK 0x70000000 2157190873Sjfv 2158230775Sjfv#define IXGBE_MACC_FLU 0x00000001 2159230775Sjfv#define IXGBE_MACC_FSV_10G 0x00030000 2160230775Sjfv#define IXGBE_MACC_FS 0x00040000 2161230775Sjfv#define IXGBE_MAC_RX2TX_LPBK 0x00000002 2162205720Sjfv 2163283620Serj/* Veto Bit definiton */ 2164283620Serj#define IXGBE_MMNGC_MNG_VETO 0x00000001 2165283620Serj 2166171384Sjfv/* LINKS Bit Masks */ 2167230775Sjfv#define IXGBE_LINKS_KX_AN_COMP 0x80000000 2168230775Sjfv#define IXGBE_LINKS_UP 0x40000000 2169230775Sjfv#define IXGBE_LINKS_SPEED 0x20000000 2170230775Sjfv#define IXGBE_LINKS_MODE 0x18000000 2171230775Sjfv#define IXGBE_LINKS_RX_MODE 0x06000000 2172230775Sjfv#define IXGBE_LINKS_TX_MODE 0x01800000 2173230775Sjfv#define IXGBE_LINKS_XGXS_EN 0x00400000 2174230775Sjfv#define IXGBE_LINKS_SGMII_EN 0x02000000 2175230775Sjfv#define IXGBE_LINKS_PCS_1G_EN 0x00200000 2176230775Sjfv#define IXGBE_LINKS_1G_AN_EN 0x00100000 2177230775Sjfv#define IXGBE_LINKS_KX_AN_IDLE 0x00080000 2178230775Sjfv#define IXGBE_LINKS_1G_SYNC 0x00040000 2179230775Sjfv#define IXGBE_LINKS_10G_ALIGN 0x00020000 2180230775Sjfv#define IXGBE_LINKS_10G_LANE_SYNC 0x00017000 2181230775Sjfv#define IXGBE_LINKS_TL_FAULT 0x00001000 2182230775Sjfv#define IXGBE_LINKS_SIGNAL 0x00000F00 2183171384Sjfv 2184283620Serj#define IXGBE_LINKS_SPEED_NON_STD 0x08000000 2185230775Sjfv#define IXGBE_LINKS_SPEED_82599 0x30000000 2186230775Sjfv#define IXGBE_LINKS_SPEED_10G_82599 0x30000000 2187230775Sjfv#define IXGBE_LINKS_SPEED_1G_82599 0x20000000 2188230775Sjfv#define IXGBE_LINKS_SPEED_100_82599 0x10000000 2189315333Serj#define IXGBE_LINKS_SPEED_10_X550EM_A 0x00000000 2190230775Sjfv#define IXGBE_LINK_UP_TIME 90 /* 9.0 Seconds */ 2191230775Sjfv#define IXGBE_AUTO_NEG_TIME 45 /* 4.5 Seconds */ 2192171384Sjfv 2193230775Sjfv#define IXGBE_LINKS2_AN_SUPPORTED 0x00000040 2194200239Sjfv 2195172043Sjfv/* PCS1GLSTA Bit Masks */ 2196230775Sjfv#define IXGBE_PCS1GLSTA_LINK_OK 1 2197230775Sjfv#define IXGBE_PCS1GLSTA_SYNK_OK 0x10 2198230775Sjfv#define IXGBE_PCS1GLSTA_AN_COMPLETE 0x10000 2199230775Sjfv#define IXGBE_PCS1GLSTA_AN_PAGE_RX 0x20000 2200230775Sjfv#define IXGBE_PCS1GLSTA_AN_TIMED_OUT 0x40000 2201230775Sjfv#define IXGBE_PCS1GLSTA_AN_REMOTE_FAULT 0x80000 2202230775Sjfv#define IXGBE_PCS1GLSTA_AN_ERROR_RWS 0x100000 2203172043Sjfv 2204230775Sjfv#define IXGBE_PCS1GANA_SYM_PAUSE 0x80 2205230775Sjfv#define IXGBE_PCS1GANA_ASM_PAUSE 0x100 2206172043Sjfv 2207172043Sjfv/* PCS1GLCTL Bit Masks */ 2208230775Sjfv#define IXGBE_PCS1GLCTL_AN_1G_TIMEOUT_EN 0x00040000 /* PCS 1G autoneg to en */ 2209230775Sjfv#define IXGBE_PCS1GLCTL_FLV_LINK_UP 1 2210230775Sjfv#define IXGBE_PCS1GLCTL_FORCE_LINK 0x20 2211230775Sjfv#define IXGBE_PCS1GLCTL_LOW_LINK_LATCH 0x40 2212230775Sjfv#define IXGBE_PCS1GLCTL_AN_ENABLE 0x10000 2213230775Sjfv#define IXGBE_PCS1GLCTL_AN_RESTART 0x20000 2214172043Sjfv 2215200239Sjfv/* ANLP1 Bit Masks */ 2216230775Sjfv#define IXGBE_ANLP1_PAUSE 0x0C00 2217230775Sjfv#define IXGBE_ANLP1_SYM_PAUSE 0x0400 2218230775Sjfv#define IXGBE_ANLP1_ASM_PAUSE 0x0800 2219230775Sjfv#define IXGBE_ANLP1_AN_STATE_MASK 0x000f0000 2220200239Sjfv 2221171384Sjfv/* SW Semaphore Register bitmasks */ 2222230775Sjfv#define IXGBE_SWSM_SMBI 0x00000001 /* Driver Semaphore bit */ 2223230775Sjfv#define IXGBE_SWSM_SWESMBI 0x00000002 /* FW Semaphore bit */ 2224230775Sjfv#define IXGBE_SWSM_WMNG 0x00000004 /* Wake MNG Clock */ 2225230775Sjfv#define IXGBE_SWFW_REGSMP 0x80000000 /* Register Semaphore bit 31 */ 2226171384Sjfv 2227200239Sjfv/* SW_FW_SYNC/GSSR definitions */ 2228283620Serj#define IXGBE_GSSR_EEP_SM 0x0001 2229283620Serj#define IXGBE_GSSR_PHY0_SM 0x0002 2230283620Serj#define IXGBE_GSSR_PHY1_SM 0x0004 2231283620Serj#define IXGBE_GSSR_MAC_CSR_SM 0x0008 2232283620Serj#define IXGBE_GSSR_FLASH_SM 0x0010 2233283620Serj#define IXGBE_GSSR_NVM_UPDATE_SM 0x0200 2234283620Serj#define IXGBE_GSSR_SW_MNG_SM 0x0400 2235315333Serj#define IXGBE_GSSR_TOKEN_SM 0x40000000 /* SW bit for shared access */ 2236283620Serj#define IXGBE_GSSR_SHARED_I2C_SM 0x1806 /* Wait for both phys and both I2Cs */ 2237283620Serj#define IXGBE_GSSR_I2C_MASK 0x1800 2238283620Serj#define IXGBE_GSSR_NVM_PHY_MASK 0xF 2239171384Sjfv 2240230775Sjfv/* FW Status register bitmask */ 2241230775Sjfv#define IXGBE_FWSTS_FWRI 0x00000200 /* Firmware Reset Indication */ 2242230775Sjfv 2243171384Sjfv/* EEC Register */ 2244230775Sjfv#define IXGBE_EEC_SK 0x00000001 /* EEPROM Clock */ 2245230775Sjfv#define IXGBE_EEC_CS 0x00000002 /* EEPROM Chip Select */ 2246230775Sjfv#define IXGBE_EEC_DI 0x00000004 /* EEPROM Data In */ 2247230775Sjfv#define IXGBE_EEC_DO 0x00000008 /* EEPROM Data Out */ 2248230775Sjfv#define IXGBE_EEC_FWE_MASK 0x00000030 /* FLASH Write Enable */ 2249230775Sjfv#define IXGBE_EEC_FWE_DIS 0x00000010 /* Disable FLASH writes */ 2250230775Sjfv#define IXGBE_EEC_FWE_EN 0x00000020 /* Enable FLASH writes */ 2251230775Sjfv#define IXGBE_EEC_FWE_SHIFT 4 2252230775Sjfv#define IXGBE_EEC_REQ 0x00000040 /* EEPROM Access Request */ 2253230775Sjfv#define IXGBE_EEC_GNT 0x00000080 /* EEPROM Access Grant */ 2254230775Sjfv#define IXGBE_EEC_PRES 0x00000100 /* EEPROM Present */ 2255230775Sjfv#define IXGBE_EEC_ARD 0x00000200 /* EEPROM Auto Read Done */ 2256230775Sjfv#define IXGBE_EEC_FLUP 0x00800000 /* Flash update command */ 2257230775Sjfv#define IXGBE_EEC_SEC1VAL 0x02000000 /* Sector 1 Valid */ 2258230775Sjfv#define IXGBE_EEC_FLUDONE 0x04000000 /* Flash update done */ 2259171384Sjfv/* EEPROM Addressing bits based on type (0-small, 1-large) */ 2260230775Sjfv#define IXGBE_EEC_ADDR_SIZE 0x00000400 2261230775Sjfv#define IXGBE_EEC_SIZE 0x00007800 /* EEPROM Size */ 2262230775Sjfv#define IXGBE_EERD_MAX_ADDR 0x00003FFF /* EERD alows 14 bits for addr. */ 2263171384Sjfv 2264230775Sjfv#define IXGBE_EEC_SIZE_SHIFT 11 2265230775Sjfv#define IXGBE_EEPROM_WORD_SIZE_SHIFT 6 2266230775Sjfv#define IXGBE_EEPROM_OPCODE_BITS 8 2267171384Sjfv 2268283620Serj/* FLA Register */ 2269283620Serj#define IXGBE_FLA_LOCKED 0x00000040 2270283620Serj 2271215911Sjfv/* Part Number String Length */ 2272230775Sjfv#define IXGBE_PBANUM_LENGTH 11 2273215911Sjfv 2274171384Sjfv/* Checksum and EEPROM pointers */ 2275283620Serj#define IXGBE_PBANUM_PTR_GUARD 0xFAFA 2276283620Serj#define IXGBE_EEPROM_CHECKSUM 0x3F 2277283620Serj#define IXGBE_EEPROM_SUM 0xBABA 2278315333Serj#define IXGBE_EEPROM_CTRL_4 0x45 2279315333Serj#define IXGBE_EE_CTRL_4_INST_ID 0x10 2280315333Serj#define IXGBE_EE_CTRL_4_INST_ID_SHIFT 4 2281283620Serj#define IXGBE_PCIE_ANALOG_PTR 0x03 2282283620Serj#define IXGBE_ATLAS0_CONFIG_PTR 0x04 2283283620Serj#define IXGBE_PHY_PTR 0x04 2284283620Serj#define IXGBE_ATLAS1_CONFIG_PTR 0x05 2285283620Serj#define IXGBE_OPTION_ROM_PTR 0x05 2286283620Serj#define IXGBE_PCIE_GENERAL_PTR 0x06 2287283620Serj#define IXGBE_PCIE_CONFIG0_PTR 0x07 2288283620Serj#define IXGBE_PCIE_CONFIG1_PTR 0x08 2289283620Serj#define IXGBE_CORE0_PTR 0x09 2290283620Serj#define IXGBE_CORE1_PTR 0x0A 2291283620Serj#define IXGBE_MAC0_PTR 0x0B 2292283620Serj#define IXGBE_MAC1_PTR 0x0C 2293283620Serj#define IXGBE_CSR0_CONFIG_PTR 0x0D 2294283620Serj#define IXGBE_CSR1_CONFIG_PTR 0x0E 2295283620Serj#define IXGBE_PCIE_ANALOG_PTR_X550 0x02 2296283620Serj#define IXGBE_SHADOW_RAM_SIZE_X550 0x4000 2297283620Serj#define IXGBE_IXGBE_PCIE_GENERAL_SIZE 0x24 2298283620Serj#define IXGBE_PCIE_CONFIG_SIZE 0x08 2299283620Serj#define IXGBE_EEPROM_LAST_WORD 0x41 2300283620Serj#define IXGBE_FW_PTR 0x0F 2301283620Serj#define IXGBE_PBANUM0_PTR 0x15 2302283620Serj#define IXGBE_PBANUM1_PTR 0x16 2303283620Serj#define IXGBE_ALT_MAC_ADDR_PTR 0x37 2304283620Serj#define IXGBE_FREE_SPACE_PTR 0X3E 2305171384Sjfv 2306230775Sjfv#define IXGBE_SAN_MAC_ADDR_PTR 0x28 2307230775Sjfv#define IXGBE_DEVICE_CAPS 0x2C 2308315333Serj#define IXGBE_82599_SERIAL_NUMBER_MAC_ADDR 0x11 2309315333Serj#define IXGBE_X550_SERIAL_NUMBER_MAC_ADDR 0x04 2310315333Serj 2311230775Sjfv#define IXGBE_PCIE_MSIX_82599_CAPS 0x72 2312238149Sjfv#define IXGBE_MAX_MSIX_VECTORS_82599 0x40 2313230775Sjfv#define IXGBE_PCIE_MSIX_82598_CAPS 0x62 2314238149Sjfv#define IXGBE_MAX_MSIX_VECTORS_82598 0x13 2315230775Sjfv 2316190873Sjfv/* MSI-X capability fields masks */ 2317230775Sjfv#define IXGBE_PCIE_MSIX_TBL_SZ_MASK 0x7FF 2318190873Sjfv 2319172043Sjfv/* Legacy EEPROM word offsets */ 2320230775Sjfv#define IXGBE_ISCSI_BOOT_CAPS 0x0033 2321230775Sjfv#define IXGBE_ISCSI_SETUP_PORT_0 0x0030 2322230775Sjfv#define IXGBE_ISCSI_SETUP_PORT_1 0x0034 2323172043Sjfv 2324171384Sjfv/* EEPROM Commands - SPI */ 2325230775Sjfv#define IXGBE_EEPROM_MAX_RETRY_SPI 5000 /* Max wait 5ms for RDY signal */ 2326230775Sjfv#define IXGBE_EEPROM_STATUS_RDY_SPI 0x01 2327230775Sjfv#define IXGBE_EEPROM_READ_OPCODE_SPI 0x03 /* EEPROM read opcode */ 2328230775Sjfv#define IXGBE_EEPROM_WRITE_OPCODE_SPI 0x02 /* EEPROM write opcode */ 2329230775Sjfv#define IXGBE_EEPROM_A8_OPCODE_SPI 0x08 /* opcode bit-3 = addr bit-8 */ 2330230775Sjfv#define IXGBE_EEPROM_WREN_OPCODE_SPI 0x06 /* EEPROM set Write Ena latch */ 2331179055Sjfv/* EEPROM reset Write Enable latch */ 2332230775Sjfv#define IXGBE_EEPROM_WRDI_OPCODE_SPI 0x04 2333230775Sjfv#define IXGBE_EEPROM_RDSR_OPCODE_SPI 0x05 /* EEPROM read Status reg */ 2334230775Sjfv#define IXGBE_EEPROM_WRSR_OPCODE_SPI 0x01 /* EEPROM write Status reg */ 2335230775Sjfv#define IXGBE_EEPROM_ERASE4K_OPCODE_SPI 0x20 /* EEPROM ERASE 4KB */ 2336230775Sjfv#define IXGBE_EEPROM_ERASE64K_OPCODE_SPI 0xD8 /* EEPROM ERASE 64KB */ 2337230775Sjfv#define IXGBE_EEPROM_ERASE256_OPCODE_SPI 0xDB /* EEPROM ERASE 256B */ 2338171384Sjfv 2339171384Sjfv/* EEPROM Read Register */ 2340230775Sjfv#define IXGBE_EEPROM_RW_REG_DATA 16 /* data offset in EEPROM read reg */ 2341230775Sjfv#define IXGBE_EEPROM_RW_REG_DONE 2 /* Offset to READ done bit */ 2342230775Sjfv#define IXGBE_EEPROM_RW_REG_START 1 /* First bit to start operation */ 2343230775Sjfv#define IXGBE_EEPROM_RW_ADDR_SHIFT 2 /* Shift to the address bits */ 2344230775Sjfv#define IXGBE_NVM_POLL_WRITE 1 /* Flag for polling for wr complete */ 2345230775Sjfv#define IXGBE_NVM_POLL_READ 0 /* Flag for polling for rd complete */ 2346171384Sjfv 2347283620Serj#define NVM_INIT_CTRL_3 0x38 2348283620Serj#define NVM_INIT_CTRL_3_LPLU 0x8 2349283620Serj#define NVM_INIT_CTRL_3_D10GMP_PORT0 0x40 2350283620Serj#define NVM_INIT_CTRL_3_D10GMP_PORT1 0x100 2351283620Serj 2352230775Sjfv#define IXGBE_ETH_LENGTH_OF_ADDRESS 6 2353171384Sjfv 2354230775Sjfv#define IXGBE_EEPROM_PAGE_SIZE_MAX 128 2355247822Sjfv#define IXGBE_EEPROM_RD_BUFFER_MAX_COUNT 256 /* words rd in burst */ 2356230775Sjfv#define IXGBE_EEPROM_WR_BUFFER_MAX_COUNT 256 /* words wr in burst */ 2357251964Sjfv#define IXGBE_EEPROM_CTRL_2 1 /* EEPROM CTRL word 2 */ 2358251964Sjfv#define IXGBE_EEPROM_CCD_BIT 2 2359230775Sjfv 2360171384Sjfv#ifndef IXGBE_EEPROM_GRANT_ATTEMPTS 2361230775Sjfv#define IXGBE_EEPROM_GRANT_ATTEMPTS 1000 /* EEPROM attempts to gain grant */ 2362171384Sjfv#endif 2363171384Sjfv 2364200239Sjfv/* Number of 5 microseconds we wait for EERD read and 2365200239Sjfv * EERW write to complete */ 2366230775Sjfv#define IXGBE_EERD_EEWR_ATTEMPTS 100000 2367171384Sjfv 2368200239Sjfv/* # attempts we wait for flush update to complete */ 2369230775Sjfv#define IXGBE_FLUDONE_ATTEMPTS 20000 2370200239Sjfv 2371230775Sjfv#define IXGBE_PCIE_CTRL2 0x5 /* PCIe Control 2 Offset */ 2372230775Sjfv#define IXGBE_PCIE_CTRL2_DUMMY_ENABLE 0x8 /* Dummy Function Enable */ 2373230775Sjfv#define IXGBE_PCIE_CTRL2_LAN_DISABLE 0x2 /* LAN PCI Disable */ 2374230775Sjfv#define IXGBE_PCIE_CTRL2_DISABLE_SELECT 0x1 /* LAN Disable Select */ 2375194875Sjfv 2376230775Sjfv#define IXGBE_SAN_MAC_ADDR_PORT0_OFFSET 0x0 2377230775Sjfv#define IXGBE_SAN_MAC_ADDR_PORT1_OFFSET 0x3 2378230775Sjfv#define IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP 0x1 2379230775Sjfv#define IXGBE_DEVICE_CAPS_FCOE_OFFLOADS 0x2 2380315333Serj#define IXGBE_DEVICE_CAPS_NO_CROSSTALK_WR (1 << 7) 2381230775Sjfv#define IXGBE_FW_LESM_PARAMETERS_PTR 0x2 2382230775Sjfv#define IXGBE_FW_LESM_STATE_1 0x1 2383230775Sjfv#define IXGBE_FW_LESM_STATE_ENABLED 0x8000 /* LESM Enable bit */ 2384230775Sjfv#define IXGBE_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2385230775Sjfv#define IXGBE_FW_PATCH_VERSION_4 0x7 2386230775Sjfv#define IXGBE_FCOE_IBA_CAPS_BLK_PTR 0x33 /* iSCSI/FCOE block */ 2387230775Sjfv#define IXGBE_FCOE_IBA_CAPS_FCOE 0x20 /* FCOE flags */ 2388230775Sjfv#define IXGBE_ISCSI_FCOE_BLK_PTR 0x17 /* iSCSI/FCOE block */ 2389230775Sjfv#define IXGBE_ISCSI_FCOE_FLAGS_OFFSET 0x0 /* FCOE flags */ 2390230775Sjfv#define IXGBE_ISCSI_FCOE_FLAGS_ENABLE 0x1 /* FCOE flags enable bit */ 2391230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_BLK_PTR 0x27 /* Alt. SAN MAC block */ 2392230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_OFFSET 0x0 /* Alt SAN MAC capability */ 2393230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_PORT0_OFFSET 0x1 /* Alt SAN MAC 0 offset */ 2394230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_PORT1_OFFSET 0x4 /* Alt SAN MAC 1 offset */ 2395230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_WWNN_OFFSET 0x7 /* Alt WWNN prefix offset */ 2396230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_WWPN_OFFSET 0x8 /* Alt WWPN prefix offset */ 2397230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_SANMAC 0x0 /* Alt SAN MAC exists */ 2398230775Sjfv#define IXGBE_ALT_SAN_MAC_ADDR_CAPS_ALTWWN 0x1 /* Alt WWN base exists */ 2399190873Sjfv 2400251964Sjfv/* FW header offset */ 2401251964Sjfv#define IXGBE_X540_FW_PASSTHROUGH_PATCH_CONFIG_PTR 0x4 2402251964Sjfv#define IXGBE_X540_FW_MODULE_MASK 0x7FFF 2403251964Sjfv/* 4KB multiplier */ 2404251964Sjfv#define IXGBE_X540_FW_MODULE_LENGTH 0x1000 2405251964Sjfv/* version word 2 (month & day) */ 2406251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_2 0x5 2407251964Sjfv/* version word 3 (silicon compatibility & year) */ 2408251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_3 0x6 2409251964Sjfv/* version word 4 (major & minor numbers) */ 2410251964Sjfv#define IXGBE_X540_FW_PATCH_VERSION_4 0x7 2411251964Sjfv 2412230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_PORT0_1 0x4 /* WoL supported on ports 0 & 1 */ 2413230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_PORT0 0x8 /* WoL supported on port 0 */ 2414230775Sjfv#define IXGBE_DEVICE_CAPS_WOL_MASK 0xC /* Mask for WoL capabilities */ 2415230775Sjfv 2416171384Sjfv/* PCI Bus Info */ 2417230775Sjfv#define IXGBE_PCI_DEVICE_STATUS 0xAA 2418230775Sjfv#define IXGBE_PCI_DEVICE_STATUS_TRANSACTION_PENDING 0x0020 2419230775Sjfv#define IXGBE_PCI_LINK_STATUS 0xB2 2420230775Sjfv#define IXGBE_PCI_DEVICE_CONTROL2 0xC8 2421230775Sjfv#define IXGBE_PCI_LINK_WIDTH 0x3F0 2422230775Sjfv#define IXGBE_PCI_LINK_WIDTH_1 0x10 2423230775Sjfv#define IXGBE_PCI_LINK_WIDTH_2 0x20 2424230775Sjfv#define IXGBE_PCI_LINK_WIDTH_4 0x40 2425230775Sjfv#define IXGBE_PCI_LINK_WIDTH_8 0x80 2426230775Sjfv#define IXGBE_PCI_LINK_SPEED 0xF 2427230775Sjfv#define IXGBE_PCI_LINK_SPEED_2500 0x1 2428230775Sjfv#define IXGBE_PCI_LINK_SPEED_5000 0x2 2429238149Sjfv#define IXGBE_PCI_LINK_SPEED_8000 0x3 2430230775Sjfv#define IXGBE_PCI_HEADER_TYPE_REGISTER 0x0E 2431230775Sjfv#define IXGBE_PCI_HEADER_TYPE_MULTIFUNC 0x80 2432230775Sjfv#define IXGBE_PCI_DEVICE_CONTROL2_16ms 0x0005 2433171384Sjfv 2434251964Sjfv#define IXGBE_PCIDEVCTRL2_TIMEO_MASK 0xf 2435251964Sjfv#define IXGBE_PCIDEVCTRL2_16_32ms_def 0x0 2436251964Sjfv#define IXGBE_PCIDEVCTRL2_50_100us 0x1 2437251964Sjfv#define IXGBE_PCIDEVCTRL2_1_2ms 0x2 2438251964Sjfv#define IXGBE_PCIDEVCTRL2_16_32ms 0x5 2439251964Sjfv#define IXGBE_PCIDEVCTRL2_65_130ms 0x6 2440251964Sjfv#define IXGBE_PCIDEVCTRL2_260_520ms 0x9 2441251964Sjfv#define IXGBE_PCIDEVCTRL2_1_2s 0xa 2442251964Sjfv#define IXGBE_PCIDEVCTRL2_4_8s 0xd 2443251964Sjfv#define IXGBE_PCIDEVCTRL2_17_34s 0xe 2444251964Sjfv 2445171384Sjfv/* Number of 100 microseconds we wait for PCI Express master disable */ 2446230775Sjfv#define IXGBE_PCI_MASTER_DISABLE_TIMEOUT 800 2447171384Sjfv 2448230775Sjfv/* Check whether address is multicast. This is little-endian specific check.*/ 2449171384Sjfv#define IXGBE_IS_MULTICAST(Address) \ 2450230775Sjfv (bool)(((u8 *)(Address))[0] & ((u8)0x01)) 2451171384Sjfv 2452171384Sjfv/* Check whether an address is broadcast. */ 2453230775Sjfv#define IXGBE_IS_BROADCAST(Address) \ 2454230775Sjfv ((((u8 *)(Address))[0] == ((u8)0xff)) && \ 2455230775Sjfv (((u8 *)(Address))[1] == ((u8)0xff))) 2456171384Sjfv 2457171384Sjfv/* RAH */ 2458230775Sjfv#define IXGBE_RAH_VIND_MASK 0x003C0000 2459230775Sjfv#define IXGBE_RAH_VIND_SHIFT 18 2460230775Sjfv#define IXGBE_RAH_AV 0x80000000 2461230775Sjfv#define IXGBE_CLEAR_VMDQ_ALL 0xFFFFFFFF 2462171384Sjfv 2463171384Sjfv/* Header split receive */ 2464230775Sjfv#define IXGBE_RFCTL_ISCSI_DIS 0x00000001 2465230775Sjfv#define IXGBE_RFCTL_ISCSI_DWC_MASK 0x0000003E 2466230775Sjfv#define IXGBE_RFCTL_ISCSI_DWC_SHIFT 1 2467283620Serj#define IXGBE_RFCTL_RSC_DIS 0x00000020 2468230775Sjfv#define IXGBE_RFCTL_NFSW_DIS 0x00000040 2469230775Sjfv#define IXGBE_RFCTL_NFSR_DIS 0x00000080 2470230775Sjfv#define IXGBE_RFCTL_NFS_VER_MASK 0x00000300 2471230775Sjfv#define IXGBE_RFCTL_NFS_VER_SHIFT 8 2472230775Sjfv#define IXGBE_RFCTL_NFS_VER_2 0 2473230775Sjfv#define IXGBE_RFCTL_NFS_VER_3 1 2474230775Sjfv#define IXGBE_RFCTL_NFS_VER_4 2 2475230775Sjfv#define IXGBE_RFCTL_IPV6_DIS 0x00000400 2476230775Sjfv#define IXGBE_RFCTL_IPV6_XSUM_DIS 0x00000800 2477230775Sjfv#define IXGBE_RFCTL_IPFRSP_DIS 0x00004000 2478230775Sjfv#define IXGBE_RFCTL_IPV6_EX_DIS 0x00010000 2479230775Sjfv#define IXGBE_RFCTL_NEW_IPV6_EXT_DIS 0x00020000 2480171384Sjfv 2481171384Sjfv/* Transmit Config masks */ 2482230775Sjfv#define IXGBE_TXDCTL_ENABLE 0x02000000 /* Ena specific Tx Queue */ 2483230775Sjfv#define IXGBE_TXDCTL_SWFLSH 0x04000000 /* Tx Desc. wr-bk flushing */ 2484230775Sjfv#define IXGBE_TXDCTL_WTHRESH_SHIFT 16 /* shift to WTHRESH bits */ 2485171384Sjfv/* Enable short packet padding to 64 bytes */ 2486230775Sjfv#define IXGBE_TX_PAD_ENABLE 0x00000400 2487230775Sjfv#define IXGBE_JUMBO_FRAME_ENABLE 0x00000004 /* Allow jumbo frames */ 2488171384Sjfv/* This allows for 16K packets + 4k for vlan */ 2489230775Sjfv#define IXGBE_MAX_FRAME_SZ 0x40040000 2490171384Sjfv 2491230775Sjfv#define IXGBE_TDWBAL_HEAD_WB_ENABLE 0x1 /* Tx head write-back enable */ 2492230775Sjfv#define IXGBE_TDWBAL_SEQNUM_WB_ENABLE 0x2 /* Tx seq# write-back enable */ 2493171384Sjfv 2494171384Sjfv/* Receive Config masks */ 2495230775Sjfv#define IXGBE_RXCTRL_RXEN 0x00000001 /* Enable Receiver */ 2496230775Sjfv#define IXGBE_RXCTRL_DMBYPS 0x00000002 /* Desc Monitor Bypass */ 2497230775Sjfv#define IXGBE_RXDCTL_ENABLE 0x02000000 /* Ena specific Rx Queue */ 2498230775Sjfv#define IXGBE_RXDCTL_SWFLSH 0x04000000 /* Rx Desc wr-bk flushing */ 2499230775Sjfv#define IXGBE_RXDCTL_RLPMLMASK 0x00003FFF /* X540 supported only */ 2500230775Sjfv#define IXGBE_RXDCTL_RLPML_EN 0x00008000 2501230775Sjfv#define IXGBE_RXDCTL_VME 0x40000000 /* VLAN mode enable */ 2502171384Sjfv 2503238149Sjfv#define IXGBE_TSAUXC_EN_CLK 0x00000004 2504238149Sjfv#define IXGBE_TSAUXC_SYNCLK 0x00000008 2505238149Sjfv#define IXGBE_TSAUXC_SDP0_INT 0x00000040 2506283620Serj#define IXGBE_TSAUXC_EN_TT0 0x00000001 2507283620Serj#define IXGBE_TSAUXC_EN_TT1 0x00000002 2508283620Serj#define IXGBE_TSAUXC_ST0 0x00000010 2509283620Serj#define IXGBE_TSAUXC_DISABLE_SYSTIME 0x80000000 2510238149Sjfv 2511283620Serj#define IXGBE_TSSDP_TS_SDP0_SEL_MASK 0x000000C0 2512283620Serj#define IXGBE_TSSDP_TS_SDP0_CLK0 0x00000080 2513283620Serj#define IXGBE_TSSDP_TS_SDP0_EN 0x00000100 2514283620Serj 2515230775Sjfv#define IXGBE_TSYNCTXCTL_VALID 0x00000001 /* Tx timestamp valid */ 2516230775Sjfv#define IXGBE_TSYNCTXCTL_ENABLED 0x00000010 /* Tx timestamping enabled */ 2517230775Sjfv 2518230775Sjfv#define IXGBE_TSYNCRXCTL_VALID 0x00000001 /* Rx timestamp valid */ 2519230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_MASK 0x0000000E /* Rx type mask */ 2520230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L2_V2 0x00 2521230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L4_V1 0x02 2522230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_L2_L4_V2 0x04 2523283620Serj#define IXGBE_TSYNCRXCTL_TYPE_ALL 0x08 2524230775Sjfv#define IXGBE_TSYNCRXCTL_TYPE_EVENT_V2 0x0A 2525230775Sjfv#define IXGBE_TSYNCRXCTL_ENABLED 0x00000010 /* Rx Timestamping enabled */ 2526283620Serj#define IXGBE_TSYNCRXCTL_TSIP_UT_EN 0x00800000 /* Rx Timestamp in Packet */ 2527283620Serj#define IXGBE_TSYNCRXCTL_TSIP_UP_MASK 0xFF000000 /* Rx Timestamp UP Mask */ 2528230775Sjfv 2529283620Serj#define IXGBE_TSIM_SYS_WRAP 0x00000001 2530283620Serj#define IXGBE_TSIM_TXTS 0x00000002 2531283620Serj#define IXGBE_TSIM_TADJ 0x00000080 2532283620Serj 2533283620Serj#define IXGBE_TSICR_SYS_WRAP IXGBE_TSIM_SYS_WRAP 2534283620Serj#define IXGBE_TSICR_TXTS IXGBE_TSIM_TXTS 2535283620Serj#define IXGBE_TSICR_TADJ IXGBE_TSIM_TADJ 2536283620Serj 2537230775Sjfv#define IXGBE_RXMTRL_V1_CTRLT_MASK 0x000000FF 2538230775Sjfv#define IXGBE_RXMTRL_V1_SYNC_MSG 0x00 2539230775Sjfv#define IXGBE_RXMTRL_V1_DELAY_REQ_MSG 0x01 2540230775Sjfv#define IXGBE_RXMTRL_V1_FOLLOWUP_MSG 0x02 2541230775Sjfv#define IXGBE_RXMTRL_V1_DELAY_RESP_MSG 0x03 2542230775Sjfv#define IXGBE_RXMTRL_V1_MGMT_MSG 0x04 2543230775Sjfv 2544230775Sjfv#define IXGBE_RXMTRL_V2_MSGID_MASK 0x0000FF00 2545230775Sjfv#define IXGBE_RXMTRL_V2_SYNC_MSG 0x0000 2546230775Sjfv#define IXGBE_RXMTRL_V2_DELAY_REQ_MSG 0x0100 2547230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_REQ_MSG 0x0200 2548230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_RESP_MSG 0x0300 2549230775Sjfv#define IXGBE_RXMTRL_V2_FOLLOWUP_MSG 0x0800 2550230775Sjfv#define IXGBE_RXMTRL_V2_DELAY_RESP_MSG 0x0900 2551230775Sjfv#define IXGBE_RXMTRL_V2_PDELAY_FOLLOWUP_MSG 0x0A00 2552230775Sjfv#define IXGBE_RXMTRL_V2_ANNOUNCE_MSG 0x0B00 2553230775Sjfv#define IXGBE_RXMTRL_V2_SIGNALLING_MSG 0x0C00 2554230775Sjfv#define IXGBE_RXMTRL_V2_MGMT_MSG 0x0D00 2555230775Sjfv 2556230775Sjfv#define IXGBE_FCTRL_SBP 0x00000002 /* Store Bad Packet */ 2557230775Sjfv#define IXGBE_FCTRL_MPE 0x00000100 /* Multicast Promiscuous Ena*/ 2558230775Sjfv#define IXGBE_FCTRL_UPE 0x00000200 /* Unicast Promiscuous Ena */ 2559230775Sjfv#define IXGBE_FCTRL_BAM 0x00000400 /* Broadcast Accept Mode */ 2560230775Sjfv#define IXGBE_FCTRL_PMCF 0x00001000 /* Pass MAC Control Frames */ 2561230775Sjfv#define IXGBE_FCTRL_DPF 0x00002000 /* Discard Pause Frame */ 2562179055Sjfv/* Receive Priority Flow Control Enable */ 2563230775Sjfv#define IXGBE_FCTRL_RPFCE 0x00004000 2564230775Sjfv#define IXGBE_FCTRL_RFCE 0x00008000 /* Receive Flow Control Ena */ 2565230775Sjfv#define IXGBE_MFLCN_PMCF 0x00000001 /* Pass MAC Control Frames */ 2566230775Sjfv#define IXGBE_MFLCN_DPF 0x00000002 /* Discard Pause Frame */ 2567230775Sjfv#define IXGBE_MFLCN_RPFCE 0x00000004 /* Receive Priority FC Enable */ 2568230775Sjfv#define IXGBE_MFLCN_RFCE 0x00000008 /* Receive FC Enable */ 2569238149Sjfv#define IXGBE_MFLCN_RPFCE_MASK 0x00000FF4 /* Rx Priority FC bitmap mask */ 2570230775Sjfv#define IXGBE_MFLCN_RPFCE_SHIFT 4 /* Rx Priority FC bitmap shift */ 2571171384Sjfv 2572171384Sjfv/* Multiple Receive Queue Control */ 2573230775Sjfv#define IXGBE_MRQC_RSSEN 0x00000001 /* RSS Enable */ 2574230775Sjfv#define IXGBE_MRQC_MRQE_MASK 0xF /* Bits 3:0 */ 2575230775Sjfv#define IXGBE_MRQC_RT8TCEN 0x00000002 /* 8 TC no RSS */ 2576230775Sjfv#define IXGBE_MRQC_RT4TCEN 0x00000003 /* 4 TC no RSS */ 2577230775Sjfv#define IXGBE_MRQC_RTRSS8TCEN 0x00000004 /* 8 TC w/ RSS */ 2578230775Sjfv#define IXGBE_MRQC_RTRSS4TCEN 0x00000005 /* 4 TC w/ RSS */ 2579230775Sjfv#define IXGBE_MRQC_VMDQEN 0x00000008 /* VMDq2 64 pools no RSS */ 2580230775Sjfv#define IXGBE_MRQC_VMDQRSS32EN 0x0000000A /* VMDq2 32 pools w/ RSS */ 2581230775Sjfv#define IXGBE_MRQC_VMDQRSS64EN 0x0000000B /* VMDq2 64 pools w/ RSS */ 2582230775Sjfv#define IXGBE_MRQC_VMDQRT8TCEN 0x0000000C /* VMDq2/RT 16 pool 8 TC */ 2583230775Sjfv#define IXGBE_MRQC_VMDQRT4TCEN 0x0000000D /* VMDq2/RT 32 pool 4 TC */ 2584230775Sjfv#define IXGBE_MRQC_RSS_FIELD_MASK 0xFFFF0000 2585230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4_TCP 0x00010000 2586230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4 0x00020000 2587171384Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_TCP 0x00040000 2588230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX 0x00080000 2589230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6 0x00100000 2590230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_TCP 0x00200000 2591230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV4_UDP 0x00400000 2592230775Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_UDP 0x00800000 2593171384Sjfv#define IXGBE_MRQC_RSS_FIELD_IPV6_EX_UDP 0x01000000 2594283620Serj#define IXGBE_MRQC_MULTIPLE_RSS 0x00002000 2595230775Sjfv#define IXGBE_MRQC_L3L4TXSWEN 0x00008000 2596171384Sjfv 2597190873Sjfv/* Queue Drop Enable */ 2598230775Sjfv#define IXGBE_QDE_ENABLE 0x00000001 2599283620Serj#define IXGBE_QDE_HIDE_VLAN 0x00000002 2600230775Sjfv#define IXGBE_QDE_IDX_MASK 0x00007F00 2601230775Sjfv#define IXGBE_QDE_IDX_SHIFT 8 2602230775Sjfv#define IXGBE_QDE_WRITE 0x00010000 2603230775Sjfv#define IXGBE_QDE_READ 0x00020000 2604190873Sjfv 2605230775Sjfv#define IXGBE_TXD_POPTS_IXSM 0x01 /* Insert IP checksum */ 2606230775Sjfv#define IXGBE_TXD_POPTS_TXSM 0x02 /* Insert TCP/UDP checksum */ 2607230775Sjfv#define IXGBE_TXD_CMD_EOP 0x01000000 /* End of Packet */ 2608230775Sjfv#define IXGBE_TXD_CMD_IFCS 0x02000000 /* Insert FCS (Ethernet CRC) */ 2609230775Sjfv#define IXGBE_TXD_CMD_IC 0x04000000 /* Insert Checksum */ 2610230775Sjfv#define IXGBE_TXD_CMD_RS 0x08000000 /* Report Status */ 2611230775Sjfv#define IXGBE_TXD_CMD_DEXT 0x20000000 /* Desc extension (0 = legacy) */ 2612230775Sjfv#define IXGBE_TXD_CMD_VLE 0x40000000 /* Add VLAN tag */ 2613230775Sjfv#define IXGBE_TXD_STAT_DD 0x00000001 /* Descriptor Done */ 2614171384Sjfv 2615230775Sjfv#define IXGBE_RXDADV_IPSEC_STATUS_SECP 0x00020000 2616230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_PROTOCOL 0x08000000 2617230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_INVALID_LENGTH 0x10000000 2618230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_AUTH_FAILED 0x18000000 2619230775Sjfv#define IXGBE_RXDADV_IPSEC_ERROR_BIT_MASK 0x18000000 2620190873Sjfv/* Multiple Transmit Queue Command Register */ 2621230775Sjfv#define IXGBE_MTQC_RT_ENA 0x1 /* DCB Enable */ 2622230775Sjfv#define IXGBE_MTQC_VT_ENA 0x2 /* VMDQ2 Enable */ 2623230775Sjfv#define IXGBE_MTQC_64Q_1PB 0x0 /* 64 queues 1 pack buffer */ 2624230775Sjfv#define IXGBE_MTQC_32VF 0x8 /* 4 TX Queues per pool w/32VF's */ 2625230775Sjfv#define IXGBE_MTQC_64VF 0x4 /* 2 TX Queues per pool w/64VF's */ 2626230775Sjfv#define IXGBE_MTQC_4TC_4TQ 0x8 /* 4 TC if RT_ENA and VT_ENA */ 2627230775Sjfv#define IXGBE_MTQC_8TC_8TQ 0xC /* 8 TC if RT_ENA or 8 TQ if VT_ENA */ 2628190873Sjfv 2629171384Sjfv/* Receive Descriptor bit definitions */ 2630230775Sjfv#define IXGBE_RXD_STAT_DD 0x01 /* Descriptor Done */ 2631230775Sjfv#define IXGBE_RXD_STAT_EOP 0x02 /* End of Packet */ 2632230775Sjfv#define IXGBE_RXD_STAT_FLM 0x04 /* FDir Match */ 2633230775Sjfv#define IXGBE_RXD_STAT_VP 0x08 /* IEEE VLAN Packet */ 2634230775Sjfv#define IXGBE_RXDADV_NEXTP_MASK 0x000FFFF0 /* Next Descriptor Index */ 2635230775Sjfv#define IXGBE_RXDADV_NEXTP_SHIFT 0x00000004 2636230775Sjfv#define IXGBE_RXD_STAT_UDPCS 0x10 /* UDP xsum calculated */ 2637230775Sjfv#define IXGBE_RXD_STAT_L4CS 0x20 /* L4 xsum calculated */ 2638230775Sjfv#define IXGBE_RXD_STAT_IPCS 0x40 /* IP xsum calculated */ 2639230775Sjfv#define IXGBE_RXD_STAT_PIF 0x80 /* passed in-exact filter */ 2640230775Sjfv#define IXGBE_RXD_STAT_CRCV 0x100 /* Speculative CRC Valid */ 2641283620Serj#define IXGBE_RXD_STAT_OUTERIPCS 0x100 /* Cloud IP xsum calculated */ 2642230775Sjfv#define IXGBE_RXD_STAT_VEXT 0x200 /* 1st VLAN found */ 2643230775Sjfv#define IXGBE_RXD_STAT_UDPV 0x400 /* Valid UDP checksum */ 2644230775Sjfv#define IXGBE_RXD_STAT_DYNINT 0x800 /* Pkt caused INT via DYNINT */ 2645230775Sjfv#define IXGBE_RXD_STAT_LLINT 0x800 /* Pkt caused Low Latency Interrupt */ 2646283620Serj#define IXGBE_RXD_STAT_TSIP 0x08000 /* Time Stamp in packet buffer */ 2647230775Sjfv#define IXGBE_RXD_STAT_TS 0x10000 /* Time Stamp */ 2648230775Sjfv#define IXGBE_RXD_STAT_SECP 0x20000 /* Security Processing */ 2649230775Sjfv#define IXGBE_RXD_STAT_LB 0x40000 /* Loopback Status */ 2650230775Sjfv#define IXGBE_RXD_STAT_ACK 0x8000 /* ACK Packet indication */ 2651230775Sjfv#define IXGBE_RXD_ERR_CE 0x01 /* CRC Error */ 2652230775Sjfv#define IXGBE_RXD_ERR_LE 0x02 /* Length Error */ 2653230775Sjfv#define IXGBE_RXD_ERR_PE 0x08 /* Packet Error */ 2654230775Sjfv#define IXGBE_RXD_ERR_OSE 0x10 /* Oversize Error */ 2655230775Sjfv#define IXGBE_RXD_ERR_USE 0x20 /* Undersize Error */ 2656230775Sjfv#define IXGBE_RXD_ERR_TCPE 0x40 /* TCP/UDP Checksum Error */ 2657230775Sjfv#define IXGBE_RXD_ERR_IPE 0x80 /* IP Checksum Error */ 2658230775Sjfv#define IXGBE_RXDADV_ERR_MASK 0xfff00000 /* RDESC.ERRORS mask */ 2659230775Sjfv#define IXGBE_RXDADV_ERR_SHIFT 20 /* RDESC.ERRORS shift */ 2660283620Serj#define IXGBE_RXDADV_ERR_OUTERIPER 0x04000000 /* CRC IP Header error */ 2661230775Sjfv#define IXGBE_RXDADV_ERR_RXE 0x20000000 /* Any MAC Error */ 2662283620Serj#define IXGBE_RXDADV_ERR_FCEOFE 0x80000000 /* FCEOFe/IPE */ 2663230775Sjfv#define IXGBE_RXDADV_ERR_FCERR 0x00700000 /* FCERR/FDIRERR */ 2664230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_LEN 0x00100000 /* FDIR Length error */ 2665230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_DROP 0x00200000 /* FDIR Drop error */ 2666230775Sjfv#define IXGBE_RXDADV_ERR_FDIR_COLL 0x00400000 /* FDIR Collision error */ 2667230775Sjfv#define IXGBE_RXDADV_ERR_HBO 0x00800000 /*Header Buffer Overflow */ 2668230775Sjfv#define IXGBE_RXDADV_ERR_CE 0x01000000 /* CRC Error */ 2669230775Sjfv#define IXGBE_RXDADV_ERR_LE 0x02000000 /* Length Error */ 2670230775Sjfv#define IXGBE_RXDADV_ERR_PE 0x08000000 /* Packet Error */ 2671230775Sjfv#define IXGBE_RXDADV_ERR_OSE 0x10000000 /* Oversize Error */ 2672230775Sjfv#define IXGBE_RXDADV_ERR_USE 0x20000000 /* Undersize Error */ 2673230775Sjfv#define IXGBE_RXDADV_ERR_TCPE 0x40000000 /* TCP/UDP Checksum Error */ 2674230775Sjfv#define IXGBE_RXDADV_ERR_IPE 0x80000000 /* IP Checksum Error */ 2675230775Sjfv#define IXGBE_RXD_VLAN_ID_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 2676230775Sjfv#define IXGBE_RXD_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 2677230775Sjfv#define IXGBE_RXD_PRI_SHIFT 13 2678230775Sjfv#define IXGBE_RXD_CFI_MASK 0x1000 /* CFI is bit 12 */ 2679230775Sjfv#define IXGBE_RXD_CFI_SHIFT 12 2680171384Sjfv 2681230775Sjfv#define IXGBE_RXDADV_STAT_DD IXGBE_RXD_STAT_DD /* Done */ 2682230775Sjfv#define IXGBE_RXDADV_STAT_EOP IXGBE_RXD_STAT_EOP /* End of Packet */ 2683230775Sjfv#define IXGBE_RXDADV_STAT_FLM IXGBE_RXD_STAT_FLM /* FDir Match */ 2684230775Sjfv#define IXGBE_RXDADV_STAT_VP IXGBE_RXD_STAT_VP /* IEEE VLAN Pkt */ 2685230775Sjfv#define IXGBE_RXDADV_STAT_MASK 0x000fffff /* Stat/NEXTP: bit 0-19 */ 2686230775Sjfv#define IXGBE_RXDADV_STAT_FCEOFS 0x00000040 /* FCoE EOF/SOF Stat */ 2687230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT 0x00000030 /* FCoE Pkt Stat */ 2688230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_NOMTCH 0x00000000 /* 00: No Ctxt Match */ 2689230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_NODDP 0x00000010 /* 01: Ctxt w/o DDP */ 2690230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_FCPRSP 0x00000020 /* 10: Recv. FCP_RSP */ 2691230775Sjfv#define IXGBE_RXDADV_STAT_FCSTAT_DDP 0x00000030 /* 11: Ctxt w/ DDP */ 2692230775Sjfv#define IXGBE_RXDADV_STAT_TS 0x00010000 /* IEEE1588 Time Stamp */ 2693283620Serj#define IXGBE_RXDADV_STAT_TSIP 0x00008000 /* Time Stamp in packet buffer */ 2694185352Sjfv 2695190873Sjfv/* PSRTYPE bit definitions */ 2696230775Sjfv#define IXGBE_PSRTYPE_TCPHDR 0x00000010 2697230775Sjfv#define IXGBE_PSRTYPE_UDPHDR 0x00000020 2698230775Sjfv#define IXGBE_PSRTYPE_IPV4HDR 0x00000100 2699230775Sjfv#define IXGBE_PSRTYPE_IPV6HDR 0x00000200 2700230775Sjfv#define IXGBE_PSRTYPE_L2HDR 0x00001000 2701190873Sjfv 2702171384Sjfv/* SRRCTL bit definitions */ 2703230775Sjfv#define IXGBE_SRRCTL_BSIZEPKT_SHIFT 10 /* so many KBs */ 2704283620Serj#define IXGBE_SRRCTL_BSIZEHDRSIZE_SHIFT 2 /* 64byte resolution (>> 6) 2705283620Serj * + at bit 8 offset (<< 8) 2706283620Serj * = (<< 2) 2707283620Serj */ 2708230775Sjfv#define IXGBE_SRRCTL_RDMTS_SHIFT 22 2709230775Sjfv#define IXGBE_SRRCTL_RDMTS_MASK 0x01C00000 2710230775Sjfv#define IXGBE_SRRCTL_DROP_EN 0x10000000 2711230775Sjfv#define IXGBE_SRRCTL_BSIZEPKT_MASK 0x0000007F 2712230775Sjfv#define IXGBE_SRRCTL_BSIZEHDR_MASK 0x00003F00 2713230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_LEGACY 0x00000000 2714171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_ADV_ONEBUF 0x02000000 2715230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT 0x04000000 2716171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_REPLICATION_LARGE_PKT 0x08000000 2717171384Sjfv#define IXGBE_SRRCTL_DESCTYPE_HDR_SPLIT_ALWAYS 0x0A000000 2718230775Sjfv#define IXGBE_SRRCTL_DESCTYPE_MASK 0x0E000000 2719171384Sjfv 2720230775Sjfv#define IXGBE_RXDPS_HDRSTAT_HDRSP 0x00008000 2721230775Sjfv#define IXGBE_RXDPS_HDRSTAT_HDRLEN_MASK 0x000003FF 2722171384Sjfv 2723230775Sjfv#define IXGBE_RXDADV_RSSTYPE_MASK 0x0000000F 2724230775Sjfv#define IXGBE_RXDADV_PKTTYPE_MASK 0x0000FFF0 2725230775Sjfv#define IXGBE_RXDADV_PKTTYPE_MASK_EX 0x0001FFF0 2726230775Sjfv#define IXGBE_RXDADV_HDRBUFLEN_MASK 0x00007FE0 2727230775Sjfv#define IXGBE_RXDADV_RSCCNT_MASK 0x001E0000 2728230775Sjfv#define IXGBE_RXDADV_RSCCNT_SHIFT 17 2729230775Sjfv#define IXGBE_RXDADV_HDRBUFLEN_SHIFT 5 2730230775Sjfv#define IXGBE_RXDADV_SPLITHEADER_EN 0x00001000 2731230775Sjfv#define IXGBE_RXDADV_SPH 0x8000 2732171384Sjfv 2733171384Sjfv/* RSS Hash results */ 2734230775Sjfv#define IXGBE_RXDADV_RSSTYPE_NONE 0x00000000 2735230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4_TCP 0x00000001 2736230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4 0x00000002 2737230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP 0x00000003 2738230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_EX 0x00000004 2739230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6 0x00000005 2740171384Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_TCP_EX 0x00000006 2741230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV4_UDP 0x00000007 2742230775Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP 0x00000008 2743171384Sjfv#define IXGBE_RXDADV_RSSTYPE_IPV6_UDP_EX 0x00000009 2744171384Sjfv 2745171384Sjfv/* RSS Packet Types as indicated in the receive descriptor. */ 2746230775Sjfv#define IXGBE_RXDADV_PKTTYPE_NONE 0x00000000 2747230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV4 0x00000010 /* IPv4 hdr present */ 2748230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV4_EX 0x00000020 /* IPv4 hdr + extensions */ 2749230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV6 0x00000040 /* IPv6 hdr present */ 2750230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPV6_EX 0x00000080 /* IPv6 hdr + extensions */ 2751230775Sjfv#define IXGBE_RXDADV_PKTTYPE_TCP 0x00000100 /* TCP hdr present */ 2752230775Sjfv#define IXGBE_RXDADV_PKTTYPE_UDP 0x00000200 /* UDP hdr present */ 2753230775Sjfv#define IXGBE_RXDADV_PKTTYPE_SCTP 0x00000400 /* SCTP hdr present */ 2754230775Sjfv#define IXGBE_RXDADV_PKTTYPE_NFS 0x00000800 /* NFS hdr present */ 2755315333Serj#define IXGBE_RXDADV_PKTTYPE_GENEVE 0x00000800 /* GENEVE hdr present */ 2756283620Serj#define IXGBE_RXDADV_PKTTYPE_VXLAN 0x00000800 /* VXLAN hdr present */ 2757283620Serj#define IXGBE_RXDADV_PKTTYPE_TUNNEL 0x00010000 /* Tunnel type */ 2758230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPSEC_ESP 0x00001000 /* IPSec ESP */ 2759230775Sjfv#define IXGBE_RXDADV_PKTTYPE_IPSEC_AH 0x00002000 /* IPSec AH */ 2760230775Sjfv#define IXGBE_RXDADV_PKTTYPE_LINKSEC 0x00004000 /* LinkSec Encap */ 2761230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF 0x00008000 /* PKTTYPE is ETQF index */ 2762230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF_MASK 0x00000070 /* ETQF has 8 indices */ 2763230775Sjfv#define IXGBE_RXDADV_PKTTYPE_ETQF_SHIFT 4 /* Right-shift 4 bits */ 2764190873Sjfv 2765190873Sjfv/* Security Processing bit Indication */ 2766230775Sjfv#define IXGBE_RXDADV_LNKSEC_STATUS_SECP 0x00020000 2767230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_NO_SA_MATCH 0x08000000 2768230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_REPLAY_ERROR 0x10000000 2769230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_BIT_MASK 0x18000000 2770230775Sjfv#define IXGBE_RXDADV_LNKSEC_ERROR_BAD_SIG 0x18000000 2771190873Sjfv 2772171384Sjfv/* Masks to determine if packets should be dropped due to frame errors */ 2773171384Sjfv#define IXGBE_RXD_ERR_FRAME_ERR_MASK ( \ 2774230775Sjfv IXGBE_RXD_ERR_CE | \ 2775230775Sjfv IXGBE_RXD_ERR_LE | \ 2776230775Sjfv IXGBE_RXD_ERR_PE | \ 2777230775Sjfv IXGBE_RXD_ERR_OSE | \ 2778230775Sjfv IXGBE_RXD_ERR_USE) 2779171384Sjfv 2780171384Sjfv#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK ( \ 2781230775Sjfv IXGBE_RXDADV_ERR_CE | \ 2782230775Sjfv IXGBE_RXDADV_ERR_LE | \ 2783230775Sjfv IXGBE_RXDADV_ERR_PE | \ 2784230775Sjfv IXGBE_RXDADV_ERR_OSE | \ 2785230775Sjfv IXGBE_RXDADV_ERR_USE) 2786171384Sjfv 2787230775Sjfv#define IXGBE_RXDADV_ERR_FRAME_ERR_MASK_82599 IXGBE_RXDADV_ERR_RXE 2788230775Sjfv 2789171384Sjfv/* Multicast bit mask */ 2790230775Sjfv#define IXGBE_MCSTCTRL_MFE 0x4 2791171384Sjfv 2792171384Sjfv/* Number of Transmit and Receive Descriptors must be a multiple of 8 */ 2793230775Sjfv#define IXGBE_REQ_TX_DESCRIPTOR_MULTIPLE 8 2794230775Sjfv#define IXGBE_REQ_RX_DESCRIPTOR_MULTIPLE 8 2795230775Sjfv#define IXGBE_REQ_TX_BUFFER_GRANULARITY 1024 2796171384Sjfv 2797171384Sjfv/* Vlan-specific macros */ 2798230775Sjfv#define IXGBE_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID in lower 12 bits */ 2799230775Sjfv#define IXGBE_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority in upper 3 bits */ 2800230775Sjfv#define IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority in upper 3 of 16 */ 2801230775Sjfv#define IXGBE_TX_DESC_SPECIAL_PRI_SHIFT IXGBE_RX_DESC_SPECIAL_PRI_SHIFT 2802171384Sjfv 2803194875Sjfv/* SR-IOV specific macros */ 2804230775Sjfv#define IXGBE_MBVFICR_INDEX(vf_number) (vf_number >> 4) 2805230775Sjfv#define IXGBE_MBVFICR(_i) (0x00710 + ((_i) * 4)) 2806230775Sjfv#define IXGBE_VFLRE(_i) (((_i & 1) ? 0x001C0 : 0x00600)) 2807230775Sjfv#define IXGBE_VFLREC(_i) (0x00700 + ((_i) * 4)) 2808283620Serj/* Translated register #defines */ 2809283620Serj#define IXGBE_PVFCTRL(P) (0x00300 + (4 * (P))) 2810283620Serj#define IXGBE_PVFSTATUS(P) (0x00008 + (0 * (P))) 2811283620Serj#define IXGBE_PVFLINKS(P) (0x042A4 + (0 * (P))) 2812283620Serj#define IXGBE_PVFRTIMER(P) (0x00048 + (0 * (P))) 2813283620Serj#define IXGBE_PVFMAILBOX(P) (0x04C00 + (4 * (P))) 2814283620Serj#define IXGBE_PVFRXMEMWRAP(P) (0x03190 + (0 * (P))) 2815283620Serj#define IXGBE_PVTEICR(P) (0x00B00 + (4 * (P))) 2816283620Serj#define IXGBE_PVTEICS(P) (0x00C00 + (4 * (P))) 2817283620Serj#define IXGBE_PVTEIMS(P) (0x00D00 + (4 * (P))) 2818283620Serj#define IXGBE_PVTEIMC(P) (0x00E00 + (4 * (P))) 2819283620Serj#define IXGBE_PVTEIAC(P) (0x00F00 + (4 * (P))) 2820283620Serj#define IXGBE_PVTEIAM(P) (0x04D00 + (4 * (P))) 2821283620Serj#define IXGBE_PVTEITR(P) (((P) < 24) ? (0x00820 + ((P) * 4)) : \ 2822283620Serj (0x012300 + (((P) - 24) * 4))) 2823283620Serj#define IXGBE_PVTIVAR(P) (0x12500 + (4 * (P))) 2824283620Serj#define IXGBE_PVTIVAR_MISC(P) (0x04E00 + (4 * (P))) 2825283620Serj#define IXGBE_PVTRSCINT(P) (0x12000 + (4 * (P))) 2826283620Serj#define IXGBE_VFPBACL(P) (0x110C8 + (4 * (P))) 2827283620Serj#define IXGBE_PVFRDBAL(P) ((P < 64) ? (0x01000 + (0x40 * (P))) \ 2828283620Serj : (0x0D000 + (0x40 * ((P) - 64)))) 2829283620Serj#define IXGBE_PVFRDBAH(P) ((P < 64) ? (0x01004 + (0x40 * (P))) \ 2830283620Serj : (0x0D004 + (0x40 * ((P) - 64)))) 2831283620Serj#define IXGBE_PVFRDLEN(P) ((P < 64) ? (0x01008 + (0x40 * (P))) \ 2832283620Serj : (0x0D008 + (0x40 * ((P) - 64)))) 2833283620Serj#define IXGBE_PVFRDH(P) ((P < 64) ? (0x01010 + (0x40 * (P))) \ 2834283620Serj : (0x0D010 + (0x40 * ((P) - 64)))) 2835283620Serj#define IXGBE_PVFRDT(P) ((P < 64) ? (0x01018 + (0x40 * (P))) \ 2836283620Serj : (0x0D018 + (0x40 * ((P) - 64)))) 2837283620Serj#define IXGBE_PVFRXDCTL(P) ((P < 64) ? (0x01028 + (0x40 * (P))) \ 2838283620Serj : (0x0D028 + (0x40 * ((P) - 64)))) 2839283620Serj#define IXGBE_PVFSRRCTL(P) ((P < 64) ? (0x01014 + (0x40 * (P))) \ 2840283620Serj : (0x0D014 + (0x40 * ((P) - 64)))) 2841283620Serj#define IXGBE_PVFPSRTYPE(P) (0x0EA00 + (4 * (P))) 2842283620Serj#define IXGBE_PVFTDBAL(P) (0x06000 + (0x40 * (P))) 2843283620Serj#define IXGBE_PVFTDBAH(P) (0x06004 + (0x40 * (P))) 2844315333Serj#define IXGBE_PVFTDLEN(P) (0x06008 + (0x40 * (P))) 2845283620Serj#define IXGBE_PVFTDH(P) (0x06010 + (0x40 * (P))) 2846283620Serj#define IXGBE_PVFTDT(P) (0x06018 + (0x40 * (P))) 2847283620Serj#define IXGBE_PVFTXDCTL(P) (0x06028 + (0x40 * (P))) 2848283620Serj#define IXGBE_PVFTDWBAL(P) (0x06038 + (0x40 * (P))) 2849283620Serj#define IXGBE_PVFTDWBAH(P) (0x0603C + (0x40 * (P))) 2850283620Serj#define IXGBE_PVFDCA_RXCTRL(P) (((P) < 64) ? (0x0100C + (0x40 * (P))) \ 2851283620Serj : (0x0D00C + (0x40 * ((P) - 64)))) 2852283620Serj#define IXGBE_PVFDCA_TXCTRL(P) (0x0600C + (0x40 * (P))) 2853283620Serj#define IXGBE_PVFGPRC(x) (0x0101C + (0x40 * (x))) 2854283620Serj#define IXGBE_PVFGPTC(x) (0x08300 + (0x04 * (x))) 2855283620Serj#define IXGBE_PVFGORC_LSB(x) (0x01020 + (0x40 * (x))) 2856283620Serj#define IXGBE_PVFGORC_MSB(x) (0x0D020 + (0x40 * (x))) 2857283620Serj#define IXGBE_PVFGOTC_LSB(x) (0x08400 + (0x08 * (x))) 2858283620Serj#define IXGBE_PVFGOTC_MSB(x) (0x08404 + (0x08 * (x))) 2859283620Serj#define IXGBE_PVFMPRC(x) (0x0D01C + (0x40 * (x))) 2860194875Sjfv 2861283620Serj#define IXGBE_PVFTDWBALn(q_per_pool, vf_number, vf_q_index) \ 2862283620Serj (IXGBE_PVFTDWBAL((q_per_pool)*(vf_number) + (vf_q_index))) 2863283620Serj#define IXGBE_PVFTDWBAHn(q_per_pool, vf_number, vf_q_index) \ 2864283620Serj (IXGBE_PVFTDWBAH((q_per_pool)*(vf_number) + (vf_q_index))) 2865283620Serj 2866283620Serj#define IXGBE_PVFTDHn(q_per_pool, vf_number, vf_q_index) \ 2867283620Serj (IXGBE_PVFTDH((q_per_pool)*(vf_number) + (vf_q_index))) 2868283620Serj#define IXGBE_PVFTDTn(q_per_pool, vf_number, vf_q_index) \ 2869283620Serj (IXGBE_PVFTDT((q_per_pool)*(vf_number) + (vf_q_index))) 2870283620Serj 2871190873Sjfv/* Little Endian defines */ 2872179055Sjfv#ifndef __le16 2873179055Sjfv#define __le16 u16 2874190873Sjfv#endif 2875190873Sjfv#ifndef __le32 2876179055Sjfv#define __le32 u32 2877190873Sjfv#endif 2878190873Sjfv#ifndef __le64 2879179055Sjfv#define __le64 u64 2880179055Sjfv 2881179055Sjfv#endif 2882185352Sjfv#ifndef __be16 2883185352Sjfv/* Big Endian defines */ 2884185352Sjfv#define __be16 u16 2885185352Sjfv#define __be32 u32 2886185352Sjfv#define __be64 u64 2887179055Sjfv 2888185352Sjfv#endif 2889190873Sjfvenum ixgbe_fdir_pballoc_type { 2890230775Sjfv IXGBE_FDIR_PBALLOC_NONE = 0, 2891230775Sjfv IXGBE_FDIR_PBALLOC_64K = 1, 2892230775Sjfv IXGBE_FDIR_PBALLOC_128K = 2, 2893230775Sjfv IXGBE_FDIR_PBALLOC_256K = 3, 2894190873Sjfv}; 2895179055Sjfv 2896190873Sjfv/* Flow Director register values */ 2897230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_64K 0x00000001 2898230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_128K 0x00000002 2899230775Sjfv#define IXGBE_FDIRCTRL_PBALLOC_256K 0x00000003 2900230775Sjfv#define IXGBE_FDIRCTRL_INIT_DONE 0x00000008 2901230775Sjfv#define IXGBE_FDIRCTRL_PERFECT_MATCH 0x00000010 2902230775Sjfv#define IXGBE_FDIRCTRL_REPORT_STATUS 0x00000020 2903230775Sjfv#define IXGBE_FDIRCTRL_REPORT_STATUS_ALWAYS 0x00000080 2904230775Sjfv#define IXGBE_FDIRCTRL_DROP_Q_SHIFT 8 2905295524Ssbruno#define IXGBE_FDIRCTRL_DROP_Q_MASK 0x00007F00 2906230775Sjfv#define IXGBE_FDIRCTRL_FLEX_SHIFT 16 2907295524Ssbruno#define IXGBE_FDIRCTRL_DROP_NO_MATCH 0x00008000 2908283620Serj#define IXGBE_FDIRCTRL_FILTERMODE_SHIFT 21 2909283620Serj#define IXGBE_FDIRCTRL_FILTERMODE_MACVLAN 0x0001 /* bit 23:21, 001b */ 2910283620Serj#define IXGBE_FDIRCTRL_FILTERMODE_CLOUD 0x0002 /* bit 23:21, 010b */ 2911230775Sjfv#define IXGBE_FDIRCTRL_SEARCHLIM 0x00800000 2912283620Serj#define IXGBE_FDIRCTRL_FILTERMODE_MASK 0x00E00000 2913230775Sjfv#define IXGBE_FDIRCTRL_MAX_LENGTH_SHIFT 24 2914230775Sjfv#define IXGBE_FDIRCTRL_FULL_THRESH_MASK 0xF0000000 2915230775Sjfv#define IXGBE_FDIRCTRL_FULL_THRESH_SHIFT 28 2916190873Sjfv 2917230775Sjfv#define IXGBE_FDIRTCPM_DPORTM_SHIFT 16 2918230775Sjfv#define IXGBE_FDIRUDPM_DPORTM_SHIFT 16 2919230775Sjfv#define IXGBE_FDIRIP6M_DIPM_SHIFT 16 2920230775Sjfv#define IXGBE_FDIRM_VLANID 0x00000001 2921230775Sjfv#define IXGBE_FDIRM_VLANP 0x00000002 2922230775Sjfv#define IXGBE_FDIRM_POOL 0x00000004 2923230775Sjfv#define IXGBE_FDIRM_L4P 0x00000008 2924230775Sjfv#define IXGBE_FDIRM_FLEX 0x00000010 2925230775Sjfv#define IXGBE_FDIRM_DIPv6 0x00000020 2926283620Serj#define IXGBE_FDIRM_L3P 0x00000040 2927190873Sjfv 2928283620Serj#define IXGBE_FDIRIP6M_INNER_MAC 0x03F0 /* bit 9:4 */ 2929283620Serj#define IXGBE_FDIRIP6M_TUNNEL_TYPE 0x0800 /* bit 11 */ 2930283620Serj#define IXGBE_FDIRIP6M_TNI_VNI 0xF000 /* bit 15:12 */ 2931283620Serj#define IXGBE_FDIRIP6M_TNI_VNI_24 0x1000 /* bit 12 */ 2932283620Serj#define IXGBE_FDIRIP6M_ALWAYS_MASK 0x040F /* bit 10, 3:0 */ 2933283620Serj 2934230775Sjfv#define IXGBE_FDIRFREE_FREE_MASK 0xFFFF 2935230775Sjfv#define IXGBE_FDIRFREE_FREE_SHIFT 0 2936230775Sjfv#define IXGBE_FDIRFREE_COLL_MASK 0x7FFF0000 2937230775Sjfv#define IXGBE_FDIRFREE_COLL_SHIFT 16 2938230775Sjfv#define IXGBE_FDIRLEN_MAXLEN_MASK 0x3F 2939230775Sjfv#define IXGBE_FDIRLEN_MAXLEN_SHIFT 0 2940230775Sjfv#define IXGBE_FDIRLEN_MAXHASH_MASK 0x7FFF0000 2941230775Sjfv#define IXGBE_FDIRLEN_MAXHASH_SHIFT 16 2942230775Sjfv#define IXGBE_FDIRUSTAT_ADD_MASK 0xFFFF 2943230775Sjfv#define IXGBE_FDIRUSTAT_ADD_SHIFT 0 2944230775Sjfv#define IXGBE_FDIRUSTAT_REMOVE_MASK 0xFFFF0000 2945230775Sjfv#define IXGBE_FDIRUSTAT_REMOVE_SHIFT 16 2946230775Sjfv#define IXGBE_FDIRFSTAT_FADD_MASK 0x00FF 2947230775Sjfv#define IXGBE_FDIRFSTAT_FADD_SHIFT 0 2948230775Sjfv#define IXGBE_FDIRFSTAT_FREMOVE_MASK 0xFF00 2949230775Sjfv#define IXGBE_FDIRFSTAT_FREMOVE_SHIFT 8 2950230775Sjfv#define IXGBE_FDIRPORT_DESTINATION_SHIFT 16 2951230775Sjfv#define IXGBE_FDIRVLAN_FLEX_SHIFT 16 2952230775Sjfv#define IXGBE_FDIRHASH_BUCKET_VALID_SHIFT 15 2953230775Sjfv#define IXGBE_FDIRHASH_SIG_SW_INDEX_SHIFT 16 2954190873Sjfv 2955230775Sjfv#define IXGBE_FDIRCMD_CMD_MASK 0x00000003 2956230775Sjfv#define IXGBE_FDIRCMD_CMD_ADD_FLOW 0x00000001 2957230775Sjfv#define IXGBE_FDIRCMD_CMD_REMOVE_FLOW 0x00000002 2958230775Sjfv#define IXGBE_FDIRCMD_CMD_QUERY_REM_FILT 0x00000003 2959230775Sjfv#define IXGBE_FDIRCMD_FILTER_VALID 0x00000004 2960230775Sjfv#define IXGBE_FDIRCMD_FILTER_UPDATE 0x00000008 2961230775Sjfv#define IXGBE_FDIRCMD_IPv6DMATCH 0x00000010 2962230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_UDP 0x00000020 2963230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_TCP 0x00000040 2964230775Sjfv#define IXGBE_FDIRCMD_L4TYPE_SCTP 0x00000060 2965230775Sjfv#define IXGBE_FDIRCMD_IPV6 0x00000080 2966230775Sjfv#define IXGBE_FDIRCMD_CLEARHT 0x00000100 2967230775Sjfv#define IXGBE_FDIRCMD_DROP 0x00000200 2968230775Sjfv#define IXGBE_FDIRCMD_INT 0x00000400 2969230775Sjfv#define IXGBE_FDIRCMD_LAST 0x00000800 2970230775Sjfv#define IXGBE_FDIRCMD_COLLISION 0x00001000 2971230775Sjfv#define IXGBE_FDIRCMD_QUEUE_EN 0x00008000 2972230775Sjfv#define IXGBE_FDIRCMD_FLOW_TYPE_SHIFT 5 2973230775Sjfv#define IXGBE_FDIRCMD_RX_QUEUE_SHIFT 16 2974283620Serj#define IXGBE_FDIRCMD_TUNNEL_FILTER_SHIFT 23 2975230775Sjfv#define IXGBE_FDIRCMD_VT_POOL_SHIFT 24 2976230775Sjfv#define IXGBE_FDIR_INIT_DONE_POLL 10 2977230775Sjfv#define IXGBE_FDIRCMD_CMD_POLL 10 2978283620Serj#define IXGBE_FDIRCMD_TUNNEL_FILTER 0x00800000 2979230775Sjfv#define IXGBE_FDIR_DROP_QUEUE 127 2980230775Sjfv 2981230775Sjfv 2982230775Sjfv/* Manageablility Host Interface defines */ 2983230775Sjfv#define IXGBE_HI_MAX_BLOCK_BYTE_LENGTH 1792 /* Num of bytes in range */ 2984230775Sjfv#define IXGBE_HI_MAX_BLOCK_DWORD_LENGTH 448 /* Num of dwords in range */ 2985230775Sjfv#define IXGBE_HI_COMMAND_TIMEOUT 500 /* Process HI command limit */ 2986283620Serj#define IXGBE_HI_FLASH_ERASE_TIMEOUT 1000 /* Process Erase command limit */ 2987283620Serj#define IXGBE_HI_FLASH_UPDATE_TIMEOUT 5000 /* Process Update command limit */ 2988283620Serj#define IXGBE_HI_FLASH_APPLY_TIMEOUT 0 /* Process Apply command limit */ 2989283620Serj#define IXGBE_HI_PHY_MGMT_REQ_TIMEOUT 2000 /* Wait up to 2 seconds */ 2990230775Sjfv 2991230775Sjfv/* CEM Support */ 2992230775Sjfv#define FW_CEM_HDR_LEN 0x4 2993230775Sjfv#define FW_CEM_CMD_DRIVER_INFO 0xDD 2994230775Sjfv#define FW_CEM_CMD_DRIVER_INFO_LEN 0x5 2995230775Sjfv#define FW_CEM_CMD_RESERVED 0X0 2996230775Sjfv#define FW_CEM_UNUSED_VER 0x0 2997230775Sjfv#define FW_CEM_MAX_RETRIES 3 2998230775Sjfv#define FW_CEM_RESP_STATUS_SUCCESS 0x1 2999315333Serj#define FW_CEM_DRIVER_VERSION_SIZE 39 /* +9 would send 48 bytes to fw */ 3000283620Serj#define FW_READ_SHADOW_RAM_CMD 0x31 3001283620Serj#define FW_READ_SHADOW_RAM_LEN 0x6 3002283620Serj#define FW_WRITE_SHADOW_RAM_CMD 0x33 3003283620Serj#define FW_WRITE_SHADOW_RAM_LEN 0xA /* 8 plus 1 WORD to write */ 3004283620Serj#define FW_SHADOW_RAM_DUMP_CMD 0x36 3005283620Serj#define FW_SHADOW_RAM_DUMP_LEN 0 3006283620Serj#define FW_DEFAULT_CHECKSUM 0xFF /* checksum always 0xFF */ 3007283620Serj#define FW_NVM_DATA_OFFSET 3 3008283620Serj#define FW_MAX_READ_BUFFER_SIZE 1024 3009283620Serj#define FW_DISABLE_RXEN_CMD 0xDE 3010283620Serj#define FW_DISABLE_RXEN_LEN 0x1 3011283620Serj#define FW_PHY_MGMT_REQ_CMD 0x20 3012315333Serj#define FW_PHY_TOKEN_REQ_CMD 0xA 3013315333Serj#define FW_PHY_TOKEN_REQ_LEN 2 3014315333Serj#define FW_PHY_TOKEN_REQ 0 3015315333Serj#define FW_PHY_TOKEN_REL 1 3016315333Serj#define FW_PHY_TOKEN_OK 1 3017315333Serj#define FW_PHY_TOKEN_RETRY 0x80 3018315333Serj#define FW_PHY_TOKEN_DELAY 5 /* milliseconds */ 3019315333Serj#define FW_PHY_TOKEN_WAIT 5 /* seconds */ 3020315333Serj#define FW_PHY_TOKEN_RETRIES ((FW_PHY_TOKEN_WAIT * 1000) / FW_PHY_TOKEN_DELAY) 3021295524Ssbruno#define FW_INT_PHY_REQ_CMD 0xB 3022295524Ssbruno#define FW_INT_PHY_REQ_LEN 10 3023295524Ssbruno#define FW_INT_PHY_REQ_READ 0 3024295524Ssbruno#define FW_INT_PHY_REQ_WRITE 1 3025315333Serj#define FW_PHY_ACT_REQ_CMD 5 3026315333Serj#define FW_PHY_ACT_DATA_COUNT 4 3027315333Serj#define FW_PHY_ACT_REQ_LEN (4 + 4 * FW_PHY_ACT_DATA_COUNT) 3028315333Serj#define FW_PHY_ACT_INIT_PHY 1 3029315333Serj#define FW_PHY_ACT_SETUP_LINK 2 3030315333Serj#define FW_PHY_ACT_LINK_SPEED_10 (1u << 0) 3031315333Serj#define FW_PHY_ACT_LINK_SPEED_100 (1u << 1) 3032315333Serj#define FW_PHY_ACT_LINK_SPEED_1G (1u << 2) 3033315333Serj#define FW_PHY_ACT_LINK_SPEED_2_5G (1u << 3) 3034315333Serj#define FW_PHY_ACT_LINK_SPEED_5G (1u << 4) 3035315333Serj#define FW_PHY_ACT_LINK_SPEED_10G (1u << 5) 3036315333Serj#define FW_PHY_ACT_LINK_SPEED_20G (1u << 6) 3037315333Serj#define FW_PHY_ACT_LINK_SPEED_25G (1u << 7) 3038315333Serj#define FW_PHY_ACT_LINK_SPEED_40G (1u << 8) 3039315333Serj#define FW_PHY_ACT_LINK_SPEED_50G (1u << 9) 3040315333Serj#define FW_PHY_ACT_LINK_SPEED_100G (1u << 10) 3041315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT 16 3042315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_MASK (3u << \ 3043315333Serj FW_PHY_ACT_SETUP_LINK_PAUSE_SHIFT) 3044315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_NONE 0u 3045315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_TX 1u 3046315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_RX 2u 3047315333Serj#define FW_PHY_ACT_SETUP_LINK_PAUSE_RXTX 3u 3048315333Serj#define FW_PHY_ACT_SETUP_LINK_LP (1u << 18) 3049315333Serj#define FW_PHY_ACT_SETUP_LINK_HP (1u << 19) 3050315333Serj#define FW_PHY_ACT_SETUP_LINK_EEE (1u << 20) 3051315333Serj#define FW_PHY_ACT_SETUP_LINK_AN (1u << 22) 3052315333Serj#define FW_PHY_ACT_SETUP_LINK_RSP_DOWN (1u << 0) 3053315333Serj#define FW_PHY_ACT_GET_LINK_INFO 3 3054315333Serj#define FW_PHY_ACT_GET_LINK_INFO_EEE (1u << 19) 3055315333Serj#define FW_PHY_ACT_GET_LINK_INFO_FC_TX (1u << 20) 3056315333Serj#define FW_PHY_ACT_GET_LINK_INFO_FC_RX (1u << 21) 3057315333Serj#define FW_PHY_ACT_GET_LINK_INFO_POWER (1u << 22) 3058315333Serj#define FW_PHY_ACT_GET_LINK_INFO_AN_COMPLETE (1u << 24) 3059315333Serj#define FW_PHY_ACT_GET_LINK_INFO_TEMP (1u << 25) 3060315333Serj#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_TX (1u << 28) 3061315333Serj#define FW_PHY_ACT_GET_LINK_INFO_LP_FC_RX (1u << 29) 3062315333Serj#define FW_PHY_ACT_FORCE_LINK_DOWN 4 3063315333Serj#define FW_PHY_ACT_FORCE_LINK_DOWN_OFF (1u << 0) 3064315333Serj#define FW_PHY_ACT_PHY_SW_RESET 5 3065315333Serj#define FW_PHY_ACT_PHY_HW_RESET 6 3066315333Serj#define FW_PHY_ACT_GET_PHY_INFO 7 3067315333Serj#define FW_PHY_ACT_UD_2 0x1002 3068315333Serj#define FW_PHY_ACT_UD_2_10G_KR_EEE (1u << 6) 3069315333Serj#define FW_PHY_ACT_UD_2_10G_KX4_EEE (1u << 5) 3070315333Serj#define FW_PHY_ACT_UD_2_1G_KX_EEE (1u << 4) 3071315333Serj#define FW_PHY_ACT_UD_2_10G_T_EEE (1u << 3) 3072315333Serj#define FW_PHY_ACT_UD_2_1G_T_EEE (1u << 2) 3073315333Serj#define FW_PHY_ACT_UD_2_100M_TX_EEE (1u << 1) 3074315333Serj#define FW_PHY_ACT_RETRIES 50 3075315333Serj#define FW_PHY_INFO_SPEED_MASK 0xFFFu 3076315333Serj#define FW_PHY_INFO_ID_HI_MASK 0xFFFF0000u 3077315333Serj#define FW_PHY_INFO_ID_LO_MASK 0x0000FFFFu 3078295524Ssbruno 3079230775Sjfv/* Host Interface Command Structures */ 3080230775Sjfv 3081315333Serj#pragma pack(push, 1) 3082315333Serj 3083230775Sjfvstruct ixgbe_hic_hdr { 3084230775Sjfv u8 cmd; 3085230775Sjfv u8 buf_len; 3086230775Sjfv union { 3087230775Sjfv u8 cmd_resv; 3088230775Sjfv u8 ret_status; 3089230775Sjfv } cmd_or_resp; 3090230775Sjfv u8 checksum; 3091230775Sjfv}; 3092230775Sjfv 3093283620Serjstruct ixgbe_hic_hdr2_req { 3094283620Serj u8 cmd; 3095283620Serj u8 buf_lenh; 3096283620Serj u8 buf_lenl; 3097283620Serj u8 checksum; 3098283620Serj}; 3099283620Serj 3100283620Serjstruct ixgbe_hic_hdr2_rsp { 3101283620Serj u8 cmd; 3102283620Serj u8 buf_lenl; 3103283620Serj u8 buf_lenh_status; /* 7-5: high bits of buf_len, 4-0: status */ 3104283620Serj u8 checksum; 3105283620Serj}; 3106283620Serj 3107283620Serjunion ixgbe_hic_hdr2 { 3108283620Serj struct ixgbe_hic_hdr2_req req; 3109283620Serj struct ixgbe_hic_hdr2_rsp rsp; 3110283620Serj}; 3111283620Serj 3112230775Sjfvstruct ixgbe_hic_drv_info { 3113230775Sjfv struct ixgbe_hic_hdr hdr; 3114230775Sjfv u8 port_num; 3115230775Sjfv u8 ver_sub; 3116230775Sjfv u8 ver_build; 3117230775Sjfv u8 ver_min; 3118230775Sjfv u8 ver_maj; 3119230775Sjfv u8 pad; /* end spacing to ensure length is mult. of dword */ 3120230775Sjfv u16 pad2; /* end spacing to ensure length is mult. of dword2 */ 3121230775Sjfv}; 3122230775Sjfv 3123315333Serjstruct ixgbe_hic_drv_info2 { 3124315333Serj struct ixgbe_hic_hdr hdr; 3125315333Serj u8 port_num; 3126315333Serj u8 ver_sub; 3127315333Serj u8 ver_build; 3128315333Serj u8 ver_min; 3129315333Serj u8 ver_maj; 3130315333Serj char driver_string[FW_CEM_DRIVER_VERSION_SIZE]; 3131315333Serj}; 3132315333Serj 3133283620Serj/* These need to be dword aligned */ 3134283620Serjstruct ixgbe_hic_read_shadow_ram { 3135283620Serj union ixgbe_hic_hdr2 hdr; 3136283620Serj u32 address; 3137283620Serj u16 length; 3138283620Serj u16 pad2; 3139283620Serj u16 data; 3140283620Serj u16 pad3; 3141283620Serj}; 3142283620Serj 3143283620Serjstruct ixgbe_hic_write_shadow_ram { 3144283620Serj union ixgbe_hic_hdr2 hdr; 3145283620Serj u32 address; 3146283620Serj u16 length; 3147283620Serj u16 pad2; 3148283620Serj u16 data; 3149283620Serj u16 pad3; 3150283620Serj}; 3151283620Serj 3152283620Serjstruct ixgbe_hic_disable_rxen { 3153283620Serj struct ixgbe_hic_hdr hdr; 3154283620Serj u8 port_number; 3155283620Serj u8 pad2; 3156283620Serj u16 pad3; 3157283620Serj}; 3158283620Serj 3159315333Serjstruct ixgbe_hic_phy_token_req { 3160315333Serj struct ixgbe_hic_hdr hdr; 3161315333Serj u8 port_number; 3162315333Serj u8 command_type; 3163315333Serj u16 pad; 3164315333Serj}; 3165315333Serj 3166295524Ssbrunostruct ixgbe_hic_internal_phy_req { 3167295524Ssbruno struct ixgbe_hic_hdr hdr; 3168295524Ssbruno u8 port_number; 3169295524Ssbruno u8 command_type; 3170315333Serj __be16 address; 3171295524Ssbruno u16 rsv1; 3172315333Serj __be32 write_data; 3173295524Ssbruno u16 pad; 3174295524Ssbruno}; 3175283620Serj 3176295524Ssbrunostruct ixgbe_hic_internal_phy_resp { 3177295524Ssbruno struct ixgbe_hic_hdr hdr; 3178315333Serj __be32 read_data; 3179295524Ssbruno}; 3180295524Ssbruno 3181315333Serjstruct ixgbe_hic_phy_activity_req { 3182315333Serj struct ixgbe_hic_hdr hdr; 3183315333Serj u8 port_number; 3184315333Serj u8 pad; 3185315333Serj __le16 activity_id; 3186315333Serj __be32 data[FW_PHY_ACT_DATA_COUNT]; 3187315333Serj}; 3188295524Ssbruno 3189315333Serjstruct ixgbe_hic_phy_activity_resp { 3190315333Serj struct ixgbe_hic_hdr hdr; 3191315333Serj __be32 data[FW_PHY_ACT_DATA_COUNT]; 3192315333Serj}; 3193315333Serj 3194315333Serj#pragma pack(pop) 3195315333Serj 3196171384Sjfv/* Transmit Descriptor - Legacy */ 3197171384Sjfvstruct ixgbe_legacy_tx_desc { 3198230775Sjfv u64 buffer_addr; /* Address of the descriptor's data buffer */ 3199171384Sjfv union { 3200179055Sjfv __le32 data; 3201171384Sjfv struct { 3202230775Sjfv __le16 length; /* Data buffer length */ 3203230775Sjfv u8 cso; /* Checksum offset */ 3204230775Sjfv u8 cmd; /* Descriptor control */ 3205171384Sjfv } flags; 3206171384Sjfv } lower; 3207171384Sjfv union { 3208179055Sjfv __le32 data; 3209171384Sjfv struct { 3210230775Sjfv u8 status; /* Descriptor status */ 3211230775Sjfv u8 css; /* Checksum start */ 3212179055Sjfv __le16 vlan; 3213171384Sjfv } fields; 3214171384Sjfv } upper; 3215171384Sjfv}; 3216171384Sjfv 3217171384Sjfv/* Transmit Descriptor - Advanced */ 3218171384Sjfvunion ixgbe_adv_tx_desc { 3219171384Sjfv struct { 3220230775Sjfv __le64 buffer_addr; /* Address of descriptor's data buf */ 3221179055Sjfv __le32 cmd_type_len; 3222179055Sjfv __le32 olinfo_status; 3223171384Sjfv } read; 3224171384Sjfv struct { 3225230775Sjfv __le64 rsvd; /* Reserved */ 3226179055Sjfv __le32 nxtseq_seed; 3227179055Sjfv __le32 status; 3228171384Sjfv } wb; 3229171384Sjfv}; 3230171384Sjfv 3231171384Sjfv/* Receive Descriptor - Legacy */ 3232171384Sjfvstruct ixgbe_legacy_rx_desc { 3233179055Sjfv __le64 buffer_addr; /* Address of the descriptor's data buffer */ 3234230775Sjfv __le16 length; /* Length of data DMAed into data buffer */ 3235230775Sjfv __le16 csum; /* Packet checksum */ 3236230775Sjfv u8 status; /* Descriptor status */ 3237230775Sjfv u8 errors; /* Descriptor Errors */ 3238179055Sjfv __le16 vlan; 3239171384Sjfv}; 3240171384Sjfv 3241171384Sjfv/* Receive Descriptor - Advanced */ 3242171384Sjfvunion ixgbe_adv_rx_desc { 3243171384Sjfv struct { 3244179055Sjfv __le64 pkt_addr; /* Packet buffer address */ 3245179055Sjfv __le64 hdr_addr; /* Header buffer address */ 3246171384Sjfv } read; 3247171384Sjfv struct { 3248171384Sjfv struct { 3249179055Sjfv union { 3250179055Sjfv __le32 data; 3251179055Sjfv struct { 3252181003Sjfv __le16 pkt_info; /* RSS, Pkt type */ 3253181003Sjfv __le16 hdr_info; /* Splithdr, hdrlen */ 3254179055Sjfv } hs_rss; 3255171384Sjfv } lo_dword; 3256171384Sjfv union { 3257179055Sjfv __le32 rss; /* RSS Hash */ 3258171384Sjfv struct { 3259179055Sjfv __le16 ip_id; /* IP id */ 3260179055Sjfv __le16 csum; /* Packet Checksum */ 3261171384Sjfv } csum_ip; 3262171384Sjfv } hi_dword; 3263171384Sjfv } lower; 3264171384Sjfv struct { 3265179055Sjfv __le32 status_error; /* ext status/error */ 3266179055Sjfv __le16 length; /* Packet length */ 3267179055Sjfv __le16 vlan; /* VLAN tag */ 3268171384Sjfv } upper; 3269171384Sjfv } wb; /* writeback */ 3270171384Sjfv}; 3271171384Sjfv 3272171384Sjfv/* Context descriptors */ 3273171384Sjfvstruct ixgbe_adv_tx_context_desc { 3274179055Sjfv __le32 vlan_macip_lens; 3275179055Sjfv __le32 seqnum_seed; 3276179055Sjfv __le32 type_tucmd_mlhl; 3277179055Sjfv __le32 mss_l4len_idx; 3278171384Sjfv}; 3279171384Sjfv 3280171384Sjfv/* Adv Transmit Descriptor Config Masks */ 3281230775Sjfv#define IXGBE_ADVTXD_DTALEN_MASK 0x0000FFFF /* Data buf length(bytes) */ 3282230775Sjfv#define IXGBE_ADVTXD_MAC_LINKSEC 0x00040000 /* Insert LinkSec */ 3283230775Sjfv#define IXGBE_ADVTXD_MAC_TSTAMP 0x00080000 /* IEEE1588 time stamp */ 3284230775Sjfv#define IXGBE_ADVTXD_IPSEC_SA_INDEX_MASK 0x000003FF /* IPSec SA index */ 3285230775Sjfv#define IXGBE_ADVTXD_IPSEC_ESP_LEN_MASK 0x000001FF /* IPSec ESP length */ 3286230775Sjfv#define IXGBE_ADVTXD_DTYP_MASK 0x00F00000 /* DTYP mask */ 3287230775Sjfv#define IXGBE_ADVTXD_DTYP_CTXT 0x00200000 /* Adv Context Desc */ 3288230775Sjfv#define IXGBE_ADVTXD_DTYP_DATA 0x00300000 /* Adv Data Descriptor */ 3289230775Sjfv#define IXGBE_ADVTXD_DCMD_EOP IXGBE_TXD_CMD_EOP /* End of Packet */ 3290230775Sjfv#define IXGBE_ADVTXD_DCMD_IFCS IXGBE_TXD_CMD_IFCS /* Insert FCS */ 3291230775Sjfv#define IXGBE_ADVTXD_DCMD_RS IXGBE_TXD_CMD_RS /* Report Status */ 3292230775Sjfv#define IXGBE_ADVTXD_DCMD_DDTYP_ISCSI 0x10000000 /* DDP hdr type or iSCSI */ 3293230775Sjfv#define IXGBE_ADVTXD_DCMD_DEXT IXGBE_TXD_CMD_DEXT /* Desc ext 1=Adv */ 3294230775Sjfv#define IXGBE_ADVTXD_DCMD_VLE IXGBE_TXD_CMD_VLE /* VLAN pkt enable */ 3295230775Sjfv#define IXGBE_ADVTXD_DCMD_TSE 0x80000000 /* TCP Seg enable */ 3296230775Sjfv#define IXGBE_ADVTXD_STAT_DD IXGBE_TXD_STAT_DD /* Descriptor Done */ 3297230775Sjfv#define IXGBE_ADVTXD_STAT_SN_CRC 0x00000002 /* NXTSEQ/SEED pres in WB */ 3298230775Sjfv#define IXGBE_ADVTXD_STAT_RSV 0x0000000C /* STA Reserved */ 3299230775Sjfv#define IXGBE_ADVTXD_IDX_SHIFT 4 /* Adv desc Index shift */ 3300230775Sjfv#define IXGBE_ADVTXD_CC 0x00000080 /* Check Context */ 3301230775Sjfv#define IXGBE_ADVTXD_POPTS_SHIFT 8 /* Adv desc POPTS shift */ 3302230775Sjfv#define IXGBE_ADVTXD_POPTS_IXSM (IXGBE_TXD_POPTS_IXSM << \ 3303230775Sjfv IXGBE_ADVTXD_POPTS_SHIFT) 3304230775Sjfv#define IXGBE_ADVTXD_POPTS_TXSM (IXGBE_TXD_POPTS_TXSM << \ 3305230775Sjfv IXGBE_ADVTXD_POPTS_SHIFT) 3306230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_1ST 0x00000000 /* 1st TSO of iSCSI PDU */ 3307230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_MDL 0x00000800 /* Middle TSO of iSCSI PDU */ 3308230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_LAST 0x00001000 /* Last TSO of iSCSI PDU */ 3309230775Sjfv/* 1st&Last TSO-full iSCSI PDU */ 3310230775Sjfv#define IXGBE_ADVTXD_POPTS_ISCO_FULL 0x00001800 3311230775Sjfv#define IXGBE_ADVTXD_POPTS_RSV 0x00002000 /* POPTS Reserved */ 3312230775Sjfv#define IXGBE_ADVTXD_PAYLEN_SHIFT 14 /* Adv desc PAYLEN shift */ 3313230775Sjfv#define IXGBE_ADVTXD_MACLEN_SHIFT 9 /* Adv ctxt desc mac len shift */ 3314230775Sjfv#define IXGBE_ADVTXD_VLAN_SHIFT 16 /* Adv ctxt vlan tag shift */ 3315230775Sjfv#define IXGBE_ADVTXD_TUCMD_IPV4 0x00000400 /* IP Packet Type: 1=IPv4 */ 3316230775Sjfv#define IXGBE_ADVTXD_TUCMD_IPV6 0x00000000 /* IP Packet Type: 0=IPv6 */ 3317230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_UDP 0x00000000 /* L4 Packet TYPE of UDP */ 3318230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_TCP 0x00000800 /* L4 Packet TYPE of TCP */ 3319230775Sjfv#define IXGBE_ADVTXD_TUCMD_L4T_SCTP 0x00001000 /* L4 Packet TYPE of SCTP */ 3320315333Serj#define IXGBE_ADVTXD_TUCMD_L4T_RSV 0x00001800 /* RSV L4 Packet TYPE */ 3321230775Sjfv#define IXGBE_ADVTXD_TUCMD_MKRREQ 0x00002000 /* req Markers and CRC */ 3322230775Sjfv#define IXGBE_ADVTXD_POPTS_IPSEC 0x00000400 /* IPSec offload request */ 3323190873Sjfv#define IXGBE_ADVTXD_TUCMD_IPSEC_TYPE_ESP 0x00002000 /* IPSec Type ESP */ 3324190873Sjfv#define IXGBE_ADVTXD_TUCMD_IPSEC_ENCRYPT_EN 0x00004000/* ESP Encrypt Enable */ 3325230775Sjfv#define IXGBE_ADVTXT_TUCMD_FCOE 0x00008000 /* FCoE Frame Type */ 3326230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_MASK (0x3 << 10) /* FC EOF index */ 3327230775Sjfv#define IXGBE_ADVTXD_FCOEF_SOF ((1 << 2) << 10) /* FC SOF index */ 3328230775Sjfv#define IXGBE_ADVTXD_FCOEF_PARINC ((1 << 3) << 10) /* Rel_Off in F_CTL */ 3329230775Sjfv#define IXGBE_ADVTXD_FCOEF_ORIE ((1 << 4) << 10) /* Orientation End */ 3330230775Sjfv#define IXGBE_ADVTXD_FCOEF_ORIS ((1 << 5) << 10) /* Orientation Start */ 3331230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_N (0x0 << 10) /* 00: EOFn */ 3332230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_T (0x1 << 10) /* 01: EOFt */ 3333230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_NI (0x2 << 10) /* 10: EOFni */ 3334230775Sjfv#define IXGBE_ADVTXD_FCOEF_EOF_A (0x3 << 10) /* 11: EOFa */ 3335230775Sjfv#define IXGBE_ADVTXD_L4LEN_SHIFT 8 /* Adv ctxt L4LEN shift */ 3336230775Sjfv#define IXGBE_ADVTXD_MSS_SHIFT 16 /* Adv ctxt MSS shift */ 3337171384Sjfv 3338283620Serj#define IXGBE_ADVTXD_OUTER_IPLEN 16 /* Adv ctxt OUTERIPLEN shift */ 3339283620Serj#define IXGBE_ADVTXD_TUNNEL_LEN 24 /* Adv ctxt TUNNELLEN shift */ 3340283620Serj#define IXGBE_ADVTXD_TUNNEL_TYPE_SHIFT 16 /* Adv Tx Desc Tunnel Type shift */ 3341283620Serj#define IXGBE_ADVTXD_OUTERIPCS_SHIFT 17 /* Adv Tx Desc OUTERIPCS Shift */ 3342283620Serj#define IXGBE_ADVTXD_TUNNEL_TYPE_NVGRE 1 /* Adv Tx Desc Tunnel Type NVGRE */ 3343315333Serj/* Adv Tx Desc OUTERIPCS Shift for X550EM_a */ 3344315333Serj#define IXGBE_ADVTXD_OUTERIPCS_SHIFT_X550EM_a 26 3345171384Sjfv/* Autonegotiation advertised speeds */ 3346171384Sjfvtypedef u32 ixgbe_autoneg_advertised; 3347171384Sjfv/* Link speed */ 3348171384Sjfvtypedef u32 ixgbe_link_speed; 3349230775Sjfv#define IXGBE_LINK_SPEED_UNKNOWN 0 3350315333Serj#define IXGBE_LINK_SPEED_10_FULL 0x0002 3351230775Sjfv#define IXGBE_LINK_SPEED_100_FULL 0x0008 3352230775Sjfv#define IXGBE_LINK_SPEED_1GB_FULL 0x0020 3353283620Serj#define IXGBE_LINK_SPEED_2_5GB_FULL 0x0400 3354283620Serj#define IXGBE_LINK_SPEED_5GB_FULL 0x0800 3355230775Sjfv#define IXGBE_LINK_SPEED_10GB_FULL 0x0080 3356230775Sjfv#define IXGBE_LINK_SPEED_82598_AUTONEG (IXGBE_LINK_SPEED_1GB_FULL | \ 3357230775Sjfv IXGBE_LINK_SPEED_10GB_FULL) 3358230775Sjfv#define IXGBE_LINK_SPEED_82599_AUTONEG (IXGBE_LINK_SPEED_100_FULL | \ 3359230775Sjfv IXGBE_LINK_SPEED_1GB_FULL | \ 3360230775Sjfv IXGBE_LINK_SPEED_10GB_FULL) 3361171384Sjfv 3362185352Sjfv/* Physical layer type */ 3363185352Sjfvtypedef u32 ixgbe_physical_layer; 3364230775Sjfv#define IXGBE_PHYSICAL_LAYER_UNKNOWN 0 3365230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_T 0x0001 3366230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_T 0x0002 3367230775Sjfv#define IXGBE_PHYSICAL_LAYER_100BASE_TX 0x0004 3368230775Sjfv#define IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU 0x0008 3369230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_LR 0x0010 3370230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_LRM 0x0020 3371230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_SR 0x0040 3372230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_KX4 0x0080 3373230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_CX4 0x0100 3374230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_KX 0x0200 3375230775Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_BX 0x0400 3376230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_KR 0x0800 3377230775Sjfv#define IXGBE_PHYSICAL_LAYER_10GBASE_XAUI 0x1000 3378230775Sjfv#define IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA 0x2000 3379238149Sjfv#define IXGBE_PHYSICAL_LAYER_1000BASE_SX 0x4000 3380315333Serj#define IXGBE_PHYSICAL_LAYER_10BASE_T 0x8000 3381185352Sjfv 3382230775Sjfv/* Flow Control Data Sheet defined values 3383230775Sjfv * Calculation and defines taken from 802.1bb Annex O 3384230775Sjfv */ 3385205720Sjfv 3386230775Sjfv/* BitTimes (BT) conversion */ 3387238149Sjfv#define IXGBE_BT2KB(BT) ((BT + (8 * 1024 - 1)) / (8 * 1024)) 3388230775Sjfv#define IXGBE_B2BT(BT) (BT * 8) 3389215911Sjfv 3390230775Sjfv/* Calculate Delay to respond to PFC */ 3391230775Sjfv#define IXGBE_PFC_D 672 3392230775Sjfv 3393230775Sjfv/* Calculate Cable Delay */ 3394230775Sjfv#define IXGBE_CABLE_DC 5556 /* Delay Copper */ 3395230775Sjfv#define IXGBE_CABLE_DO 5000 /* Delay Optical */ 3396230775Sjfv 3397230775Sjfv/* Calculate Interface Delay X540 */ 3398230775Sjfv#define IXGBE_PHY_DC 25600 /* Delay 10G BASET */ 3399230775Sjfv#define IXGBE_MAC_DC 8192 /* Delay Copper XAUI interface */ 3400230775Sjfv#define IXGBE_XAUI_DC (2 * 2048) /* Delay Copper Phy */ 3401230775Sjfv 3402230775Sjfv#define IXGBE_ID_X540 (IXGBE_MAC_DC + IXGBE_XAUI_DC + IXGBE_PHY_DC) 3403230775Sjfv 3404230775Sjfv/* Calculate Interface Delay 82598, 82599 */ 3405230775Sjfv#define IXGBE_PHY_D 12800 3406230775Sjfv#define IXGBE_MAC_D 4096 3407230775Sjfv#define IXGBE_XAUI_D (2 * 1024) 3408230775Sjfv 3409230775Sjfv#define IXGBE_ID (IXGBE_MAC_D + IXGBE_XAUI_D + IXGBE_PHY_D) 3410230775Sjfv 3411230775Sjfv/* Calculate Delay incurred from higher layer */ 3412230775Sjfv#define IXGBE_HD 6144 3413230775Sjfv 3414230775Sjfv/* Calculate PCI Bus delay for low thresholds */ 3415230775Sjfv#define IXGBE_PCI_DELAY 10000 3416230775Sjfv 3417230775Sjfv/* Calculate X540 delay value in bit times */ 3418238149Sjfv#define IXGBE_DV_X540(_max_frame_link, _max_frame_tc) \ 3419238149Sjfv ((36 * \ 3420238149Sjfv (IXGBE_B2BT(_max_frame_link) + \ 3421238149Sjfv IXGBE_PFC_D + \ 3422238149Sjfv (2 * IXGBE_CABLE_DC) + \ 3423238149Sjfv (2 * IXGBE_ID_X540) + \ 3424238149Sjfv IXGBE_HD) / 25 + 1) + \ 3425238149Sjfv 2 * IXGBE_B2BT(_max_frame_tc)) 3426230775Sjfv 3427230775Sjfv/* Calculate 82599, 82598 delay value in bit times */ 3428238149Sjfv#define IXGBE_DV(_max_frame_link, _max_frame_tc) \ 3429238149Sjfv ((36 * \ 3430238149Sjfv (IXGBE_B2BT(_max_frame_link) + \ 3431238149Sjfv IXGBE_PFC_D + \ 3432238149Sjfv (2 * IXGBE_CABLE_DC) + \ 3433238149Sjfv (2 * IXGBE_ID) + \ 3434238149Sjfv IXGBE_HD) / 25 + 1) + \ 3435238149Sjfv 2 * IXGBE_B2BT(_max_frame_tc)) 3436230775Sjfv 3437230775Sjfv/* Calculate low threshold delay values */ 3438238149Sjfv#define IXGBE_LOW_DV_X540(_max_frame_tc) \ 3439238149Sjfv (2 * IXGBE_B2BT(_max_frame_tc) + \ 3440238149Sjfv (36 * IXGBE_PCI_DELAY / 25) + 1) 3441238149Sjfv#define IXGBE_LOW_DV(_max_frame_tc) \ 3442238149Sjfv (2 * IXGBE_LOW_DV_X540(_max_frame_tc)) 3443230775Sjfv 3444190873Sjfv/* Software ATR hash keys */ 3445230775Sjfv#define IXGBE_ATR_BUCKET_HASH_KEY 0x3DAD14E2 3446230775Sjfv#define IXGBE_ATR_SIGNATURE_HASH_KEY 0x174D3614 3447185352Sjfv 3448215911Sjfv/* Software ATR input stream values and masks */ 3449230775Sjfv#define IXGBE_ATR_HASH_MASK 0x7fff 3450230775Sjfv#define IXGBE_ATR_L4TYPE_MASK 0x3 3451230775Sjfv#define IXGBE_ATR_L4TYPE_UDP 0x1 3452230775Sjfv#define IXGBE_ATR_L4TYPE_TCP 0x2 3453230775Sjfv#define IXGBE_ATR_L4TYPE_SCTP 0x3 3454230775Sjfv#define IXGBE_ATR_L4TYPE_IPV6_MASK 0x4 3455283620Serj#define IXGBE_ATR_L4TYPE_TUNNEL_MASK 0x10 3456215911Sjfvenum ixgbe_atr_flow_type { 3457230775Sjfv IXGBE_ATR_FLOW_TYPE_IPV4 = 0x0, 3458230775Sjfv IXGBE_ATR_FLOW_TYPE_UDPV4 = 0x1, 3459230775Sjfv IXGBE_ATR_FLOW_TYPE_TCPV4 = 0x2, 3460230775Sjfv IXGBE_ATR_FLOW_TYPE_SCTPV4 = 0x3, 3461230775Sjfv IXGBE_ATR_FLOW_TYPE_IPV6 = 0x4, 3462230775Sjfv IXGBE_ATR_FLOW_TYPE_UDPV6 = 0x5, 3463230775Sjfv IXGBE_ATR_FLOW_TYPE_TCPV6 = 0x6, 3464230775Sjfv IXGBE_ATR_FLOW_TYPE_SCTPV6 = 0x7, 3465283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV4 = 0x10, 3466283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV4 = 0x11, 3467283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV4 = 0x12, 3468283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV4 = 0x13, 3469283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_IPV6 = 0x14, 3470283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_UDPV6 = 0x15, 3471283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_TCPV6 = 0x16, 3472283620Serj IXGBE_ATR_FLOW_TYPE_TUNNELED_SCTPV6 = 0x17, 3473215911Sjfv}; 3474190873Sjfv 3475190873Sjfv/* Flow Director ATR input struct. */ 3476215911Sjfvunion ixgbe_atr_input { 3477217593Sjfv /* 3478217593Sjfv * Byte layout in order, all values with MSB first: 3479190873Sjfv * 3480230775Sjfv * vm_pool - 1 byte 3481230775Sjfv * flow_type - 1 byte 3482230775Sjfv * vlan_id - 2 bytes 3483230775Sjfv * src_ip - 16 bytes 3484283620Serj * inner_mac - 6 bytes 3485283620Serj * cloud_mode - 2 bytes 3486283620Serj * tni_vni - 4 bytes 3487230775Sjfv * dst_ip - 16 bytes 3488230775Sjfv * src_port - 2 bytes 3489230775Sjfv * dst_port - 2 bytes 3490230775Sjfv * flex_bytes - 2 bytes 3491230775Sjfv * bkt_hash - 2 bytes 3492190873Sjfv */ 3493215911Sjfv struct { 3494230775Sjfv u8 vm_pool; 3495230775Sjfv u8 flow_type; 3496215911Sjfv __be16 vlan_id; 3497215911Sjfv __be32 dst_ip[4]; 3498215911Sjfv __be32 src_ip[4]; 3499283620Serj u8 inner_mac[6]; 3500283620Serj __be16 tunnel_type; 3501283620Serj __be32 tni_vni; 3502215911Sjfv __be16 src_port; 3503215911Sjfv __be16 dst_port; 3504215911Sjfv __be16 flex_bytes; 3505230775Sjfv __be16 bkt_hash; 3506215911Sjfv } formatted; 3507283620Serj __be32 dword_stream[14]; 3508190873Sjfv}; 3509190873Sjfv 3510217593Sjfv/* Flow Director compressed ATR hash input struct */ 3511217593Sjfvunion ixgbe_atr_hash_dword { 3512217593Sjfv struct { 3513217593Sjfv u8 vm_pool; 3514217593Sjfv u8 flow_type; 3515217593Sjfv __be16 vlan_id; 3516217593Sjfv } formatted; 3517217593Sjfv __be32 ip; 3518217593Sjfv struct { 3519217593Sjfv __be16 src; 3520217593Sjfv __be16 dst; 3521217593Sjfv } port; 3522217593Sjfv __be16 flex_bytes; 3523217593Sjfv __be32 dword; 3524217593Sjfv}; 3525217593Sjfv 3526217593Sjfv 3527283620Serj#define IXGBE_MVALS_INIT(m) \ 3528283620Serj IXGBE_CAT(EEC, m), \ 3529283620Serj IXGBE_CAT(FLA, m), \ 3530283620Serj IXGBE_CAT(GRC, m), \ 3531283620Serj IXGBE_CAT(SRAMREL, m), \ 3532283620Serj IXGBE_CAT(FACTPS, m), \ 3533283620Serj IXGBE_CAT(SWSM, m), \ 3534295524Ssbruno IXGBE_CAT(SWFW_SYNC, m), \ 3535283620Serj IXGBE_CAT(FWSM, m), \ 3536283620Serj IXGBE_CAT(SDP0_GPIEN, m), \ 3537283620Serj IXGBE_CAT(SDP1_GPIEN, m), \ 3538283620Serj IXGBE_CAT(SDP2_GPIEN, m), \ 3539283620Serj IXGBE_CAT(EICR_GPI_SDP0, m), \ 3540283620Serj IXGBE_CAT(EICR_GPI_SDP1, m), \ 3541283620Serj IXGBE_CAT(EICR_GPI_SDP2, m), \ 3542283620Serj IXGBE_CAT(CIAA, m), \ 3543283620Serj IXGBE_CAT(CIAD, m), \ 3544283620Serj IXGBE_CAT(I2C_CLK_IN, m), \ 3545283620Serj IXGBE_CAT(I2C_CLK_OUT, m), \ 3546283620Serj IXGBE_CAT(I2C_DATA_IN, m), \ 3547283620Serj IXGBE_CAT(I2C_DATA_OUT, m), \ 3548283620Serj IXGBE_CAT(I2C_DATA_OE_N_EN, m), \ 3549283620Serj IXGBE_CAT(I2C_BB_EN, m), \ 3550283620Serj IXGBE_CAT(I2C_CLK_OE_N_EN, m), \ 3551283620Serj IXGBE_CAT(I2CCTL, m) 3552283620Serj 3553283620Serjenum ixgbe_mvals { 3554283620Serj IXGBE_MVALS_INIT(_IDX), 3555283620Serj IXGBE_MVALS_IDX_LIMIT 3556283620Serj}; 3557283620Serj 3558215911Sjfv/* 3559215911Sjfv * Unavailable: The FCoE Boot Option ROM is not present in the flash. 3560215911Sjfv * Disabled: Present; boot order is not set for any targets on the port. 3561215911Sjfv * Enabled: Present; boot order is set for at least one target on the port. 3562215911Sjfv */ 3563215911Sjfvenum ixgbe_fcoe_boot_status { 3564230775Sjfv ixgbe_fcoe_bootstatus_disabled = 0, 3565230775Sjfv ixgbe_fcoe_bootstatus_enabled = 1, 3566230775Sjfv ixgbe_fcoe_bootstatus_unavailable = 0xFFFF 3567215911Sjfv}; 3568215911Sjfv 3569171384Sjfvenum ixgbe_eeprom_type { 3570171384Sjfv ixgbe_eeprom_uninitialized = 0, 3571171384Sjfv ixgbe_eeprom_spi, 3572200239Sjfv ixgbe_flash, 3573171384Sjfv ixgbe_eeprom_none /* No NVM support */ 3574171384Sjfv}; 3575171384Sjfv 3576171384Sjfvenum ixgbe_mac_type { 3577171384Sjfv ixgbe_mac_unknown = 0, 3578171384Sjfv ixgbe_mac_82598EB, 3579190873Sjfv ixgbe_mac_82599EB, 3580230775Sjfv ixgbe_mac_X540, 3581283620Serj ixgbe_mac_X550, 3582283620Serj ixgbe_mac_X550EM_x, 3583315333Serj ixgbe_mac_X550EM_a, 3584171384Sjfv ixgbe_num_macs 3585171384Sjfv}; 3586171384Sjfv 3587171384Sjfvenum ixgbe_phy_type { 3588171384Sjfv ixgbe_phy_unknown = 0, 3589190873Sjfv ixgbe_phy_none, 3590179055Sjfv ixgbe_phy_tn, 3591190873Sjfv ixgbe_phy_aq, 3592283620Serj ixgbe_phy_x550em_kr, 3593283620Serj ixgbe_phy_x550em_kx4, 3594315333Serj ixgbe_phy_x550em_xfi, 3595283620Serj ixgbe_phy_x550em_ext_t, 3596190873Sjfv ixgbe_phy_cu_unknown, 3597171384Sjfv ixgbe_phy_qt, 3598179055Sjfv ixgbe_phy_xaui, 3599185352Sjfv ixgbe_phy_nl, 3600205720Sjfv ixgbe_phy_sfp_passive_tyco, 3601205720Sjfv ixgbe_phy_sfp_passive_unknown, 3602205720Sjfv ixgbe_phy_sfp_active_unknown, 3603185352Sjfv ixgbe_phy_sfp_avago, 3604185352Sjfv ixgbe_phy_sfp_ftl, 3605205720Sjfv ixgbe_phy_sfp_ftl_active, 3606185352Sjfv ixgbe_phy_sfp_unknown, 3607190873Sjfv ixgbe_phy_sfp_intel, 3608283620Serj ixgbe_phy_qsfp_passive_unknown, 3609283620Serj ixgbe_phy_qsfp_active_unknown, 3610283620Serj ixgbe_phy_qsfp_intel, 3611283620Serj ixgbe_phy_qsfp_unknown, 3612190873Sjfv ixgbe_phy_sfp_unsupported, /*Enforce bit set with unsupported module*/ 3613315333Serj ixgbe_phy_sgmii, 3614315333Serj ixgbe_phy_fw, 3615179055Sjfv ixgbe_phy_generic 3616171384Sjfv}; 3617171384Sjfv 3618185352Sjfv/* 3619185352Sjfv * SFP+ module type IDs: 3620185352Sjfv * 3621185352Sjfv * ID Module Type 3622185352Sjfv * ============= 3623185352Sjfv * 0 SFP_DA_CU 3624185352Sjfv * 1 SFP_SR 3625185352Sjfv * 2 SFP_LR 3626230775Sjfv * 3 SFP_DA_CU_CORE0 - 82599-specific 3627230775Sjfv * 4 SFP_DA_CU_CORE1 - 82599-specific 3628230775Sjfv * 5 SFP_SR/LR_CORE0 - 82599-specific 3629230775Sjfv * 6 SFP_SR/LR_CORE1 - 82599-specific 3630185352Sjfv */ 3631185352Sjfvenum ixgbe_sfp_type { 3632185352Sjfv ixgbe_sfp_type_da_cu = 0, 3633185352Sjfv ixgbe_sfp_type_sr = 1, 3634185352Sjfv ixgbe_sfp_type_lr = 2, 3635190873Sjfv ixgbe_sfp_type_da_cu_core0 = 3, 3636190873Sjfv ixgbe_sfp_type_da_cu_core1 = 4, 3637190873Sjfv ixgbe_sfp_type_srlr_core0 = 5, 3638190873Sjfv ixgbe_sfp_type_srlr_core1 = 6, 3639205720Sjfv ixgbe_sfp_type_da_act_lmt_core0 = 7, 3640205720Sjfv ixgbe_sfp_type_da_act_lmt_core1 = 8, 3641215911Sjfv ixgbe_sfp_type_1g_cu_core0 = 9, 3642215911Sjfv ixgbe_sfp_type_1g_cu_core1 = 10, 3643238149Sjfv ixgbe_sfp_type_1g_sx_core0 = 11, 3644238149Sjfv ixgbe_sfp_type_1g_sx_core1 = 12, 3645283620Serj ixgbe_sfp_type_1g_lx_core0 = 13, 3646283620Serj ixgbe_sfp_type_1g_lx_core1 = 14, 3647185352Sjfv ixgbe_sfp_type_not_present = 0xFFFE, 3648185352Sjfv ixgbe_sfp_type_unknown = 0xFFFF 3649185352Sjfv}; 3650185352Sjfv 3651171384Sjfvenum ixgbe_media_type { 3652171384Sjfv ixgbe_media_type_unknown = 0, 3653171384Sjfv ixgbe_media_type_fiber, 3654247822Sjfv ixgbe_media_type_fiber_fixed, 3655283620Serj ixgbe_media_type_fiber_qsfp, 3656171384Sjfv ixgbe_media_type_copper, 3657179055Sjfv ixgbe_media_type_backplane, 3658200239Sjfv ixgbe_media_type_cx4, 3659179055Sjfv ixgbe_media_type_virtual 3660171384Sjfv}; 3661171384Sjfv 3662171384Sjfv/* Flow Control Settings */ 3663185352Sjfvenum ixgbe_fc_mode { 3664171384Sjfv ixgbe_fc_none = 0, 3665171384Sjfv ixgbe_fc_rx_pause, 3666171384Sjfv ixgbe_fc_tx_pause, 3667171384Sjfv ixgbe_fc_full, 3668171384Sjfv ixgbe_fc_default 3669171384Sjfv}; 3670171384Sjfv 3671200239Sjfv/* Smart Speed Settings */ 3672200239Sjfv#define IXGBE_SMARTSPEED_MAX_RETRIES 3 3673200239Sjfvenum ixgbe_smart_speed { 3674200239Sjfv ixgbe_smart_speed_auto = 0, 3675200239Sjfv ixgbe_smart_speed_on, 3676200239Sjfv ixgbe_smart_speed_off 3677200239Sjfv}; 3678200239Sjfv 3679171384Sjfv/* PCI bus types */ 3680171384Sjfvenum ixgbe_bus_type { 3681171384Sjfv ixgbe_bus_type_unknown = 0, 3682171384Sjfv ixgbe_bus_type_pci, 3683171384Sjfv ixgbe_bus_type_pcix, 3684171384Sjfv ixgbe_bus_type_pci_express, 3685283620Serj ixgbe_bus_type_internal, 3686171384Sjfv ixgbe_bus_type_reserved 3687171384Sjfv}; 3688171384Sjfv 3689171384Sjfv/* PCI bus speeds */ 3690171384Sjfvenum ixgbe_bus_speed { 3691230775Sjfv ixgbe_bus_speed_unknown = 0, 3692230775Sjfv ixgbe_bus_speed_33 = 33, 3693230775Sjfv ixgbe_bus_speed_66 = 66, 3694230775Sjfv ixgbe_bus_speed_100 = 100, 3695230775Sjfv ixgbe_bus_speed_120 = 120, 3696230775Sjfv ixgbe_bus_speed_133 = 133, 3697230775Sjfv ixgbe_bus_speed_2500 = 2500, 3698230775Sjfv ixgbe_bus_speed_5000 = 5000, 3699238149Sjfv ixgbe_bus_speed_8000 = 8000, 3700171384Sjfv ixgbe_bus_speed_reserved 3701171384Sjfv}; 3702171384Sjfv 3703171384Sjfv/* PCI bus widths */ 3704171384Sjfvenum ixgbe_bus_width { 3705230775Sjfv ixgbe_bus_width_unknown = 0, 3706230775Sjfv ixgbe_bus_width_pcie_x1 = 1, 3707230775Sjfv ixgbe_bus_width_pcie_x2 = 2, 3708230775Sjfv ixgbe_bus_width_pcie_x4 = 4, 3709230775Sjfv ixgbe_bus_width_pcie_x8 = 8, 3710230775Sjfv ixgbe_bus_width_32 = 32, 3711230775Sjfv ixgbe_bus_width_64 = 64, 3712171384Sjfv ixgbe_bus_width_reserved 3713171384Sjfv}; 3714171384Sjfv 3715171384Sjfvstruct ixgbe_addr_filter_info { 3716171384Sjfv u32 num_mc_addrs; 3717171384Sjfv u32 rar_used_count; 3718171384Sjfv u32 mta_in_use; 3719179055Sjfv u32 overflow_promisc; 3720179055Sjfv bool user_set_promisc; 3721171384Sjfv}; 3722171384Sjfv 3723171384Sjfv/* Bus parameters */ 3724171384Sjfvstruct ixgbe_bus_info { 3725171384Sjfv enum ixgbe_bus_speed speed; 3726171384Sjfv enum ixgbe_bus_width width; 3727171384Sjfv enum ixgbe_bus_type type; 3728185352Sjfv 3729185352Sjfv u16 func; 3730315333Serj u8 lan_id; 3731315333Serj u16 instance_id; 3732171384Sjfv}; 3733171384Sjfv 3734171384Sjfv/* Flow control parameters */ 3735171384Sjfvstruct ixgbe_fc_info { 3736230775Sjfv u32 high_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl High-water */ 3737238149Sjfv u32 low_water[IXGBE_DCB_MAX_TRAFFIC_CLASS]; /* Flow Ctrl Low-water */ 3738171384Sjfv u16 pause_time; /* Flow Control Pause timer */ 3739171384Sjfv bool send_xon; /* Flow control send XON */ 3740171384Sjfv bool strict_ieee; /* Strict IEEE mode */ 3741190873Sjfv bool disable_fc_autoneg; /* Do not autonegotiate FC */ 3742190873Sjfv bool fc_was_autonegged; /* Is current_mode the result of autonegging? */ 3743185352Sjfv enum ixgbe_fc_mode current_mode; /* FC mode in effect */ 3744185352Sjfv enum ixgbe_fc_mode requested_mode; /* FC mode requested by caller */ 3745171384Sjfv}; 3746171384Sjfv 3747171384Sjfv/* Statistics counters collected by the MAC */ 3748171384Sjfvstruct ixgbe_hw_stats { 3749171384Sjfv u64 crcerrs; 3750171384Sjfv u64 illerrc; 3751171384Sjfv u64 errbc; 3752171384Sjfv u64 mspdc; 3753171384Sjfv u64 mpctotal; 3754171384Sjfv u64 mpc[8]; 3755171384Sjfv u64 mlfc; 3756171384Sjfv u64 mrfc; 3757171384Sjfv u64 rlec; 3758171384Sjfv u64 lxontxc; 3759171384Sjfv u64 lxonrxc; 3760171384Sjfv u64 lxofftxc; 3761171384Sjfv u64 lxoffrxc; 3762171384Sjfv u64 pxontxc[8]; 3763171384Sjfv u64 pxonrxc[8]; 3764171384Sjfv u64 pxofftxc[8]; 3765171384Sjfv u64 pxoffrxc[8]; 3766171384Sjfv u64 prc64; 3767171384Sjfv u64 prc127; 3768171384Sjfv u64 prc255; 3769171384Sjfv u64 prc511; 3770171384Sjfv u64 prc1023; 3771171384Sjfv u64 prc1522; 3772171384Sjfv u64 gprc; 3773171384Sjfv u64 bprc; 3774171384Sjfv u64 mprc; 3775171384Sjfv u64 gptc; 3776171384Sjfv u64 gorc; 3777171384Sjfv u64 gotc; 3778171384Sjfv u64 rnbc[8]; 3779171384Sjfv u64 ruc; 3780171384Sjfv u64 rfc; 3781171384Sjfv u64 roc; 3782171384Sjfv u64 rjc; 3783171384Sjfv u64 mngprc; 3784171384Sjfv u64 mngpdc; 3785171384Sjfv u64 mngptc; 3786171384Sjfv u64 tor; 3787171384Sjfv u64 tpr; 3788171384Sjfv u64 tpt; 3789171384Sjfv u64 ptc64; 3790171384Sjfv u64 ptc127; 3791171384Sjfv u64 ptc255; 3792171384Sjfv u64 ptc511; 3793171384Sjfv u64 ptc1023; 3794171384Sjfv u64 ptc1522; 3795171384Sjfv u64 mptc; 3796171384Sjfv u64 bptc; 3797171384Sjfv u64 xec; 3798171384Sjfv u64 qprc[16]; 3799171384Sjfv u64 qptc[16]; 3800171384Sjfv u64 qbrc[16]; 3801171384Sjfv u64 qbtc[16]; 3802190873Sjfv u64 qprdc[16]; 3803190873Sjfv u64 pxon2offc[8]; 3804190873Sjfv u64 fdirustat_add; 3805190873Sjfv u64 fdirustat_remove; 3806190873Sjfv u64 fdirfstat_fadd; 3807190873Sjfv u64 fdirfstat_fremove; 3808190873Sjfv u64 fdirmatch; 3809190873Sjfv u64 fdirmiss; 3810190873Sjfv u64 fccrc; 3811190873Sjfv u64 fclast; 3812190873Sjfv u64 fcoerpdc; 3813190873Sjfv u64 fcoeprc; 3814190873Sjfv u64 fcoeptc; 3815190873Sjfv u64 fcoedwrc; 3816190873Sjfv u64 fcoedwtc; 3817230775Sjfv u64 fcoe_noddp; 3818230775Sjfv u64 fcoe_noddp_ext_buff; 3819230775Sjfv u64 ldpcec; 3820230775Sjfv u64 pcrc8ec; 3821230775Sjfv u64 b2ospc; 3822230775Sjfv u64 b2ogprc; 3823230775Sjfv u64 o2bgptc; 3824230775Sjfv u64 o2bspc; 3825171384Sjfv}; 3826171384Sjfv 3827171384Sjfv/* forward declaration */ 3828171384Sjfvstruct ixgbe_hw; 3829171384Sjfv 3830179055Sjfv/* iterator type for walking multicast address lists */ 3831179055Sjfvtypedef u8* (*ixgbe_mc_addr_itr) (struct ixgbe_hw *hw, u8 **mc_addr_ptr, 3832230775Sjfv u32 *vmdq); 3833179055Sjfv 3834171384Sjfv/* Function pointer table */ 3835179055Sjfvstruct ixgbe_eeprom_operations { 3836179055Sjfv s32 (*init_params)(struct ixgbe_hw *); 3837179055Sjfv s32 (*read)(struct ixgbe_hw *, u16, u16 *); 3838230775Sjfv s32 (*read_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3839179055Sjfv s32 (*write)(struct ixgbe_hw *, u16, u16); 3840230775Sjfv s32 (*write_buffer)(struct ixgbe_hw *, u16, u16, u16 *); 3841179055Sjfv s32 (*validate_checksum)(struct ixgbe_hw *, u16 *); 3842179055Sjfv s32 (*update_checksum)(struct ixgbe_hw *); 3843283620Serj s32 (*calc_checksum)(struct ixgbe_hw *); 3844179055Sjfv}; 3845171384Sjfv 3846179055Sjfvstruct ixgbe_mac_operations { 3847179055Sjfv s32 (*init_hw)(struct ixgbe_hw *); 3848179055Sjfv s32 (*reset_hw)(struct ixgbe_hw *); 3849179055Sjfv s32 (*start_hw)(struct ixgbe_hw *); 3850179055Sjfv s32 (*clear_hw_cntrs)(struct ixgbe_hw *); 3851205720Sjfv void (*enable_relaxed_ordering)(struct ixgbe_hw *); 3852179055Sjfv enum ixgbe_media_type (*get_media_type)(struct ixgbe_hw *); 3853185352Sjfv u32 (*get_supported_physical_layer)(struct ixgbe_hw *); 3854179055Sjfv s32 (*get_mac_addr)(struct ixgbe_hw *, u8 *); 3855190873Sjfv s32 (*get_san_mac_addr)(struct ixgbe_hw *, u8 *); 3856190873Sjfv s32 (*set_san_mac_addr)(struct ixgbe_hw *, u8 *); 3857190873Sjfv s32 (*get_device_caps)(struct ixgbe_hw *, u16 *); 3858200239Sjfv s32 (*get_wwn_prefix)(struct ixgbe_hw *, u16 *, u16 *); 3859215911Sjfv s32 (*get_fcoe_boot_status)(struct ixgbe_hw *, u16 *); 3860179055Sjfv s32 (*stop_adapter)(struct ixgbe_hw *); 3861179055Sjfv s32 (*get_bus_info)(struct ixgbe_hw *); 3862185352Sjfv void (*set_lan_id)(struct ixgbe_hw *); 3863179055Sjfv s32 (*read_analog_reg8)(struct ixgbe_hw*, u32, u8*); 3864179055Sjfv s32 (*write_analog_reg8)(struct ixgbe_hw*, u32, u8); 3865190873Sjfv s32 (*setup_sfp)(struct ixgbe_hw *); 3866190873Sjfv s32 (*enable_rx_dma)(struct ixgbe_hw *, u32); 3867230775Sjfv s32 (*disable_sec_rx_path)(struct ixgbe_hw *); 3868230775Sjfv s32 (*enable_sec_rx_path)(struct ixgbe_hw *); 3869283620Serj s32 (*acquire_swfw_sync)(struct ixgbe_hw *, u32); 3870283620Serj void (*release_swfw_sync)(struct ixgbe_hw *, u32); 3871315333Serj void (*init_swfw_sync)(struct ixgbe_hw *); 3872283620Serj s32 (*prot_autoc_read)(struct ixgbe_hw *, bool *, u32 *); 3873283620Serj s32 (*prot_autoc_write)(struct ixgbe_hw *, u32, bool); 3874179055Sjfv 3875171384Sjfv /* Link */ 3876215911Sjfv void (*disable_tx_laser)(struct ixgbe_hw *); 3877215911Sjfv void (*enable_tx_laser)(struct ixgbe_hw *); 3878215911Sjfv void (*flap_tx_laser)(struct ixgbe_hw *); 3879247822Sjfv s32 (*setup_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3880283620Serj s32 (*setup_mac_link)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3881179055Sjfv s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *, bool); 3882179055Sjfv s32 (*get_link_capabilities)(struct ixgbe_hw *, ixgbe_link_speed *, 3883230775Sjfv bool *); 3884283620Serj void (*set_rate_select_speed)(struct ixgbe_hw *, ixgbe_link_speed); 3885171384Sjfv 3886230775Sjfv /* Packet Buffer manipulation */ 3887230775Sjfv void (*setup_rxpba)(struct ixgbe_hw *, int, u32, int); 3888230775Sjfv 3889171384Sjfv /* LED */ 3890179055Sjfv s32 (*led_on)(struct ixgbe_hw *, u32); 3891179055Sjfv s32 (*led_off)(struct ixgbe_hw *, u32); 3892179055Sjfv s32 (*blink_led_start)(struct ixgbe_hw *, u32); 3893179055Sjfv s32 (*blink_led_stop)(struct ixgbe_hw *, u32); 3894315333Serj s32 (*init_led_link_act)(struct ixgbe_hw *); 3895171384Sjfv 3896171384Sjfv /* RAR, Multicast, VLAN */ 3897179055Sjfv s32 (*set_rar)(struct ixgbe_hw *, u32, u8 *, u32, u32); 3898230775Sjfv s32 (*set_uc_addr)(struct ixgbe_hw *, u32, u8 *); 3899181003Sjfv s32 (*clear_rar)(struct ixgbe_hw *, u32); 3900190873Sjfv s32 (*insert_mac_addr)(struct ixgbe_hw *, u8 *, u32); 3901179055Sjfv s32 (*set_vmdq)(struct ixgbe_hw *, u32, u32); 3902238149Sjfv s32 (*set_vmdq_san_mac)(struct ixgbe_hw *, u32); 3903181003Sjfv s32 (*clear_vmdq)(struct ixgbe_hw *, u32, u32); 3904179055Sjfv s32 (*init_rx_addrs)(struct ixgbe_hw *); 3905179055Sjfv s32 (*update_uc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3906230775Sjfv ixgbe_mc_addr_itr); 3907179055Sjfv s32 (*update_mc_addr_list)(struct ixgbe_hw *, u8 *, u32, 3908230775Sjfv ixgbe_mc_addr_itr, bool clear); 3909179055Sjfv s32 (*enable_mc)(struct ixgbe_hw *); 3910179055Sjfv s32 (*disable_mc)(struct ixgbe_hw *); 3911179055Sjfv s32 (*clear_vfta)(struct ixgbe_hw *); 3912315333Serj s32 (*set_vfta)(struct ixgbe_hw *, u32, u32, bool, bool); 3913315333Serj s32 (*set_vlvf)(struct ixgbe_hw *, u32, u32, bool, u32 *, u32, 3914315333Serj bool); 3915181003Sjfv s32 (*init_uta_tables)(struct ixgbe_hw *); 3916215911Sjfv void (*set_mac_anti_spoofing)(struct ixgbe_hw *, bool, int); 3917215911Sjfv void (*set_vlan_anti_spoofing)(struct ixgbe_hw *, bool, int); 3918171384Sjfv 3919171384Sjfv /* Flow Control */ 3920238149Sjfv s32 (*fc_enable)(struct ixgbe_hw *); 3921283620Serj s32 (*setup_fc)(struct ixgbe_hw *); 3922315333Serj void (*fc_autoneg)(struct ixgbe_hw *); 3923230775Sjfv 3924230775Sjfv /* Manageability interface */ 3925315333Serj s32 (*set_fw_drv_ver)(struct ixgbe_hw *, u8, u8, u8, u8, u16, 3926315333Serj const char *); 3927315333Serj s32 (*bypass_rw) (struct ixgbe_hw *hw, u32 cmd, u32 *status); 3928315333Serj bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg); 3929315333Serj s32 (*bypass_set) (struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action); 3930315333Serj s32 (*bypass_rd_eep) (struct ixgbe_hw *hw, u32 addr, u8 *value); 3931283620Serj void (*get_rtrup2tc)(struct ixgbe_hw *hw, u8 *map); 3932283620Serj void (*disable_rx)(struct ixgbe_hw *hw); 3933283620Serj void (*enable_rx)(struct ixgbe_hw *hw); 3934283620Serj void (*set_source_address_pruning)(struct ixgbe_hw *, bool, 3935283620Serj unsigned int); 3936283620Serj void (*set_ethertype_anti_spoofing)(struct ixgbe_hw *, bool, int); 3937251964Sjfv s32 (*dmac_update_tcs)(struct ixgbe_hw *hw); 3938251964Sjfv s32 (*dmac_config_tcs)(struct ixgbe_hw *hw); 3939283620Serj s32 (*dmac_config)(struct ixgbe_hw *hw); 3940283620Serj s32 (*setup_eee)(struct ixgbe_hw *hw, bool enable_eee); 3941283620Serj s32 (*read_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32 *); 3942283620Serj s32 (*write_iosf_sb_reg)(struct ixgbe_hw *, u32, u32, u32); 3943283620Serj void (*disable_mdd)(struct ixgbe_hw *hw); 3944283620Serj void (*enable_mdd)(struct ixgbe_hw *hw); 3945283620Serj void (*mdd_event)(struct ixgbe_hw *hw, u32 *vf_bitmap); 3946283620Serj void (*restore_mdd_vf)(struct ixgbe_hw *hw, u32 vf); 3947171384Sjfv}; 3948171384Sjfv 3949179055Sjfvstruct ixgbe_phy_operations { 3950179055Sjfv s32 (*identify)(struct ixgbe_hw *); 3951185352Sjfv s32 (*identify_sfp)(struct ixgbe_hw *); 3952190873Sjfv s32 (*init)(struct ixgbe_hw *); 3953179055Sjfv s32 (*reset)(struct ixgbe_hw *); 3954179055Sjfv s32 (*read_reg)(struct ixgbe_hw *, u32, u32, u16 *); 3955179055Sjfv s32 (*write_reg)(struct ixgbe_hw *, u32, u32, u16); 3956251964Sjfv s32 (*read_reg_mdi)(struct ixgbe_hw *, u32, u32, u16 *); 3957251964Sjfv s32 (*write_reg_mdi)(struct ixgbe_hw *, u32, u32, u16); 3958179055Sjfv s32 (*setup_link)(struct ixgbe_hw *); 3959283620Serj s32 (*setup_internal_link)(struct ixgbe_hw *); 3960247822Sjfv s32 (*setup_link_speed)(struct ixgbe_hw *, ixgbe_link_speed, bool); 3961179055Sjfv s32 (*check_link)(struct ixgbe_hw *, ixgbe_link_speed *, bool *); 3962179055Sjfv s32 (*get_firmware_version)(struct ixgbe_hw *, u16 *); 3963185352Sjfv s32 (*read_i2c_byte)(struct ixgbe_hw *, u8, u8, u8 *); 3964185352Sjfv s32 (*write_i2c_byte)(struct ixgbe_hw *, u8, u8, u8); 3965247822Sjfv s32 (*read_i2c_sff8472)(struct ixgbe_hw *, u8 , u8 *); 3966185352Sjfv s32 (*read_i2c_eeprom)(struct ixgbe_hw *, u8 , u8 *); 3967185352Sjfv s32 (*write_i2c_eeprom)(struct ixgbe_hw *, u8, u8); 3968190873Sjfv void (*i2c_bus_clear)(struct ixgbe_hw *); 3969205720Sjfv s32 (*check_overtemp)(struct ixgbe_hw *); 3970283620Serj s32 (*set_phy_power)(struct ixgbe_hw *, bool on); 3971283620Serj s32 (*enter_lplu)(struct ixgbe_hw *); 3972283620Serj s32 (*handle_lasi)(struct ixgbe_hw *hw); 3973283620Serj s32 (*read_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 3974283620Serj u8 *value); 3975283620Serj s32 (*write_i2c_byte_unlocked)(struct ixgbe_hw *, u8 offset, u8 addr, 3976283620Serj u8 value); 3977179055Sjfv}; 3978179055Sjfv 3979315333Serjstruct ixgbe_link_operations { 3980315333Serj s32 (*read_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 *val); 3981315333Serj s32 (*read_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 3982315333Serj u16 *val); 3983315333Serj s32 (*write_link)(struct ixgbe_hw *, u8 addr, u16 reg, u16 val); 3984315333Serj s32 (*write_link_unlocked)(struct ixgbe_hw *, u8 addr, u16 reg, 3985315333Serj u16 val); 3986315333Serj}; 3987315333Serj 3988315333Serjstruct ixgbe_link_info { 3989315333Serj struct ixgbe_link_operations ops; 3990315333Serj u8 addr; 3991315333Serj}; 3992315333Serj 3993179055Sjfvstruct ixgbe_eeprom_info { 3994230775Sjfv struct ixgbe_eeprom_operations ops; 3995230775Sjfv enum ixgbe_eeprom_type type; 3996230775Sjfv u32 semaphore_delay; 3997230775Sjfv u16 word_size; 3998230775Sjfv u16 address_bits; 3999230775Sjfv u16 word_page_size; 4000283620Serj u16 ctrl_word_3; 4001179055Sjfv}; 4002179055Sjfv 4003205720Sjfv#define IXGBE_FLAGS_DOUBLE_RESET_REQUIRED 0x01 4004171384Sjfvstruct ixgbe_mac_info { 4005230775Sjfv struct ixgbe_mac_operations ops; 4006230775Sjfv enum ixgbe_mac_type type; 4007230775Sjfv u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4008230775Sjfv u8 perm_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4009230775Sjfv u8 san_addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 4010200239Sjfv /* prefix for World Wide Node Name (WWNN) */ 4011230775Sjfv u16 wwnn_prefix; 4012200239Sjfv /* prefix for World Wide Port Name (WWPN) */ 4013230775Sjfv u16 wwpn_prefix; 4014215911Sjfv#define IXGBE_MAX_MTA 128 4015230775Sjfv u32 mta_shadow[IXGBE_MAX_MTA]; 4016230775Sjfv s32 mc_filter_type; 4017230775Sjfv u32 mcft_size; 4018230775Sjfv u32 vft_size; 4019230775Sjfv u32 num_rar_entries; 4020230775Sjfv u32 rar_highwater; 4021230775Sjfv u32 rx_pb_size; 4022230775Sjfv u32 max_tx_queues; 4023230775Sjfv u32 max_rx_queues; 4024230775Sjfv u32 orig_autoc; 4025238149Sjfv u8 san_mac_rar_index; 4026247822Sjfv bool get_link_status; 4027238149Sjfv u32 orig_autoc2; 4028238149Sjfv u16 max_msix_vectors; 4029230775Sjfv bool arc_subsystem_valid; 4030230775Sjfv bool orig_link_settings_stored; 4031230775Sjfv bool autotry_restart; 4032230775Sjfv u8 flags; 4033283620Serj struct ixgbe_dmac_config dmac_config; 4034283620Serj bool set_lben; 4035295524Ssbruno u32 max_link_up_time; 4036315333Serj u8 led_link_act; 4037171384Sjfv}; 4038171384Sjfv 4039171384Sjfvstruct ixgbe_phy_info { 4040230775Sjfv struct ixgbe_phy_operations ops; 4041230775Sjfv enum ixgbe_phy_type type; 4042230775Sjfv u32 addr; 4043230775Sjfv u32 id; 4044230775Sjfv enum ixgbe_sfp_type sfp_type; 4045230775Sjfv bool sfp_setup_needed; 4046230775Sjfv u32 revision; 4047230775Sjfv enum ixgbe_media_type media_type; 4048283620Serj u32 phy_semaphore_mask; 4049230775Sjfv bool reset_disable; 4050230775Sjfv ixgbe_autoneg_advertised autoneg_advertised; 4051295524Ssbruno ixgbe_link_speed speeds_supported; 4052315333Serj ixgbe_link_speed eee_speeds_supported; 4053315333Serj ixgbe_link_speed eee_speeds_advertised; 4054230775Sjfv enum ixgbe_smart_speed smart_speed; 4055230775Sjfv bool smart_speed_active; 4056230775Sjfv bool multispeed_fiber; 4057230775Sjfv bool reset_if_overtemp; 4058283620Serj bool qsfp_shared_i2c_bus; 4059283620Serj u32 nw_mng_if_sel; 4060171384Sjfv}; 4061171384Sjfv 4062215911Sjfv#include "ixgbe_mbx.h" 4063215911Sjfv 4064215911Sjfvstruct ixgbe_mbx_operations { 4065215911Sjfv void (*init_params)(struct ixgbe_hw *hw); 4066215911Sjfv s32 (*read)(struct ixgbe_hw *, u32 *, u16, u16); 4067215911Sjfv s32 (*write)(struct ixgbe_hw *, u32 *, u16, u16); 4068215911Sjfv s32 (*read_posted)(struct ixgbe_hw *, u32 *, u16, u16); 4069215911Sjfv s32 (*write_posted)(struct ixgbe_hw *, u32 *, u16, u16); 4070215911Sjfv s32 (*check_for_msg)(struct ixgbe_hw *, u16); 4071215911Sjfv s32 (*check_for_ack)(struct ixgbe_hw *, u16); 4072215911Sjfv s32 (*check_for_rst)(struct ixgbe_hw *, u16); 4073215911Sjfv}; 4074215911Sjfv 4075215911Sjfvstruct ixgbe_mbx_stats { 4076215911Sjfv u32 msgs_tx; 4077215911Sjfv u32 msgs_rx; 4078215911Sjfv 4079215911Sjfv u32 acks; 4080215911Sjfv u32 reqs; 4081215911Sjfv u32 rsts; 4082215911Sjfv}; 4083215911Sjfv 4084215911Sjfvstruct ixgbe_mbx_info { 4085215911Sjfv struct ixgbe_mbx_operations ops; 4086215911Sjfv struct ixgbe_mbx_stats stats; 4087215911Sjfv u32 timeout; 4088215911Sjfv u32 usec_delay; 4089215911Sjfv u32 v2p_mailbox; 4090215911Sjfv u16 size; 4091215911Sjfv}; 4092215911Sjfv 4093171384Sjfvstruct ixgbe_hw { 4094283620Serj u8 IOMEM *hw_addr; 4095230775Sjfv void *back; 4096230775Sjfv struct ixgbe_mac_info mac; 4097230775Sjfv struct ixgbe_addr_filter_info addr_ctrl; 4098230775Sjfv struct ixgbe_fc_info fc; 4099230775Sjfv struct ixgbe_phy_info phy; 4100315333Serj struct ixgbe_link_info link; 4101230775Sjfv struct ixgbe_eeprom_info eeprom; 4102230775Sjfv struct ixgbe_bus_info bus; 4103230775Sjfv struct ixgbe_mbx_info mbx; 4104283620Serj const u32 *mvals; 4105230775Sjfv u16 device_id; 4106230775Sjfv u16 vendor_id; 4107230775Sjfv u16 subsystem_device_id; 4108230775Sjfv u16 subsystem_vendor_id; 4109230775Sjfv u8 revision_id; 4110230775Sjfv bool adapter_stopped; 4111247822Sjfv int api_version; 4112230775Sjfv bool force_full_reset; 4113238149Sjfv bool allow_unsupported_sfp; 4114251964Sjfv bool wol_enabled; 4115315333Serj bool need_crosstalk_fix; 4116171384Sjfv}; 4117171384Sjfv 4118171384Sjfv#define ixgbe_call_func(hw, func, params, error) \ 4119230775Sjfv (func != NULL) ? func params : error 4120171384Sjfv 4121194875Sjfv 4122171384Sjfv/* Error Codes */ 4123230775Sjfv#define IXGBE_SUCCESS 0 4124230775Sjfv#define IXGBE_ERR_EEPROM -1 4125230775Sjfv#define IXGBE_ERR_EEPROM_CHECKSUM -2 4126230775Sjfv#define IXGBE_ERR_PHY -3 4127230775Sjfv#define IXGBE_ERR_CONFIG -4 4128230775Sjfv#define IXGBE_ERR_PARAM -5 4129230775Sjfv#define IXGBE_ERR_MAC_TYPE -6 4130230775Sjfv#define IXGBE_ERR_UNKNOWN_PHY -7 4131230775Sjfv#define IXGBE_ERR_LINK_SETUP -8 4132230775Sjfv#define IXGBE_ERR_ADAPTER_STOPPED -9 4133230775Sjfv#define IXGBE_ERR_INVALID_MAC_ADDR -10 4134230775Sjfv#define IXGBE_ERR_DEVICE_NOT_SUPPORTED -11 4135230775Sjfv#define IXGBE_ERR_MASTER_REQUESTS_PENDING -12 4136230775Sjfv#define IXGBE_ERR_INVALID_LINK_SETTINGS -13 4137230775Sjfv#define IXGBE_ERR_AUTONEG_NOT_COMPLETE -14 4138230775Sjfv#define IXGBE_ERR_RESET_FAILED -15 4139230775Sjfv#define IXGBE_ERR_SWFW_SYNC -16 4140230775Sjfv#define IXGBE_ERR_PHY_ADDR_INVALID -17 4141230775Sjfv#define IXGBE_ERR_I2C -18 4142230775Sjfv#define IXGBE_ERR_SFP_NOT_SUPPORTED -19 4143230775Sjfv#define IXGBE_ERR_SFP_NOT_PRESENT -20 4144230775Sjfv#define IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT -21 4145230775Sjfv#define IXGBE_ERR_NO_SAN_ADDR_PTR -22 4146230775Sjfv#define IXGBE_ERR_FDIR_REINIT_FAILED -23 4147230775Sjfv#define IXGBE_ERR_EEPROM_VERSION -24 4148230775Sjfv#define IXGBE_ERR_NO_SPACE -25 4149230775Sjfv#define IXGBE_ERR_OVERTEMP -26 4150230775Sjfv#define IXGBE_ERR_FC_NOT_NEGOTIATED -27 4151230775Sjfv#define IXGBE_ERR_FC_NOT_SUPPORTED -28 4152230775Sjfv#define IXGBE_ERR_SFP_SETUP_NOT_COMPLETE -30 4153230775Sjfv#define IXGBE_ERR_PBA_SECTION -31 4154230775Sjfv#define IXGBE_ERR_INVALID_ARGUMENT -32 4155230775Sjfv#define IXGBE_ERR_HOST_INTERFACE_COMMAND -33 4156230775Sjfv#define IXGBE_ERR_OUT_OF_MEM -34 4157315333Serj#define IXGBE_BYPASS_FW_WRITE_FAILURE -35 4158247822Sjfv#define IXGBE_ERR_FEATURE_NOT_SUPPORTED -36 4159251964Sjfv#define IXGBE_ERR_EEPROM_PROTECTED_REGION -37 4160283620Serj#define IXGBE_ERR_FDIR_CMD_INCOMPLETE -38 4161315333Serj#define IXGBE_ERR_FW_RESP_INVALID -39 4162315333Serj#define IXGBE_ERR_TOKEN_RETRY -40 4163171384Sjfv 4164230775Sjfv#define IXGBE_NOT_IMPLEMENTED 0x7FFFFFFF 4165171384Sjfv 4166283620Serj 4167315333Serj#define BYPASS_PAGE_CTL0 0x00000000 4168315333Serj#define BYPASS_PAGE_CTL1 0x40000000 4169315333Serj#define BYPASS_PAGE_CTL2 0x80000000 4170315333Serj#define BYPASS_PAGE_M 0xc0000000 4171315333Serj#define BYPASS_WE 0x20000000 4172315333Serj 4173315333Serj#define BYPASS_AUTO 0x0 4174315333Serj#define BYPASS_NOP 0x0 4175315333Serj#define BYPASS_NORM 0x1 4176315333Serj#define BYPASS_BYPASS 0x2 4177315333Serj#define BYPASS_ISOLATE 0x3 4178315333Serj 4179315333Serj#define BYPASS_EVENT_MAIN_ON 0x1 4180315333Serj#define BYPASS_EVENT_AUX_ON 0x2 4181315333Serj#define BYPASS_EVENT_MAIN_OFF 0x3 4182315333Serj#define BYPASS_EVENT_AUX_OFF 0x4 4183315333Serj#define BYPASS_EVENT_WDT_TO 0x5 4184315333Serj#define BYPASS_EVENT_USR 0x6 4185315333Serj 4186315333Serj#define BYPASS_MODE_OFF_M 0x00000003 4187315333Serj#define BYPASS_STATUS_OFF_M 0x0000000c 4188315333Serj#define BYPASS_AUX_ON_M 0x00000030 4189315333Serj#define BYPASS_MAIN_ON_M 0x000000c0 4190315333Serj#define BYPASS_MAIN_OFF_M 0x00000300 4191315333Serj#define BYPASS_AUX_OFF_M 0x00000c00 4192315333Serj#define BYPASS_WDTIMEOUT_M 0x00003000 4193315333Serj#define BYPASS_WDT_ENABLE_M 0x00004000 4194315333Serj#define BYPASS_WDT_VALUE_M 0x00070000 4195315333Serj 4196315333Serj#define BYPASS_MODE_OFF_SHIFT 0 4197315333Serj#define BYPASS_STATUS_OFF_SHIFT 2 4198315333Serj#define BYPASS_AUX_ON_SHIFT 4 4199315333Serj#define BYPASS_MAIN_ON_SHIFT 6 4200315333Serj#define BYPASS_MAIN_OFF_SHIFT 8 4201315333Serj#define BYPASS_AUX_OFF_SHIFT 10 4202315333Serj#define BYPASS_WDTIMEOUT_SHIFT 12 4203315333Serj#define BYPASS_WDT_ENABLE_SHIFT 14 4204315333Serj#define BYPASS_WDT_TIME_SHIFT 16 4205315333Serj 4206315333Serj#define BYPASS_WDT_1 0x0 4207315333Serj#define BYPASS_WDT_1_5 0x1 4208315333Serj#define BYPASS_WDT_2 0x2 4209315333Serj#define BYPASS_WDT_3 0x3 4210315333Serj#define BYPASS_WDT_4 0x4 4211315333Serj#define BYPASS_WDT_8 0x5 4212315333Serj#define BYPASS_WDT_16 0x6 4213315333Serj#define BYPASS_WDT_32 0x7 4214315333Serj#define BYPASS_WDT_OFF 0xffff 4215315333Serj 4216315333Serj#define BYPASS_CTL1_TIME_M 0x01ffffff 4217315333Serj#define BYPASS_CTL1_VALID_M 0x02000000 4218315333Serj#define BYPASS_CTL1_OFFTRST_M 0x04000000 4219315333Serj#define BYPASS_CTL1_WDT_PET_M 0x08000000 4220315333Serj 4221315333Serj#define BYPASS_CTL1_VALID 0x02000000 4222315333Serj#define BYPASS_CTL1_OFFTRST 0x04000000 4223315333Serj#define BYPASS_CTL1_WDT_PET 0x08000000 4224315333Serj 4225315333Serj#define BYPASS_CTL2_DATA_M 0x000000ff 4226315333Serj#define BYPASS_CTL2_OFFSET_M 0x0000ff00 4227315333Serj#define BYPASS_CTL2_RW_M 0x00010000 4228315333Serj#define BYPASS_CTL2_HEAD_M 0x0ff00000 4229315333Serj 4230315333Serj#define BYPASS_CTL2_OFFSET_SHIFT 8 4231315333Serj#define BYPASS_CTL2_HEAD_SHIFT 20 4232315333Serj 4233315333Serj#define BYPASS_CTL2_RW 0x00010000 4234315333Serj 4235315333Serjstruct ixgbe_bypass_eeprom { 4236315333Serj u32 logs; 4237315333Serj u32 clear_off; 4238315333Serj u8 actions; 4239315333Serj}; 4240315333Serj 4241315333Serj#define BYPASS_MAX_LOGS 43 4242315333Serj#define BYPASS_LOG_SIZE 5 4243315333Serj#define BYPASS_LOG_LINE_SIZE 37 4244315333Serj 4245315333Serj#define BYPASS_EEPROM_VER_ADD 0x02 4246315333Serj 4247315333Serj#define BYPASS_LOG_TIME_M 0x01ffffff 4248315333Serj#define BYPASS_LOG_TIME_VALID_M 0x02000000 4249315333Serj#define BYPASS_LOG_HEAD_M 0x04000000 4250315333Serj#define BYPASS_LOG_CLEAR_M 0x08000000 4251315333Serj#define BYPASS_LOG_EVENT_M 0xf0000000 4252315333Serj#define BYPASS_LOG_ACTION_M 0x03 4253315333Serj 4254315333Serj#define BYPASS_LOG_EVENT_SHIFT 28 4255315333Serj#define BYPASS_LOG_CLEAR_SHIFT 24 /* bit offset */ 4256315333Serj 4257315333Serj 4258283620Serj#define IXGBE_FUSES0_GROUP(_i) (0x11158 + ((_i) * 4)) 4259283620Serj#define IXGBE_FUSES0_300MHZ (1 << 5) 4260315333Serj#define IXGBE_FUSES0_REV_MASK (3 << 6) 4261283620Serj 4262295524Ssbruno#define IXGBE_KRM_PORT_CAR_GEN_CTRL(P) ((P) ? 0x8010 : 0x4010) 4263315333Serj#define IXGBE_KRM_LINK_S1(P) ((P) ? 0x8200 : 0x4200) 4264295524Ssbruno#define IXGBE_KRM_LINK_CTRL_1(P) ((P) ? 0x820C : 0x420C) 4265295524Ssbruno#define IXGBE_KRM_AN_CNTL_1(P) ((P) ? 0x822C : 0x422C) 4266315333Serj#define IXGBE_KRM_AN_CNTL_4(P) ((P) ? 0x8238 : 0x4238) 4267315333Serj#define IXGBE_KRM_AN_CNTL_8(P) ((P) ? 0x8248 : 0x4248) 4268315333Serj#define IXGBE_KRM_PCS_KX_AN(P) ((P) ? 0x9918 : 0x5918) 4269315333Serj#define IXGBE_KRM_PCS_KX_AN_LP(P) ((P) ? 0x991C : 0x591C) 4270315333Serj#define IXGBE_KRM_SGMII_CTRL(P) ((P) ? 0x82A0 : 0x42A0) 4271315333Serj#define IXGBE_KRM_LP_BASE_PAGE_HIGH(P) ((P) ? 0x836C : 0x436C) 4272295524Ssbruno#define IXGBE_KRM_DSP_TXFFE_STATE_4(P) ((P) ? 0x8634 : 0x4634) 4273295524Ssbruno#define IXGBE_KRM_DSP_TXFFE_STATE_5(P) ((P) ? 0x8638 : 0x4638) 4274295524Ssbruno#define IXGBE_KRM_RX_TRN_LINKUP_CTRL(P) ((P) ? 0x8B00 : 0x4B00) 4275295524Ssbruno#define IXGBE_KRM_PMD_DFX_BURNIN(P) ((P) ? 0x8E00 : 0x4E00) 4276315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20(P) ((P) ? 0x9054 : 0x5054) 4277295524Ssbruno#define IXGBE_KRM_TX_COEFF_CTRL_1(P) ((P) ? 0x9520 : 0x5520) 4278295524Ssbruno#define IXGBE_KRM_RX_ANA_CTL(P) ((P) ? 0x9A00 : 0x5A00) 4279283620Serj 4280315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_DA ~(0x3 << 20) 4281315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_SR (1u << 20) 4282315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SFI_10G_LR (0x2 << 20) 4283315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SGMII_EN (1u << 25) 4284315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN37_EN (1u << 26) 4285315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_AN_EN (1u << 27) 4286315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10M ~(0x7 << 28) 4287315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_100M (1u << 28) 4288315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_1G (0x2 << 28) 4289315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_10G (0x3 << 28) 4290315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_AN (0x4 << 28) 4291315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_2_5G (0x7 << 28) 4292315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_SPEED_MASK (0x7 << 28) 4293315333Serj#define IXGBE_KRM_PMD_FLX_MASK_ST20_FW_AN_RESTART (1u << 31) 4294315333Serj 4295283620Serj#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_32B (1 << 9) 4296283620Serj#define IXGBE_KRM_PORT_CAR_GEN_CTRL_NELB_KRPCS (1 << 11) 4297283620Serj 4298283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_MASK (0x7 << 8) 4299283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_1G (2 << 8) 4300283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_FORCE_SPEED_10G (4 << 8) 4301315333Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_SGMII_EN (1 << 12) 4302315333Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CLAUSE_37_EN (1 << 13) 4303283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_FEC_REQ (1 << 14) 4304283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_FEC (1 << 15) 4305283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KX (1 << 16) 4306283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_CAP_KR (1 << 18) 4307283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KX (1 << 24) 4308283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_EEE_CAP_KR (1 << 26) 4309315333Serj#define IXGBE_KRM_LINK_S1_MAC_AN_COMPLETE (1 << 28) 4310283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_ENABLE (1 << 29) 4311283620Serj#define IXGBE_KRM_LINK_CTRL_1_TETH_AN_RESTART (1 << 31) 4312283620Serj 4313283620Serj#define IXGBE_KRM_AN_CNTL_1_SYM_PAUSE (1 << 28) 4314283620Serj#define IXGBE_KRM_AN_CNTL_1_ASM_PAUSE (1 << 29) 4315315333Serj#define IXGBE_KRM_PCS_KX_AN_SYM_PAUSE (1 << 1) 4316315333Serj#define IXGBE_KRM_PCS_KX_AN_ASM_PAUSE (1 << 2) 4317315333Serj#define IXGBE_KRM_PCS_KX_AN_LP_SYM_PAUSE (1 << 2) 4318315333Serj#define IXGBE_KRM_PCS_KX_AN_LP_ASM_PAUSE (1 << 3) 4319315333Serj#define IXGBE_KRM_AN_CNTL_4_ECSR_AN37_OVER_73 (1 << 29) 4320315333Serj#define IXGBE_KRM_AN_CNTL_8_LINEAR (1 << 0) 4321315333Serj#define IXGBE_KRM_AN_CNTL_8_LIMITING (1 << 1) 4322283620Serj 4323315333Serj#define IXGBE_KRM_LP_BASE_PAGE_HIGH_SYM_PAUSE (1 << 10) 4324315333Serj#define IXGBE_KRM_LP_BASE_PAGE_HIGH_ASM_PAUSE (1 << 11) 4325315333Serj 4326315333Serj#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_100_D (1 << 12) 4327315333Serj#define IXGBE_KRM_SGMII_CTRL_MAC_TAR_FORCE_10_D (1 << 19) 4328315333Serj 4329283620Serj#define IXGBE_KRM_DSP_TXFFE_STATE_C0_EN (1 << 6) 4330283620Serj#define IXGBE_KRM_DSP_TXFFE_STATE_CP1_CN1_EN (1 << 15) 4331283620Serj#define IXGBE_KRM_DSP_TXFFE_STATE_CO_ADAPT_EN (1 << 16) 4332283620Serj 4333283620Serj#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_CONV_WO_PROTOCOL (1 << 4) 4334283620Serj#define IXGBE_KRM_RX_TRN_LINKUP_CTRL_PROTOCOL_BYPASS (1 << 2) 4335283620Serj 4336283620Serj#define IXGBE_KRM_PMD_DFX_BURNIN_TX_RX_KR_LB_MASK (0x3 << 16) 4337283620Serj 4338283620Serj#define IXGBE_KRM_TX_COEFF_CTRL_1_CMINUS1_OVRRD_EN (1 << 1) 4339283620Serj#define IXGBE_KRM_TX_COEFF_CTRL_1_CPLUS1_OVRRD_EN (1 << 2) 4340283620Serj#define IXGBE_KRM_TX_COEFF_CTRL_1_CZERO_EN (1 << 3) 4341283620Serj#define IXGBE_KRM_TX_COEFF_CTRL_1_OVRRD_EN (1 << 31) 4342283620Serj 4343283620Serj#define IXGBE_SB_IOSF_INDIRECT_CTRL 0x00011144 4344283620Serj#define IXGBE_SB_IOSF_INDIRECT_DATA 0x00011148 4345283620Serj 4346283620Serj#define IXGBE_SB_IOSF_CTRL_ADDR_SHIFT 0 4347283620Serj#define IXGBE_SB_IOSF_CTRL_ADDR_MASK 0xFF 4348283620Serj#define IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT 18 4349283620Serj#define IXGBE_SB_IOSF_CTRL_RESP_STAT_MASK \ 4350283620Serj (0x3 << IXGBE_SB_IOSF_CTRL_RESP_STAT_SHIFT) 4351283620Serj#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT 20 4352283620Serj#define IXGBE_SB_IOSF_CTRL_CMPL_ERR_MASK \ 4353283620Serj (0xFF << IXGBE_SB_IOSF_CTRL_CMPL_ERR_SHIFT) 4354283620Serj#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_SHIFT 28 4355283620Serj#define IXGBE_SB_IOSF_CTRL_TARGET_SELECT_MASK 0x7 4356283620Serj#define IXGBE_SB_IOSF_CTRL_BUSY_SHIFT 31 4357283620Serj#define IXGBE_SB_IOSF_CTRL_BUSY (1 << IXGBE_SB_IOSF_CTRL_BUSY_SHIFT) 4358283620Serj#define IXGBE_SB_IOSF_TARGET_KR_PHY 0 4359283620Serj 4360283620Serj#define IXGBE_NW_MNG_IF_SEL 0x00011178 4361315333Serj#define IXGBE_NW_MNG_IF_SEL_MDIO_ACT (1u << 1) 4362315333Serj#define IXGBE_NW_MNG_IF_SEL_MDIO_IF_MODE (1u << 2) 4363315333Serj#define IXGBE_NW_MNG_IF_SEL_EN_SHARED_MDIO (1u << 13) 4364315333Serj#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10M (1u << 17) 4365315333Serj#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_100M (1u << 18) 4366315333Serj#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_1G (1u << 19) 4367315333Serj#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_2_5G (1u << 20) 4368315333Serj#define IXGBE_NW_MNG_IF_SEL_PHY_SPEED_10G (1u << 21) 4369315333Serj#define IXGBE_NW_MNG_IF_SEL_SGMII_ENABLE (1u << 25) 4370315333Serj#define IXGBE_NW_MNG_IF_SEL_INT_PHY_MODE (1 << 24) /* X552 reg field only */ 4371315333Serj#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT 3 4372315333Serj#define IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD \ 4373315333Serj (0x1F << IXGBE_NW_MNG_IF_SEL_MDIO_PHY_ADD_SHIFT) 4374283620Serj 4375171384Sjfv#endif /* _IXGBE_TYPE_H_ */ 4376