1315333Serj/******************************************************************************
2315333Serj
3315333Serj  Copyright (c) 2001-2017, Intel Corporation
4315333Serj  All rights reserved.
5315333Serj
6315333Serj  Redistribution and use in source and binary forms, with or without
7315333Serj  modification, are permitted provided that the following conditions are met:
8315333Serj
9315333Serj   1. Redistributions of source code must retain the above copyright notice,
10315333Serj      this list of conditions and the following disclaimer.
11315333Serj
12315333Serj   2. Redistributions in binary form must reproduce the above copyright
13315333Serj      notice, this list of conditions and the following disclaimer in the
14315333Serj      documentation and/or other materials provided with the distribution.
15315333Serj
16315333Serj   3. Neither the name of the Intel Corporation nor the names of its
17315333Serj      contributors may be used to endorse or promote products derived from
18315333Serj      this software without specific prior written permission.
19315333Serj
20315333Serj  THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
21315333Serj  AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
22315333Serj  IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
23315333Serj  ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
24315333Serj  LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR
25315333Serj  CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF
26315333Serj  SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS
27315333Serj  INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN
28315333Serj  CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE)
29315333Serj  ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
30315333Serj  POSSIBILITY OF SUCH DAMAGE.
31315333Serj
32315333Serj******************************************************************************/
33315333Serj/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_sriov.h 315333 2017-03-15 21:20:17Z erj $*/
34315333Serj
35315333Serj
36315333Serj#ifndef _IXGBE_SRIOV_H_
37315333Serj#define _IXGBE_SRIOV_H_
38315333Serj
39315333Serj#ifdef PCI_IOV
40315333Serj
41315333Serj#include <sys/nv.h>
42315333Serj#include <sys/iov_schema.h>
43315333Serj#include <dev/pci/pci_iov.h>
44315333Serj#include "ixgbe_mbx.h"
45315333Serj
46315333Serj#define IXGBE_VF_CTS            (1 << 0) /* VF is clear to send. */
47315333Serj#define IXGBE_VF_CAP_MAC        (1 << 1) /* VF is permitted to change MAC. */
48315333Serj#define IXGBE_VF_CAP_VLAN       (1 << 2) /* VF is permitted to join vlans. */
49315333Serj#define IXGBE_VF_ACTIVE         (1 << 3) /* VF is active. */
50315333Serj#define IXGBE_VF_INDEX(vmdq)    ((vmdq) / 32)
51315333Serj#define IXGBE_VF_BIT(vmdq)      (1 << ((vmdq) % 32))
52315333Serj
53315333Serj#define IXGBE_VT_MSG_MASK	0xFFFF
54315333Serj
55315333Serj#define IXGBE_VT_MSGINFO(msg)	\
56315333Serj	(((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT)
57315333Serj
58315333Serj#define IXGBE_VF_GET_QUEUES_RESP_LEN	5
59315333Serj
60315333Serj#define IXGBE_API_VER_1_0	0
61315333Serj#define IXGBE_API_VER_2_0	1	/* Solaris API.  Not supported. */
62315333Serj#define IXGBE_API_VER_1_1	2
63315333Serj#define IXGBE_API_VER_UNKNOWN	UINT16_MAX
64315333Serj
65315333Serj#define IXGBE_NO_VM             0
66315333Serj#define IXGBE_32_VM             32
67315333Serj#define IXGBE_64_VM             64
68315333Serj
69315333Serjint  ixgbe_add_vf(device_t, u16, const nvlist_t *);
70315333Serjint  ixgbe_init_iov(device_t, u16, const nvlist_t *);
71315333Serjvoid ixgbe_uninit_iov(device_t);
72315333Serjvoid ixgbe_initialize_iov(struct adapter *);
73315333Serjvoid ixgbe_recalculate_max_frame(struct adapter *);
74315333Serjvoid ixgbe_ping_all_vfs(struct adapter *);
75315333Serjint  ixgbe_pci_iov_detach(device_t);
76315333Serjvoid ixgbe_define_iov_schemas(device_t, int *);
77315333Serjvoid ixgbe_align_all_queue_indices(struct adapter *);
78315333Serjint  ixgbe_vf_que_index(int, int, int);
79315333Serju32  ixgbe_get_mtqc(int);
80315333Serju32  ixgbe_get_mrqc(int);
81315333Serj
82315333Serj/******************************************************************************/
83315333Serj#else  /* PCI_IOV */
84315333Serj/******************************************************************************/
85315333Serj
86315333Serj#define ixgbe_add_vf(_a,_b,_c)
87315333Serj#define ixgbe_init_iov(_a,_b,_c)
88315333Serj#define ixgbe_uninit_iov(_a)
89315333Serj#define ixgbe_initialize_iov(_a)
90315333Serj#define ixgbe_recalculate_max_frame(_a)
91315333Serj#define ixgbe_ping_all_vfs(_a)
92315333Serj#define ixgbe_pci_iov_detach(_a) 0
93315333Serj#define ixgbe_define_iov_schemas(_a,_b)
94315333Serj#define ixgbe_align_all_queue_indices(_a)
95315333Serj#define ixgbe_vf_que_index(_a,_b,_c) (_c)
96315333Serj#define ixgbe_get_mtqc(_a) IXGBE_MTQC_64Q_1PB
97315333Serj#define ixgbe_get_mrqc(_a) 0
98315333Serj
99315333Serj#endif /* PCI_IOV */
100315333Serj
101315333Serjvoid ixgbe_handle_mbx(void *, int);
102315333Serj
103315333Serj#endif
104