ixgbe_phy.c revision 295524
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_phy.c 295524 2016-02-11 16:16:10Z sbruno $*/ 34 35#include "ixgbe_api.h" 36#include "ixgbe_common.h" 37#include "ixgbe_phy.h" 38 39static void ixgbe_i2c_start(struct ixgbe_hw *hw); 40static void ixgbe_i2c_stop(struct ixgbe_hw *hw); 41static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data); 42static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data); 43static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw); 44static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data); 45static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data); 46static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 47static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl); 48static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data); 49static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl); 50static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 51 u8 *sff8472_data); 52 53/** 54 * ixgbe_out_i2c_byte_ack - Send I2C byte with ack 55 * @hw: pointer to the hardware structure 56 * @byte: byte to send 57 * 58 * Returns an error code on error. 59 */ 60static s32 ixgbe_out_i2c_byte_ack(struct ixgbe_hw *hw, u8 byte) 61{ 62 s32 status; 63 64 status = ixgbe_clock_out_i2c_byte(hw, byte); 65 if (status) 66 return status; 67 return ixgbe_get_i2c_ack(hw); 68} 69 70/** 71 * ixgbe_in_i2c_byte_ack - Receive an I2C byte and send ack 72 * @hw: pointer to the hardware structure 73 * @byte: pointer to a u8 to receive the byte 74 * 75 * Returns an error code on error. 76 */ 77static s32 ixgbe_in_i2c_byte_ack(struct ixgbe_hw *hw, u8 *byte) 78{ 79 s32 status; 80 81 status = ixgbe_clock_in_i2c_byte(hw, byte); 82 if (status) 83 return status; 84 /* ACK */ 85 return ixgbe_clock_out_i2c_bit(hw, FALSE); 86} 87 88/** 89 * ixgbe_ones_comp_byte_add - Perform one's complement addition 90 * @add1 - addend 1 91 * @add2 - addend 2 92 * 93 * Returns one's complement 8-bit sum. 94 */ 95static u8 ixgbe_ones_comp_byte_add(u8 add1, u8 add2) 96{ 97 u16 sum = add1 + add2; 98 99 sum = (sum & 0xFF) + (sum >> 8); 100 return sum & 0xFF; 101} 102 103/** 104 * ixgbe_read_i2c_combined_generic_int - Perform I2C read combined operation 105 * @hw: pointer to the hardware structure 106 * @addr: I2C bus address to read from 107 * @reg: I2C device register to read from 108 * @val: pointer to location to receive read value 109 * @lock: TRUE if to take and release semaphore 110 * 111 * Returns an error code on error. 112 */ 113static s32 ixgbe_read_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 114 u16 reg, u16 *val, bool lock) 115{ 116 u32 swfw_mask = hw->phy.phy_semaphore_mask; 117 int max_retry = 10; 118 int retry = 0; 119 u8 csum_byte; 120 u8 high_bits; 121 u8 low_bits; 122 u8 reg_high; 123 u8 csum; 124 125 if (hw->mac.type >= ixgbe_mac_X550) 126 max_retry = 3; 127 reg_high = ((reg >> 7) & 0xFE) | 1; /* Indicate read combined */ 128 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 129 csum = ~csum; 130 do { 131 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 132 return IXGBE_ERR_SWFW_SYNC; 133 ixgbe_i2c_start(hw); 134 /* Device Address and write indication */ 135 if (ixgbe_out_i2c_byte_ack(hw, addr)) 136 goto fail; 137 /* Write bits 14:8 */ 138 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 139 goto fail; 140 /* Write bits 7:0 */ 141 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 142 goto fail; 143 /* Write csum */ 144 if (ixgbe_out_i2c_byte_ack(hw, csum)) 145 goto fail; 146 /* Re-start condition */ 147 ixgbe_i2c_start(hw); 148 /* Device Address and read indication */ 149 if (ixgbe_out_i2c_byte_ack(hw, addr | 1)) 150 goto fail; 151 /* Get upper bits */ 152 if (ixgbe_in_i2c_byte_ack(hw, &high_bits)) 153 goto fail; 154 /* Get low bits */ 155 if (ixgbe_in_i2c_byte_ack(hw, &low_bits)) 156 goto fail; 157 /* Get csum */ 158 if (ixgbe_clock_in_i2c_byte(hw, &csum_byte)) 159 goto fail; 160 /* NACK */ 161 if (ixgbe_clock_out_i2c_bit(hw, FALSE)) 162 goto fail; 163 ixgbe_i2c_stop(hw); 164 if (lock) 165 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 166 *val = (high_bits << 8) | low_bits; 167 return 0; 168 169fail: 170 ixgbe_i2c_bus_clear(hw); 171 if (lock) 172 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 173 retry++; 174 if (retry < max_retry) 175 DEBUGOUT("I2C byte read combined error - Retrying.\n"); 176 else 177 DEBUGOUT("I2C byte read combined error.\n"); 178 } while (retry < max_retry); 179 180 return IXGBE_ERR_I2C; 181} 182 183/** 184 * ixgbe_read_i2c_combined_generic - Perform I2C read combined operation 185 * @hw: pointer to the hardware structure 186 * @addr: I2C bus address to read from 187 * @reg: I2C device register to read from 188 * @val: pointer to location to receive read value 189 * 190 * Returns an error code on error. 191 **/ 192static s32 ixgbe_read_i2c_combined_generic(struct ixgbe_hw *hw, u8 addr, 193 u16 reg, u16 *val) 194{ 195 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 196} 197 198/** 199 * ixgbe_read_i2c_combined_generic_unlocked - Do I2C read combined operation 200 * @hw: pointer to the hardware structure 201 * @addr: I2C bus address to read from 202 * @reg: I2C device register to read from 203 * @val: pointer to location to receive read value 204 * 205 * Returns an error code on error. 206 **/ 207static s32 208ixgbe_read_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, u8 addr, 209 u16 reg, u16 *val) 210{ 211 return ixgbe_read_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 212} 213 214/** 215 * ixgbe_write_i2c_combined_generic_int - Perform I2C write combined operation 216 * @hw: pointer to the hardware structure 217 * @addr: I2C bus address to write to 218 * @reg: I2C device register to write to 219 * @val: value to write 220 * @lock: TRUE if to take and release semaphore 221 * 222 * Returns an error code on error. 223 */ 224static s32 ixgbe_write_i2c_combined_generic_int(struct ixgbe_hw *hw, u8 addr, 225 u16 reg, u16 val, bool lock) 226{ 227 u32 swfw_mask = hw->phy.phy_semaphore_mask; 228 int max_retry = 1; 229 int retry = 0; 230 u8 reg_high; 231 u8 csum; 232 233 reg_high = (reg >> 7) & 0xFE; /* Indicate write combined */ 234 csum = ixgbe_ones_comp_byte_add(reg_high, reg & 0xFF); 235 csum = ixgbe_ones_comp_byte_add(csum, val >> 8); 236 csum = ixgbe_ones_comp_byte_add(csum, val & 0xFF); 237 csum = ~csum; 238 do { 239 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 240 return IXGBE_ERR_SWFW_SYNC; 241 ixgbe_i2c_start(hw); 242 /* Device Address and write indication */ 243 if (ixgbe_out_i2c_byte_ack(hw, addr)) 244 goto fail; 245 /* Write bits 14:8 */ 246 if (ixgbe_out_i2c_byte_ack(hw, reg_high)) 247 goto fail; 248 /* Write bits 7:0 */ 249 if (ixgbe_out_i2c_byte_ack(hw, reg & 0xFF)) 250 goto fail; 251 /* Write data 15:8 */ 252 if (ixgbe_out_i2c_byte_ack(hw, val >> 8)) 253 goto fail; 254 /* Write data 7:0 */ 255 if (ixgbe_out_i2c_byte_ack(hw, val & 0xFF)) 256 goto fail; 257 /* Write csum */ 258 if (ixgbe_out_i2c_byte_ack(hw, csum)) 259 goto fail; 260 ixgbe_i2c_stop(hw); 261 if (lock) 262 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 263 return 0; 264 265fail: 266 ixgbe_i2c_bus_clear(hw); 267 if (lock) 268 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 269 retry++; 270 if (retry < max_retry) 271 DEBUGOUT("I2C byte write combined error - Retrying.\n"); 272 else 273 DEBUGOUT("I2C byte write combined error.\n"); 274 } while (retry < max_retry); 275 276 return IXGBE_ERR_I2C; 277} 278 279/** 280 * ixgbe_write_i2c_combined_generic - Perform I2C write combined operation 281 * @hw: pointer to the hardware structure 282 * @addr: I2C bus address to write to 283 * @reg: I2C device register to write to 284 * @val: value to write 285 * 286 * Returns an error code on error. 287 **/ 288static s32 ixgbe_write_i2c_combined_generic(struct ixgbe_hw *hw, 289 u8 addr, u16 reg, u16 val) 290{ 291 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, TRUE); 292} 293 294/** 295 * ixgbe_write_i2c_combined_generic_unlocked - Do I2C write combined operation 296 * @hw: pointer to the hardware structure 297 * @addr: I2C bus address to write to 298 * @reg: I2C device register to write to 299 * @val: value to write 300 * 301 * Returns an error code on error. 302 **/ 303static s32 304ixgbe_write_i2c_combined_generic_unlocked(struct ixgbe_hw *hw, 305 u8 addr, u16 reg, u16 val) 306{ 307 return ixgbe_write_i2c_combined_generic_int(hw, addr, reg, val, FALSE); 308} 309 310/** 311 * ixgbe_init_phy_ops_generic - Inits PHY function ptrs 312 * @hw: pointer to the hardware structure 313 * 314 * Initialize the function pointers. 315 **/ 316s32 ixgbe_init_phy_ops_generic(struct ixgbe_hw *hw) 317{ 318 struct ixgbe_phy_info *phy = &hw->phy; 319 320 DEBUGFUNC("ixgbe_init_phy_ops_generic"); 321 322 /* PHY */ 323 phy->ops.identify = ixgbe_identify_phy_generic; 324 phy->ops.reset = ixgbe_reset_phy_generic; 325 phy->ops.read_reg = ixgbe_read_phy_reg_generic; 326 phy->ops.write_reg = ixgbe_write_phy_reg_generic; 327 phy->ops.read_reg_mdi = ixgbe_read_phy_reg_mdi; 328 phy->ops.write_reg_mdi = ixgbe_write_phy_reg_mdi; 329 phy->ops.setup_link = ixgbe_setup_phy_link_generic; 330 phy->ops.setup_link_speed = ixgbe_setup_phy_link_speed_generic; 331 phy->ops.check_link = NULL; 332 phy->ops.get_firmware_version = ixgbe_get_phy_firmware_version_generic; 333 phy->ops.read_i2c_byte = ixgbe_read_i2c_byte_generic; 334 phy->ops.write_i2c_byte = ixgbe_write_i2c_byte_generic; 335 phy->ops.read_i2c_sff8472 = ixgbe_read_i2c_sff8472_generic; 336 phy->ops.read_i2c_eeprom = ixgbe_read_i2c_eeprom_generic; 337 phy->ops.write_i2c_eeprom = ixgbe_write_i2c_eeprom_generic; 338 phy->ops.i2c_bus_clear = ixgbe_i2c_bus_clear; 339 phy->ops.identify_sfp = ixgbe_identify_module_generic; 340 phy->sfp_type = ixgbe_sfp_type_unknown; 341 phy->ops.read_i2c_combined = ixgbe_read_i2c_combined_generic; 342 phy->ops.write_i2c_combined = ixgbe_write_i2c_combined_generic; 343 phy->ops.read_i2c_combined_unlocked = 344 ixgbe_read_i2c_combined_generic_unlocked; 345 phy->ops.write_i2c_combined_unlocked = 346 ixgbe_write_i2c_combined_generic_unlocked; 347 phy->ops.read_i2c_byte_unlocked = ixgbe_read_i2c_byte_generic_unlocked; 348 phy->ops.write_i2c_byte_unlocked = 349 ixgbe_write_i2c_byte_generic_unlocked; 350 phy->ops.check_overtemp = ixgbe_tn_check_overtemp; 351 return IXGBE_SUCCESS; 352} 353 354/** 355 * ixgbe_identify_phy_generic - Get physical layer module 356 * @hw: pointer to hardware structure 357 * 358 * Determines the physical layer module found on the current adapter. 359 **/ 360s32 ixgbe_identify_phy_generic(struct ixgbe_hw *hw) 361{ 362 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 363 u32 phy_addr; 364 u16 ext_ability = 0; 365 366 DEBUGFUNC("ixgbe_identify_phy_generic"); 367 368 if (!hw->phy.phy_semaphore_mask) { 369 if (hw->bus.lan_id) 370 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY1_SM; 371 else 372 hw->phy.phy_semaphore_mask = IXGBE_GSSR_PHY0_SM; 373 } 374 375 if (hw->phy.type == ixgbe_phy_unknown) { 376 for (phy_addr = 0; phy_addr < IXGBE_MAX_PHY_ADDR; phy_addr++) { 377 if (ixgbe_validate_phy_addr(hw, phy_addr)) { 378 hw->phy.addr = phy_addr; 379 ixgbe_get_phy_id(hw); 380 hw->phy.type = 381 ixgbe_get_phy_type_from_id(hw->phy.id); 382 383 if (hw->phy.type == ixgbe_phy_unknown) { 384 hw->phy.ops.read_reg(hw, 385 IXGBE_MDIO_PHY_EXT_ABILITY, 386 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 387 &ext_ability); 388 if (ext_ability & 389 (IXGBE_MDIO_PHY_10GBASET_ABILITY | 390 IXGBE_MDIO_PHY_1000BASET_ABILITY)) 391 hw->phy.type = 392 ixgbe_phy_cu_unknown; 393 else 394 hw->phy.type = 395 ixgbe_phy_generic; 396 } 397 398 status = IXGBE_SUCCESS; 399 break; 400 } 401 } 402 403 /* Certain media types do not have a phy so an address will not 404 * be found and the code will take this path. Caller has to 405 * decide if it is an error or not. 406 */ 407 if (status != IXGBE_SUCCESS) { 408 hw->phy.addr = 0; 409 } 410 } else { 411 status = IXGBE_SUCCESS; 412 } 413 414 return status; 415} 416 417/** 418 * ixgbe_check_reset_blocked - check status of MNG FW veto bit 419 * @hw: pointer to the hardware structure 420 * 421 * This function checks the MMNGC.MNG_VETO bit to see if there are 422 * any constraints on link from manageability. For MAC's that don't 423 * have this bit just return faluse since the link can not be blocked 424 * via this method. 425 **/ 426s32 ixgbe_check_reset_blocked(struct ixgbe_hw *hw) 427{ 428 u32 mmngc; 429 430 DEBUGFUNC("ixgbe_check_reset_blocked"); 431 432 /* If we don't have this bit, it can't be blocking */ 433 if (hw->mac.type == ixgbe_mac_82598EB) 434 return FALSE; 435 436 mmngc = IXGBE_READ_REG(hw, IXGBE_MMNGC); 437 if (mmngc & IXGBE_MMNGC_MNG_VETO) { 438 ERROR_REPORT1(IXGBE_ERROR_SOFTWARE, 439 "MNG_VETO bit detected.\n"); 440 return TRUE; 441 } 442 443 return FALSE; 444} 445 446/** 447 * ixgbe_validate_phy_addr - Determines phy address is valid 448 * @hw: pointer to hardware structure 449 * 450 **/ 451bool ixgbe_validate_phy_addr(struct ixgbe_hw *hw, u32 phy_addr) 452{ 453 u16 phy_id = 0; 454 bool valid = FALSE; 455 456 DEBUGFUNC("ixgbe_validate_phy_addr"); 457 458 hw->phy.addr = phy_addr; 459 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 460 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_id); 461 462 if (phy_id != 0xFFFF && phy_id != 0x0) 463 valid = TRUE; 464 465 return valid; 466} 467 468/** 469 * ixgbe_get_phy_id - Get the phy type 470 * @hw: pointer to hardware structure 471 * 472 **/ 473s32 ixgbe_get_phy_id(struct ixgbe_hw *hw) 474{ 475 u32 status; 476 u16 phy_id_high = 0; 477 u16 phy_id_low = 0; 478 479 DEBUGFUNC("ixgbe_get_phy_id"); 480 481 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_HIGH, 482 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 483 &phy_id_high); 484 485 if (status == IXGBE_SUCCESS) { 486 hw->phy.id = (u32)(phy_id_high << 16); 487 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_ID_LOW, 488 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 489 &phy_id_low); 490 hw->phy.id |= (u32)(phy_id_low & IXGBE_PHY_REVISION_MASK); 491 hw->phy.revision = (u32)(phy_id_low & ~IXGBE_PHY_REVISION_MASK); 492 } 493 return status; 494} 495 496/** 497 * ixgbe_get_phy_type_from_id - Get the phy type 498 * @hw: pointer to hardware structure 499 * 500 **/ 501enum ixgbe_phy_type ixgbe_get_phy_type_from_id(u32 phy_id) 502{ 503 enum ixgbe_phy_type phy_type; 504 505 DEBUGFUNC("ixgbe_get_phy_type_from_id"); 506 507 switch (phy_id) { 508 case TN1010_PHY_ID: 509 phy_type = ixgbe_phy_tn; 510 break; 511 case X550_PHY_ID1: 512 case X550_PHY_ID2: 513 case X550_PHY_ID3: 514 case X540_PHY_ID: 515 phy_type = ixgbe_phy_aq; 516 break; 517 case QT2022_PHY_ID: 518 phy_type = ixgbe_phy_qt; 519 break; 520 case ATH_PHY_ID: 521 phy_type = ixgbe_phy_nl; 522 break; 523 case X557_PHY_ID: 524 phy_type = ixgbe_phy_x550em_ext_t; 525 break; 526 default: 527 phy_type = ixgbe_phy_unknown; 528 break; 529 } 530 531 DEBUGOUT1("phy type found is %d\n", phy_type); 532 return phy_type; 533} 534 535/** 536 * ixgbe_reset_phy_generic - Performs a PHY reset 537 * @hw: pointer to hardware structure 538 **/ 539s32 ixgbe_reset_phy_generic(struct ixgbe_hw *hw) 540{ 541 u32 i; 542 u16 ctrl = 0; 543 s32 status = IXGBE_SUCCESS; 544 545 DEBUGFUNC("ixgbe_reset_phy_generic"); 546 547 if (hw->phy.type == ixgbe_phy_unknown) 548 status = ixgbe_identify_phy_generic(hw); 549 550 if (status != IXGBE_SUCCESS || hw->phy.type == ixgbe_phy_none) 551 goto out; 552 553 /* Don't reset PHY if it's shut down due to overtemp. */ 554 if (!hw->phy.reset_if_overtemp && 555 (IXGBE_ERR_OVERTEMP == hw->phy.ops.check_overtemp(hw))) 556 goto out; 557 558 /* Blocked by MNG FW so bail */ 559 if (ixgbe_check_reset_blocked(hw)) 560 goto out; 561 562 /* 563 * Perform soft PHY reset to the PHY_XS. 564 * This will cause a soft reset to the PHY 565 */ 566 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 567 IXGBE_MDIO_PHY_XS_DEV_TYPE, 568 IXGBE_MDIO_PHY_XS_RESET); 569 570 /* 571 * Poll for reset bit to self-clear indicating reset is complete. 572 * Some PHYs could take up to 3 seconds to complete and need about 573 * 1.7 usec delay after the reset is complete. 574 */ 575 for (i = 0; i < 30; i++) { 576 msec_delay(100); 577 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 578 IXGBE_MDIO_PHY_XS_DEV_TYPE, &ctrl); 579 if (!(ctrl & IXGBE_MDIO_PHY_XS_RESET)) { 580 usec_delay(2); 581 break; 582 } 583 } 584 585 if (ctrl & IXGBE_MDIO_PHY_XS_RESET) { 586 status = IXGBE_ERR_RESET_FAILED; 587 ERROR_REPORT1(IXGBE_ERROR_POLLING, 588 "PHY reset polling failed to complete.\n"); 589 } 590 591out: 592 return status; 593} 594 595/** 596 * ixgbe_read_phy_mdi - Reads a value from a specified PHY register without 597 * the SWFW lock 598 * @hw: pointer to hardware structure 599 * @reg_addr: 32 bit address of PHY register to read 600 * @phy_data: Pointer to read data from PHY register 601 **/ 602s32 ixgbe_read_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 603 u16 *phy_data) 604{ 605 u32 i, data, command; 606 607 /* Setup and write the address cycle command */ 608 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 609 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 610 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 611 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 612 613 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 614 615 /* 616 * Check every 10 usec to see if the address cycle completed. 617 * The MDI Command bit will clear when the operation is 618 * complete 619 */ 620 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 621 usec_delay(10); 622 623 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 624 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 625 break; 626 } 627 628 629 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 630 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address command did not complete.\n"); 631 return IXGBE_ERR_PHY; 632 } 633 634 /* 635 * Address cycle complete, setup and write the read 636 * command 637 */ 638 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 639 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 640 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 641 (IXGBE_MSCA_READ | IXGBE_MSCA_MDI_COMMAND)); 642 643 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 644 645 /* 646 * Check every 10 usec to see if the address cycle 647 * completed. The MDI Command bit will clear when the 648 * operation is complete 649 */ 650 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 651 usec_delay(10); 652 653 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 654 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 655 break; 656 } 657 658 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 659 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY read command didn't complete\n"); 660 return IXGBE_ERR_PHY; 661 } 662 663 /* 664 * Read operation is complete. Get the data 665 * from MSRWD 666 */ 667 data = IXGBE_READ_REG(hw, IXGBE_MSRWD); 668 data >>= IXGBE_MSRWD_READ_DATA_SHIFT; 669 *phy_data = (u16)(data); 670 671 return IXGBE_SUCCESS; 672} 673 674/** 675 * ixgbe_read_phy_reg_generic - Reads a value from a specified PHY register 676 * using the SWFW lock - this function is needed in most cases 677 * @hw: pointer to hardware structure 678 * @reg_addr: 32 bit address of PHY register to read 679 * @phy_data: Pointer to read data from PHY register 680 **/ 681s32 ixgbe_read_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 682 u32 device_type, u16 *phy_data) 683{ 684 s32 status; 685 u32 gssr = hw->phy.phy_semaphore_mask; 686 687 DEBUGFUNC("ixgbe_read_phy_reg_generic"); 688 689 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 690 status = ixgbe_read_phy_reg_mdi(hw, reg_addr, device_type, 691 phy_data); 692 hw->mac.ops.release_swfw_sync(hw, gssr); 693 } else { 694 status = IXGBE_ERR_SWFW_SYNC; 695 } 696 697 return status; 698} 699 700/** 701 * ixgbe_write_phy_reg_mdi - Writes a value to specified PHY register 702 * without SWFW lock 703 * @hw: pointer to hardware structure 704 * @reg_addr: 32 bit PHY register to write 705 * @device_type: 5 bit device type 706 * @phy_data: Data to write to the PHY register 707 **/ 708s32 ixgbe_write_phy_reg_mdi(struct ixgbe_hw *hw, u32 reg_addr, 709 u32 device_type, u16 phy_data) 710{ 711 u32 i, command; 712 713 /* Put the data in the MDI single read and write data register*/ 714 IXGBE_WRITE_REG(hw, IXGBE_MSRWD, (u32)phy_data); 715 716 /* Setup and write the address cycle command */ 717 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 718 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 719 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 720 (IXGBE_MSCA_ADDR_CYCLE | IXGBE_MSCA_MDI_COMMAND)); 721 722 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 723 724 /* 725 * Check every 10 usec to see if the address cycle completed. 726 * The MDI Command bit will clear when the operation is 727 * complete 728 */ 729 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 730 usec_delay(10); 731 732 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 733 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 734 break; 735 } 736 737 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 738 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY address cmd didn't complete\n"); 739 return IXGBE_ERR_PHY; 740 } 741 742 /* 743 * Address cycle complete, setup and write the write 744 * command 745 */ 746 command = ((reg_addr << IXGBE_MSCA_NP_ADDR_SHIFT) | 747 (device_type << IXGBE_MSCA_DEV_TYPE_SHIFT) | 748 (hw->phy.addr << IXGBE_MSCA_PHY_ADDR_SHIFT) | 749 (IXGBE_MSCA_WRITE | IXGBE_MSCA_MDI_COMMAND)); 750 751 IXGBE_WRITE_REG(hw, IXGBE_MSCA, command); 752 753 /* 754 * Check every 10 usec to see if the address cycle 755 * completed. The MDI Command bit will clear when the 756 * operation is complete 757 */ 758 for (i = 0; i < IXGBE_MDIO_COMMAND_TIMEOUT; i++) { 759 usec_delay(10); 760 761 command = IXGBE_READ_REG(hw, IXGBE_MSCA); 762 if ((command & IXGBE_MSCA_MDI_COMMAND) == 0) 763 break; 764 } 765 766 if ((command & IXGBE_MSCA_MDI_COMMAND) != 0) { 767 ERROR_REPORT1(IXGBE_ERROR_POLLING, "PHY write cmd didn't complete\n"); 768 return IXGBE_ERR_PHY; 769 } 770 771 return IXGBE_SUCCESS; 772} 773 774/** 775 * ixgbe_write_phy_reg_generic - Writes a value to specified PHY register 776 * using SWFW lock- this function is needed in most cases 777 * @hw: pointer to hardware structure 778 * @reg_addr: 32 bit PHY register to write 779 * @device_type: 5 bit device type 780 * @phy_data: Data to write to the PHY register 781 **/ 782s32 ixgbe_write_phy_reg_generic(struct ixgbe_hw *hw, u32 reg_addr, 783 u32 device_type, u16 phy_data) 784{ 785 s32 status; 786 u32 gssr = hw->phy.phy_semaphore_mask; 787 788 DEBUGFUNC("ixgbe_write_phy_reg_generic"); 789 790 if (hw->mac.ops.acquire_swfw_sync(hw, gssr) == IXGBE_SUCCESS) { 791 status = ixgbe_write_phy_reg_mdi(hw, reg_addr, device_type, 792 phy_data); 793 hw->mac.ops.release_swfw_sync(hw, gssr); 794 } else { 795 status = IXGBE_ERR_SWFW_SYNC; 796 } 797 798 return status; 799} 800 801/** 802 * ixgbe_setup_phy_link_generic - Set and restart auto-neg 803 * @hw: pointer to hardware structure 804 * 805 * Restart auto-negotiation and PHY and waits for completion. 806 **/ 807s32 ixgbe_setup_phy_link_generic(struct ixgbe_hw *hw) 808{ 809 s32 status = IXGBE_SUCCESS; 810 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 811 bool autoneg = FALSE; 812 ixgbe_link_speed speed; 813 814 DEBUGFUNC("ixgbe_setup_phy_link_generic"); 815 816 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 817 818 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 819 /* Set or unset auto-negotiation 10G advertisement */ 820 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 821 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 822 &autoneg_reg); 823 824 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 825 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 826 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 827 828 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 829 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 830 autoneg_reg); 831 } 832 833 if (hw->mac.type == ixgbe_mac_X550) { 834 if (speed & IXGBE_LINK_SPEED_5GB_FULL) { 835 /* Set or unset auto-negotiation 5G advertisement */ 836 hw->phy.ops.read_reg(hw, 837 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 838 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 839 &autoneg_reg); 840 841 autoneg_reg &= ~IXGBE_MII_5GBASE_T_ADVERTISE; 842 if (hw->phy.autoneg_advertised & 843 IXGBE_LINK_SPEED_5GB_FULL) 844 autoneg_reg |= IXGBE_MII_5GBASE_T_ADVERTISE; 845 846 hw->phy.ops.write_reg(hw, 847 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 848 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 849 autoneg_reg); 850 } 851 852 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) { 853 /* Set or unset auto-negotiation 2.5G advertisement */ 854 hw->phy.ops.read_reg(hw, 855 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 856 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 857 &autoneg_reg); 858 859 autoneg_reg &= ~IXGBE_MII_2_5GBASE_T_ADVERTISE; 860 if (hw->phy.autoneg_advertised & 861 IXGBE_LINK_SPEED_2_5GB_FULL) 862 autoneg_reg |= IXGBE_MII_2_5GBASE_T_ADVERTISE; 863 864 hw->phy.ops.write_reg(hw, 865 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 866 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 867 autoneg_reg); 868 } 869 } 870 871 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 872 /* Set or unset auto-negotiation 1G advertisement */ 873 hw->phy.ops.read_reg(hw, 874 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 875 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 876 &autoneg_reg); 877 878 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE; 879 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 880 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE; 881 882 hw->phy.ops.write_reg(hw, 883 IXGBE_MII_AUTONEG_VENDOR_PROVISION_1_REG, 884 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 885 autoneg_reg); 886 } 887 888 if (speed & IXGBE_LINK_SPEED_100_FULL) { 889 /* Set or unset auto-negotiation 100M advertisement */ 890 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 891 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 892 &autoneg_reg); 893 894 autoneg_reg &= ~(IXGBE_MII_100BASE_T_ADVERTISE | 895 IXGBE_MII_100BASE_T_ADVERTISE_HALF); 896 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 897 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 898 899 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 900 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 901 autoneg_reg); 902 } 903 904 /* Blocked by MNG FW so don't reset PHY */ 905 if (ixgbe_check_reset_blocked(hw)) 906 return status; 907 908 /* Restart PHY auto-negotiation. */ 909 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 910 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 911 912 autoneg_reg |= IXGBE_MII_RESTART; 913 914 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 915 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 916 917 return status; 918} 919 920/** 921 * ixgbe_setup_phy_link_speed_generic - Sets the auto advertised capabilities 922 * @hw: pointer to hardware structure 923 * @speed: new link speed 924 **/ 925s32 ixgbe_setup_phy_link_speed_generic(struct ixgbe_hw *hw, 926 ixgbe_link_speed speed, 927 bool autoneg_wait_to_complete) 928{ 929 UNREFERENCED_1PARAMETER(autoneg_wait_to_complete); 930 931 DEBUGFUNC("ixgbe_setup_phy_link_speed_generic"); 932 933 /* 934 * Clear autoneg_advertised and set new values based on input link 935 * speed. 936 */ 937 hw->phy.autoneg_advertised = 0; 938 939 if (speed & IXGBE_LINK_SPEED_10GB_FULL) 940 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_10GB_FULL; 941 942 if (speed & IXGBE_LINK_SPEED_5GB_FULL) 943 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_5GB_FULL; 944 945 if (speed & IXGBE_LINK_SPEED_2_5GB_FULL) 946 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_2_5GB_FULL; 947 948 if (speed & IXGBE_LINK_SPEED_1GB_FULL) 949 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_1GB_FULL; 950 951 if (speed & IXGBE_LINK_SPEED_100_FULL) 952 hw->phy.autoneg_advertised |= IXGBE_LINK_SPEED_100_FULL; 953 954 /* Setup link based on the new speed settings */ 955 ixgbe_setup_phy_link(hw); 956 957 return IXGBE_SUCCESS; 958} 959 960/** 961 * ixgbe_get_copper_speeds_supported - Get copper link speeds from phy 962 * @hw: pointer to hardware structure 963 * 964 * Determines the supported link capabilities by reading the PHY auto 965 * negotiation register. 966 **/ 967static s32 ixgbe_get_copper_speeds_supported(struct ixgbe_hw *hw) 968{ 969 s32 status; 970 u16 speed_ability; 971 972 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_SPEED_ABILITY, 973 IXGBE_MDIO_PMA_PMD_DEV_TYPE, 974 &speed_ability); 975 if (status) 976 return status; 977 978 if (speed_ability & IXGBE_MDIO_PHY_SPEED_10G) 979 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_10GB_FULL; 980 if (speed_ability & IXGBE_MDIO_PHY_SPEED_1G) 981 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_1GB_FULL; 982 if (speed_ability & IXGBE_MDIO_PHY_SPEED_100M) 983 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_100_FULL; 984 985 switch (hw->mac.type) { 986 case ixgbe_mac_X550: 987 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_2_5GB_FULL; 988 hw->phy.speeds_supported |= IXGBE_LINK_SPEED_5GB_FULL; 989 break; 990 case ixgbe_mac_X550EM_x: 991 hw->phy.speeds_supported &= ~IXGBE_LINK_SPEED_100_FULL; 992 break; 993 default: 994 break; 995 } 996 997 return status; 998} 999 1000/** 1001 * ixgbe_get_copper_link_capabilities_generic - Determines link capabilities 1002 * @hw: pointer to hardware structure 1003 * @speed: pointer to link speed 1004 * @autoneg: boolean auto-negotiation value 1005 **/ 1006s32 ixgbe_get_copper_link_capabilities_generic(struct ixgbe_hw *hw, 1007 ixgbe_link_speed *speed, 1008 bool *autoneg) 1009{ 1010 s32 status = IXGBE_SUCCESS; 1011 1012 DEBUGFUNC("ixgbe_get_copper_link_capabilities_generic"); 1013 1014 *autoneg = TRUE; 1015 if (!hw->phy.speeds_supported) 1016 status = ixgbe_get_copper_speeds_supported(hw); 1017 1018 *speed = hw->phy.speeds_supported; 1019 return status; 1020} 1021 1022/** 1023 * ixgbe_check_phy_link_tnx - Determine link and speed status 1024 * @hw: pointer to hardware structure 1025 * 1026 * Reads the VS1 register to determine if link is up and the current speed for 1027 * the PHY. 1028 **/ 1029s32 ixgbe_check_phy_link_tnx(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 1030 bool *link_up) 1031{ 1032 s32 status = IXGBE_SUCCESS; 1033 u32 time_out; 1034 u32 max_time_out = 10; 1035 u16 phy_link = 0; 1036 u16 phy_speed = 0; 1037 u16 phy_data = 0; 1038 1039 DEBUGFUNC("ixgbe_check_phy_link_tnx"); 1040 1041 /* Initialize speed and link to default case */ 1042 *link_up = FALSE; 1043 *speed = IXGBE_LINK_SPEED_10GB_FULL; 1044 1045 /* 1046 * Check current speed and link status of the PHY register. 1047 * This is a vendor specific register and may have to 1048 * be changed for other copper PHYs. 1049 */ 1050 for (time_out = 0; time_out < max_time_out; time_out++) { 1051 usec_delay(10); 1052 status = hw->phy.ops.read_reg(hw, 1053 IXGBE_MDIO_VENDOR_SPECIFIC_1_STATUS, 1054 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1055 &phy_data); 1056 phy_link = phy_data & IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS; 1057 phy_speed = phy_data & 1058 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS; 1059 if (phy_link == IXGBE_MDIO_VENDOR_SPECIFIC_1_LINK_STATUS) { 1060 *link_up = TRUE; 1061 if (phy_speed == 1062 IXGBE_MDIO_VENDOR_SPECIFIC_1_SPEED_STATUS) 1063 *speed = IXGBE_LINK_SPEED_1GB_FULL; 1064 break; 1065 } 1066 } 1067 1068 return status; 1069} 1070 1071/** 1072 * ixgbe_setup_phy_link_tnx - Set and restart auto-neg 1073 * @hw: pointer to hardware structure 1074 * 1075 * Restart auto-negotiation and PHY and waits for completion. 1076 **/ 1077s32 ixgbe_setup_phy_link_tnx(struct ixgbe_hw *hw) 1078{ 1079 s32 status = IXGBE_SUCCESS; 1080 u16 autoneg_reg = IXGBE_MII_AUTONEG_REG; 1081 bool autoneg = FALSE; 1082 ixgbe_link_speed speed; 1083 1084 DEBUGFUNC("ixgbe_setup_phy_link_tnx"); 1085 1086 ixgbe_get_copper_link_capabilities_generic(hw, &speed, &autoneg); 1087 1088 if (speed & IXGBE_LINK_SPEED_10GB_FULL) { 1089 /* Set or unset auto-negotiation 10G advertisement */ 1090 hw->phy.ops.read_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1091 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1092 &autoneg_reg); 1093 1094 autoneg_reg &= ~IXGBE_MII_10GBASE_T_ADVERTISE; 1095 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_10GB_FULL) 1096 autoneg_reg |= IXGBE_MII_10GBASE_T_ADVERTISE; 1097 1098 hw->phy.ops.write_reg(hw, IXGBE_MII_10GBASE_T_AUTONEG_CTRL_REG, 1099 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1100 autoneg_reg); 1101 } 1102 1103 if (speed & IXGBE_LINK_SPEED_1GB_FULL) { 1104 /* Set or unset auto-negotiation 1G advertisement */ 1105 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1106 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1107 &autoneg_reg); 1108 1109 autoneg_reg &= ~IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1110 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_1GB_FULL) 1111 autoneg_reg |= IXGBE_MII_1GBASE_T_ADVERTISE_XNP_TX; 1112 1113 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_XNP_TX_REG, 1114 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1115 autoneg_reg); 1116 } 1117 1118 if (speed & IXGBE_LINK_SPEED_100_FULL) { 1119 /* Set or unset auto-negotiation 100M advertisement */ 1120 hw->phy.ops.read_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1121 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1122 &autoneg_reg); 1123 1124 autoneg_reg &= ~IXGBE_MII_100BASE_T_ADVERTISE; 1125 if (hw->phy.autoneg_advertised & IXGBE_LINK_SPEED_100_FULL) 1126 autoneg_reg |= IXGBE_MII_100BASE_T_ADVERTISE; 1127 1128 hw->phy.ops.write_reg(hw, IXGBE_MII_AUTONEG_ADVERTISE_REG, 1129 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, 1130 autoneg_reg); 1131 } 1132 1133 /* Blocked by MNG FW so don't reset PHY */ 1134 if (ixgbe_check_reset_blocked(hw)) 1135 return status; 1136 1137 /* Restart PHY auto-negotiation. */ 1138 hw->phy.ops.read_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1139 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, &autoneg_reg); 1140 1141 autoneg_reg |= IXGBE_MII_RESTART; 1142 1143 hw->phy.ops.write_reg(hw, IXGBE_MDIO_AUTO_NEG_CONTROL, 1144 IXGBE_MDIO_AUTO_NEG_DEV_TYPE, autoneg_reg); 1145 1146 return status; 1147} 1148 1149/** 1150 * ixgbe_get_phy_firmware_version_tnx - Gets the PHY Firmware Version 1151 * @hw: pointer to hardware structure 1152 * @firmware_version: pointer to the PHY Firmware Version 1153 **/ 1154s32 ixgbe_get_phy_firmware_version_tnx(struct ixgbe_hw *hw, 1155 u16 *firmware_version) 1156{ 1157 s32 status; 1158 1159 DEBUGFUNC("ixgbe_get_phy_firmware_version_tnx"); 1160 1161 status = hw->phy.ops.read_reg(hw, TNX_FW_REV, 1162 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1163 firmware_version); 1164 1165 return status; 1166} 1167 1168/** 1169 * ixgbe_get_phy_firmware_version_generic - Gets the PHY Firmware Version 1170 * @hw: pointer to hardware structure 1171 * @firmware_version: pointer to the PHY Firmware Version 1172 **/ 1173s32 ixgbe_get_phy_firmware_version_generic(struct ixgbe_hw *hw, 1174 u16 *firmware_version) 1175{ 1176 s32 status; 1177 1178 DEBUGFUNC("ixgbe_get_phy_firmware_version_generic"); 1179 1180 status = hw->phy.ops.read_reg(hw, AQ_FW_REV, 1181 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 1182 firmware_version); 1183 1184 return status; 1185} 1186 1187/** 1188 * ixgbe_reset_phy_nl - Performs a PHY reset 1189 * @hw: pointer to hardware structure 1190 **/ 1191s32 ixgbe_reset_phy_nl(struct ixgbe_hw *hw) 1192{ 1193 u16 phy_offset, control, eword, edata, block_crc; 1194 bool end_data = FALSE; 1195 u16 list_offset, data_offset; 1196 u16 phy_data = 0; 1197 s32 ret_val = IXGBE_SUCCESS; 1198 u32 i; 1199 1200 DEBUGFUNC("ixgbe_reset_phy_nl"); 1201 1202 /* Blocked by MNG FW so bail */ 1203 if (ixgbe_check_reset_blocked(hw)) 1204 goto out; 1205 1206 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1207 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1208 1209 /* reset the PHY and poll for completion */ 1210 hw->phy.ops.write_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1211 IXGBE_MDIO_PHY_XS_DEV_TYPE, 1212 (phy_data | IXGBE_MDIO_PHY_XS_RESET)); 1213 1214 for (i = 0; i < 100; i++) { 1215 hw->phy.ops.read_reg(hw, IXGBE_MDIO_PHY_XS_CONTROL, 1216 IXGBE_MDIO_PHY_XS_DEV_TYPE, &phy_data); 1217 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) == 0) 1218 break; 1219 msec_delay(10); 1220 } 1221 1222 if ((phy_data & IXGBE_MDIO_PHY_XS_RESET) != 0) { 1223 DEBUGOUT("PHY reset did not complete.\n"); 1224 ret_val = IXGBE_ERR_PHY; 1225 goto out; 1226 } 1227 1228 /* Get init offsets */ 1229 ret_val = ixgbe_get_sfp_init_sequence_offsets(hw, &list_offset, 1230 &data_offset); 1231 if (ret_val != IXGBE_SUCCESS) 1232 goto out; 1233 1234 ret_val = hw->eeprom.ops.read(hw, data_offset, &block_crc); 1235 data_offset++; 1236 while (!end_data) { 1237 /* 1238 * Read control word from PHY init contents offset 1239 */ 1240 ret_val = hw->eeprom.ops.read(hw, data_offset, &eword); 1241 if (ret_val) 1242 goto err_eeprom; 1243 control = (eword & IXGBE_CONTROL_MASK_NL) >> 1244 IXGBE_CONTROL_SHIFT_NL; 1245 edata = eword & IXGBE_DATA_MASK_NL; 1246 switch (control) { 1247 case IXGBE_DELAY_NL: 1248 data_offset++; 1249 DEBUGOUT1("DELAY: %d MS\n", edata); 1250 msec_delay(edata); 1251 break; 1252 case IXGBE_DATA_NL: 1253 DEBUGOUT("DATA:\n"); 1254 data_offset++; 1255 ret_val = hw->eeprom.ops.read(hw, data_offset, 1256 &phy_offset); 1257 if (ret_val) 1258 goto err_eeprom; 1259 data_offset++; 1260 for (i = 0; i < edata; i++) { 1261 ret_val = hw->eeprom.ops.read(hw, data_offset, 1262 &eword); 1263 if (ret_val) 1264 goto err_eeprom; 1265 hw->phy.ops.write_reg(hw, phy_offset, 1266 IXGBE_TWINAX_DEV, eword); 1267 DEBUGOUT2("Wrote %4.4x to %4.4x\n", eword, 1268 phy_offset); 1269 data_offset++; 1270 phy_offset++; 1271 } 1272 break; 1273 case IXGBE_CONTROL_NL: 1274 data_offset++; 1275 DEBUGOUT("CONTROL:\n"); 1276 if (edata == IXGBE_CONTROL_EOL_NL) { 1277 DEBUGOUT("EOL\n"); 1278 end_data = TRUE; 1279 } else if (edata == IXGBE_CONTROL_SOL_NL) { 1280 DEBUGOUT("SOL\n"); 1281 } else { 1282 DEBUGOUT("Bad control value\n"); 1283 ret_val = IXGBE_ERR_PHY; 1284 goto out; 1285 } 1286 break; 1287 default: 1288 DEBUGOUT("Bad control type\n"); 1289 ret_val = IXGBE_ERR_PHY; 1290 goto out; 1291 } 1292 } 1293 1294out: 1295 return ret_val; 1296 1297err_eeprom: 1298 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1299 "eeprom read at offset %d failed", data_offset); 1300 return IXGBE_ERR_PHY; 1301} 1302 1303/** 1304 * ixgbe_identify_module_generic - Identifies module type 1305 * @hw: pointer to hardware structure 1306 * 1307 * Determines HW type and calls appropriate function. 1308 **/ 1309s32 ixgbe_identify_module_generic(struct ixgbe_hw *hw) 1310{ 1311 s32 status = IXGBE_ERR_SFP_NOT_PRESENT; 1312 1313 DEBUGFUNC("ixgbe_identify_module_generic"); 1314 1315 switch (hw->mac.ops.get_media_type(hw)) { 1316 case ixgbe_media_type_fiber: 1317 status = ixgbe_identify_sfp_module_generic(hw); 1318 break; 1319 1320 case ixgbe_media_type_fiber_qsfp: 1321 status = ixgbe_identify_qsfp_module_generic(hw); 1322 break; 1323 1324 default: 1325 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1326 status = IXGBE_ERR_SFP_NOT_PRESENT; 1327 break; 1328 } 1329 1330 return status; 1331} 1332 1333/** 1334 * ixgbe_identify_sfp_module_generic - Identifies SFP modules 1335 * @hw: pointer to hardware structure 1336 * 1337 * Searches for and identifies the SFP module and assigns appropriate PHY type. 1338 **/ 1339s32 ixgbe_identify_sfp_module_generic(struct ixgbe_hw *hw) 1340{ 1341 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1342 u32 vendor_oui = 0; 1343 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1344 u8 identifier = 0; 1345 u8 comp_codes_1g = 0; 1346 u8 comp_codes_10g = 0; 1347 u8 oui_bytes[3] = {0, 0, 0}; 1348 u8 cable_tech = 0; 1349 u8 cable_spec = 0; 1350 u16 enforce_sfp = 0; 1351 1352 DEBUGFUNC("ixgbe_identify_sfp_module_generic"); 1353 1354 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber) { 1355 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1356 status = IXGBE_ERR_SFP_NOT_PRESENT; 1357 goto out; 1358 } 1359 1360 /* LAN ID is needed for I2C access */ 1361 hw->mac.ops.set_lan_id(hw); 1362 1363 status = hw->phy.ops.read_i2c_eeprom(hw, 1364 IXGBE_SFF_IDENTIFIER, 1365 &identifier); 1366 1367 if (status != IXGBE_SUCCESS) 1368 goto err_read_i2c_eeprom; 1369 1370 if (identifier != IXGBE_SFF_IDENTIFIER_SFP) { 1371 hw->phy.type = ixgbe_phy_sfp_unsupported; 1372 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1373 } else { 1374 status = hw->phy.ops.read_i2c_eeprom(hw, 1375 IXGBE_SFF_1GBE_COMP_CODES, 1376 &comp_codes_1g); 1377 1378 if (status != IXGBE_SUCCESS) 1379 goto err_read_i2c_eeprom; 1380 1381 status = hw->phy.ops.read_i2c_eeprom(hw, 1382 IXGBE_SFF_10GBE_COMP_CODES, 1383 &comp_codes_10g); 1384 1385 if (status != IXGBE_SUCCESS) 1386 goto err_read_i2c_eeprom; 1387 status = hw->phy.ops.read_i2c_eeprom(hw, 1388 IXGBE_SFF_CABLE_TECHNOLOGY, 1389 &cable_tech); 1390 1391 if (status != IXGBE_SUCCESS) 1392 goto err_read_i2c_eeprom; 1393 1394 /* ID Module 1395 * ========= 1396 * 0 SFP_DA_CU 1397 * 1 SFP_SR 1398 * 2 SFP_LR 1399 * 3 SFP_DA_CORE0 - 82599-specific 1400 * 4 SFP_DA_CORE1 - 82599-specific 1401 * 5 SFP_SR/LR_CORE0 - 82599-specific 1402 * 6 SFP_SR/LR_CORE1 - 82599-specific 1403 * 7 SFP_act_lmt_DA_CORE0 - 82599-specific 1404 * 8 SFP_act_lmt_DA_CORE1 - 82599-specific 1405 * 9 SFP_1g_cu_CORE0 - 82599-specific 1406 * 10 SFP_1g_cu_CORE1 - 82599-specific 1407 * 11 SFP_1g_sx_CORE0 - 82599-specific 1408 * 12 SFP_1g_sx_CORE1 - 82599-specific 1409 */ 1410 if (hw->mac.type == ixgbe_mac_82598EB) { 1411 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1412 hw->phy.sfp_type = ixgbe_sfp_type_da_cu; 1413 else if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1414 hw->phy.sfp_type = ixgbe_sfp_type_sr; 1415 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1416 hw->phy.sfp_type = ixgbe_sfp_type_lr; 1417 else 1418 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1419 } else { 1420 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) { 1421 if (hw->bus.lan_id == 0) 1422 hw->phy.sfp_type = 1423 ixgbe_sfp_type_da_cu_core0; 1424 else 1425 hw->phy.sfp_type = 1426 ixgbe_sfp_type_da_cu_core1; 1427 } else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) { 1428 hw->phy.ops.read_i2c_eeprom( 1429 hw, IXGBE_SFF_CABLE_SPEC_COMP, 1430 &cable_spec); 1431 if (cable_spec & 1432 IXGBE_SFF_DA_SPEC_ACTIVE_LIMITING) { 1433 if (hw->bus.lan_id == 0) 1434 hw->phy.sfp_type = 1435 ixgbe_sfp_type_da_act_lmt_core0; 1436 else 1437 hw->phy.sfp_type = 1438 ixgbe_sfp_type_da_act_lmt_core1; 1439 } else { 1440 hw->phy.sfp_type = 1441 ixgbe_sfp_type_unknown; 1442 } 1443 } else if (comp_codes_10g & 1444 (IXGBE_SFF_10GBASESR_CAPABLE | 1445 IXGBE_SFF_10GBASELR_CAPABLE)) { 1446 if (hw->bus.lan_id == 0) 1447 hw->phy.sfp_type = 1448 ixgbe_sfp_type_srlr_core0; 1449 else 1450 hw->phy.sfp_type = 1451 ixgbe_sfp_type_srlr_core1; 1452 } else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) { 1453 if (hw->bus.lan_id == 0) 1454 hw->phy.sfp_type = 1455 ixgbe_sfp_type_1g_cu_core0; 1456 else 1457 hw->phy.sfp_type = 1458 ixgbe_sfp_type_1g_cu_core1; 1459 } else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) { 1460 if (hw->bus.lan_id == 0) 1461 hw->phy.sfp_type = 1462 ixgbe_sfp_type_1g_sx_core0; 1463 else 1464 hw->phy.sfp_type = 1465 ixgbe_sfp_type_1g_sx_core1; 1466 } else if (comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) { 1467 if (hw->bus.lan_id == 0) 1468 hw->phy.sfp_type = 1469 ixgbe_sfp_type_1g_lx_core0; 1470 else 1471 hw->phy.sfp_type = 1472 ixgbe_sfp_type_1g_lx_core1; 1473 } else { 1474 hw->phy.sfp_type = ixgbe_sfp_type_unknown; 1475 } 1476 } 1477 1478 if (hw->phy.sfp_type != stored_sfp_type) 1479 hw->phy.sfp_setup_needed = TRUE; 1480 1481 /* Determine if the SFP+ PHY is dual speed or not. */ 1482 hw->phy.multispeed_fiber = FALSE; 1483 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1484 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1485 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1486 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1487 hw->phy.multispeed_fiber = TRUE; 1488 1489 /* Determine PHY vendor */ 1490 if (hw->phy.type != ixgbe_phy_nl) { 1491 hw->phy.id = identifier; 1492 status = hw->phy.ops.read_i2c_eeprom(hw, 1493 IXGBE_SFF_VENDOR_OUI_BYTE0, 1494 &oui_bytes[0]); 1495 1496 if (status != IXGBE_SUCCESS) 1497 goto err_read_i2c_eeprom; 1498 1499 status = hw->phy.ops.read_i2c_eeprom(hw, 1500 IXGBE_SFF_VENDOR_OUI_BYTE1, 1501 &oui_bytes[1]); 1502 1503 if (status != IXGBE_SUCCESS) 1504 goto err_read_i2c_eeprom; 1505 1506 status = hw->phy.ops.read_i2c_eeprom(hw, 1507 IXGBE_SFF_VENDOR_OUI_BYTE2, 1508 &oui_bytes[2]); 1509 1510 if (status != IXGBE_SUCCESS) 1511 goto err_read_i2c_eeprom; 1512 1513 vendor_oui = 1514 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1515 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1516 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1517 1518 switch (vendor_oui) { 1519 case IXGBE_SFF_VENDOR_OUI_TYCO: 1520 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1521 hw->phy.type = 1522 ixgbe_phy_sfp_passive_tyco; 1523 break; 1524 case IXGBE_SFF_VENDOR_OUI_FTL: 1525 if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1526 hw->phy.type = ixgbe_phy_sfp_ftl_active; 1527 else 1528 hw->phy.type = ixgbe_phy_sfp_ftl; 1529 break; 1530 case IXGBE_SFF_VENDOR_OUI_AVAGO: 1531 hw->phy.type = ixgbe_phy_sfp_avago; 1532 break; 1533 case IXGBE_SFF_VENDOR_OUI_INTEL: 1534 hw->phy.type = ixgbe_phy_sfp_intel; 1535 break; 1536 default: 1537 if (cable_tech & IXGBE_SFF_DA_PASSIVE_CABLE) 1538 hw->phy.type = 1539 ixgbe_phy_sfp_passive_unknown; 1540 else if (cable_tech & IXGBE_SFF_DA_ACTIVE_CABLE) 1541 hw->phy.type = 1542 ixgbe_phy_sfp_active_unknown; 1543 else 1544 hw->phy.type = ixgbe_phy_sfp_unknown; 1545 break; 1546 } 1547 } 1548 1549 /* Allow any DA cable vendor */ 1550 if (cable_tech & (IXGBE_SFF_DA_PASSIVE_CABLE | 1551 IXGBE_SFF_DA_ACTIVE_CABLE)) { 1552 status = IXGBE_SUCCESS; 1553 goto out; 1554 } 1555 1556 /* Verify supported 1G SFP modules */ 1557 if (comp_codes_10g == 0 && 1558 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1559 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1560 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1561 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1562 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1563 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1564 hw->phy.type = ixgbe_phy_sfp_unsupported; 1565 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1566 goto out; 1567 } 1568 1569 /* Anything else 82598-based is supported */ 1570 if (hw->mac.type == ixgbe_mac_82598EB) { 1571 status = IXGBE_SUCCESS; 1572 goto out; 1573 } 1574 1575 ixgbe_get_device_caps(hw, &enforce_sfp); 1576 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP) && 1577 !(hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1578 hw->phy.sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1579 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1580 hw->phy.sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1581 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core0 || 1582 hw->phy.sfp_type == ixgbe_sfp_type_1g_sx_core1)) { 1583 /* Make sure we're a supported PHY type */ 1584 if (hw->phy.type == ixgbe_phy_sfp_intel) { 1585 status = IXGBE_SUCCESS; 1586 } else { 1587 if (hw->allow_unsupported_sfp == TRUE) { 1588 EWARN(hw, "WARNING: Intel (R) Network " 1589 "Connections are quality tested " 1590 "using Intel (R) Ethernet Optics." 1591 " Using untested modules is not " 1592 "supported and may cause unstable" 1593 " operation or damage to the " 1594 "module or the adapter. Intel " 1595 "Corporation is not responsible " 1596 "for any harm caused by using " 1597 "untested modules.\n", status); 1598 status = IXGBE_SUCCESS; 1599 } else { 1600 DEBUGOUT("SFP+ module not supported\n"); 1601 hw->phy.type = 1602 ixgbe_phy_sfp_unsupported; 1603 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1604 } 1605 } 1606 } else { 1607 status = IXGBE_SUCCESS; 1608 } 1609 } 1610 1611out: 1612 return status; 1613 1614err_read_i2c_eeprom: 1615 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1616 if (hw->phy.type != ixgbe_phy_nl) { 1617 hw->phy.id = 0; 1618 hw->phy.type = ixgbe_phy_unknown; 1619 } 1620 return IXGBE_ERR_SFP_NOT_PRESENT; 1621} 1622 1623/** 1624 * ixgbe_get_supported_phy_sfp_layer_generic - Returns physical layer type 1625 * @hw: pointer to hardware structure 1626 * 1627 * Determines physical layer capabilities of the current SFP. 1628 */ 1629s32 ixgbe_get_supported_phy_sfp_layer_generic(struct ixgbe_hw *hw) 1630{ 1631 u32 physical_layer = IXGBE_PHYSICAL_LAYER_UNKNOWN; 1632 u8 comp_codes_10g = 0; 1633 u8 comp_codes_1g = 0; 1634 1635 DEBUGFUNC("ixgbe_get_supported_phy_sfp_layer_generic"); 1636 1637 hw->phy.ops.identify_sfp(hw); 1638 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1639 return physical_layer; 1640 1641 switch (hw->phy.type) { 1642 case ixgbe_phy_sfp_passive_tyco: 1643 case ixgbe_phy_sfp_passive_unknown: 1644 case ixgbe_phy_qsfp_passive_unknown: 1645 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_PLUS_CU; 1646 break; 1647 case ixgbe_phy_sfp_ftl_active: 1648 case ixgbe_phy_sfp_active_unknown: 1649 case ixgbe_phy_qsfp_active_unknown: 1650 physical_layer = IXGBE_PHYSICAL_LAYER_SFP_ACTIVE_DA; 1651 break; 1652 case ixgbe_phy_sfp_avago: 1653 case ixgbe_phy_sfp_ftl: 1654 case ixgbe_phy_sfp_intel: 1655 case ixgbe_phy_sfp_unknown: 1656 hw->phy.ops.read_i2c_eeprom(hw, 1657 IXGBE_SFF_1GBE_COMP_CODES, &comp_codes_1g); 1658 hw->phy.ops.read_i2c_eeprom(hw, 1659 IXGBE_SFF_10GBE_COMP_CODES, &comp_codes_10g); 1660 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1661 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1662 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1663 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1664 else if (comp_codes_1g & IXGBE_SFF_1GBASET_CAPABLE) 1665 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_T; 1666 else if (comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) 1667 physical_layer = IXGBE_PHYSICAL_LAYER_1000BASE_SX; 1668 break; 1669 case ixgbe_phy_qsfp_intel: 1670 case ixgbe_phy_qsfp_unknown: 1671 hw->phy.ops.read_i2c_eeprom(hw, 1672 IXGBE_SFF_QSFP_10GBE_COMP, &comp_codes_10g); 1673 if (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE) 1674 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_SR; 1675 else if (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE) 1676 physical_layer = IXGBE_PHYSICAL_LAYER_10GBASE_LR; 1677 break; 1678 default: 1679 break; 1680 } 1681 1682 return physical_layer; 1683} 1684 1685/** 1686 * ixgbe_identify_qsfp_module_generic - Identifies QSFP modules 1687 * @hw: pointer to hardware structure 1688 * 1689 * Searches for and identifies the QSFP module and assigns appropriate PHY type 1690 **/ 1691s32 ixgbe_identify_qsfp_module_generic(struct ixgbe_hw *hw) 1692{ 1693 s32 status = IXGBE_ERR_PHY_ADDR_INVALID; 1694 u32 vendor_oui = 0; 1695 enum ixgbe_sfp_type stored_sfp_type = hw->phy.sfp_type; 1696 u8 identifier = 0; 1697 u8 comp_codes_1g = 0; 1698 u8 comp_codes_10g = 0; 1699 u8 oui_bytes[3] = {0, 0, 0}; 1700 u16 enforce_sfp = 0; 1701 u8 connector = 0; 1702 u8 cable_length = 0; 1703 u8 device_tech = 0; 1704 bool active_cable = FALSE; 1705 1706 DEBUGFUNC("ixgbe_identify_qsfp_module_generic"); 1707 1708 if (hw->mac.ops.get_media_type(hw) != ixgbe_media_type_fiber_qsfp) { 1709 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1710 status = IXGBE_ERR_SFP_NOT_PRESENT; 1711 goto out; 1712 } 1713 1714 /* LAN ID is needed for I2C access */ 1715 hw->mac.ops.set_lan_id(hw); 1716 1717 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_IDENTIFIER, 1718 &identifier); 1719 1720 if (status != IXGBE_SUCCESS) 1721 goto err_read_i2c_eeprom; 1722 1723 if (identifier != IXGBE_SFF_IDENTIFIER_QSFP_PLUS) { 1724 hw->phy.type = ixgbe_phy_sfp_unsupported; 1725 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1726 goto out; 1727 } 1728 1729 hw->phy.id = identifier; 1730 1731 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_10GBE_COMP, 1732 &comp_codes_10g); 1733 1734 if (status != IXGBE_SUCCESS) 1735 goto err_read_i2c_eeprom; 1736 1737 status = hw->phy.ops.read_i2c_eeprom(hw, IXGBE_SFF_QSFP_1GBE_COMP, 1738 &comp_codes_1g); 1739 1740 if (status != IXGBE_SUCCESS) 1741 goto err_read_i2c_eeprom; 1742 1743 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_PASSIVE_CABLE) { 1744 hw->phy.type = ixgbe_phy_qsfp_passive_unknown; 1745 if (hw->bus.lan_id == 0) 1746 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core0; 1747 else 1748 hw->phy.sfp_type = ixgbe_sfp_type_da_cu_core1; 1749 } else if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1750 IXGBE_SFF_10GBASELR_CAPABLE)) { 1751 if (hw->bus.lan_id == 0) 1752 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core0; 1753 else 1754 hw->phy.sfp_type = ixgbe_sfp_type_srlr_core1; 1755 } else { 1756 if (comp_codes_10g & IXGBE_SFF_QSFP_DA_ACTIVE_CABLE) 1757 active_cable = TRUE; 1758 1759 if (!active_cable) { 1760 /* check for active DA cables that pre-date 1761 * SFF-8436 v3.6 */ 1762 hw->phy.ops.read_i2c_eeprom(hw, 1763 IXGBE_SFF_QSFP_CONNECTOR, 1764 &connector); 1765 1766 hw->phy.ops.read_i2c_eeprom(hw, 1767 IXGBE_SFF_QSFP_CABLE_LENGTH, 1768 &cable_length); 1769 1770 hw->phy.ops.read_i2c_eeprom(hw, 1771 IXGBE_SFF_QSFP_DEVICE_TECH, 1772 &device_tech); 1773 1774 if ((connector == 1775 IXGBE_SFF_QSFP_CONNECTOR_NOT_SEPARABLE) && 1776 (cable_length > 0) && 1777 ((device_tech >> 4) == 1778 IXGBE_SFF_QSFP_TRANSMITER_850NM_VCSEL)) 1779 active_cable = TRUE; 1780 } 1781 1782 if (active_cable) { 1783 hw->phy.type = ixgbe_phy_qsfp_active_unknown; 1784 if (hw->bus.lan_id == 0) 1785 hw->phy.sfp_type = 1786 ixgbe_sfp_type_da_act_lmt_core0; 1787 else 1788 hw->phy.sfp_type = 1789 ixgbe_sfp_type_da_act_lmt_core1; 1790 } else { 1791 /* unsupported module type */ 1792 hw->phy.type = ixgbe_phy_sfp_unsupported; 1793 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1794 goto out; 1795 } 1796 } 1797 1798 if (hw->phy.sfp_type != stored_sfp_type) 1799 hw->phy.sfp_setup_needed = TRUE; 1800 1801 /* Determine if the QSFP+ PHY is dual speed or not. */ 1802 hw->phy.multispeed_fiber = FALSE; 1803 if (((comp_codes_1g & IXGBE_SFF_1GBASESX_CAPABLE) && 1804 (comp_codes_10g & IXGBE_SFF_10GBASESR_CAPABLE)) || 1805 ((comp_codes_1g & IXGBE_SFF_1GBASELX_CAPABLE) && 1806 (comp_codes_10g & IXGBE_SFF_10GBASELR_CAPABLE))) 1807 hw->phy.multispeed_fiber = TRUE; 1808 1809 /* Determine PHY vendor for optical modules */ 1810 if (comp_codes_10g & (IXGBE_SFF_10GBASESR_CAPABLE | 1811 IXGBE_SFF_10GBASELR_CAPABLE)) { 1812 status = hw->phy.ops.read_i2c_eeprom(hw, 1813 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE0, 1814 &oui_bytes[0]); 1815 1816 if (status != IXGBE_SUCCESS) 1817 goto err_read_i2c_eeprom; 1818 1819 status = hw->phy.ops.read_i2c_eeprom(hw, 1820 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE1, 1821 &oui_bytes[1]); 1822 1823 if (status != IXGBE_SUCCESS) 1824 goto err_read_i2c_eeprom; 1825 1826 status = hw->phy.ops.read_i2c_eeprom(hw, 1827 IXGBE_SFF_QSFP_VENDOR_OUI_BYTE2, 1828 &oui_bytes[2]); 1829 1830 if (status != IXGBE_SUCCESS) 1831 goto err_read_i2c_eeprom; 1832 1833 vendor_oui = 1834 ((oui_bytes[0] << IXGBE_SFF_VENDOR_OUI_BYTE0_SHIFT) | 1835 (oui_bytes[1] << IXGBE_SFF_VENDOR_OUI_BYTE1_SHIFT) | 1836 (oui_bytes[2] << IXGBE_SFF_VENDOR_OUI_BYTE2_SHIFT)); 1837 1838 if (vendor_oui == IXGBE_SFF_VENDOR_OUI_INTEL) 1839 hw->phy.type = ixgbe_phy_qsfp_intel; 1840 else 1841 hw->phy.type = ixgbe_phy_qsfp_unknown; 1842 1843 ixgbe_get_device_caps(hw, &enforce_sfp); 1844 if (!(enforce_sfp & IXGBE_DEVICE_CAPS_ALLOW_ANY_SFP)) { 1845 /* Make sure we're a supported PHY type */ 1846 if (hw->phy.type == ixgbe_phy_qsfp_intel) { 1847 status = IXGBE_SUCCESS; 1848 } else { 1849 if (hw->allow_unsupported_sfp == TRUE) { 1850 EWARN(hw, "WARNING: Intel (R) Network " 1851 "Connections are quality tested " 1852 "using Intel (R) Ethernet Optics." 1853 " Using untested modules is not " 1854 "supported and may cause unstable" 1855 " operation or damage to the " 1856 "module or the adapter. Intel " 1857 "Corporation is not responsible " 1858 "for any harm caused by using " 1859 "untested modules.\n", status); 1860 status = IXGBE_SUCCESS; 1861 } else { 1862 DEBUGOUT("QSFP module not supported\n"); 1863 hw->phy.type = 1864 ixgbe_phy_sfp_unsupported; 1865 status = IXGBE_ERR_SFP_NOT_SUPPORTED; 1866 } 1867 } 1868 } else { 1869 status = IXGBE_SUCCESS; 1870 } 1871 } 1872 1873out: 1874 return status; 1875 1876err_read_i2c_eeprom: 1877 hw->phy.sfp_type = ixgbe_sfp_type_not_present; 1878 hw->phy.id = 0; 1879 hw->phy.type = ixgbe_phy_unknown; 1880 1881 return IXGBE_ERR_SFP_NOT_PRESENT; 1882} 1883 1884 1885/** 1886 * ixgbe_get_sfp_init_sequence_offsets - Provides offset of PHY init sequence 1887 * @hw: pointer to hardware structure 1888 * @list_offset: offset to the SFP ID list 1889 * @data_offset: offset to the SFP data block 1890 * 1891 * Checks the MAC's EEPROM to see if it supports a given SFP+ module type, if 1892 * so it returns the offsets to the phy init sequence block. 1893 **/ 1894s32 ixgbe_get_sfp_init_sequence_offsets(struct ixgbe_hw *hw, 1895 u16 *list_offset, 1896 u16 *data_offset) 1897{ 1898 u16 sfp_id; 1899 u16 sfp_type = hw->phy.sfp_type; 1900 1901 DEBUGFUNC("ixgbe_get_sfp_init_sequence_offsets"); 1902 1903 if (hw->phy.sfp_type == ixgbe_sfp_type_unknown) 1904 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1905 1906 if (hw->phy.sfp_type == ixgbe_sfp_type_not_present) 1907 return IXGBE_ERR_SFP_NOT_PRESENT; 1908 1909 if ((hw->device_id == IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM) && 1910 (hw->phy.sfp_type == ixgbe_sfp_type_da_cu)) 1911 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1912 1913 /* 1914 * Limiting active cables and 1G Phys must be initialized as 1915 * SR modules 1916 */ 1917 if (sfp_type == ixgbe_sfp_type_da_act_lmt_core0 || 1918 sfp_type == ixgbe_sfp_type_1g_lx_core0 || 1919 sfp_type == ixgbe_sfp_type_1g_cu_core0 || 1920 sfp_type == ixgbe_sfp_type_1g_sx_core0) 1921 sfp_type = ixgbe_sfp_type_srlr_core0; 1922 else if (sfp_type == ixgbe_sfp_type_da_act_lmt_core1 || 1923 sfp_type == ixgbe_sfp_type_1g_lx_core1 || 1924 sfp_type == ixgbe_sfp_type_1g_cu_core1 || 1925 sfp_type == ixgbe_sfp_type_1g_sx_core1) 1926 sfp_type = ixgbe_sfp_type_srlr_core1; 1927 1928 /* Read offset to PHY init contents */ 1929 if (hw->eeprom.ops.read(hw, IXGBE_PHY_INIT_OFFSET_NL, list_offset)) { 1930 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1931 "eeprom read at offset %d failed", 1932 IXGBE_PHY_INIT_OFFSET_NL); 1933 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1934 } 1935 1936 if ((!*list_offset) || (*list_offset == 0xFFFF)) 1937 return IXGBE_ERR_SFP_NO_INIT_SEQ_PRESENT; 1938 1939 /* Shift offset to first ID word */ 1940 (*list_offset)++; 1941 1942 /* 1943 * Find the matching SFP ID in the EEPROM 1944 * and program the init sequence 1945 */ 1946 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1947 goto err_phy; 1948 1949 while (sfp_id != IXGBE_PHY_INIT_END_NL) { 1950 if (sfp_id == sfp_type) { 1951 (*list_offset)++; 1952 if (hw->eeprom.ops.read(hw, *list_offset, data_offset)) 1953 goto err_phy; 1954 if ((!*data_offset) || (*data_offset == 0xFFFF)) { 1955 DEBUGOUT("SFP+ module not supported\n"); 1956 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1957 } else { 1958 break; 1959 } 1960 } else { 1961 (*list_offset) += 2; 1962 if (hw->eeprom.ops.read(hw, *list_offset, &sfp_id)) 1963 goto err_phy; 1964 } 1965 } 1966 1967 if (sfp_id == IXGBE_PHY_INIT_END_NL) { 1968 DEBUGOUT("No matching SFP+ module found\n"); 1969 return IXGBE_ERR_SFP_NOT_SUPPORTED; 1970 } 1971 1972 return IXGBE_SUCCESS; 1973 1974err_phy: 1975 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 1976 "eeprom read at offset %d failed", *list_offset); 1977 return IXGBE_ERR_PHY; 1978} 1979 1980/** 1981 * ixgbe_read_i2c_eeprom_generic - Reads 8 bit EEPROM word over I2C interface 1982 * @hw: pointer to hardware structure 1983 * @byte_offset: EEPROM byte offset to read 1984 * @eeprom_data: value read 1985 * 1986 * Performs byte read operation to SFP module's EEPROM over I2C interface. 1987 **/ 1988s32 ixgbe_read_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 1989 u8 *eeprom_data) 1990{ 1991 DEBUGFUNC("ixgbe_read_i2c_eeprom_generic"); 1992 1993 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 1994 IXGBE_I2C_EEPROM_DEV_ADDR, 1995 eeprom_data); 1996} 1997 1998/** 1999 * ixgbe_read_i2c_sff8472_generic - Reads 8 bit word over I2C interface 2000 * @hw: pointer to hardware structure 2001 * @byte_offset: byte offset at address 0xA2 2002 * @eeprom_data: value read 2003 * 2004 * Performs byte read operation to SFP module's SFF-8472 data over I2C 2005 **/ 2006static s32 ixgbe_read_i2c_sff8472_generic(struct ixgbe_hw *hw, u8 byte_offset, 2007 u8 *sff8472_data) 2008{ 2009 return hw->phy.ops.read_i2c_byte(hw, byte_offset, 2010 IXGBE_I2C_EEPROM_DEV_ADDR2, 2011 sff8472_data); 2012} 2013 2014/** 2015 * ixgbe_write_i2c_eeprom_generic - Writes 8 bit EEPROM word over I2C interface 2016 * @hw: pointer to hardware structure 2017 * @byte_offset: EEPROM byte offset to write 2018 * @eeprom_data: value to write 2019 * 2020 * Performs byte write operation to SFP module's EEPROM over I2C interface. 2021 **/ 2022s32 ixgbe_write_i2c_eeprom_generic(struct ixgbe_hw *hw, u8 byte_offset, 2023 u8 eeprom_data) 2024{ 2025 DEBUGFUNC("ixgbe_write_i2c_eeprom_generic"); 2026 2027 return hw->phy.ops.write_i2c_byte(hw, byte_offset, 2028 IXGBE_I2C_EEPROM_DEV_ADDR, 2029 eeprom_data); 2030} 2031 2032/** 2033 * ixgbe_is_sfp_probe - Returns TRUE if SFP is being detected 2034 * @hw: pointer to hardware structure 2035 * @offset: eeprom offset to be read 2036 * @addr: I2C address to be read 2037 */ 2038static bool ixgbe_is_sfp_probe(struct ixgbe_hw *hw, u8 offset, u8 addr) 2039{ 2040 if (addr == IXGBE_I2C_EEPROM_DEV_ADDR && 2041 offset == IXGBE_SFF_IDENTIFIER && 2042 hw->phy.sfp_type == ixgbe_sfp_type_not_present) 2043 return TRUE; 2044 return FALSE; 2045} 2046 2047/** 2048 * ixgbe_read_i2c_byte_generic_int - Reads 8 bit word over I2C 2049 * @hw: pointer to hardware structure 2050 * @byte_offset: byte offset to read 2051 * @data: value read 2052 * @lock: TRUE if to take and release semaphore 2053 * 2054 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2055 * a specified device address. 2056 **/ 2057static s32 ixgbe_read_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2058 u8 dev_addr, u8 *data, bool lock) 2059{ 2060 s32 status; 2061 u32 max_retry = 10; 2062 u32 retry = 0; 2063 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2064 bool nack = 1; 2065 *data = 0; 2066 2067 DEBUGFUNC("ixgbe_read_i2c_byte_generic"); 2068 2069 if (hw->mac.type >= ixgbe_mac_X550) 2070 max_retry = 3; 2071 if (ixgbe_is_sfp_probe(hw, byte_offset, dev_addr)) 2072 max_retry = IXGBE_SFP_DETECT_RETRIES; 2073 2074 do { 2075 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask)) 2076 return IXGBE_ERR_SWFW_SYNC; 2077 2078 ixgbe_i2c_start(hw); 2079 2080 /* Device Address and write indication */ 2081 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2082 if (status != IXGBE_SUCCESS) 2083 goto fail; 2084 2085 status = ixgbe_get_i2c_ack(hw); 2086 if (status != IXGBE_SUCCESS) 2087 goto fail; 2088 2089 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2090 if (status != IXGBE_SUCCESS) 2091 goto fail; 2092 2093 status = ixgbe_get_i2c_ack(hw); 2094 if (status != IXGBE_SUCCESS) 2095 goto fail; 2096 2097 ixgbe_i2c_start(hw); 2098 2099 /* Device Address and read indication */ 2100 status = ixgbe_clock_out_i2c_byte(hw, (dev_addr | 0x1)); 2101 if (status != IXGBE_SUCCESS) 2102 goto fail; 2103 2104 status = ixgbe_get_i2c_ack(hw); 2105 if (status != IXGBE_SUCCESS) 2106 goto fail; 2107 2108 status = ixgbe_clock_in_i2c_byte(hw, data); 2109 if (status != IXGBE_SUCCESS) 2110 goto fail; 2111 2112 status = ixgbe_clock_out_i2c_bit(hw, nack); 2113 if (status != IXGBE_SUCCESS) 2114 goto fail; 2115 2116 ixgbe_i2c_stop(hw); 2117 if (lock) 2118 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2119 return IXGBE_SUCCESS; 2120 2121fail: 2122 ixgbe_i2c_bus_clear(hw); 2123 if (lock) { 2124 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2125 msec_delay(100); 2126 } 2127 retry++; 2128 if (retry < max_retry) 2129 DEBUGOUT("I2C byte read error - Retrying.\n"); 2130 else 2131 DEBUGOUT("I2C byte read error.\n"); 2132 2133 } while (retry < max_retry); 2134 2135 return status; 2136} 2137 2138/** 2139 * ixgbe_read_i2c_byte_generic - Reads 8 bit word over I2C 2140 * @hw: pointer to hardware structure 2141 * @byte_offset: byte offset to read 2142 * @data: value read 2143 * 2144 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2145 * a specified device address. 2146 **/ 2147s32 ixgbe_read_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2148 u8 dev_addr, u8 *data) 2149{ 2150 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2151 data, TRUE); 2152} 2153 2154/** 2155 * ixgbe_read_i2c_byte_generic_unlocked - Reads 8 bit word over I2C 2156 * @hw: pointer to hardware structure 2157 * @byte_offset: byte offset to read 2158 * @data: value read 2159 * 2160 * Performs byte read operation to SFP module's EEPROM over I2C interface at 2161 * a specified device address. 2162 **/ 2163s32 ixgbe_read_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2164 u8 dev_addr, u8 *data) 2165{ 2166 return ixgbe_read_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2167 data, FALSE); 2168} 2169 2170/** 2171 * ixgbe_write_i2c_byte_generic_int - Writes 8 bit word over I2C 2172 * @hw: pointer to hardware structure 2173 * @byte_offset: byte offset to write 2174 * @data: value to write 2175 * @lock: TRUE if to take and release semaphore 2176 * 2177 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2178 * a specified device address. 2179 **/ 2180static s32 ixgbe_write_i2c_byte_generic_int(struct ixgbe_hw *hw, u8 byte_offset, 2181 u8 dev_addr, u8 data, bool lock) 2182{ 2183 s32 status; 2184 u32 max_retry = 1; 2185 u32 retry = 0; 2186 u32 swfw_mask = hw->phy.phy_semaphore_mask; 2187 2188 DEBUGFUNC("ixgbe_write_i2c_byte_generic"); 2189 2190 if (lock && hw->mac.ops.acquire_swfw_sync(hw, swfw_mask) != 2191 IXGBE_SUCCESS) 2192 return IXGBE_ERR_SWFW_SYNC; 2193 2194 do { 2195 ixgbe_i2c_start(hw); 2196 2197 status = ixgbe_clock_out_i2c_byte(hw, dev_addr); 2198 if (status != IXGBE_SUCCESS) 2199 goto fail; 2200 2201 status = ixgbe_get_i2c_ack(hw); 2202 if (status != IXGBE_SUCCESS) 2203 goto fail; 2204 2205 status = ixgbe_clock_out_i2c_byte(hw, byte_offset); 2206 if (status != IXGBE_SUCCESS) 2207 goto fail; 2208 2209 status = ixgbe_get_i2c_ack(hw); 2210 if (status != IXGBE_SUCCESS) 2211 goto fail; 2212 2213 status = ixgbe_clock_out_i2c_byte(hw, data); 2214 if (status != IXGBE_SUCCESS) 2215 goto fail; 2216 2217 status = ixgbe_get_i2c_ack(hw); 2218 if (status != IXGBE_SUCCESS) 2219 goto fail; 2220 2221 ixgbe_i2c_stop(hw); 2222 if (lock) 2223 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2224 return IXGBE_SUCCESS; 2225 2226fail: 2227 ixgbe_i2c_bus_clear(hw); 2228 retry++; 2229 if (retry < max_retry) 2230 DEBUGOUT("I2C byte write error - Retrying.\n"); 2231 else 2232 DEBUGOUT("I2C byte write error.\n"); 2233 } while (retry < max_retry); 2234 2235 if (lock) 2236 hw->mac.ops.release_swfw_sync(hw, swfw_mask); 2237 2238 return status; 2239} 2240 2241/** 2242 * ixgbe_write_i2c_byte_generic - Writes 8 bit word over I2C 2243 * @hw: pointer to hardware structure 2244 * @byte_offset: byte offset to write 2245 * @data: value to write 2246 * 2247 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2248 * a specified device address. 2249 **/ 2250s32 ixgbe_write_i2c_byte_generic(struct ixgbe_hw *hw, u8 byte_offset, 2251 u8 dev_addr, u8 data) 2252{ 2253 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2254 data, TRUE); 2255} 2256 2257/** 2258 * ixgbe_write_i2c_byte_generic_unlocked - Writes 8 bit word over I2C 2259 * @hw: pointer to hardware structure 2260 * @byte_offset: byte offset to write 2261 * @data: value to write 2262 * 2263 * Performs byte write operation to SFP module's EEPROM over I2C interface at 2264 * a specified device address. 2265 **/ 2266s32 ixgbe_write_i2c_byte_generic_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 2267 u8 dev_addr, u8 data) 2268{ 2269 return ixgbe_write_i2c_byte_generic_int(hw, byte_offset, dev_addr, 2270 data, FALSE); 2271} 2272 2273/** 2274 * ixgbe_i2c_start - Sets I2C start condition 2275 * @hw: pointer to hardware structure 2276 * 2277 * Sets I2C start condition (High -> Low on SDA while SCL is High) 2278 * Set bit-bang mode on X550 hardware. 2279 **/ 2280static void ixgbe_i2c_start(struct ixgbe_hw *hw) 2281{ 2282 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2283 2284 DEBUGFUNC("ixgbe_i2c_start"); 2285 2286 i2cctl |= IXGBE_I2C_BB_EN_BY_MAC(hw); 2287 2288 /* Start condition must begin with data and clock high */ 2289 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2290 ixgbe_raise_i2c_clk(hw, &i2cctl); 2291 2292 /* Setup time for start condition (4.7us) */ 2293 usec_delay(IXGBE_I2C_T_SU_STA); 2294 2295 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2296 2297 /* Hold time for start condition (4us) */ 2298 usec_delay(IXGBE_I2C_T_HD_STA); 2299 2300 ixgbe_lower_i2c_clk(hw, &i2cctl); 2301 2302 /* Minimum low period of clock is 4.7 us */ 2303 usec_delay(IXGBE_I2C_T_LOW); 2304 2305} 2306 2307/** 2308 * ixgbe_i2c_stop - Sets I2C stop condition 2309 * @hw: pointer to hardware structure 2310 * 2311 * Sets I2C stop condition (Low -> High on SDA while SCL is High) 2312 * Disables bit-bang mode and negates data output enable on X550 2313 * hardware. 2314 **/ 2315static void ixgbe_i2c_stop(struct ixgbe_hw *hw) 2316{ 2317 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2318 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2319 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2320 u32 bb_en_bit = IXGBE_I2C_BB_EN_BY_MAC(hw); 2321 2322 DEBUGFUNC("ixgbe_i2c_stop"); 2323 2324 /* Stop condition must begin with data low and clock high */ 2325 ixgbe_set_i2c_data(hw, &i2cctl, 0); 2326 ixgbe_raise_i2c_clk(hw, &i2cctl); 2327 2328 /* Setup time for stop condition (4us) */ 2329 usec_delay(IXGBE_I2C_T_SU_STO); 2330 2331 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2332 2333 /* bus free time between stop and start (4.7us)*/ 2334 usec_delay(IXGBE_I2C_T_BUF); 2335 2336 if (bb_en_bit || data_oe_bit || clk_oe_bit) { 2337 i2cctl &= ~bb_en_bit; 2338 i2cctl |= data_oe_bit | clk_oe_bit; 2339 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2340 IXGBE_WRITE_FLUSH(hw); 2341 } 2342} 2343 2344/** 2345 * ixgbe_clock_in_i2c_byte - Clocks in one byte via I2C 2346 * @hw: pointer to hardware structure 2347 * @data: data byte to clock in 2348 * 2349 * Clocks in one byte data via I2C data/clock 2350 **/ 2351static s32 ixgbe_clock_in_i2c_byte(struct ixgbe_hw *hw, u8 *data) 2352{ 2353 s32 i; 2354 bool bit = 0; 2355 2356 DEBUGFUNC("ixgbe_clock_in_i2c_byte"); 2357 2358 *data = 0; 2359 for (i = 7; i >= 0; i--) { 2360 ixgbe_clock_in_i2c_bit(hw, &bit); 2361 *data |= bit << i; 2362 } 2363 2364 return IXGBE_SUCCESS; 2365} 2366 2367/** 2368 * ixgbe_clock_out_i2c_byte - Clocks out one byte via I2C 2369 * @hw: pointer to hardware structure 2370 * @data: data byte clocked out 2371 * 2372 * Clocks out one byte data via I2C data/clock 2373 **/ 2374static s32 ixgbe_clock_out_i2c_byte(struct ixgbe_hw *hw, u8 data) 2375{ 2376 s32 status = IXGBE_SUCCESS; 2377 s32 i; 2378 u32 i2cctl; 2379 bool bit; 2380 2381 DEBUGFUNC("ixgbe_clock_out_i2c_byte"); 2382 2383 for (i = 7; i >= 0; i--) { 2384 bit = (data >> i) & 0x1; 2385 status = ixgbe_clock_out_i2c_bit(hw, bit); 2386 2387 if (status != IXGBE_SUCCESS) 2388 break; 2389 } 2390 2391 /* Release SDA line (set high) */ 2392 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2393 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2394 i2cctl |= IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2395 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2396 IXGBE_WRITE_FLUSH(hw); 2397 2398 return status; 2399} 2400 2401/** 2402 * ixgbe_get_i2c_ack - Polls for I2C ACK 2403 * @hw: pointer to hardware structure 2404 * 2405 * Clocks in/out one bit via I2C data/clock 2406 **/ 2407static s32 ixgbe_get_i2c_ack(struct ixgbe_hw *hw) 2408{ 2409 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2410 s32 status = IXGBE_SUCCESS; 2411 u32 i = 0; 2412 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2413 u32 timeout = 10; 2414 bool ack = 1; 2415 2416 DEBUGFUNC("ixgbe_get_i2c_ack"); 2417 2418 if (data_oe_bit) { 2419 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2420 i2cctl |= data_oe_bit; 2421 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2422 IXGBE_WRITE_FLUSH(hw); 2423 } 2424 ixgbe_raise_i2c_clk(hw, &i2cctl); 2425 2426 /* Minimum high period of clock is 4us */ 2427 usec_delay(IXGBE_I2C_T_HIGH); 2428 2429 /* Poll for ACK. Note that ACK in I2C spec is 2430 * transition from 1 to 0 */ 2431 for (i = 0; i < timeout; i++) { 2432 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2433 ack = ixgbe_get_i2c_data(hw, &i2cctl); 2434 2435 usec_delay(1); 2436 if (!ack) 2437 break; 2438 } 2439 2440 if (ack) { 2441 DEBUGOUT("I2C ack was not received.\n"); 2442 status = IXGBE_ERR_I2C; 2443 } 2444 2445 ixgbe_lower_i2c_clk(hw, &i2cctl); 2446 2447 /* Minimum low period of clock is 4.7 us */ 2448 usec_delay(IXGBE_I2C_T_LOW); 2449 2450 return status; 2451} 2452 2453/** 2454 * ixgbe_clock_in_i2c_bit - Clocks in one bit via I2C data/clock 2455 * @hw: pointer to hardware structure 2456 * @data: read data value 2457 * 2458 * Clocks in one bit via I2C data/clock 2459 **/ 2460static s32 ixgbe_clock_in_i2c_bit(struct ixgbe_hw *hw, bool *data) 2461{ 2462 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2463 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2464 2465 DEBUGFUNC("ixgbe_clock_in_i2c_bit"); 2466 2467 if (data_oe_bit) { 2468 i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2469 i2cctl |= data_oe_bit; 2470 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), i2cctl); 2471 IXGBE_WRITE_FLUSH(hw); 2472 } 2473 ixgbe_raise_i2c_clk(hw, &i2cctl); 2474 2475 /* Minimum high period of clock is 4us */ 2476 usec_delay(IXGBE_I2C_T_HIGH); 2477 2478 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2479 *data = ixgbe_get_i2c_data(hw, &i2cctl); 2480 2481 ixgbe_lower_i2c_clk(hw, &i2cctl); 2482 2483 /* Minimum low period of clock is 4.7 us */ 2484 usec_delay(IXGBE_I2C_T_LOW); 2485 2486 return IXGBE_SUCCESS; 2487} 2488 2489/** 2490 * ixgbe_clock_out_i2c_bit - Clocks in/out one bit via I2C data/clock 2491 * @hw: pointer to hardware structure 2492 * @data: data value to write 2493 * 2494 * Clocks out one bit via I2C data/clock 2495 **/ 2496static s32 ixgbe_clock_out_i2c_bit(struct ixgbe_hw *hw, bool data) 2497{ 2498 s32 status; 2499 u32 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2500 2501 DEBUGFUNC("ixgbe_clock_out_i2c_bit"); 2502 2503 status = ixgbe_set_i2c_data(hw, &i2cctl, data); 2504 if (status == IXGBE_SUCCESS) { 2505 ixgbe_raise_i2c_clk(hw, &i2cctl); 2506 2507 /* Minimum high period of clock is 4us */ 2508 usec_delay(IXGBE_I2C_T_HIGH); 2509 2510 ixgbe_lower_i2c_clk(hw, &i2cctl); 2511 2512 /* Minimum low period of clock is 4.7 us. 2513 * This also takes care of the data hold time. 2514 */ 2515 usec_delay(IXGBE_I2C_T_LOW); 2516 } else { 2517 status = IXGBE_ERR_I2C; 2518 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2519 "I2C data was not set to %X\n", data); 2520 } 2521 2522 return status; 2523} 2524 2525/** 2526 * ixgbe_raise_i2c_clk - Raises the I2C SCL clock 2527 * @hw: pointer to hardware structure 2528 * @i2cctl: Current value of I2CCTL register 2529 * 2530 * Raises the I2C clock line '0'->'1' 2531 * Negates the I2C clock output enable on X550 hardware. 2532 **/ 2533static void ixgbe_raise_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2534{ 2535 u32 clk_oe_bit = IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2536 u32 i = 0; 2537 u32 timeout = IXGBE_I2C_CLOCK_STRETCHING_TIMEOUT; 2538 u32 i2cctl_r = 0; 2539 2540 DEBUGFUNC("ixgbe_raise_i2c_clk"); 2541 2542 if (clk_oe_bit) { 2543 *i2cctl |= clk_oe_bit; 2544 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2545 } 2546 2547 for (i = 0; i < timeout; i++) { 2548 *i2cctl |= IXGBE_I2C_CLK_OUT_BY_MAC(hw); 2549 2550 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2551 IXGBE_WRITE_FLUSH(hw); 2552 /* SCL rise time (1000ns) */ 2553 usec_delay(IXGBE_I2C_T_RISE); 2554 2555 i2cctl_r = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2556 if (i2cctl_r & IXGBE_I2C_CLK_IN_BY_MAC(hw)) 2557 break; 2558 } 2559} 2560 2561/** 2562 * ixgbe_lower_i2c_clk - Lowers the I2C SCL clock 2563 * @hw: pointer to hardware structure 2564 * @i2cctl: Current value of I2CCTL register 2565 * 2566 * Lowers the I2C clock line '1'->'0' 2567 * Asserts the I2C clock output enable on X550 hardware. 2568 **/ 2569static void ixgbe_lower_i2c_clk(struct ixgbe_hw *hw, u32 *i2cctl) 2570{ 2571 DEBUGFUNC("ixgbe_lower_i2c_clk"); 2572 2573 *i2cctl &= ~(IXGBE_I2C_CLK_OUT_BY_MAC(hw)); 2574 *i2cctl &= ~IXGBE_I2C_CLK_OE_N_EN_BY_MAC(hw); 2575 2576 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2577 IXGBE_WRITE_FLUSH(hw); 2578 2579 /* SCL fall time (300ns) */ 2580 usec_delay(IXGBE_I2C_T_FALL); 2581} 2582 2583/** 2584 * ixgbe_set_i2c_data - Sets the I2C data bit 2585 * @hw: pointer to hardware structure 2586 * @i2cctl: Current value of I2CCTL register 2587 * @data: I2C data value (0 or 1) to set 2588 * 2589 * Sets the I2C data bit 2590 * Asserts the I2C data output enable on X550 hardware. 2591 **/ 2592static s32 ixgbe_set_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl, bool data) 2593{ 2594 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2595 s32 status = IXGBE_SUCCESS; 2596 2597 DEBUGFUNC("ixgbe_set_i2c_data"); 2598 2599 if (data) 2600 *i2cctl |= IXGBE_I2C_DATA_OUT_BY_MAC(hw); 2601 else 2602 *i2cctl &= ~(IXGBE_I2C_DATA_OUT_BY_MAC(hw)); 2603 *i2cctl &= ~data_oe_bit; 2604 2605 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2606 IXGBE_WRITE_FLUSH(hw); 2607 2608 /* Data rise/fall (1000ns/300ns) and set-up time (250ns) */ 2609 usec_delay(IXGBE_I2C_T_RISE + IXGBE_I2C_T_FALL + IXGBE_I2C_T_SU_DATA); 2610 2611 if (!data) /* Can't verify data in this case */ 2612 return IXGBE_SUCCESS; 2613 if (data_oe_bit) { 2614 *i2cctl |= data_oe_bit; 2615 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2616 IXGBE_WRITE_FLUSH(hw); 2617 } 2618 2619 /* Verify data was set correctly */ 2620 *i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2621 if (data != ixgbe_get_i2c_data(hw, i2cctl)) { 2622 status = IXGBE_ERR_I2C; 2623 ERROR_REPORT2(IXGBE_ERROR_INVALID_STATE, 2624 "Error - I2C data was not set to %X.\n", 2625 data); 2626 } 2627 2628 return status; 2629} 2630 2631/** 2632 * ixgbe_get_i2c_data - Reads the I2C SDA data bit 2633 * @hw: pointer to hardware structure 2634 * @i2cctl: Current value of I2CCTL register 2635 * 2636 * Returns the I2C data bit value 2637 * Negates the I2C data output enable on X550 hardware. 2638 **/ 2639static bool ixgbe_get_i2c_data(struct ixgbe_hw *hw, u32 *i2cctl) 2640{ 2641 u32 data_oe_bit = IXGBE_I2C_DATA_OE_N_EN_BY_MAC(hw); 2642 bool data; 2643 2644 DEBUGFUNC("ixgbe_get_i2c_data"); 2645 2646 if (data_oe_bit) { 2647 *i2cctl |= data_oe_bit; 2648 IXGBE_WRITE_REG(hw, IXGBE_I2CCTL_BY_MAC(hw), *i2cctl); 2649 IXGBE_WRITE_FLUSH(hw); 2650 usec_delay(IXGBE_I2C_T_FALL); 2651 } 2652 2653 if (*i2cctl & IXGBE_I2C_DATA_IN_BY_MAC(hw)) 2654 data = 1; 2655 else 2656 data = 0; 2657 2658 return data; 2659} 2660 2661/** 2662 * ixgbe_i2c_bus_clear - Clears the I2C bus 2663 * @hw: pointer to hardware structure 2664 * 2665 * Clears the I2C bus by sending nine clock pulses. 2666 * Used when data line is stuck low. 2667 **/ 2668void ixgbe_i2c_bus_clear(struct ixgbe_hw *hw) 2669{ 2670 u32 i2cctl; 2671 u32 i; 2672 2673 DEBUGFUNC("ixgbe_i2c_bus_clear"); 2674 2675 ixgbe_i2c_start(hw); 2676 i2cctl = IXGBE_READ_REG(hw, IXGBE_I2CCTL_BY_MAC(hw)); 2677 2678 ixgbe_set_i2c_data(hw, &i2cctl, 1); 2679 2680 for (i = 0; i < 9; i++) { 2681 ixgbe_raise_i2c_clk(hw, &i2cctl); 2682 2683 /* Min high period of clock is 4us */ 2684 usec_delay(IXGBE_I2C_T_HIGH); 2685 2686 ixgbe_lower_i2c_clk(hw, &i2cctl); 2687 2688 /* Min low period of clock is 4.7us*/ 2689 usec_delay(IXGBE_I2C_T_LOW); 2690 } 2691 2692 ixgbe_i2c_start(hw); 2693 2694 /* Put the i2c bus back to default state */ 2695 ixgbe_i2c_stop(hw); 2696} 2697 2698/** 2699 * ixgbe_tn_check_overtemp - Checks if an overtemp occurred. 2700 * @hw: pointer to hardware structure 2701 * 2702 * Checks if the LASI temp alarm status was triggered due to overtemp 2703 **/ 2704s32 ixgbe_tn_check_overtemp(struct ixgbe_hw *hw) 2705{ 2706 s32 status = IXGBE_SUCCESS; 2707 u16 phy_data = 0; 2708 2709 DEBUGFUNC("ixgbe_tn_check_overtemp"); 2710 2711 if (hw->device_id != IXGBE_DEV_ID_82599_T3_LOM) 2712 goto out; 2713 2714 /* Check that the LASI temp alarm status was triggered */ 2715 hw->phy.ops.read_reg(hw, IXGBE_TN_LASI_STATUS_REG, 2716 IXGBE_MDIO_PMA_PMD_DEV_TYPE, &phy_data); 2717 2718 if (!(phy_data & IXGBE_TN_LASI_STATUS_TEMP_ALARM)) 2719 goto out; 2720 2721 status = IXGBE_ERR_OVERTEMP; 2722 ERROR_REPORT1(IXGBE_ERROR_CAUTION, "Device over temperature"); 2723out: 2724 return status; 2725} 2726 2727/** 2728 * ixgbe_set_copper_phy_power - Control power for copper phy 2729 * @hw: pointer to hardware structure 2730 * @on: TRUE for on, FALSE for off 2731 */ 2732s32 ixgbe_set_copper_phy_power(struct ixgbe_hw *hw, bool on) 2733{ 2734 u32 status; 2735 u16 reg; 2736 2737 status = hw->phy.ops.read_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2738 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2739 ®); 2740 if (status) 2741 return status; 2742 2743 if (on) { 2744 reg &= ~IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2745 } else { 2746 if (ixgbe_check_reset_blocked(hw)) 2747 return 0; 2748 reg |= IXGBE_MDIO_PHY_SET_LOW_POWER_MODE; 2749 } 2750 2751 status = hw->phy.ops.write_reg(hw, IXGBE_MDIO_VENDOR_SPECIFIC_1_CONTROL, 2752 IXGBE_MDIO_VENDOR_SPECIFIC_1_DEV_TYPE, 2753 reg); 2754 return status; 2755} 2756