1179055Sjfv/****************************************************************************** 2171384Sjfv 3315333Serj Copyright (c) 2001-2017, Intel Corporation 4171384Sjfv All rights reserved. 5315333Serj 6315333Serj Redistribution and use in source and binary forms, with or without 7171384Sjfv modification, are permitted provided that the following conditions are met: 8315333Serj 9315333Serj 1. Redistributions of source code must retain the above copyright notice, 10171384Sjfv this list of conditions and the following disclaimer. 11315333Serj 12315333Serj 2. Redistributions in binary form must reproduce the above copyright 13315333Serj notice, this list of conditions and the following disclaimer in the 14171384Sjfv documentation and/or other materials provided with the distribution. 15315333Serj 16315333Serj 3. Neither the name of the Intel Corporation nor the names of its 17315333Serj contributors may be used to endorse or promote products derived from 18171384Sjfv this software without specific prior written permission. 19315333Serj 20171384Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21315333Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22315333Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23315333Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24315333Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25315333Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26315333Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27315333Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28315333Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29171384Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30171384Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe_api.c 315333 2017-03-15 21:20:17Z erj $*/ 34171384Sjfv 35171384Sjfv#include "ixgbe_api.h" 36171384Sjfv#include "ixgbe_common.h" 37171384Sjfv 38295524Ssbruno#define IXGBE_EMPTY_PARAM 39295524Ssbruno 40283620Serjstatic const u32 ixgbe_mvals_base[IXGBE_MVALS_IDX_LIMIT] = { 41295524Ssbruno IXGBE_MVALS_INIT(IXGBE_EMPTY_PARAM) 42283620Serj}; 43283620Serj 44283620Serjstatic const u32 ixgbe_mvals_X540[IXGBE_MVALS_IDX_LIMIT] = { 45283620Serj IXGBE_MVALS_INIT(_X540) 46283620Serj}; 47283620Serj 48283620Serjstatic const u32 ixgbe_mvals_X550[IXGBE_MVALS_IDX_LIMIT] = { 49283620Serj IXGBE_MVALS_INIT(_X550) 50283620Serj}; 51283620Serj 52283620Serjstatic const u32 ixgbe_mvals_X550EM_x[IXGBE_MVALS_IDX_LIMIT] = { 53283620Serj IXGBE_MVALS_INIT(_X550EM_x) 54283620Serj}; 55283620Serj 56315333Serjstatic const u32 ixgbe_mvals_X550EM_a[IXGBE_MVALS_IDX_LIMIT] = { 57315333Serj IXGBE_MVALS_INIT(_X550EM_a) 58315333Serj}; 59315333Serj 60171384Sjfv/** 61251964Sjfv * ixgbe_dcb_get_rtrup2tc - read rtrup2tc reg 62251964Sjfv * @hw: pointer to hardware structure 63251964Sjfv * @map: pointer to u8 arr for returning map 64251964Sjfv * 65251964Sjfv * Read the rtrup2tc HW register and resolve its content into map 66251964Sjfv **/ 67251964Sjfvvoid ixgbe_dcb_get_rtrup2tc(struct ixgbe_hw *hw, u8 *map) 68251964Sjfv{ 69251964Sjfv if (hw->mac.ops.get_rtrup2tc) 70251964Sjfv hw->mac.ops.get_rtrup2tc(hw, map); 71251964Sjfv} 72251964Sjfv 73251964Sjfv/** 74171384Sjfv * ixgbe_init_shared_code - Initialize the shared code 75171384Sjfv * @hw: pointer to hardware structure 76171384Sjfv * 77171384Sjfv * This will assign function pointers and assign the MAC type and PHY code. 78171384Sjfv * Does not touch the hardware. This function must be called prior to any 79171384Sjfv * other function in the shared code. The ixgbe_hw structure should be 80171384Sjfv * memset to 0 prior to calling this function. The following fields in 81171384Sjfv * hw structure should be filled in prior to calling this function: 82171384Sjfv * hw_addr, back, device_id, vendor_id, subsystem_device_id, 83185352Sjfv * subsystem_vendor_id, and revision_id 84171384Sjfv **/ 85171384Sjfvs32 ixgbe_init_shared_code(struct ixgbe_hw *hw) 86171384Sjfv{ 87172043Sjfv s32 status; 88171384Sjfv 89200239Sjfv DEBUGFUNC("ixgbe_init_shared_code"); 90200239Sjfv 91171384Sjfv /* 92172043Sjfv * Set the mac type 93172043Sjfv */ 94172043Sjfv ixgbe_set_mac_type(hw); 95172043Sjfv 96172043Sjfv switch (hw->mac.type) { 97172043Sjfv case ixgbe_mac_82598EB: 98179055Sjfv status = ixgbe_init_ops_82598(hw); 99172043Sjfv break; 100190873Sjfv case ixgbe_mac_82599EB: 101190873Sjfv status = ixgbe_init_ops_82599(hw); 102190873Sjfv break; 103283620Serj case ixgbe_mac_X540: 104283620Serj status = ixgbe_init_ops_X540(hw); 105283620Serj break; 106283620Serj case ixgbe_mac_X550: 107283620Serj status = ixgbe_init_ops_X550(hw); 108283620Serj break; 109283620Serj case ixgbe_mac_X550EM_x: 110315333Serj status = ixgbe_init_ops_X550EM_x(hw); 111283620Serj break; 112315333Serj case ixgbe_mac_X550EM_a: 113315333Serj status = ixgbe_init_ops_X550EM_a(hw); 114215911Sjfv break; 115172043Sjfv default: 116172043Sjfv status = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 117172043Sjfv break; 118172043Sjfv } 119295524Ssbruno hw->mac.max_link_up_time = IXGBE_LINK_UP_TIME; 120172043Sjfv 121172043Sjfv return status; 122172043Sjfv} 123172043Sjfv 124172043Sjfv/** 125172043Sjfv * ixgbe_set_mac_type - Sets MAC type 126172043Sjfv * @hw: pointer to the HW structure 127172043Sjfv * 128172043Sjfv * This function sets the mac type of the adapter based on the 129172043Sjfv * vendor ID and device ID stored in the hw structure. 130172043Sjfv **/ 131172043Sjfvs32 ixgbe_set_mac_type(struct ixgbe_hw *hw) 132172043Sjfv{ 133172043Sjfv s32 ret_val = IXGBE_SUCCESS; 134172043Sjfv 135179055Sjfv DEBUGFUNC("ixgbe_set_mac_type\n"); 136172043Sjfv 137251964Sjfv if (hw->vendor_id != IXGBE_INTEL_VENDOR_ID) { 138251964Sjfv ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 139251964Sjfv "Unsupported vendor id: %x", hw->vendor_id); 140251964Sjfv return IXGBE_ERR_DEVICE_NOT_SUPPORTED; 141251964Sjfv } 142251964Sjfv 143283620Serj hw->mvals = ixgbe_mvals_base; 144283620Serj 145247822Sjfv switch (hw->device_id) { 146247822Sjfv case IXGBE_DEV_ID_82598: 147247822Sjfv case IXGBE_DEV_ID_82598_BX: 148247822Sjfv case IXGBE_DEV_ID_82598AF_SINGLE_PORT: 149247822Sjfv case IXGBE_DEV_ID_82598AF_DUAL_PORT: 150247822Sjfv case IXGBE_DEV_ID_82598AT: 151247822Sjfv case IXGBE_DEV_ID_82598AT2: 152247822Sjfv case IXGBE_DEV_ID_82598EB_CX4: 153247822Sjfv case IXGBE_DEV_ID_82598_CX4_DUAL_PORT: 154247822Sjfv case IXGBE_DEV_ID_82598_DA_DUAL_PORT: 155247822Sjfv case IXGBE_DEV_ID_82598_SR_DUAL_PORT_EM: 156247822Sjfv case IXGBE_DEV_ID_82598EB_XF_LR: 157247822Sjfv case IXGBE_DEV_ID_82598EB_SFP_LOM: 158247822Sjfv hw->mac.type = ixgbe_mac_82598EB; 159247822Sjfv break; 160247822Sjfv case IXGBE_DEV_ID_82599_KX4: 161247822Sjfv case IXGBE_DEV_ID_82599_KX4_MEZZ: 162247822Sjfv case IXGBE_DEV_ID_82599_XAUI_LOM: 163247822Sjfv case IXGBE_DEV_ID_82599_COMBO_BACKPLANE: 164247822Sjfv case IXGBE_DEV_ID_82599_KR: 165247822Sjfv case IXGBE_DEV_ID_82599_SFP: 166247822Sjfv case IXGBE_DEV_ID_82599_BACKPLANE_FCOE: 167247822Sjfv case IXGBE_DEV_ID_82599_SFP_FCOE: 168247822Sjfv case IXGBE_DEV_ID_82599_SFP_EM: 169247822Sjfv case IXGBE_DEV_ID_82599_SFP_SF2: 170247822Sjfv case IXGBE_DEV_ID_82599_SFP_SF_QP: 171283620Serj case IXGBE_DEV_ID_82599_QSFP_SF_QP: 172247822Sjfv case IXGBE_DEV_ID_82599EN_SFP: 173247822Sjfv case IXGBE_DEV_ID_82599_CX4: 174247822Sjfv case IXGBE_DEV_ID_82599_BYPASS: 175247822Sjfv case IXGBE_DEV_ID_82599_T3_LOM: 176247822Sjfv hw->mac.type = ixgbe_mac_82599EB; 177247822Sjfv break; 178247822Sjfv case IXGBE_DEV_ID_X540T: 179283620Serj case IXGBE_DEV_ID_X540T1: 180247822Sjfv case IXGBE_DEV_ID_X540_BYPASS: 181247822Sjfv hw->mac.type = ixgbe_mac_X540; 182283620Serj hw->mvals = ixgbe_mvals_X540; 183247822Sjfv break; 184283620Serj case IXGBE_DEV_ID_X550T: 185295524Ssbruno case IXGBE_DEV_ID_X550T1: 186283620Serj hw->mac.type = ixgbe_mac_X550; 187283620Serj hw->mvals = ixgbe_mvals_X550; 188283620Serj break; 189283620Serj case IXGBE_DEV_ID_X550EM_X_KX4: 190283620Serj case IXGBE_DEV_ID_X550EM_X_KR: 191283620Serj case IXGBE_DEV_ID_X550EM_X_10G_T: 192283620Serj case IXGBE_DEV_ID_X550EM_X_1G_T: 193283620Serj case IXGBE_DEV_ID_X550EM_X_SFP: 194315333Serj case IXGBE_DEV_ID_X550EM_X_XFI: 195283620Serj hw->mac.type = ixgbe_mac_X550EM_x; 196283620Serj hw->mvals = ixgbe_mvals_X550EM_x; 197283620Serj break; 198315333Serj case IXGBE_DEV_ID_X550EM_A_KR: 199315333Serj case IXGBE_DEV_ID_X550EM_A_KR_L: 200315333Serj case IXGBE_DEV_ID_X550EM_A_SFP_N: 201315333Serj case IXGBE_DEV_ID_X550EM_A_SGMII: 202315333Serj case IXGBE_DEV_ID_X550EM_A_SGMII_L: 203315333Serj case IXGBE_DEV_ID_X550EM_A_1G_T: 204315333Serj case IXGBE_DEV_ID_X550EM_A_1G_T_L: 205315333Serj case IXGBE_DEV_ID_X550EM_A_10G_T: 206315333Serj case IXGBE_DEV_ID_X550EM_A_QSFP: 207315333Serj case IXGBE_DEV_ID_X550EM_A_QSFP_N: 208315333Serj case IXGBE_DEV_ID_X550EM_A_SFP: 209315333Serj hw->mac.type = ixgbe_mac_X550EM_a; 210315333Serj hw->mvals = ixgbe_mvals_X550EM_a; 211283620Serj break; 212247822Sjfv default: 213172043Sjfv ret_val = IXGBE_ERR_DEVICE_NOT_SUPPORTED; 214251964Sjfv ERROR_REPORT2(IXGBE_ERROR_UNSUPPORTED, 215251964Sjfv "Unsupported device id: %x", 216251964Sjfv hw->device_id); 217247822Sjfv break; 218171384Sjfv } 219171384Sjfv 220179055Sjfv DEBUGOUT2("ixgbe_set_mac_type found mac: %d, returns: %d\n", 221230775Sjfv hw->mac.type, ret_val); 222172043Sjfv return ret_val; 223171384Sjfv} 224171384Sjfv 225171384Sjfv/** 226171384Sjfv * ixgbe_init_hw - Initialize the hardware 227171384Sjfv * @hw: pointer to hardware structure 228171384Sjfv * 229171384Sjfv * Initialize the hardware by resetting and then starting the hardware 230171384Sjfv **/ 231171384Sjfvs32 ixgbe_init_hw(struct ixgbe_hw *hw) 232171384Sjfv{ 233179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_hw, (hw), 234230775Sjfv IXGBE_NOT_IMPLEMENTED); 235171384Sjfv} 236171384Sjfv 237171384Sjfv/** 238171384Sjfv * ixgbe_reset_hw - Performs a hardware reset 239171384Sjfv * @hw: pointer to hardware structure 240171384Sjfv * 241171384Sjfv * Resets the hardware by resetting the transmit and receive units, masks and 242171384Sjfv * clears all interrupts, performs a PHY reset, and performs a MAC reset 243171384Sjfv **/ 244171384Sjfvs32 ixgbe_reset_hw(struct ixgbe_hw *hw) 245171384Sjfv{ 246179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.reset_hw, (hw), 247230775Sjfv IXGBE_NOT_IMPLEMENTED); 248171384Sjfv} 249171384Sjfv 250171384Sjfv/** 251179055Sjfv * ixgbe_start_hw - Prepares hardware for Rx/Tx 252171384Sjfv * @hw: pointer to hardware structure 253171384Sjfv * 254171384Sjfv * Starts the hardware by filling the bus info structure and media type, 255171384Sjfv * clears all on chip counters, initializes receive address registers, 256171384Sjfv * multicast table, VLAN filter table, calls routine to setup link and 257171384Sjfv * flow control settings, and leaves transmit and receive units disabled 258171384Sjfv * and uninitialized. 259171384Sjfv **/ 260171384Sjfvs32 ixgbe_start_hw(struct ixgbe_hw *hw) 261171384Sjfv{ 262179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.start_hw, (hw), 263230775Sjfv IXGBE_NOT_IMPLEMENTED); 264171384Sjfv} 265171384Sjfv 266171384Sjfv/** 267205720Sjfv * ixgbe_enable_relaxed_ordering - Enables tx relaxed ordering, 268205720Sjfv * which is disabled by default in ixgbe_start_hw(); 269205720Sjfv * 270205720Sjfv * @hw: pointer to hardware structure 271205720Sjfv * 272205720Sjfv * Enable relaxed ordering; 273205720Sjfv **/ 274205720Sjfvvoid ixgbe_enable_relaxed_ordering(struct ixgbe_hw *hw) 275205720Sjfv{ 276205720Sjfv if (hw->mac.ops.enable_relaxed_ordering) 277205720Sjfv hw->mac.ops.enable_relaxed_ordering(hw); 278205720Sjfv} 279205720Sjfv 280205720Sjfv/** 281171384Sjfv * ixgbe_clear_hw_cntrs - Clear hardware counters 282171384Sjfv * @hw: pointer to hardware structure 283171384Sjfv * 284171384Sjfv * Clears all hardware statistics counters by reading them from the hardware 285171384Sjfv * Statistics counters are clear on read. 286171384Sjfv **/ 287171384Sjfvs32 ixgbe_clear_hw_cntrs(struct ixgbe_hw *hw) 288171384Sjfv{ 289179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_hw_cntrs, (hw), 290230775Sjfv IXGBE_NOT_IMPLEMENTED); 291171384Sjfv} 292171384Sjfv 293171384Sjfv/** 294171384Sjfv * ixgbe_get_media_type - Get media type 295171384Sjfv * @hw: pointer to hardware structure 296171384Sjfv * 297171384Sjfv * Returns the media type (fiber, copper, backplane) 298171384Sjfv **/ 299171384Sjfvenum ixgbe_media_type ixgbe_get_media_type(struct ixgbe_hw *hw) 300171384Sjfv{ 301179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_media_type, (hw), 302230775Sjfv ixgbe_media_type_unknown); 303171384Sjfv} 304171384Sjfv 305171384Sjfv/** 306171384Sjfv * ixgbe_get_mac_addr - Get MAC address 307171384Sjfv * @hw: pointer to hardware structure 308171384Sjfv * @mac_addr: Adapter MAC address 309171384Sjfv * 310171384Sjfv * Reads the adapter's MAC address from the first Receive Address Register 311179055Sjfv * (RAR0) A reset of the adapter must have been performed prior to calling 312179055Sjfv * this function in order for the MAC address to have been loaded from the 313179055Sjfv * EEPROM into RAR0 314171384Sjfv **/ 315171384Sjfvs32 ixgbe_get_mac_addr(struct ixgbe_hw *hw, u8 *mac_addr) 316171384Sjfv{ 317179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_mac_addr, 318230775Sjfv (hw, mac_addr), IXGBE_NOT_IMPLEMENTED); 319171384Sjfv} 320171384Sjfv 321171384Sjfv/** 322190873Sjfv * ixgbe_get_san_mac_addr - Get SAN MAC address 323190873Sjfv * @hw: pointer to hardware structure 324190873Sjfv * @san_mac_addr: SAN MAC address 325190873Sjfv * 326190873Sjfv * Reads the SAN MAC address from the EEPROM, if it's available. This is 327190873Sjfv * per-port, so set_lan_id() must be called before reading the addresses. 328190873Sjfv **/ 329190873Sjfvs32 ixgbe_get_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 330190873Sjfv{ 331190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_san_mac_addr, 332230775Sjfv (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 333190873Sjfv} 334190873Sjfv 335190873Sjfv/** 336190873Sjfv * ixgbe_set_san_mac_addr - Write a SAN MAC address 337190873Sjfv * @hw: pointer to hardware structure 338190873Sjfv * @san_mac_addr: SAN MAC address 339190873Sjfv * 340190873Sjfv * Writes A SAN MAC address to the EEPROM. 341190873Sjfv **/ 342190873Sjfvs32 ixgbe_set_san_mac_addr(struct ixgbe_hw *hw, u8 *san_mac_addr) 343190873Sjfv{ 344190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_san_mac_addr, 345230775Sjfv (hw, san_mac_addr), IXGBE_NOT_IMPLEMENTED); 346190873Sjfv} 347190873Sjfv 348190873Sjfv/** 349190873Sjfv * ixgbe_get_device_caps - Get additional device capabilities 350190873Sjfv * @hw: pointer to hardware structure 351190873Sjfv * @device_caps: the EEPROM word for device capabilities 352190873Sjfv * 353190873Sjfv * Reads the extra device capabilities from the EEPROM 354190873Sjfv **/ 355190873Sjfvs32 ixgbe_get_device_caps(struct ixgbe_hw *hw, u16 *device_caps) 356190873Sjfv{ 357190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_device_caps, 358230775Sjfv (hw, device_caps), IXGBE_NOT_IMPLEMENTED); 359190873Sjfv} 360190873Sjfv 361190873Sjfv/** 362200239Sjfv * ixgbe_get_wwn_prefix - Get alternative WWNN/WWPN prefix from the EEPROM 363200239Sjfv * @hw: pointer to hardware structure 364200239Sjfv * @wwnn_prefix: the alternative WWNN prefix 365200239Sjfv * @wwpn_prefix: the alternative WWPN prefix 366200239Sjfv * 367200239Sjfv * This function will read the EEPROM from the alternative SAN MAC address 368200239Sjfv * block to check the support for the alternative WWNN/WWPN prefix support. 369200239Sjfv **/ 370200239Sjfvs32 ixgbe_get_wwn_prefix(struct ixgbe_hw *hw, u16 *wwnn_prefix, 371230775Sjfv u16 *wwpn_prefix) 372200239Sjfv{ 373200239Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_wwn_prefix, 374230775Sjfv (hw, wwnn_prefix, wwpn_prefix), 375230775Sjfv IXGBE_NOT_IMPLEMENTED); 376200239Sjfv} 377200239Sjfv 378200239Sjfv/** 379215911Sjfv * ixgbe_get_fcoe_boot_status - Get FCOE boot status from EEPROM 380215911Sjfv * @hw: pointer to hardware structure 381215911Sjfv * @bs: the fcoe boot status 382215911Sjfv * 383215911Sjfv * This function will read the FCOE boot status from the iSCSI FCOE block 384215911Sjfv **/ 385215911Sjfvs32 ixgbe_get_fcoe_boot_status(struct ixgbe_hw *hw, u16 *bs) 386215911Sjfv{ 387215911Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_fcoe_boot_status, 388230775Sjfv (hw, bs), 389230775Sjfv IXGBE_NOT_IMPLEMENTED); 390215911Sjfv} 391215911Sjfv 392215911Sjfv/** 393171384Sjfv * ixgbe_get_bus_info - Set PCI bus info 394171384Sjfv * @hw: pointer to hardware structure 395171384Sjfv * 396171384Sjfv * Sets the PCI bus info (speed, width, type) within the ixgbe_hw structure 397171384Sjfv **/ 398171384Sjfvs32 ixgbe_get_bus_info(struct ixgbe_hw *hw) 399171384Sjfv{ 400179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_bus_info, (hw), 401230775Sjfv IXGBE_NOT_IMPLEMENTED); 402171384Sjfv} 403171384Sjfv 404171384Sjfv/** 405179055Sjfv * ixgbe_get_num_of_tx_queues - Get Tx queues 406171384Sjfv * @hw: pointer to hardware structure 407171384Sjfv * 408171384Sjfv * Returns the number of transmit queues for the given adapter. 409171384Sjfv **/ 410171384Sjfvu32 ixgbe_get_num_of_tx_queues(struct ixgbe_hw *hw) 411171384Sjfv{ 412179055Sjfv return hw->mac.max_tx_queues; 413171384Sjfv} 414171384Sjfv 415171384Sjfv/** 416179055Sjfv * ixgbe_get_num_of_rx_queues - Get Rx queues 417171384Sjfv * @hw: pointer to hardware structure 418171384Sjfv * 419171384Sjfv * Returns the number of receive queues for the given adapter. 420171384Sjfv **/ 421171384Sjfvu32 ixgbe_get_num_of_rx_queues(struct ixgbe_hw *hw) 422171384Sjfv{ 423179055Sjfv return hw->mac.max_rx_queues; 424171384Sjfv} 425171384Sjfv 426171384Sjfv/** 427179055Sjfv * ixgbe_stop_adapter - Disable Rx/Tx units 428171384Sjfv * @hw: pointer to hardware structure 429171384Sjfv * 430171384Sjfv * Sets the adapter_stopped flag within ixgbe_hw struct. Clears interrupts, 431171384Sjfv * disables transmit and receive units. The adapter_stopped flag is used by 432171384Sjfv * the shared code and drivers to determine if the adapter is in a stopped 433171384Sjfv * state and should not touch the hardware. 434171384Sjfv **/ 435171384Sjfvs32 ixgbe_stop_adapter(struct ixgbe_hw *hw) 436171384Sjfv{ 437179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.stop_adapter, (hw), 438230775Sjfv IXGBE_NOT_IMPLEMENTED); 439171384Sjfv} 440171384Sjfv 441171384Sjfv/** 442215911Sjfv * ixgbe_read_pba_string - Reads part number string from EEPROM 443215911Sjfv * @hw: pointer to hardware structure 444215911Sjfv * @pba_num: stores the part number string from the EEPROM 445215911Sjfv * @pba_num_size: part number string buffer length 446215911Sjfv * 447215911Sjfv * Reads the part number string from the EEPROM. 448215911Sjfv **/ 449215911Sjfvs32 ixgbe_read_pba_string(struct ixgbe_hw *hw, u8 *pba_num, u32 pba_num_size) 450215911Sjfv{ 451215911Sjfv return ixgbe_read_pba_string_generic(hw, pba_num, pba_num_size); 452215911Sjfv} 453215911Sjfv 454215911Sjfv/** 455179055Sjfv * ixgbe_read_pba_num - Reads part number from EEPROM 456179055Sjfv * @hw: pointer to hardware structure 457179055Sjfv * @pba_num: stores the part number from the EEPROM 458179055Sjfv * 459179055Sjfv * Reads the part number from the EEPROM. 460179055Sjfv **/ 461179055Sjfvs32 ixgbe_read_pba_num(struct ixgbe_hw *hw, u32 *pba_num) 462179055Sjfv{ 463179055Sjfv return ixgbe_read_pba_num_generic(hw, pba_num); 464179055Sjfv} 465179055Sjfv 466179055Sjfv/** 467171384Sjfv * ixgbe_identify_phy - Get PHY type 468171384Sjfv * @hw: pointer to hardware structure 469171384Sjfv * 470171384Sjfv * Determines the physical layer module found on the current adapter. 471171384Sjfv **/ 472171384Sjfvs32 ixgbe_identify_phy(struct ixgbe_hw *hw) 473171384Sjfv{ 474171384Sjfv s32 status = IXGBE_SUCCESS; 475171384Sjfv 476171384Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 477215911Sjfv status = ixgbe_call_func(hw, hw->phy.ops.identify, (hw), 478230775Sjfv IXGBE_NOT_IMPLEMENTED); 479171384Sjfv } 480171384Sjfv 481171384Sjfv return status; 482171384Sjfv} 483171384Sjfv 484171384Sjfv/** 485171384Sjfv * ixgbe_reset_phy - Perform a PHY reset 486171384Sjfv * @hw: pointer to hardware structure 487171384Sjfv **/ 488171384Sjfvs32 ixgbe_reset_phy(struct ixgbe_hw *hw) 489171384Sjfv{ 490171384Sjfv s32 status = IXGBE_SUCCESS; 491171384Sjfv 492171384Sjfv if (hw->phy.type == ixgbe_phy_unknown) { 493185352Sjfv if (ixgbe_identify_phy(hw) != IXGBE_SUCCESS) 494185352Sjfv status = IXGBE_ERR_PHY; 495171384Sjfv } 496171384Sjfv 497171384Sjfv if (status == IXGBE_SUCCESS) { 498179055Sjfv status = ixgbe_call_func(hw, hw->phy.ops.reset, (hw), 499230775Sjfv IXGBE_NOT_IMPLEMENTED); 500171384Sjfv } 501171384Sjfv return status; 502171384Sjfv} 503171384Sjfv 504171384Sjfv/** 505179055Sjfv * ixgbe_get_phy_firmware_version - 506179055Sjfv * @hw: pointer to hardware structure 507179055Sjfv * @firmware_version: pointer to firmware version 508179055Sjfv **/ 509179055Sjfvs32 ixgbe_get_phy_firmware_version(struct ixgbe_hw *hw, u16 *firmware_version) 510179055Sjfv{ 511179055Sjfv s32 status = IXGBE_SUCCESS; 512179055Sjfv 513179055Sjfv status = ixgbe_call_func(hw, hw->phy.ops.get_firmware_version, 514230775Sjfv (hw, firmware_version), 515230775Sjfv IXGBE_NOT_IMPLEMENTED); 516179055Sjfv return status; 517179055Sjfv} 518179055Sjfv 519179055Sjfv/** 520171384Sjfv * ixgbe_read_phy_reg - Read PHY register 521171384Sjfv * @hw: pointer to hardware structure 522171384Sjfv * @reg_addr: 32 bit address of PHY register to read 523171384Sjfv * @phy_data: Pointer to read data from PHY register 524171384Sjfv * 525171384Sjfv * Reads a value from a specified PHY register 526171384Sjfv **/ 527171384Sjfvs32 ixgbe_read_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 528230775Sjfv u16 *phy_data) 529171384Sjfv{ 530190873Sjfv if (hw->phy.id == 0) 531190873Sjfv ixgbe_identify_phy(hw); 532190873Sjfv 533179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_reg, (hw, reg_addr, 534230775Sjfv device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 535171384Sjfv} 536171384Sjfv 537171384Sjfv/** 538171384Sjfv * ixgbe_write_phy_reg - Write PHY register 539171384Sjfv * @hw: pointer to hardware structure 540171384Sjfv * @reg_addr: 32 bit PHY register to write 541171384Sjfv * @phy_data: Data to write to the PHY register 542171384Sjfv * 543171384Sjfv * Writes a value to specified PHY register 544171384Sjfv **/ 545171384Sjfvs32 ixgbe_write_phy_reg(struct ixgbe_hw *hw, u32 reg_addr, u32 device_type, 546230775Sjfv u16 phy_data) 547171384Sjfv{ 548190873Sjfv if (hw->phy.id == 0) 549190873Sjfv ixgbe_identify_phy(hw); 550190873Sjfv 551179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_reg, (hw, reg_addr, 552230775Sjfv device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 553179055Sjfv} 554171384Sjfv 555179055Sjfv/** 556179055Sjfv * ixgbe_setup_phy_link - Restart PHY autoneg 557179055Sjfv * @hw: pointer to hardware structure 558179055Sjfv * 559179055Sjfv * Restart autonegotiation and PHY and waits for completion. 560179055Sjfv **/ 561179055Sjfvs32 ixgbe_setup_phy_link(struct ixgbe_hw *hw) 562179055Sjfv{ 563179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.setup_link, (hw), 564230775Sjfv IXGBE_NOT_IMPLEMENTED); 565179055Sjfv} 566171384Sjfv 567179055Sjfv/** 568283620Serj * ixgbe_setup_internal_phy - Configure integrated PHY 569283620Serj * @hw: pointer to hardware structure 570283620Serj * 571283620Serj * Reconfigure the integrated PHY in order to enable talk to the external PHY. 572283620Serj * Returns success if not implemented, since nothing needs to be done in this 573283620Serj * case. 574283620Serj */ 575283620Serjs32 ixgbe_setup_internal_phy(struct ixgbe_hw *hw) 576283620Serj{ 577283620Serj return ixgbe_call_func(hw, hw->phy.ops.setup_internal_link, (hw), 578283620Serj IXGBE_SUCCESS); 579283620Serj} 580283620Serj 581283620Serj/** 582179055Sjfv * ixgbe_check_phy_link - Determine link and speed status 583179055Sjfv * @hw: pointer to hardware structure 584179055Sjfv * 585179055Sjfv * Reads a PHY register to determine if link is up and the current speed for 586179055Sjfv * the PHY. 587179055Sjfv **/ 588179055Sjfvs32 ixgbe_check_phy_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 589230775Sjfv bool *link_up) 590179055Sjfv{ 591179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.check_link, (hw, speed, 592230775Sjfv link_up), IXGBE_NOT_IMPLEMENTED); 593171384Sjfv} 594171384Sjfv 595171384Sjfv/** 596179055Sjfv * ixgbe_setup_phy_link_speed - Set auto advertise 597179055Sjfv * @hw: pointer to hardware structure 598179055Sjfv * @speed: new link speed 599179055Sjfv * 600179055Sjfv * Sets the auto advertised capabilities 601179055Sjfv **/ 602179055Sjfvs32 ixgbe_setup_phy_link_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed, 603230775Sjfv bool autoneg_wait_to_complete) 604179055Sjfv{ 605179055Sjfv return ixgbe_call_func(hw, hw->phy.ops.setup_link_speed, (hw, speed, 606247822Sjfv autoneg_wait_to_complete), 607230775Sjfv IXGBE_NOT_IMPLEMENTED); 608179055Sjfv} 609179055Sjfv 610179055Sjfv/** 611283620Serj * ixgbe_set_phy_power - Control the phy power state 612283620Serj * @hw: pointer to hardware structure 613283620Serj * @on: TRUE for on, FALSE for off 614283620Serj */ 615283620Serjs32 ixgbe_set_phy_power(struct ixgbe_hw *hw, bool on) 616283620Serj{ 617283620Serj return ixgbe_call_func(hw, hw->phy.ops.set_phy_power, (hw, on), 618283620Serj IXGBE_NOT_IMPLEMENTED); 619283620Serj} 620283620Serj 621283620Serj/** 622171384Sjfv * ixgbe_check_link - Get link and speed status 623171384Sjfv * @hw: pointer to hardware structure 624171384Sjfv * 625171384Sjfv * Reads the links register to determine if link is up and the current speed 626171384Sjfv **/ 627171384Sjfvs32 ixgbe_check_link(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 628230775Sjfv bool *link_up, bool link_up_wait_to_complete) 629171384Sjfv{ 630179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.check_link, (hw, speed, 631230775Sjfv link_up, link_up_wait_to_complete), 632230775Sjfv IXGBE_NOT_IMPLEMENTED); 633171384Sjfv} 634171384Sjfv 635171384Sjfv/** 636215911Sjfv * ixgbe_disable_tx_laser - Disable Tx laser 637215911Sjfv * @hw: pointer to hardware structure 638215911Sjfv * 639215911Sjfv * If the driver needs to disable the laser on SFI optics. 640215911Sjfv **/ 641215911Sjfvvoid ixgbe_disable_tx_laser(struct ixgbe_hw *hw) 642215911Sjfv{ 643215911Sjfv if (hw->mac.ops.disable_tx_laser) 644215911Sjfv hw->mac.ops.disable_tx_laser(hw); 645215911Sjfv} 646215911Sjfv 647215911Sjfv/** 648215911Sjfv * ixgbe_enable_tx_laser - Enable Tx laser 649215911Sjfv * @hw: pointer to hardware structure 650215911Sjfv * 651215911Sjfv * If the driver needs to enable the laser on SFI optics. 652215911Sjfv **/ 653215911Sjfvvoid ixgbe_enable_tx_laser(struct ixgbe_hw *hw) 654215911Sjfv{ 655215911Sjfv if (hw->mac.ops.enable_tx_laser) 656215911Sjfv hw->mac.ops.enable_tx_laser(hw); 657215911Sjfv} 658215911Sjfv 659215911Sjfv/** 660215911Sjfv * ixgbe_flap_tx_laser - flap Tx laser to start autotry process 661215911Sjfv * @hw: pointer to hardware structure 662215911Sjfv * 663215911Sjfv * When the driver changes the link speeds that it can support then 664215911Sjfv * flap the tx laser to alert the link partner to start autotry 665215911Sjfv * process on its end. 666215911Sjfv **/ 667215911Sjfvvoid ixgbe_flap_tx_laser(struct ixgbe_hw *hw) 668215911Sjfv{ 669215911Sjfv if (hw->mac.ops.flap_tx_laser) 670215911Sjfv hw->mac.ops.flap_tx_laser(hw); 671215911Sjfv} 672215911Sjfv 673215911Sjfv/** 674200239Sjfv * ixgbe_setup_link - Set link speed 675171384Sjfv * @hw: pointer to hardware structure 676171384Sjfv * @speed: new link speed 677171384Sjfv * 678200239Sjfv * Configures link settings. Restarts the link. 679200239Sjfv * Performs autonegotiation if needed. 680171384Sjfv **/ 681200239Sjfvs32 ixgbe_setup_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 682230775Sjfv bool autoneg_wait_to_complete) 683171384Sjfv{ 684200239Sjfv return ixgbe_call_func(hw, hw->mac.ops.setup_link, (hw, speed, 685247822Sjfv autoneg_wait_to_complete), 686230775Sjfv IXGBE_NOT_IMPLEMENTED); 687171384Sjfv} 688171384Sjfv 689171384Sjfv/** 690283620Serj * ixgbe_setup_mac_link - Set link speed 691283620Serj * @hw: pointer to hardware structure 692283620Serj * @speed: new link speed 693283620Serj * 694283620Serj * Configures link settings. Restarts the link. 695283620Serj * Performs autonegotiation if needed. 696283620Serj **/ 697283620Serjs32 ixgbe_setup_mac_link(struct ixgbe_hw *hw, ixgbe_link_speed speed, 698283620Serj bool autoneg_wait_to_complete) 699283620Serj{ 700283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_mac_link, (hw, speed, 701283620Serj autoneg_wait_to_complete), 702283620Serj IXGBE_NOT_IMPLEMENTED); 703283620Serj} 704283620Serj 705283620Serj/** 706179055Sjfv * ixgbe_get_link_capabilities - Returns link capabilities 707171384Sjfv * @hw: pointer to hardware structure 708171384Sjfv * 709179055Sjfv * Determines the link capabilities of the current configuration. 710171384Sjfv **/ 711179055Sjfvs32 ixgbe_get_link_capabilities(struct ixgbe_hw *hw, ixgbe_link_speed *speed, 712230775Sjfv bool *autoneg) 713171384Sjfv{ 714179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_link_capabilities, (hw, 715230775Sjfv speed, autoneg), IXGBE_NOT_IMPLEMENTED); 716171384Sjfv} 717171384Sjfv 718171384Sjfv/** 719179055Sjfv * ixgbe_led_on - Turn on LEDs 720171384Sjfv * @hw: pointer to hardware structure 721171384Sjfv * @index: led number to turn on 722171384Sjfv * 723171384Sjfv * Turns on the software controllable LEDs. 724171384Sjfv **/ 725171384Sjfvs32 ixgbe_led_on(struct ixgbe_hw *hw, u32 index) 726171384Sjfv{ 727179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.led_on, (hw, index), 728230775Sjfv IXGBE_NOT_IMPLEMENTED); 729171384Sjfv} 730171384Sjfv 731171384Sjfv/** 732179055Sjfv * ixgbe_led_off - Turn off LEDs 733171384Sjfv * @hw: pointer to hardware structure 734171384Sjfv * @index: led number to turn off 735171384Sjfv * 736171384Sjfv * Turns off the software controllable LEDs. 737171384Sjfv **/ 738171384Sjfvs32 ixgbe_led_off(struct ixgbe_hw *hw, u32 index) 739171384Sjfv{ 740179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.led_off, (hw, index), 741230775Sjfv IXGBE_NOT_IMPLEMENTED); 742171384Sjfv} 743171384Sjfv 744171384Sjfv/** 745179055Sjfv * ixgbe_blink_led_start - Blink LEDs 746171384Sjfv * @hw: pointer to hardware structure 747171384Sjfv * @index: led number to blink 748171384Sjfv * 749171384Sjfv * Blink LED based on index. 750171384Sjfv **/ 751171384Sjfvs32 ixgbe_blink_led_start(struct ixgbe_hw *hw, u32 index) 752171384Sjfv{ 753179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.blink_led_start, (hw, index), 754230775Sjfv IXGBE_NOT_IMPLEMENTED); 755171384Sjfv} 756171384Sjfv 757171384Sjfv/** 758179055Sjfv * ixgbe_blink_led_stop - Stop blinking LEDs 759171384Sjfv * @hw: pointer to hardware structure 760171384Sjfv * 761171384Sjfv * Stop blinking LED based on index. 762171384Sjfv **/ 763171384Sjfvs32 ixgbe_blink_led_stop(struct ixgbe_hw *hw, u32 index) 764171384Sjfv{ 765179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.blink_led_stop, (hw, index), 766230775Sjfv IXGBE_NOT_IMPLEMENTED); 767171384Sjfv} 768171384Sjfv 769171384Sjfv/** 770179055Sjfv * ixgbe_init_eeprom_params - Initialize EEPROM parameters 771171384Sjfv * @hw: pointer to hardware structure 772171384Sjfv * 773171384Sjfv * Initializes the EEPROM parameters ixgbe_eeprom_info within the 774171384Sjfv * ixgbe_hw struct in order to set up EEPROM access. 775171384Sjfv **/ 776171384Sjfvs32 ixgbe_init_eeprom_params(struct ixgbe_hw *hw) 777171384Sjfv{ 778179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.init_params, (hw), 779230775Sjfv IXGBE_NOT_IMPLEMENTED); 780171384Sjfv} 781171384Sjfv 782171384Sjfv 783171384Sjfv/** 784171384Sjfv * ixgbe_write_eeprom - Write word to EEPROM 785171384Sjfv * @hw: pointer to hardware structure 786171384Sjfv * @offset: offset within the EEPROM to be written to 787171384Sjfv * @data: 16 bit word to be written to the EEPROM 788171384Sjfv * 789171384Sjfv * Writes 16 bit value to EEPROM. If ixgbe_eeprom_update_checksum is not 790171384Sjfv * called after this function, the EEPROM will most likely contain an 791171384Sjfv * invalid checksum. 792171384Sjfv **/ 793171384Sjfvs32 ixgbe_write_eeprom(struct ixgbe_hw *hw, u16 offset, u16 data) 794171384Sjfv{ 795179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.write, (hw, offset, data), 796230775Sjfv IXGBE_NOT_IMPLEMENTED); 797171384Sjfv} 798171384Sjfv 799171384Sjfv/** 800230775Sjfv * ixgbe_write_eeprom_buffer - Write word(s) to EEPROM 801230775Sjfv * @hw: pointer to hardware structure 802230775Sjfv * @offset: offset within the EEPROM to be written to 803230775Sjfv * @data: 16 bit word(s) to be written to the EEPROM 804230775Sjfv * @words: number of words 805230775Sjfv * 806230775Sjfv * Writes 16 bit word(s) to EEPROM. If ixgbe_eeprom_update_checksum is not 807230775Sjfv * called after this function, the EEPROM will most likely contain an 808230775Sjfv * invalid checksum. 809230775Sjfv **/ 810230775Sjfvs32 ixgbe_write_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, u16 words, 811230775Sjfv u16 *data) 812230775Sjfv{ 813230775Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.write_buffer, 814230775Sjfv (hw, offset, words, data), 815230775Sjfv IXGBE_NOT_IMPLEMENTED); 816230775Sjfv} 817230775Sjfv 818230775Sjfv/** 819171384Sjfv * ixgbe_read_eeprom - Read word from EEPROM 820171384Sjfv * @hw: pointer to hardware structure 821171384Sjfv * @offset: offset within the EEPROM to be read 822171384Sjfv * @data: read 16 bit value from EEPROM 823171384Sjfv * 824171384Sjfv * Reads 16 bit value from EEPROM 825171384Sjfv **/ 826171384Sjfvs32 ixgbe_read_eeprom(struct ixgbe_hw *hw, u16 offset, u16 *data) 827171384Sjfv{ 828179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.read, (hw, offset, data), 829230775Sjfv IXGBE_NOT_IMPLEMENTED); 830171384Sjfv} 831171384Sjfv 832171384Sjfv/** 833230775Sjfv * ixgbe_read_eeprom_buffer - Read word(s) from EEPROM 834230775Sjfv * @hw: pointer to hardware structure 835230775Sjfv * @offset: offset within the EEPROM to be read 836230775Sjfv * @data: read 16 bit word(s) from EEPROM 837230775Sjfv * @words: number of words 838230775Sjfv * 839230775Sjfv * Reads 16 bit word(s) from EEPROM 840230775Sjfv **/ 841230775Sjfvs32 ixgbe_read_eeprom_buffer(struct ixgbe_hw *hw, u16 offset, 842230775Sjfv u16 words, u16 *data) 843230775Sjfv{ 844230775Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.read_buffer, 845230775Sjfv (hw, offset, words, data), 846230775Sjfv IXGBE_NOT_IMPLEMENTED); 847230775Sjfv} 848230775Sjfv 849230775Sjfv/** 850171384Sjfv * ixgbe_validate_eeprom_checksum - Validate EEPROM checksum 851171384Sjfv * @hw: pointer to hardware structure 852171384Sjfv * @checksum_val: calculated checksum 853171384Sjfv * 854171384Sjfv * Performs checksum calculation and validates the EEPROM checksum 855171384Sjfv **/ 856171384Sjfvs32 ixgbe_validate_eeprom_checksum(struct ixgbe_hw *hw, u16 *checksum_val) 857171384Sjfv{ 858179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.validate_checksum, 859230775Sjfv (hw, checksum_val), IXGBE_NOT_IMPLEMENTED); 860171384Sjfv} 861171384Sjfv 862171384Sjfv/** 863171384Sjfv * ixgbe_eeprom_update_checksum - Updates the EEPROM checksum 864171384Sjfv * @hw: pointer to hardware structure 865171384Sjfv **/ 866171384Sjfvs32 ixgbe_update_eeprom_checksum(struct ixgbe_hw *hw) 867171384Sjfv{ 868179055Sjfv return ixgbe_call_func(hw, hw->eeprom.ops.update_checksum, (hw), 869230775Sjfv IXGBE_NOT_IMPLEMENTED); 870171384Sjfv} 871171384Sjfv 872171384Sjfv/** 873190873Sjfv * ixgbe_insert_mac_addr - Find a RAR for this mac address 874190873Sjfv * @hw: pointer to hardware structure 875190873Sjfv * @addr: Address to put into receive address register 876190873Sjfv * @vmdq: VMDq pool to assign 877190873Sjfv * 878190873Sjfv * Puts an ethernet address into a receive address register, or 879190873Sjfv * finds the rar that it is aleady in; adds to the pool list 880190873Sjfv **/ 881190873Sjfvs32 ixgbe_insert_mac_addr(struct ixgbe_hw *hw, u8 *addr, u32 vmdq) 882190873Sjfv{ 883190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.insert_mac_addr, 884230775Sjfv (hw, addr, vmdq), 885190873Sjfv IXGBE_NOT_IMPLEMENTED); 886190873Sjfv} 887190873Sjfv 888190873Sjfv/** 889179055Sjfv * ixgbe_set_rar - Set Rx address register 890171384Sjfv * @hw: pointer to hardware structure 891179055Sjfv * @index: Receive address register to write 892171384Sjfv * @addr: Address to put into receive address register 893179055Sjfv * @vmdq: VMDq "set" 894171384Sjfv * @enable_addr: set flag that address is active 895171384Sjfv * 896171384Sjfv * Puts an ethernet address into a receive address register. 897171384Sjfv **/ 898179055Sjfvs32 ixgbe_set_rar(struct ixgbe_hw *hw, u32 index, u8 *addr, u32 vmdq, 899230775Sjfv u32 enable_addr) 900171384Sjfv{ 901179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_rar, (hw, index, addr, vmdq, 902230775Sjfv enable_addr), IXGBE_NOT_IMPLEMENTED); 903171384Sjfv} 904171384Sjfv 905171384Sjfv/** 906181003Sjfv * ixgbe_clear_rar - Clear Rx address register 907181003Sjfv * @hw: pointer to hardware structure 908181003Sjfv * @index: Receive address register to write 909181003Sjfv * 910181003Sjfv * Puts an ethernet address into a receive address register. 911181003Sjfv **/ 912181003Sjfvs32 ixgbe_clear_rar(struct ixgbe_hw *hw, u32 index) 913181003Sjfv{ 914181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_rar, (hw, index), 915230775Sjfv IXGBE_NOT_IMPLEMENTED); 916181003Sjfv} 917181003Sjfv 918181003Sjfv/** 919179055Sjfv * ixgbe_set_vmdq - Associate a VMDq index with a receive address 920179055Sjfv * @hw: pointer to hardware structure 921179055Sjfv * @rar: receive address register index to associate with VMDq index 922179055Sjfv * @vmdq: VMDq set or pool index 923179055Sjfv **/ 924179055Sjfvs32 ixgbe_set_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 925179055Sjfv{ 926179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vmdq, (hw, rar, vmdq), 927230775Sjfv IXGBE_NOT_IMPLEMENTED); 928238149Sjfv 929179055Sjfv} 930179055Sjfv 931179055Sjfv/** 932238149Sjfv * ixgbe_set_vmdq_san_mac - Associate VMDq index 127 with a receive address 933238149Sjfv * @hw: pointer to hardware structure 934238149Sjfv * @vmdq: VMDq default pool index 935238149Sjfv **/ 936238149Sjfvs32 ixgbe_set_vmdq_san_mac(struct ixgbe_hw *hw, u32 vmdq) 937238149Sjfv{ 938238149Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vmdq_san_mac, 939238149Sjfv (hw, vmdq), IXGBE_NOT_IMPLEMENTED); 940238149Sjfv} 941238149Sjfv 942238149Sjfv/** 943181003Sjfv * ixgbe_clear_vmdq - Disassociate a VMDq index from a receive address 944181003Sjfv * @hw: pointer to hardware structure 945181003Sjfv * @rar: receive address register index to disassociate with VMDq index 946181003Sjfv * @vmdq: VMDq set or pool index 947181003Sjfv **/ 948181003Sjfvs32 ixgbe_clear_vmdq(struct ixgbe_hw *hw, u32 rar, u32 vmdq) 949181003Sjfv{ 950181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_vmdq, (hw, rar, vmdq), 951230775Sjfv IXGBE_NOT_IMPLEMENTED); 952181003Sjfv} 953181003Sjfv 954181003Sjfv/** 955171384Sjfv * ixgbe_init_rx_addrs - Initializes receive address filters. 956171384Sjfv * @hw: pointer to hardware structure 957171384Sjfv * 958171384Sjfv * Places the MAC address in receive address register 0 and clears the rest 959179055Sjfv * of the receive address registers. Clears the multicast table. Assumes 960171384Sjfv * the receiver is in reset when the routine is called. 961171384Sjfv **/ 962171384Sjfvs32 ixgbe_init_rx_addrs(struct ixgbe_hw *hw) 963171384Sjfv{ 964179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_rx_addrs, (hw), 965230775Sjfv IXGBE_NOT_IMPLEMENTED); 966171384Sjfv} 967171384Sjfv 968171384Sjfv/** 969171384Sjfv * ixgbe_get_num_rx_addrs - Returns the number of RAR entries. 970171384Sjfv * @hw: pointer to hardware structure 971171384Sjfv **/ 972171384Sjfvu32 ixgbe_get_num_rx_addrs(struct ixgbe_hw *hw) 973171384Sjfv{ 974179055Sjfv return hw->mac.num_rar_entries; 975171384Sjfv} 976171384Sjfv 977171384Sjfv/** 978179055Sjfv * ixgbe_update_uc_addr_list - Updates the MAC's list of secondary addresses 979179055Sjfv * @hw: pointer to hardware structure 980179055Sjfv * @addr_list: the list of new multicast addresses 981179055Sjfv * @addr_count: number of addresses 982179055Sjfv * @func: iterator function to walk the multicast address list 983179055Sjfv * 984179055Sjfv * The given list replaces any existing list. Clears the secondary addrs from 985179055Sjfv * receive address registers. Uses unused receive address registers for the 986179055Sjfv * first secondary addresses, and falls back to promiscuous mode as needed. 987179055Sjfv **/ 988179055Sjfvs32 ixgbe_update_uc_addr_list(struct ixgbe_hw *hw, u8 *addr_list, 989230775Sjfv u32 addr_count, ixgbe_mc_addr_itr func) 990179055Sjfv{ 991179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.update_uc_addr_list, (hw, 992230775Sjfv addr_list, addr_count, func), 993230775Sjfv IXGBE_NOT_IMPLEMENTED); 994179055Sjfv} 995179055Sjfv 996179055Sjfv/** 997171384Sjfv * ixgbe_update_mc_addr_list - Updates the MAC's list of multicast addresses 998171384Sjfv * @hw: pointer to hardware structure 999171384Sjfv * @mc_addr_list: the list of new multicast addresses 1000171384Sjfv * @mc_addr_count: number of addresses 1001179055Sjfv * @func: iterator function to walk the multicast address list 1002171384Sjfv * 1003171384Sjfv * The given list replaces any existing list. Clears the MC addrs from receive 1004179055Sjfv * address registers and the multicast table. Uses unused receive address 1005171384Sjfv * registers for the first multicast addresses, and hashes the rest into the 1006171384Sjfv * multicast table. 1007171384Sjfv **/ 1008171384Sjfvs32 ixgbe_update_mc_addr_list(struct ixgbe_hw *hw, u8 *mc_addr_list, 1009230775Sjfv u32 mc_addr_count, ixgbe_mc_addr_itr func, 1010230775Sjfv bool clear) 1011171384Sjfv{ 1012179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.update_mc_addr_list, (hw, 1013230775Sjfv mc_addr_list, mc_addr_count, func, clear), 1014230775Sjfv IXGBE_NOT_IMPLEMENTED); 1015171384Sjfv} 1016171384Sjfv 1017171384Sjfv/** 1018171384Sjfv * ixgbe_enable_mc - Enable multicast address in RAR 1019171384Sjfv * @hw: pointer to hardware structure 1020171384Sjfv * 1021171384Sjfv * Enables multicast address in RAR and the use of the multicast hash table. 1022171384Sjfv **/ 1023171384Sjfvs32 ixgbe_enable_mc(struct ixgbe_hw *hw) 1024171384Sjfv{ 1025179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_mc, (hw), 1026230775Sjfv IXGBE_NOT_IMPLEMENTED); 1027171384Sjfv} 1028171384Sjfv 1029171384Sjfv/** 1030171384Sjfv * ixgbe_disable_mc - Disable multicast address in RAR 1031171384Sjfv * @hw: pointer to hardware structure 1032171384Sjfv * 1033171384Sjfv * Disables multicast address in RAR and the use of the multicast hash table. 1034171384Sjfv **/ 1035171384Sjfvs32 ixgbe_disable_mc(struct ixgbe_hw *hw) 1036171384Sjfv{ 1037179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.disable_mc, (hw), 1038230775Sjfv IXGBE_NOT_IMPLEMENTED); 1039171384Sjfv} 1040171384Sjfv 1041171384Sjfv/** 1042171384Sjfv * ixgbe_clear_vfta - Clear VLAN filter table 1043171384Sjfv * @hw: pointer to hardware structure 1044171384Sjfv * 1045171384Sjfv * Clears the VLAN filer table, and the VMDq index associated with the filter 1046171384Sjfv **/ 1047171384Sjfvs32 ixgbe_clear_vfta(struct ixgbe_hw *hw) 1048171384Sjfv{ 1049179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.clear_vfta, (hw), 1050230775Sjfv IXGBE_NOT_IMPLEMENTED); 1051171384Sjfv} 1052171384Sjfv 1053171384Sjfv/** 1054171384Sjfv * ixgbe_set_vfta - Set VLAN filter table 1055171384Sjfv * @hw: pointer to hardware structure 1056171384Sjfv * @vlan: VLAN id to write to VLAN filter 1057315333Serj * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1058315333Serj * @vlan_on: boolean flag to turn on/off VLAN 1059315333Serj * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1060171384Sjfv * 1061171384Sjfv * Turn on/off specified VLAN in the VLAN filter table. 1062171384Sjfv **/ 1063315333Serjs32 ixgbe_set_vfta(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1064315333Serj bool vlvf_bypass) 1065171384Sjfv{ 1066179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vfta, (hw, vlan, vind, 1067315333Serj vlan_on, vlvf_bypass), IXGBE_NOT_IMPLEMENTED); 1068171384Sjfv} 1069171384Sjfv 1070171384Sjfv/** 1071230775Sjfv * ixgbe_set_vlvf - Set VLAN Pool Filter 1072230775Sjfv * @hw: pointer to hardware structure 1073230775Sjfv * @vlan: VLAN id to write to VLAN filter 1074315333Serj * @vind: VMDq output index that maps queue to VLAN id in VLVFB 1075315333Serj * @vlan_on: boolean flag to turn on/off VLAN in VLVF 1076315333Serj * @vfta_delta: pointer to the difference between the current value of VFTA 1077315333Serj * and the desired value 1078315333Serj * @vfta: the desired value of the VFTA 1079315333Serj * @vlvf_bypass: boolean flag indicating updating the default pool is okay 1080230775Sjfv * 1081230775Sjfv * Turn on/off specified bit in VLVF table. 1082230775Sjfv **/ 1083230775Sjfvs32 ixgbe_set_vlvf(struct ixgbe_hw *hw, u32 vlan, u32 vind, bool vlan_on, 1084315333Serj u32 *vfta_delta, u32 vfta, bool vlvf_bypass) 1085230775Sjfv{ 1086230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_vlvf, (hw, vlan, vind, 1087315333Serj vlan_on, vfta_delta, vfta, vlvf_bypass), 1088315333Serj IXGBE_NOT_IMPLEMENTED); 1089230775Sjfv} 1090230775Sjfv 1091230775Sjfv/** 1092190873Sjfv * ixgbe_fc_enable - Enable flow control 1093171384Sjfv * @hw: pointer to hardware structure 1094171384Sjfv * 1095171384Sjfv * Configures the flow control settings based on SW configuration. 1096171384Sjfv **/ 1097238149Sjfvs32 ixgbe_fc_enable(struct ixgbe_hw *hw) 1098171384Sjfv{ 1099238149Sjfv return ixgbe_call_func(hw, hw->mac.ops.fc_enable, (hw), 1100230775Sjfv IXGBE_NOT_IMPLEMENTED); 1101171384Sjfv} 1102171384Sjfv 1103172043Sjfv/** 1104283620Serj * ixgbe_setup_fc - Set up flow control 1105283620Serj * @hw: pointer to hardware structure 1106283620Serj * 1107283620Serj * Called at init time to set up flow control. 1108283620Serj **/ 1109283620Serjs32 ixgbe_setup_fc(struct ixgbe_hw *hw) 1110283620Serj{ 1111283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_fc, (hw), 1112283620Serj IXGBE_NOT_IMPLEMENTED); 1113283620Serj} 1114283620Serj 1115283620Serj/** 1116230775Sjfv * ixgbe_set_fw_drv_ver - Try to send the driver version number FW 1117230775Sjfv * @hw: pointer to hardware structure 1118230775Sjfv * @maj: driver major number to be sent to firmware 1119230775Sjfv * @min: driver minor number to be sent to firmware 1120230775Sjfv * @build: driver build number to be sent to firmware 1121230775Sjfv * @ver: driver version number to be sent to firmware 1122315333Serj * @len: length of driver_ver string 1123315333Serj * @driver_ver: driver string 1124230775Sjfv **/ 1125230775Sjfvs32 ixgbe_set_fw_drv_ver(struct ixgbe_hw *hw, u8 maj, u8 min, u8 build, 1126315333Serj u8 ver, u16 len, char *driver_ver) 1127230775Sjfv{ 1128230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.set_fw_drv_ver, (hw, maj, min, 1129315333Serj build, ver, len, driver_ver), 1130315333Serj IXGBE_NOT_IMPLEMENTED); 1131230775Sjfv} 1132230775Sjfv 1133230775Sjfv 1134251964Sjfv 1135283620Serj/** 1136283620Serj * ixgbe_dmac_config - Configure DMA Coalescing registers. 1137283620Serj * @hw: pointer to hardware structure 1138283620Serj * 1139283620Serj * Configure DMA coalescing. If enabling dmac, dmac is activated. 1140283620Serj * When disabling dmac, dmac enable dmac bit is cleared. 1141283620Serj **/ 1142283620Serjs32 ixgbe_dmac_config(struct ixgbe_hw *hw) 1143283620Serj{ 1144283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_config, (hw), 1145283620Serj IXGBE_NOT_IMPLEMENTED); 1146283620Serj} 1147251964Sjfv 1148230775Sjfv/** 1149283620Serj * ixgbe_dmac_update_tcs - Configure DMA Coalescing registers. 1150283620Serj * @hw: pointer to hardware structure 1151283620Serj * 1152283620Serj * Disables dmac, updates per TC settings, and then enable dmac. 1153283620Serj **/ 1154283620Serjs32 ixgbe_dmac_update_tcs(struct ixgbe_hw *hw) 1155283620Serj{ 1156283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_update_tcs, (hw), 1157283620Serj IXGBE_NOT_IMPLEMENTED); 1158283620Serj} 1159283620Serj 1160283620Serj/** 1161283620Serj * ixgbe_dmac_config_tcs - Configure DMA Coalescing registers. 1162283620Serj * @hw: pointer to hardware structure 1163283620Serj * 1164283620Serj * Configure DMA coalescing threshold per TC and set high priority bit for 1165283620Serj * FCOE TC. The dmac enable bit must be cleared before configuring. 1166283620Serj **/ 1167283620Serjs32 ixgbe_dmac_config_tcs(struct ixgbe_hw *hw) 1168283620Serj{ 1169283620Serj return ixgbe_call_func(hw, hw->mac.ops.dmac_config_tcs, (hw), 1170283620Serj IXGBE_NOT_IMPLEMENTED); 1171283620Serj} 1172283620Serj 1173283620Serj/** 1174283620Serj * ixgbe_setup_eee - Enable/disable EEE support 1175283620Serj * @hw: pointer to the HW structure 1176283620Serj * @enable_eee: boolean flag to enable EEE 1177283620Serj * 1178283620Serj * Enable/disable EEE based on enable_ee flag. 1179283620Serj * Auto-negotiation must be started after BASE-T EEE bits in PHY register 7.3C 1180283620Serj * are modified. 1181283620Serj * 1182283620Serj **/ 1183283620Serjs32 ixgbe_setup_eee(struct ixgbe_hw *hw, bool enable_eee) 1184283620Serj{ 1185283620Serj return ixgbe_call_func(hw, hw->mac.ops.setup_eee, (hw, enable_eee), 1186283620Serj IXGBE_NOT_IMPLEMENTED); 1187283620Serj} 1188283620Serj 1189283620Serj/** 1190283620Serj * ixgbe_set_source_address_pruning - Enable/Disable source address pruning 1191283620Serj * @hw: pointer to hardware structure 1192283620Serj * @enbale: enable or disable source address pruning 1193283620Serj * @pool: Rx pool - Rx pool to toggle source address pruning 1194283620Serj **/ 1195283620Serjvoid ixgbe_set_source_address_pruning(struct ixgbe_hw *hw, bool enable, 1196283620Serj unsigned int pool) 1197283620Serj{ 1198283620Serj if (hw->mac.ops.set_source_address_pruning) 1199283620Serj hw->mac.ops.set_source_address_pruning(hw, enable, pool); 1200283620Serj} 1201283620Serj 1202283620Serj/** 1203283620Serj * ixgbe_set_ethertype_anti_spoofing - Enable/Disable Ethertype anti-spoofing 1204283620Serj * @hw: pointer to hardware structure 1205283620Serj * @enable: enable or disable switch for Ethertype anti-spoofing 1206283620Serj * @vf: Virtual Function pool - VF Pool to set for Ethertype anti-spoofing 1207283620Serj * 1208283620Serj **/ 1209283620Serjvoid ixgbe_set_ethertype_anti_spoofing(struct ixgbe_hw *hw, bool enable, int vf) 1210283620Serj{ 1211283620Serj if (hw->mac.ops.set_ethertype_anti_spoofing) 1212283620Serj hw->mac.ops.set_ethertype_anti_spoofing(hw, enable, vf); 1213283620Serj} 1214283620Serj 1215283620Serj/** 1216283620Serj * ixgbe_read_iosf_sb_reg - Read 32 bit PHY register 1217283620Serj * @hw: pointer to hardware structure 1218283620Serj * @reg_addr: 32 bit address of PHY register to read 1219283620Serj * @device_type: type of device you want to communicate with 1220283620Serj * @phy_data: Pointer to read data from PHY register 1221283620Serj * 1222283620Serj * Reads a value from a specified PHY register 1223283620Serj **/ 1224283620Serjs32 ixgbe_read_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1225283620Serj u32 device_type, u32 *phy_data) 1226283620Serj{ 1227283620Serj return ixgbe_call_func(hw, hw->mac.ops.read_iosf_sb_reg, (hw, reg_addr, 1228283620Serj device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1229283620Serj} 1230283620Serj 1231283620Serj/** 1232283620Serj * ixgbe_write_iosf_sb_reg - Write 32 bit register through IOSF Sideband 1233283620Serj * @hw: pointer to hardware structure 1234283620Serj * @reg_addr: 32 bit PHY register to write 1235283620Serj * @device_type: type of device you want to communicate with 1236283620Serj * @phy_data: Data to write to the PHY register 1237283620Serj * 1238283620Serj * Writes a value to specified PHY register 1239283620Serj **/ 1240283620Serjs32 ixgbe_write_iosf_sb_reg(struct ixgbe_hw *hw, u32 reg_addr, 1241283620Serj u32 device_type, u32 phy_data) 1242283620Serj{ 1243283620Serj return ixgbe_call_func(hw, hw->mac.ops.write_iosf_sb_reg, (hw, reg_addr, 1244283620Serj device_type, phy_data), IXGBE_NOT_IMPLEMENTED); 1245283620Serj} 1246283620Serj 1247283620Serj/** 1248283620Serj * ixgbe_disable_mdd - Disable malicious driver detection 1249283620Serj * @hw: pointer to hardware structure 1250283620Serj * 1251283620Serj **/ 1252283620Serjvoid ixgbe_disable_mdd(struct ixgbe_hw *hw) 1253283620Serj{ 1254283620Serj if (hw->mac.ops.disable_mdd) 1255283620Serj hw->mac.ops.disable_mdd(hw); 1256283620Serj} 1257283620Serj 1258283620Serj/** 1259283620Serj * ixgbe_enable_mdd - Enable malicious driver detection 1260283620Serj * @hw: pointer to hardware structure 1261283620Serj * 1262283620Serj **/ 1263283620Serjvoid ixgbe_enable_mdd(struct ixgbe_hw *hw) 1264283620Serj{ 1265283620Serj if (hw->mac.ops.enable_mdd) 1266283620Serj hw->mac.ops.enable_mdd(hw); 1267283620Serj} 1268283620Serj 1269283620Serj/** 1270283620Serj * ixgbe_mdd_event - Handle malicious driver detection event 1271283620Serj * @hw: pointer to hardware structure 1272283620Serj * @vf_bitmap: vf bitmap of malicious vfs 1273283620Serj * 1274283620Serj **/ 1275283620Serjvoid ixgbe_mdd_event(struct ixgbe_hw *hw, u32 *vf_bitmap) 1276283620Serj{ 1277283620Serj if (hw->mac.ops.mdd_event) 1278283620Serj hw->mac.ops.mdd_event(hw, vf_bitmap); 1279283620Serj} 1280283620Serj 1281283620Serj/** 1282283620Serj * ixgbe_restore_mdd_vf - Restore VF that was disabled during malicious driver 1283283620Serj * detection event 1284283620Serj * @hw: pointer to hardware structure 1285283620Serj * @vf: vf index 1286283620Serj * 1287283620Serj **/ 1288283620Serjvoid ixgbe_restore_mdd_vf(struct ixgbe_hw *hw, u32 vf) 1289283620Serj{ 1290283620Serj if (hw->mac.ops.restore_mdd_vf) 1291283620Serj hw->mac.ops.restore_mdd_vf(hw, vf); 1292283620Serj} 1293283620Serj 1294283620Serj/** 1295283620Serj * ixgbe_enter_lplu - Transition to low power states 1296283620Serj * @hw: pointer to hardware structure 1297283620Serj * 1298283620Serj * Configures Low Power Link Up on transition to low power states 1299283620Serj * (from D0 to non-D0). 1300283620Serj **/ 1301283620Serjs32 ixgbe_enter_lplu(struct ixgbe_hw *hw) 1302283620Serj{ 1303283620Serj return ixgbe_call_func(hw, hw->phy.ops.enter_lplu, (hw), 1304283620Serj IXGBE_NOT_IMPLEMENTED); 1305283620Serj} 1306283620Serj 1307283620Serj/** 1308283620Serj * ixgbe_handle_lasi - Handle external Base T PHY interrupt 1309283620Serj * @hw: pointer to hardware structure 1310283620Serj * 1311283620Serj * Handle external Base T PHY interrupt. If high temperature 1312283620Serj * failure alarm then return error, else if link status change 1313283620Serj * then setup internal/external PHY link 1314283620Serj * 1315283620Serj * Return IXGBE_ERR_OVERTEMP if interrupt is high temperature 1316283620Serj * failure alarm, else return PHY access status. 1317283620Serj */ 1318283620Serjs32 ixgbe_handle_lasi(struct ixgbe_hw *hw) 1319283620Serj{ 1320283620Serj return ixgbe_call_func(hw, hw->phy.ops.handle_lasi, (hw), 1321283620Serj IXGBE_NOT_IMPLEMENTED); 1322283620Serj} 1323283620Serj 1324283620Serj/** 1325315333Serj * ixgbe_bypass_rw - Bit bang data into by_pass FW 1326315333Serj * @hw: pointer to hardware structure 1327315333Serj * @cmd: Command we send to the FW 1328315333Serj * @status: The reply from the FW 1329315333Serj * 1330315333Serj * Bit-bangs the cmd to the by_pass FW status points to what is returned. 1331315333Serj **/ 1332315333Serjs32 ixgbe_bypass_rw(struct ixgbe_hw *hw, u32 cmd, u32 *status) 1333315333Serj{ 1334315333Serj return ixgbe_call_func(hw, hw->mac.ops.bypass_rw, (hw, cmd, status), 1335315333Serj IXGBE_NOT_IMPLEMENTED); 1336315333Serj} 1337315333Serj 1338315333Serj/** 1339315333Serj * ixgbe_bypass_valid_rd - Verify valid return from bit-bang. 1340315333Serj * 1341315333Serj * If we send a write we can't be sure it took until we can read back 1342315333Serj * that same register. It can be a problem as some of the feilds may 1343315333Serj * for valid reasons change inbetween the time wrote the register and 1344315333Serj * we read it again to verify. So this function check everything we 1345315333Serj * can check and then assumes it worked. 1346315333Serj * 1347315333Serj * @u32 in_reg - The register cmd for the bit-bang read. 1348315333Serj * @u32 out_reg - The register returned from a bit-bang read. 1349315333Serj **/ 1350315333Serjbool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) 1351315333Serj{ 1352315333Serj return ixgbe_call_func(hw, hw->mac.ops.bypass_valid_rd, 1353315333Serj (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); 1354315333Serj} 1355315333Serj 1356315333Serj/** 1357315333Serj * ixgbe_bypass_set - Set a bypass field in the FW CTRL Regiter. 1358315333Serj * @hw: pointer to hardware structure 1359315333Serj * @cmd: The control word we are setting. 1360315333Serj * @event: The event we are setting in the FW. This also happens to 1361315333Serj * be the mask for the event we are setting (handy) 1362315333Serj * @action: The action we set the event to in the FW. This is in a 1363315333Serj * bit field that happens to be what we want to put in 1364315333Serj * the event spot (also handy) 1365315333Serj * 1366315333Serj * Writes to the cmd control the bits in actions. 1367315333Serj **/ 1368315333Serjs32 ixgbe_bypass_set(struct ixgbe_hw *hw, u32 cmd, u32 event, u32 action) 1369315333Serj{ 1370315333Serj return ixgbe_call_func(hw, hw->mac.ops.bypass_set, 1371315333Serj (hw, cmd, event, action), 1372315333Serj IXGBE_NOT_IMPLEMENTED); 1373315333Serj} 1374315333Serj 1375315333Serj/** 1376315333Serj * ixgbe_bypass_rd_eep - Read the bypass FW eeprom address 1377315333Serj * @hw: pointer to hardware structure 1378315333Serj * @addr: The bypass eeprom address to read. 1379315333Serj * @value: The 8b of data at the address above. 1380315333Serj **/ 1381315333Serjs32 ixgbe_bypass_rd_eep(struct ixgbe_hw *hw, u32 addr, u8 *value) 1382315333Serj{ 1383315333Serj return ixgbe_call_func(hw, hw->mac.ops.bypass_rd_eep, 1384315333Serj (hw, addr, value), IXGBE_NOT_IMPLEMENTED); 1385315333Serj} 1386315333Serj 1387315333Serj/** 1388172043Sjfv * ixgbe_read_analog_reg8 - Reads 8 bit analog register 1389172043Sjfv * @hw: pointer to hardware structure 1390172043Sjfv * @reg: analog register to read 1391172043Sjfv * @val: read value 1392172043Sjfv * 1393172043Sjfv * Performs write operation to analog register specified. 1394172043Sjfv **/ 1395172043Sjfvs32 ixgbe_read_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 *val) 1396172043Sjfv{ 1397179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.read_analog_reg8, (hw, reg, 1398230775Sjfv val), IXGBE_NOT_IMPLEMENTED); 1399172043Sjfv} 1400172043Sjfv 1401172043Sjfv/** 1402172043Sjfv * ixgbe_write_analog_reg8 - Writes 8 bit analog register 1403172043Sjfv * @hw: pointer to hardware structure 1404172043Sjfv * @reg: analog register to write 1405172043Sjfv * @val: value to write 1406172043Sjfv * 1407172043Sjfv * Performs write operation to Atlas analog register specified. 1408172043Sjfv **/ 1409172043Sjfvs32 ixgbe_write_analog_reg8(struct ixgbe_hw *hw, u32 reg, u8 val) 1410172043Sjfv{ 1411179055Sjfv return ixgbe_call_func(hw, hw->mac.ops.write_analog_reg8, (hw, reg, 1412230775Sjfv val), IXGBE_NOT_IMPLEMENTED); 1413172043Sjfv} 1414172043Sjfv 1415181003Sjfv/** 1416181003Sjfv * ixgbe_init_uta_tables - Initializes Unicast Table Arrays. 1417181003Sjfv * @hw: pointer to hardware structure 1418181003Sjfv * 1419185352Sjfv * Initializes the Unicast Table Arrays to zero on device load. This 1420185352Sjfv * is part of the Rx init addr execution path. 1421181003Sjfv **/ 1422181003Sjfvs32 ixgbe_init_uta_tables(struct ixgbe_hw *hw) 1423181003Sjfv{ 1424181003Sjfv return ixgbe_call_func(hw, hw->mac.ops.init_uta_tables, (hw), 1425230775Sjfv IXGBE_NOT_IMPLEMENTED); 1426181003Sjfv} 1427185352Sjfv 1428185352Sjfv/** 1429190873Sjfv * ixgbe_read_i2c_byte - Reads 8 bit word over I2C at specified device address 1430190873Sjfv * @hw: pointer to hardware structure 1431190873Sjfv * @byte_offset: byte offset to read 1432283620Serj * @dev_addr: I2C bus address to read from 1433190873Sjfv * @data: value read 1434190873Sjfv * 1435190873Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1436190873Sjfv **/ 1437190873Sjfvs32 ixgbe_read_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1438230775Sjfv u8 *data) 1439190873Sjfv{ 1440190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte, (hw, byte_offset, 1441230775Sjfv dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1442190873Sjfv} 1443190873Sjfv 1444190873Sjfv/** 1445283620Serj * ixgbe_read_i2c_byte_unlocked - Reads 8 bit word via I2C from device address 1446283620Serj * @hw: pointer to hardware structure 1447283620Serj * @byte_offset: byte offset to read 1448283620Serj * @dev_addr: I2C bus address to read from 1449283620Serj * @data: value read 1450283620Serj * 1451283620Serj * Performs byte read operation to SFP module's EEPROM over I2C interface. 1452283620Serj **/ 1453283620Serjs32 ixgbe_read_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1454283620Serj u8 dev_addr, u8 *data) 1455283620Serj{ 1456283620Serj return ixgbe_call_func(hw, hw->phy.ops.read_i2c_byte_unlocked, 1457283620Serj (hw, byte_offset, dev_addr, data), 1458283620Serj IXGBE_NOT_IMPLEMENTED); 1459283620Serj} 1460283620Serj 1461283620Serj/** 1462315333Serj * ixgbe_read_link - Perform read operation on link device 1463283620Serj * @hw: pointer to the hardware structure 1464315333Serj * @addr: bus address to read from 1465315333Serj * @reg: device register to read from 1466283620Serj * @val: pointer to location to receive read value 1467283620Serj * 1468283620Serj * Returns an error code on error. 1469283620Serj */ 1470315333Serjs32 ixgbe_read_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1471283620Serj{ 1472315333Serj return ixgbe_call_func(hw, hw->link.ops.read_link, (hw, addr, 1473283620Serj reg, val), IXGBE_NOT_IMPLEMENTED); 1474283620Serj} 1475283620Serj 1476283620Serj/** 1477315333Serj * ixgbe_read_link_unlocked - Perform read operation on link device 1478283620Serj * @hw: pointer to the hardware structure 1479315333Serj * @addr: bus address to read from 1480315333Serj * @reg: device register to read from 1481283620Serj * @val: pointer to location to receive read value 1482283620Serj * 1483283620Serj * Returns an error code on error. 1484283620Serj **/ 1485315333Serjs32 ixgbe_read_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 *val) 1486283620Serj{ 1487315333Serj return ixgbe_call_func(hw, hw->link.ops.read_link_unlocked, 1488315333Serj (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1489283620Serj} 1490283620Serj 1491283620Serj/** 1492190873Sjfv * ixgbe_write_i2c_byte - Writes 8 bit word over I2C 1493190873Sjfv * @hw: pointer to hardware structure 1494190873Sjfv * @byte_offset: byte offset to write 1495283620Serj * @dev_addr: I2C bus address to write to 1496190873Sjfv * @data: value to write 1497190873Sjfv * 1498190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface 1499190873Sjfv * at a specified device address. 1500190873Sjfv **/ 1501190873Sjfvs32 ixgbe_write_i2c_byte(struct ixgbe_hw *hw, u8 byte_offset, u8 dev_addr, 1502230775Sjfv u8 data) 1503190873Sjfv{ 1504190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte, (hw, byte_offset, 1505230775Sjfv dev_addr, data), IXGBE_NOT_IMPLEMENTED); 1506190873Sjfv} 1507190873Sjfv 1508190873Sjfv/** 1509283620Serj * ixgbe_write_i2c_byte_unlocked - Writes 8 bit word over I2C 1510283620Serj * @hw: pointer to hardware structure 1511283620Serj * @byte_offset: byte offset to write 1512283620Serj * @dev_addr: I2C bus address to write to 1513283620Serj * @data: value to write 1514283620Serj * 1515283620Serj * Performs byte write operation to SFP module's EEPROM over I2C interface 1516283620Serj * at a specified device address. 1517283620Serj **/ 1518283620Serjs32 ixgbe_write_i2c_byte_unlocked(struct ixgbe_hw *hw, u8 byte_offset, 1519283620Serj u8 dev_addr, u8 data) 1520283620Serj{ 1521283620Serj return ixgbe_call_func(hw, hw->phy.ops.write_i2c_byte_unlocked, 1522283620Serj (hw, byte_offset, dev_addr, data), 1523283620Serj IXGBE_NOT_IMPLEMENTED); 1524283620Serj} 1525283620Serj 1526283620Serj/** 1527315333Serj * ixgbe_write_link - Perform write operation on link device 1528283620Serj * @hw: pointer to the hardware structure 1529315333Serj * @addr: bus address to write to 1530315333Serj * @reg: device register to write to 1531283620Serj * @val: value to write 1532283620Serj * 1533283620Serj * Returns an error code on error. 1534283620Serj */ 1535315333Serjs32 ixgbe_write_link(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1536283620Serj{ 1537315333Serj return ixgbe_call_func(hw, hw->link.ops.write_link, 1538315333Serj (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1539283620Serj} 1540283620Serj 1541283620Serj/** 1542315333Serj * ixgbe_write_link_unlocked - Perform write operation on link device 1543283620Serj * @hw: pointer to the hardware structure 1544315333Serj * @addr: bus address to write to 1545315333Serj * @reg: device register to write to 1546283620Serj * @val: value to write 1547283620Serj * 1548283620Serj * Returns an error code on error. 1549283620Serj **/ 1550315333Serjs32 ixgbe_write_link_unlocked(struct ixgbe_hw *hw, u8 addr, u16 reg, u16 val) 1551283620Serj{ 1552315333Serj return ixgbe_call_func(hw, hw->link.ops.write_link_unlocked, 1553283620Serj (hw, addr, reg, val), IXGBE_NOT_IMPLEMENTED); 1554283620Serj} 1555283620Serj 1556283620Serj/** 1557190873Sjfv * ixgbe_write_i2c_eeprom - Writes 8 bit EEPROM word over I2C interface 1558190873Sjfv * @hw: pointer to hardware structure 1559190873Sjfv * @byte_offset: EEPROM byte offset to write 1560190873Sjfv * @eeprom_data: value to write 1561190873Sjfv * 1562190873Sjfv * Performs byte write operation to SFP module's EEPROM over I2C interface. 1563190873Sjfv **/ 1564190873Sjfvs32 ixgbe_write_i2c_eeprom(struct ixgbe_hw *hw, 1565230775Sjfv u8 byte_offset, u8 eeprom_data) 1566190873Sjfv{ 1567190873Sjfv return ixgbe_call_func(hw, hw->phy.ops.write_i2c_eeprom, 1568230775Sjfv (hw, byte_offset, eeprom_data), 1569230775Sjfv IXGBE_NOT_IMPLEMENTED); 1570190873Sjfv} 1571190873Sjfv 1572190873Sjfv/** 1573185352Sjfv * ixgbe_read_i2c_eeprom - Reads 8 bit EEPROM word over I2C interface 1574185352Sjfv * @hw: pointer to hardware structure 1575185352Sjfv * @byte_offset: EEPROM byte offset to read 1576185352Sjfv * @eeprom_data: value read 1577185352Sjfv * 1578185352Sjfv * Performs byte read operation to SFP module's EEPROM over I2C interface. 1579185352Sjfv **/ 1580185352Sjfvs32 ixgbe_read_i2c_eeprom(struct ixgbe_hw *hw, u8 byte_offset, u8 *eeprom_data) 1581185352Sjfv{ 1582185352Sjfv return ixgbe_call_func(hw, hw->phy.ops.read_i2c_eeprom, 1583230775Sjfv (hw, byte_offset, eeprom_data), 1584230775Sjfv IXGBE_NOT_IMPLEMENTED); 1585185352Sjfv} 1586185352Sjfv 1587185352Sjfv/** 1588185352Sjfv * ixgbe_get_supported_physical_layer - Returns physical layer type 1589185352Sjfv * @hw: pointer to hardware structure 1590185352Sjfv * 1591185352Sjfv * Determines physical layer capabilities of the current configuration. 1592185352Sjfv **/ 1593185352Sjfvu32 ixgbe_get_supported_physical_layer(struct ixgbe_hw *hw) 1594185352Sjfv{ 1595185352Sjfv return ixgbe_call_func(hw, hw->mac.ops.get_supported_physical_layer, 1596230775Sjfv (hw), IXGBE_PHYSICAL_LAYER_UNKNOWN); 1597185352Sjfv} 1598190873Sjfv 1599190873Sjfv/** 1600238149Sjfv * ixgbe_enable_rx_dma - Enables Rx DMA unit, dependent on device specifics 1601190873Sjfv * @hw: pointer to hardware structure 1602190873Sjfv * @regval: bitfield to write to the Rx DMA register 1603190873Sjfv * 1604190873Sjfv * Enables the Rx DMA unit of the device. 1605190873Sjfv **/ 1606190873Sjfvs32 ixgbe_enable_rx_dma(struct ixgbe_hw *hw, u32 regval) 1607190873Sjfv{ 1608190873Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_rx_dma, 1609230775Sjfv (hw, regval), IXGBE_NOT_IMPLEMENTED); 1610190873Sjfv} 1611194875Sjfv 1612194875Sjfv/** 1613230775Sjfv * ixgbe_disable_sec_rx_path - Stops the receive data path 1614230775Sjfv * @hw: pointer to hardware structure 1615230775Sjfv * 1616230775Sjfv * Stops the receive data path. 1617230775Sjfv **/ 1618230775Sjfvs32 ixgbe_disable_sec_rx_path(struct ixgbe_hw *hw) 1619230775Sjfv{ 1620230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.disable_sec_rx_path, 1621230775Sjfv (hw), IXGBE_NOT_IMPLEMENTED); 1622230775Sjfv} 1623230775Sjfv 1624230775Sjfv/** 1625230775Sjfv * ixgbe_enable_sec_rx_path - Enables the receive data path 1626230775Sjfv * @hw: pointer to hardware structure 1627230775Sjfv * 1628230775Sjfv * Enables the receive data path. 1629230775Sjfv **/ 1630230775Sjfvs32 ixgbe_enable_sec_rx_path(struct ixgbe_hw *hw) 1631230775Sjfv{ 1632230775Sjfv return ixgbe_call_func(hw, hw->mac.ops.enable_sec_rx_path, 1633230775Sjfv (hw), IXGBE_NOT_IMPLEMENTED); 1634230775Sjfv} 1635230775Sjfv 1636230775Sjfv/** 1637194875Sjfv * ixgbe_acquire_swfw_semaphore - Acquire SWFW semaphore 1638194875Sjfv * @hw: pointer to hardware structure 1639194875Sjfv * @mask: Mask to specify which semaphore to acquire 1640194875Sjfv * 1641194875Sjfv * Acquires the SWFW semaphore through SW_FW_SYNC register for the specified 1642194875Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 1643194875Sjfv **/ 1644283620Serjs32 ixgbe_acquire_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1645194875Sjfv{ 1646194875Sjfv return ixgbe_call_func(hw, hw->mac.ops.acquire_swfw_sync, 1647230775Sjfv (hw, mask), IXGBE_NOT_IMPLEMENTED); 1648194875Sjfv} 1649194875Sjfv 1650194875Sjfv/** 1651194875Sjfv * ixgbe_release_swfw_semaphore - Release SWFW semaphore 1652194875Sjfv * @hw: pointer to hardware structure 1653194875Sjfv * @mask: Mask to specify which semaphore to release 1654194875Sjfv * 1655194875Sjfv * Releases the SWFW semaphore through SW_FW_SYNC register for the specified 1656194875Sjfv * function (CSR, PHY0, PHY1, EEPROM, Flash) 1657194875Sjfv **/ 1658283620Serjvoid ixgbe_release_swfw_semaphore(struct ixgbe_hw *hw, u32 mask) 1659194875Sjfv{ 1660194875Sjfv if (hw->mac.ops.release_swfw_sync) 1661194875Sjfv hw->mac.ops.release_swfw_sync(hw, mask); 1662194875Sjfv} 1663194875Sjfv 1664315333Serj/** 1665315333Serj * ixgbe_init_swfw_semaphore - Clean up SWFW semaphore 1666315333Serj * @hw: pointer to hardware structure 1667315333Serj * 1668315333Serj * Attempts to acquire the SWFW semaphore through SW_FW_SYNC register. 1669315333Serj * Regardless of whether is succeeds or not it then release the semaphore. 1670315333Serj * This is function is called to recover from catastrophic failures that 1671315333Serj * may have left the semaphore locked. 1672315333Serj **/ 1673315333Serjvoid ixgbe_init_swfw_semaphore(struct ixgbe_hw *hw) 1674315333Serj{ 1675315333Serj if (hw->mac.ops.init_swfw_sync) 1676315333Serj hw->mac.ops.init_swfw_sync(hw); 1677315333Serj} 1678283620Serj 1679315333Serj 1680283620Serjvoid ixgbe_disable_rx(struct ixgbe_hw *hw) 1681283620Serj{ 1682283620Serj if (hw->mac.ops.disable_rx) 1683283620Serj hw->mac.ops.disable_rx(hw); 1684283620Serj} 1685283620Serj 1686283620Serjvoid ixgbe_enable_rx(struct ixgbe_hw *hw) 1687283620Serj{ 1688283620Serj if (hw->mac.ops.enable_rx) 1689283620Serj hw->mac.ops.enable_rx(hw); 1690283620Serj} 1691283620Serj 1692283620Serj/** 1693283620Serj * ixgbe_set_rate_select_speed - Set module link speed 1694283620Serj * @hw: pointer to hardware structure 1695283620Serj * @speed: link speed to set 1696283620Serj * 1697283620Serj * Set module link speed via the rate select. 1698283620Serj */ 1699283620Serjvoid ixgbe_set_rate_select_speed(struct ixgbe_hw *hw, ixgbe_link_speed speed) 1700283620Serj{ 1701283620Serj if (hw->mac.ops.set_rate_select_speed) 1702283620Serj hw->mac.ops.set_rate_select_speed(hw, speed); 1703283620Serj} 1704