ixgbe.h revision 315333
1100384Speter/****************************************************************************** 2100384Speter 3100384Speter Copyright (c) 2001-2017, Intel Corporation 4100384Speter All rights reserved. 5100384Speter 6100384Speter Redistribution and use in source and binary forms, with or without 7100384Speter modification, are permitted provided that the following conditions are met: 8100384Speter 9100384Speter 1. Redistributions of source code must retain the above copyright notice, 10100384Speter this list of conditions and the following disclaimer. 11100384Speter 12100384Speter 2. Redistributions in binary form must reproduce the above copyright 13100384Speter notice, this list of conditions and the following disclaimer in the 14100384Speter documentation and/or other materials provided with the distribution. 15100384Speter 16100384Speter 3. Neither the name of the Intel Corporation nor the names of its 17100384Speter contributors may be used to endorse or promote products derived from 18100384Speter this software without specific prior written permission. 19100384Speter 20100384Speter THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21100384Speter AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22100384Speter IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23100384Speter ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24100384Speter LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25100384Speter CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26100384Speter SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27116182Sobrien INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28116182Sobrien CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29116182Sobrien ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30100384Speter POSSIBILITY OF SUCH DAMAGE. 31100384Speter 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe.h 315333 2017-03-15 21:20:17Z erj $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#include <sys/buf_ring.h> 43#include <sys/mbuf.h> 44#include <sys/protosw.h> 45#include <sys/socket.h> 46#include <sys/malloc.h> 47#include <sys/kernel.h> 48#include <sys/module.h> 49#include <sys/sockio.h> 50#include <sys/eventhandler.h> 51 52#include <net/if.h> 53#include <net/if_var.h> 54#include <net/if_arp.h> 55#include <net/bpf.h> 56#include <net/ethernet.h> 57#include <net/if_dl.h> 58#include <net/if_media.h> 59 60#include <net/bpf.h> 61#include <net/if_types.h> 62#include <net/if_vlan_var.h> 63 64#include <netinet/in_systm.h> 65#include <netinet/in.h> 66#include <netinet/if_ether.h> 67#include <netinet/ip.h> 68#include <netinet/ip6.h> 69#include <netinet/tcp.h> 70#include <netinet/tcp_lro.h> 71#include <netinet/udp.h> 72 73#include <machine/in_cksum.h> 74 75#include <sys/bus.h> 76#include <machine/bus.h> 77#include <sys/rman.h> 78#include <machine/resource.h> 79#include <vm/vm.h> 80#include <vm/pmap.h> 81#include <machine/clock.h> 82#include <dev/pci/pcivar.h> 83#include <dev/pci/pcireg.h> 84#include <sys/proc.h> 85#include <sys/sysctl.h> 86#include <sys/endian.h> 87#include <sys/taskqueue.h> 88#include <sys/pcpu.h> 89#include <sys/smp.h> 90#include <machine/smp.h> 91#include <sys/sbuf.h> 92 93#include "ixgbe_features.h" 94#include "ixgbe_api.h" 95#include "ixgbe_common.h" 96#include "ixgbe_phy.h" 97 98/* Tunables */ 99 100/* 101 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102 * number of transmit descriptors allocated by the driver. Increasing this 103 * value allows the driver to queue more transmits. Each descriptor is 16 104 * bytes. Performance tests have show the 2K value to be optimal for top 105 * performance. 106 */ 107#define DEFAULT_TXD 1024 108#define PERFORM_TXD 2048 109#define MAX_TXD 4096 110#define MIN_TXD 64 111 112/* 113 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114 * number of receive descriptors allocated for each RX queue. Increasing this 115 * value allows the driver to buffer more incoming packets. Each descriptor 116 * is 16 bytes. A receive buffer is also allocated for each descriptor. 117 * 118 * Note: with 8 rings and a dual port card, it is possible to bump up 119 * against the system mbuf pool limit, you can tune nmbclusters 120 * to adjust for this. 121 */ 122#define DEFAULT_RXD 1024 123#define PERFORM_RXD 2048 124#define MAX_RXD 4096 125#define MIN_RXD 64 126 127/* Alignment for rings */ 128#define DBA_ALIGN 128 129 130/* 131 * This is the max watchdog interval, ie. the time that can 132 * pass between any two TX clean operations, such only happening 133 * when the TX hardware is functioning. 134 */ 135#define IXGBE_WATCHDOG (10 * hz) 136 137/* 138 * This parameters control when the driver calls the routine to reclaim 139 * transmit descriptors. 140 */ 141#define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8) 142#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) 143 144/* These defines are used in MTU calculations */ 145#define IXGBE_MAX_FRAME_SIZE 9728 146#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 147#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 148 ETHER_VLAN_ENCAP_LEN) 149#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 150#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 151 152/* Flow control constants */ 153#define IXGBE_FC_PAUSE 0xFFFF 154#define IXGBE_FC_HI 0x20000 155#define IXGBE_FC_LO 0x10000 156 157/* 158 * Used for optimizing small rx mbufs. Effort is made to keep the copy 159 * small and aligned for the CPU L1 cache. 160 * 161 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 162 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 163 * wasted. Getting 64 byte alignment, which _should_ be ideal for 164 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 165 * in observed efficiency of the optimization, 97.9% -> 81.8%. 166 */ 167#if __FreeBSD_version < 1002000 168#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 169#endif 170#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 171#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 172#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 173 174/* Keep older OS drivers building... */ 175#if !defined(SYSCTL_ADD_UQUAD) 176#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 177#endif 178 179/* Defines for printing debug information */ 180#define DEBUG_INIT 0 181#define DEBUG_IOCTL 0 182#define DEBUG_HW 0 183 184#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 185#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 186#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 187#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 188#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 189#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 190#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 191#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 192#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 193 194#define MAX_NUM_MULTICAST_ADDRESSES 128 195#define IXGBE_82598_SCATTER 100 196#define IXGBE_82599_SCATTER 32 197#define MSIX_82598_BAR 3 198#define MSIX_82599_BAR 4 199#define IXGBE_TSO_SIZE 262140 200#define IXGBE_RX_HDR 128 201#define IXGBE_VFTA_SIZE 128 202#define IXGBE_BR_SIZE 4096 203#define IXGBE_QUEUE_MIN_FREE 32 204#define IXGBE_MAX_TX_BUSY 10 205#define IXGBE_QUEUE_HUNG 0x80000000 206 207#define IXGBE_EITR_DEFAULT 128 208 209/* Supported offload bits in mbuf flag */ 210#if __FreeBSD_version >= 1000000 211#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 212 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 213 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 214#elif __FreeBSD_version >= 800000 215#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 216#else 217#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 218#endif 219 220/* Backward compatibility items for very old versions */ 221#ifndef pci_find_cap 222#define pci_find_cap pci_find_extcap 223#endif 224 225#ifndef DEVMETHOD_END 226#define DEVMETHOD_END { NULL, NULL } 227#endif 228 229/* 230 * Interrupt Moderation parameters 231 */ 232#define IXGBE_LOW_LATENCY 128 233#define IXGBE_AVE_LATENCY 400 234#define IXGBE_BULK_LATENCY 1200 235 236/* Using 1FF (the max value), the interval is ~1.05ms */ 237#define IXGBE_LINK_ITR_QUANTA 0x1FF 238#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 239 IXGBE_EITR_ITR_INT_MASK) 240 241#define IXGBE_IS_VF(_x) 0 242#define IXGBE_IS_X550VF(_x) 0 243 244/* Netmap helper macro */ 245#define IXGBE_VFTDH IXGBE_TDH 246 247/************************************************************************ 248 * vendor_info_array 249 * 250 * This array contains the list of Subvendor/Subdevice IDs on 251 * which the driver should load. 252 ************************************************************************/ 253typedef struct _ixgbe_vendor_info_t { 254 unsigned int vendor_id; 255 unsigned int device_id; 256 unsigned int subvendor_id; 257 unsigned int subdevice_id; 258 unsigned int index; 259} ixgbe_vendor_info_t; 260 261struct ixgbe_bp_data { 262 u32 low; 263 u32 high; 264 u32 log; 265}; 266 267struct ixgbe_tx_buf { 268 union ixgbe_adv_tx_desc *eop; 269 struct mbuf *m_head; 270 bus_dmamap_t map; 271}; 272 273struct ixgbe_rx_buf { 274 struct mbuf *buf; 275 struct mbuf *fmp; 276 bus_dmamap_t pmap; 277 u_int flags; 278#define IXGBE_RX_COPY 0x01 279 uint64_t addr; 280}; 281 282/* 283 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free 284 */ 285struct ixgbe_dma_alloc { 286 bus_addr_t dma_paddr; 287 caddr_t dma_vaddr; 288 bus_dma_tag_t dma_tag; 289 bus_dmamap_t dma_map; 290 bus_dma_segment_t dma_seg; 291 bus_size_t dma_size; 292 int dma_nseg; 293}; 294 295struct ixgbe_mc_addr { 296 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 297 u32 vmdq; 298}; 299 300/* 301 * Driver queue struct: this is the interrupt container 302 * for the associated tx and rx ring. 303 */ 304struct ix_queue { 305 struct adapter *adapter; 306 u32 msix; /* This queue's MSI-X vector */ 307 u32 eims; /* This queue's EIMS bit */ 308 u32 eitr_setting; 309 u32 me; 310 struct resource *res; 311 void *tag; 312 int busy; 313 struct tx_ring *txr; 314 struct rx_ring *rxr; 315 struct task que_task; 316 struct taskqueue *tq; 317 u64 irqs; 318}; 319 320/* 321 * The transmit ring, one per queue 322 */ 323struct tx_ring { 324 struct adapter *adapter; 325 struct mtx tx_mtx; 326 u32 me; 327 u32 tail; 328 int busy; 329 union ixgbe_adv_tx_desc *tx_base; 330 struct ixgbe_tx_buf *tx_buffers; 331 struct ixgbe_dma_alloc txdma; 332 volatile u16 tx_avail; 333 u16 next_avail_desc; 334 u16 next_to_clean; 335 u16 num_desc; 336 u32 txd_cmd; 337 bus_dma_tag_t txtag; 338 char mtx_name[16]; 339 struct buf_ring *br; 340 struct task txq_task; 341 342 /* Flow Director */ 343 u16 atr_sample; 344 u16 atr_count; 345 346 u32 bytes; /* used for AIM */ 347 u32 packets; 348 /* Soft Stats */ 349 unsigned long tso_tx; 350 unsigned long no_tx_map_avail; 351 unsigned long no_tx_dma_setup; 352 u64 no_desc_avail; 353 u64 total_packets; 354}; 355 356 357/* 358 * The Receive ring, one per rx queue 359 */ 360struct rx_ring { 361 struct adapter *adapter; 362 struct mtx rx_mtx; 363 u32 me; 364 u32 tail; 365 union ixgbe_adv_rx_desc *rx_base; 366 struct ixgbe_dma_alloc rxdma; 367 struct lro_ctrl lro; 368 bool lro_enabled; 369 bool hw_rsc; 370 bool vtag_strip; 371 u16 next_to_refresh; 372 u16 next_to_check; 373 u16 num_desc; 374 u16 mbuf_sz; 375 char mtx_name[16]; 376 struct ixgbe_rx_buf *rx_buffers; 377 bus_dma_tag_t ptag; 378 379 u32 bytes; /* Used for AIM calc */ 380 u32 packets; 381 382 /* Soft stats */ 383 u64 rx_irq; 384 u64 rx_copies; 385 u64 rx_packets; 386 u64 rx_bytes; 387 u64 rx_discarded; 388 u64 rsc_num; 389 390 /* Flow Director */ 391 u64 flm; 392}; 393 394#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 395 396struct ixgbe_vf { 397 u_int pool; 398 u_int rar_index; 399 u_int max_frame_size; 400 uint32_t flags; 401 uint8_t ether_addr[ETHER_ADDR_LEN]; 402 uint16_t mc_hash[IXGBE_MAX_VF_MC]; 403 uint16_t num_mc_hashes; 404 uint16_t default_vlan; 405 uint16_t vlan_tag; 406 uint16_t api_ver; 407}; 408 409/* Our adapter structure */ 410struct adapter { 411 struct ixgbe_hw hw; 412 struct ixgbe_osdep osdep; 413 414 struct device *dev; 415 struct ifnet *ifp; 416 417 struct resource *pci_mem; 418 struct resource *msix_mem; 419 420 /* 421 * Interrupt resources: this set is 422 * either used for legacy, or for Link 423 * when doing MSI-X 424 */ 425 void *tag; 426 struct resource *res; 427 428 struct ifmedia media; 429 struct callout timer; 430 int link_rid; 431 int if_flags; 432 433 struct mtx core_mtx; 434 435 eventhandler_tag vlan_attach; 436 eventhandler_tag vlan_detach; 437 438 u16 num_vlans; 439 u16 num_queues; 440 441 /* 442 * Shadow VFTA table, this is needed because 443 * the real vlan filter table gets cleared during 444 * a soft reset and the driver needs to be able 445 * to repopulate it. 446 */ 447 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 448 449 /* Info about the interface */ 450 int advertise; /* link speeds */ 451 bool enable_aim; /* adaptive interrupt moderation */ 452 bool link_active; 453 u16 max_frame_size; 454 u16 num_segs; 455 u32 link_speed; 456 bool link_up; 457 u32 vector; 458 u16 dmac; 459 u32 phy_layer; 460 461 /* Power management-related */ 462 bool wol_support; 463 u32 wufc; 464 465 /* Mbuf cluster size */ 466 u32 rx_mbuf_sz; 467 468 /* Support for pluggable optics */ 469 bool sfp_probe; 470 struct task link_task; /* Link tasklet */ 471 struct task mod_task; /* SFP tasklet */ 472 struct task msf_task; /* Multispeed Fiber */ 473 struct task mbx_task; /* VF -> PF mailbox interrupt */ 474 475 /* Flow Director */ 476 int fdir_reinit; 477 struct task fdir_task; 478 479 struct task phy_task; /* PHY intr tasklet */ 480 struct taskqueue *tq; 481 482 /* 483 * Queues: 484 * This is the irq holder, it has 485 * and RX/TX pair or rings associated 486 * with it. 487 */ 488 struct ix_queue *queues; 489 490 /* 491 * Transmit rings 492 * Allocated at run time, an array of rings 493 */ 494 struct tx_ring *tx_rings; 495 u32 num_tx_desc; 496 u32 tx_process_limit; 497 498 /* 499 * Receive rings 500 * Allocated at run time, an array of rings 501 */ 502 struct rx_ring *rx_rings; 503 u64 active_queues; 504 u32 num_rx_desc; 505 u32 rx_process_limit; 506 507 /* Multicast array memory */ 508 struct ixgbe_mc_addr *mta; 509 510 /* SR-IOV */ 511 int iov_mode; 512 int num_vfs; 513 int pool; 514 struct ixgbe_vf *vfs; 515 516 /* Bypass */ 517 struct ixgbe_bp_data bypass; 518 519 /* Netmap */ 520 void (*init_locked)(struct adapter *); 521 void (*stop_locked)(void *); 522 523 /* Misc stats maintained by the driver */ 524 unsigned long dropped_pkts; 525 unsigned long mbuf_defrag_failed; 526 unsigned long mbuf_header_failed; 527 unsigned long mbuf_packet_failed; 528 unsigned long watchdog_events; 529 unsigned long link_irq; 530 struct ixgbe_hw_stats stats_pf; 531#if __FreeBSD_version >= 1100036 532 /* counter(9) stats */ 533 u64 ipackets; 534 u64 ierrors; 535 u64 opackets; 536 u64 oerrors; 537 u64 ibytes; 538 u64 obytes; 539 u64 imcasts; 540 u64 omcasts; 541 u64 iqdrops; 542 u64 noproto; 543#endif 544 /* Feature capable/enabled flags. See ixgbe_features.h */ 545 u32 feat_cap; 546 u32 feat_en; 547}; 548 549 550/* Precision Time Sync (IEEE 1588) defines */ 551#define ETHERTYPE_IEEE1588 0x88F7 552#define PICOSECS_PER_TICK 20833 553#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 554#define IXGBE_ADVTXD_TSTAMP 0x00080000 555 556 557#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 558 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 559#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 560#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 561#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 562#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 563#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 564#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 565#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 566#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 567#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 568#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 569#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 570#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 571 572/* For backward compatibility */ 573#if !defined(PCIER_LINK_STA) 574#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 575#endif 576 577/* Stats macros */ 578#if __FreeBSD_version >= 1100036 579#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 580#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 581#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 582#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 583#define IXGBE_SET_COLLISIONS(sc, count) 584#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 585#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 586#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 587#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 588#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 589#else 590#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 591#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 592#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 593#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 594#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 595#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 596#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 597#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 598#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 599#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 600#endif 601 602/* External PHY register addresses */ 603#define IXGBE_PHY_CURRENT_TEMP 0xC820 604#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 605 606/* Sysctl help messages; displayed with sysctl -d */ 607#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 608 "\nControl advertised link speed using these flags:\n" \ 609 "\t0x1 - advertise 100M\n" \ 610 "\t0x2 - advertise 1G\n" \ 611 "\t0x4 - advertise 10G\n" \ 612 "\t0x8 - advertise 10M\n\n" \ 613 "\t100M and 10M are only supported on certain adapters.\n" 614 615#define IXGBE_SYSCTL_DESC_SET_FC \ 616 "\nSet flow control mode using these values:\n" \ 617 "\t0 - off\n" \ 618 "\t1 - rx pause\n" \ 619 "\t2 - tx pause\n" \ 620 "\t3 - tx and rx pause" 621 622/* Workaround to make 8.0 buildable */ 623#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 624static __inline int 625drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 626{ 627#ifdef ALTQ 628 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 629 return (1); 630#endif 631 return (!buf_ring_empty(br)); 632} 633#endif 634 635/* 636 * Find the number of unrefreshed RX descriptors 637 */ 638static inline u16 639ixgbe_rx_unrefreshed(struct rx_ring *rxr) 640{ 641 if (rxr->next_to_check > rxr->next_to_refresh) 642 return (rxr->next_to_check - rxr->next_to_refresh - 1); 643 else 644 return ((rxr->num_desc + rxr->next_to_check) - 645 rxr->next_to_refresh - 1); 646} 647 648static inline int 649ixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy) 650{ 651 UNREFERENCED_1PARAMETER(dummy); 652 653 return IFQ_DRV_IS_EMPTY(&ifp->if_snd); 654} 655 656/* 657 * This checks for a zero mac addr, something that will be likely 658 * unless the Admin on the Host has created one. 659 */ 660static inline bool 661ixv_check_ether_addr(u8 *addr) 662{ 663 bool status = TRUE; 664 665 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 666 addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 667 status = FALSE; 668 669 return (status); 670} 671 672/* Shared Prototypes */ 673void ixgbe_legacy_start(struct ifnet *); 674int ixgbe_legacy_start_locked(struct ifnet *, struct tx_ring *); 675int ixgbe_mq_start(struct ifnet *, struct mbuf *); 676int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 677void ixgbe_qflush(struct ifnet *); 678void ixgbe_deferred_mq_start(void *, int); 679void ixgbe_init_locked(struct adapter *); 680 681int ixgbe_allocate_queues(struct adapter *); 682int ixgbe_setup_transmit_structures(struct adapter *); 683void ixgbe_free_transmit_structures(struct adapter *); 684int ixgbe_setup_receive_structures(struct adapter *); 685void ixgbe_free_receive_structures(struct adapter *); 686void ixgbe_txeof(struct tx_ring *); 687bool ixgbe_rxeof(struct ix_queue *); 688 689#include "ixgbe_sriov.h" 690#include "ixgbe_bypass.h" 691#include "ixgbe_fdir.h" 692#include "ixgbe_rss.h" 693#include "ixgbe_netmap.h" 694 695#endif /* _IXGBE_H_ */ 696