ixgbe.h revision 295524
1/****************************************************************************** 2 3 Copyright (c) 2001-2015, Intel Corporation 4 All rights reserved. 5 6 Redistribution and use in source and binary forms, with or without 7 modification, are permitted provided that the following conditions are met: 8 9 1. Redistributions of source code must retain the above copyright notice, 10 this list of conditions and the following disclaimer. 11 12 2. Redistributions in binary form must reproduce the above copyright 13 notice, this list of conditions and the following disclaimer in the 14 documentation and/or other materials provided with the distribution. 15 16 3. Neither the name of the Intel Corporation nor the names of its 17 contributors may be used to endorse or promote products derived from 18 this software without specific prior written permission. 19 20 THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21 AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22 IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23 ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24 LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25 CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26 SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27 INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28 CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29 ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30 POSSIBILITY OF SUCH DAMAGE. 31 32******************************************************************************/ 33/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe.h 295524 2016-02-11 16:16:10Z sbruno $*/ 34 35 36#ifndef _IXGBE_H_ 37#define _IXGBE_H_ 38 39 40#include <sys/param.h> 41#include <sys/systm.h> 42#ifndef IXGBE_LEGACY_TX 43#include <sys/buf_ring.h> 44#endif 45#include <sys/mbuf.h> 46#include <sys/protosw.h> 47#include <sys/socket.h> 48#include <sys/malloc.h> 49#include <sys/kernel.h> 50#include <sys/module.h> 51#include <sys/sockio.h> 52#include <sys/eventhandler.h> 53 54#include <net/if.h> 55#include <net/if_var.h> 56#include <net/if_arp.h> 57#include <net/bpf.h> 58#include <net/ethernet.h> 59#include <net/if_dl.h> 60#include <net/if_media.h> 61 62#include <net/bpf.h> 63#include <net/if_types.h> 64#include <net/if_vlan_var.h> 65 66#include <netinet/in_systm.h> 67#include <netinet/in.h> 68#include <netinet/if_ether.h> 69#include <netinet/ip.h> 70#include <netinet/ip6.h> 71#include <netinet/tcp.h> 72#include <netinet/tcp_lro.h> 73#include <netinet/udp.h> 74 75#include <machine/in_cksum.h> 76 77#include <sys/bus.h> 78#include <machine/bus.h> 79#include <sys/rman.h> 80#include <machine/resource.h> 81#include <vm/vm.h> 82#include <vm/pmap.h> 83#include <machine/clock.h> 84#include <dev/pci/pcivar.h> 85#include <dev/pci/pcireg.h> 86#include <sys/proc.h> 87#include <sys/sysctl.h> 88#include <sys/endian.h> 89#include <sys/taskqueue.h> 90#include <sys/pcpu.h> 91#include <sys/smp.h> 92#include <machine/smp.h> 93#include <sys/sbuf.h> 94 95#ifdef PCI_IOV 96#include <sys/nv.h> 97#include <sys/iov_schema.h> 98#include <dev/pci/pci_iov.h> 99#endif 100 101#include "ixgbe_api.h" 102#include "ixgbe_common.h" 103#include "ixgbe_phy.h" 104#include "ixgbe_vf.h" 105 106#ifdef PCI_IOV 107#include "ixgbe_common.h" 108#include "ixgbe_mbx.h" 109#endif 110 111/* Tunables */ 112 113/* 114 * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 115 * number of transmit descriptors allocated by the driver. Increasing this 116 * value allows the driver to queue more transmits. Each descriptor is 16 117 * bytes. Performance tests have show the 2K value to be optimal for top 118 * performance. 119 */ 120#define DEFAULT_TXD 1024 121#define PERFORM_TXD 2048 122#define MAX_TXD 4096 123#define MIN_TXD 64 124 125/* 126 * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 127 * number of receive descriptors allocated for each RX queue. Increasing this 128 * value allows the driver to buffer more incoming packets. Each descriptor 129 * is 16 bytes. A receive buffer is also allocated for each descriptor. 130 * 131 * Note: with 8 rings and a dual port card, it is possible to bump up 132 * against the system mbuf pool limit, you can tune nmbclusters 133 * to adjust for this. 134 */ 135#define DEFAULT_RXD 1024 136#define PERFORM_RXD 2048 137#define MAX_RXD 4096 138#define MIN_RXD 64 139 140/* Alignment for rings */ 141#define DBA_ALIGN 128 142 143/* 144 * This is the max watchdog interval, ie. the time that can 145 * pass between any two TX clean operations, such only happening 146 * when the TX hardware is functioning. 147 */ 148#define IXGBE_WATCHDOG (10 * hz) 149 150/* 151 * This parameters control when the driver calls the routine to reclaim 152 * transmit descriptors. 153 */ 154#define IXGBE_TX_CLEANUP_THRESHOLD (adapter->num_tx_desc / 8) 155#define IXGBE_TX_OP_THRESHOLD (adapter->num_tx_desc / 32) 156 157/* These defines are used in MTU calculations */ 158#define IXGBE_MAX_FRAME_SIZE 9728 159#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 160#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 161 ETHER_VLAN_ENCAP_LEN) 162#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 163#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 164 165/* Flow control constants */ 166#define IXGBE_FC_PAUSE 0xFFFF 167#define IXGBE_FC_HI 0x20000 168#define IXGBE_FC_LO 0x10000 169 170/* 171 * Used for optimizing small rx mbufs. Effort is made to keep the copy 172 * small and aligned for the CPU L1 cache. 173 * 174 * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 175 * 32 byte alignment needed for the fast bcopy results in 8 bytes being 176 * wasted. Getting 64 byte alignment, which _should_ be ideal for 177 * modern Intel CPUs, results in 40 bytes wasted and a significant drop 178 * in observed efficiency of the optimization, 97.9% -> 81.8%. 179 */ 180#if __FreeBSD_version < 1002000 181#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 182#endif 183#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 184#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 185#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 186 187/* Keep older OS drivers building... */ 188#if !defined(SYSCTL_ADD_UQUAD) 189#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 190#endif 191 192/* Defines for printing debug information */ 193#define DEBUG_INIT 0 194#define DEBUG_IOCTL 0 195#define DEBUG_HW 0 196 197#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 198#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 199#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 200#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 201#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 202#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 203#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 204#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 205#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 206 207#define MAX_NUM_MULTICAST_ADDRESSES 128 208#define IXGBE_82598_SCATTER 100 209#define IXGBE_82599_SCATTER 32 210#define MSIX_82598_BAR 3 211#define MSIX_82599_BAR 4 212#define IXGBE_TSO_SIZE 262140 213#define IXGBE_RX_HDR 128 214#define IXGBE_VFTA_SIZE 128 215#define IXGBE_BR_SIZE 4096 216#define IXGBE_QUEUE_MIN_FREE 32 217#define IXGBE_MAX_TX_BUSY 10 218#define IXGBE_QUEUE_HUNG 0x80000000 219 220#define IXV_EITR_DEFAULT 128 221 222/* Supported offload bits in mbuf flag */ 223#if __FreeBSD_version >= 1000000 224#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 225 CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 226 CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 227#elif __FreeBSD_version >= 800000 228#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 229#else 230#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 231#endif 232 233/* Backward compatibility items for very old versions */ 234#ifndef pci_find_cap 235#define pci_find_cap pci_find_extcap 236#endif 237 238#ifndef DEVMETHOD_END 239#define DEVMETHOD_END { NULL, NULL } 240#endif 241 242/* 243 * Interrupt Moderation parameters 244 */ 245#define IXGBE_LOW_LATENCY 128 246#define IXGBE_AVE_LATENCY 400 247#define IXGBE_BULK_LATENCY 1200 248 249/* Using 1FF (the max value), the interval is ~1.05ms */ 250#define IXGBE_LINK_ITR_QUANTA 0x1FF 251#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 252 IXGBE_EITR_ITR_INT_MASK) 253 254/* MAC type macros */ 255#define IXGBE_IS_X550VF(_adapter) \ 256 ((_adapter->hw.mac.type == ixgbe_mac_X550_vf) || \ 257 (_adapter->hw.mac.type == ixgbe_mac_X550EM_x_vf)) 258 259#define IXGBE_IS_VF(_adapter) \ 260 (IXGBE_IS_X550VF(_adapter) || \ 261 (_adapter->hw.mac.type == ixgbe_mac_X540_vf) || \ 262 (_adapter->hw.mac.type == ixgbe_mac_82599_vf)) 263 264#ifdef PCI_IOV 265#define IXGBE_VF_INDEX(vmdq) ((vmdq) / 32) 266#define IXGBE_VF_BIT(vmdq) (1 << ((vmdq) % 32)) 267 268#define IXGBE_VT_MSG_MASK 0xFFFF 269 270#define IXGBE_VT_MSGINFO(msg) \ 271 (((msg) & IXGBE_VT_MSGINFO_MASK) >> IXGBE_VT_MSGINFO_SHIFT) 272 273#define IXGBE_VF_GET_QUEUES_RESP_LEN 5 274 275#define IXGBE_API_VER_1_0 0 276#define IXGBE_API_VER_2_0 1 /* Solaris API. Not supported. */ 277#define IXGBE_API_VER_1_1 2 278#define IXGBE_API_VER_UNKNOWN UINT16_MAX 279 280enum ixgbe_iov_mode { 281 IXGBE_64_VM, 282 IXGBE_32_VM, 283 IXGBE_NO_VM 284}; 285#endif /* PCI_IOV */ 286 287 288/* 289 ***************************************************************************** 290 * vendor_info_array 291 * 292 * This array contains the list of Subvendor/Subdevice IDs on which the driver 293 * should load. 294 * 295 ***************************************************************************** 296 */ 297typedef struct _ixgbe_vendor_info_t { 298 unsigned int vendor_id; 299 unsigned int device_id; 300 unsigned int subvendor_id; 301 unsigned int subdevice_id; 302 unsigned int index; 303} ixgbe_vendor_info_t; 304 305 306struct ixgbe_tx_buf { 307 union ixgbe_adv_tx_desc *eop; 308 struct mbuf *m_head; 309 bus_dmamap_t map; 310}; 311 312struct ixgbe_rx_buf { 313 struct mbuf *buf; 314 struct mbuf *fmp; 315 bus_dmamap_t pmap; 316 u_int flags; 317#define IXGBE_RX_COPY 0x01 318 uint64_t addr; 319}; 320 321/* 322 * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free. 323 */ 324struct ixgbe_dma_alloc { 325 bus_addr_t dma_paddr; 326 caddr_t dma_vaddr; 327 bus_dma_tag_t dma_tag; 328 bus_dmamap_t dma_map; 329 bus_dma_segment_t dma_seg; 330 bus_size_t dma_size; 331 int dma_nseg; 332}; 333 334struct ixgbe_mc_addr { 335 u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 336 u32 vmdq; 337}; 338 339/* 340** Driver queue struct: this is the interrupt container 341** for the associated tx and rx ring. 342*/ 343struct ix_queue { 344 struct adapter *adapter; 345 u32 msix; /* This queue's MSIX vector */ 346 u32 eims; /* This queue's EIMS bit */ 347 u32 eitr_setting; 348 u32 me; 349 struct resource *res; 350 void *tag; 351 int busy; 352 struct tx_ring *txr; 353 struct rx_ring *rxr; 354 struct task que_task; 355 struct taskqueue *tq; 356 u64 irqs; 357}; 358 359/* 360 * The transmit ring, one per queue 361 */ 362struct tx_ring { 363 struct adapter *adapter; 364 struct mtx tx_mtx; 365 u32 me; 366 u32 tail; 367 int busy; 368 union ixgbe_adv_tx_desc *tx_base; 369 struct ixgbe_tx_buf *tx_buffers; 370 struct ixgbe_dma_alloc txdma; 371 volatile u16 tx_avail; 372 u16 next_avail_desc; 373 u16 next_to_clean; 374 u16 num_desc; 375 u32 txd_cmd; 376 bus_dma_tag_t txtag; 377 char mtx_name[16]; 378#ifndef IXGBE_LEGACY_TX 379 struct buf_ring *br; 380 struct task txq_task; 381#endif 382#ifdef IXGBE_FDIR 383 u16 atr_sample; 384 u16 atr_count; 385#endif 386 u32 bytes; /* used for AIM */ 387 u32 packets; 388 /* Soft Stats */ 389 unsigned long tso_tx; 390 unsigned long no_tx_map_avail; 391 unsigned long no_tx_dma_setup; 392 u64 no_desc_avail; 393 u64 total_packets; 394}; 395 396 397/* 398 * The Receive ring, one per rx queue 399 */ 400struct rx_ring { 401 struct adapter *adapter; 402 struct mtx rx_mtx; 403 u32 me; 404 u32 tail; 405 union ixgbe_adv_rx_desc *rx_base; 406 struct ixgbe_dma_alloc rxdma; 407 struct lro_ctrl lro; 408 bool lro_enabled; 409 bool hw_rsc; 410 bool vtag_strip; 411 u16 next_to_refresh; 412 u16 next_to_check; 413 u16 num_desc; 414 u16 mbuf_sz; 415 char mtx_name[16]; 416 struct ixgbe_rx_buf *rx_buffers; 417 bus_dma_tag_t ptag; 418 419 u32 bytes; /* Used for AIM calc */ 420 u32 packets; 421 422 /* Soft stats */ 423 u64 rx_irq; 424 u64 rx_copies; 425 u64 rx_packets; 426 u64 rx_bytes; 427 u64 rx_discarded; 428 u64 rsc_num; 429#ifdef IXGBE_FDIR 430 u64 flm; 431#endif 432}; 433 434#ifdef PCI_IOV 435#define IXGBE_VF_CTS (1 << 0) /* VF is clear to send. */ 436#define IXGBE_VF_CAP_MAC (1 << 1) /* VF is permitted to change MAC. */ 437#define IXGBE_VF_CAP_VLAN (1 << 2) /* VF is permitted to join vlans. */ 438#define IXGBE_VF_ACTIVE (1 << 3) /* VF is active. */ 439 440#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 441 442struct ixgbe_vf { 443 u_int pool; 444 u_int rar_index; 445 u_int max_frame_size; 446 uint32_t flags; 447 uint8_t ether_addr[ETHER_ADDR_LEN]; 448 uint16_t mc_hash[IXGBE_MAX_VF_MC]; 449 uint16_t num_mc_hashes; 450 uint16_t default_vlan; 451 uint16_t vlan_tag; 452 uint16_t api_ver; 453}; 454#endif /* PCI_IOV */ 455 456/* Our adapter structure */ 457struct adapter { 458 struct ixgbe_hw hw; 459 struct ixgbe_osdep osdep; 460 461 struct device *dev; 462 struct ifnet *ifp; 463 464 struct resource *pci_mem; 465 struct resource *msix_mem; 466 467 /* 468 * Interrupt resources: this set is 469 * either used for legacy, or for Link 470 * when doing MSIX 471 */ 472 void *tag; 473 struct resource *res; 474 475 struct ifmedia media; 476 struct callout timer; 477 int msix; 478 int if_flags; 479 480 struct mtx core_mtx; 481 482 eventhandler_tag vlan_attach; 483 eventhandler_tag vlan_detach; 484 485 u16 num_vlans; 486 u16 num_queues; 487 488 /* 489 ** Shadow VFTA table, this is needed because 490 ** the real vlan filter table gets cleared during 491 ** a soft reset and the driver needs to be able 492 ** to repopulate it. 493 */ 494 u32 shadow_vfta[IXGBE_VFTA_SIZE]; 495 496 /* Info about the interface */ 497 u32 optics; 498 u32 fc; /* local flow ctrl setting */ 499 int advertise; /* link speeds */ 500 bool link_active; 501 u16 max_frame_size; 502 u16 num_segs; 503 u32 link_speed; 504 bool link_up; 505 u32 vector; 506 u16 dmac; 507 bool eee_enabled; 508 u32 phy_layer; 509 510 /* Power management-related */ 511 bool wol_support; 512 u32 wufc; 513 514 /* Mbuf cluster size */ 515 u32 rx_mbuf_sz; 516 517 /* Support for pluggable optics */ 518 bool sfp_probe; 519 struct task link_task; /* Link tasklet */ 520 struct task mod_task; /* SFP tasklet */ 521 struct task msf_task; /* Multispeed Fiber */ 522#ifdef PCI_IOV 523 struct task mbx_task; /* VF -> PF mailbox interrupt */ 524#endif /* PCI_IOV */ 525#ifdef IXGBE_FDIR 526 int fdir_reinit; 527 struct task fdir_task; 528#endif 529 struct task phy_task; /* PHY intr tasklet */ 530 struct taskqueue *tq; 531 532 /* 533 ** Queues: 534 ** This is the irq holder, it has 535 ** and RX/TX pair or rings associated 536 ** with it. 537 */ 538 struct ix_queue *queues; 539 540 /* 541 * Transmit rings: 542 * Allocated at run time, an array of rings. 543 */ 544 struct tx_ring *tx_rings; 545 u32 num_tx_desc; 546 u32 tx_process_limit; 547 548 /* 549 * Receive rings: 550 * Allocated at run time, an array of rings. 551 */ 552 struct rx_ring *rx_rings; 553 u64 active_queues; 554 u32 num_rx_desc; 555 u32 rx_process_limit; 556 557 /* Multicast array memory */ 558 struct ixgbe_mc_addr *mta; 559 int num_vfs; 560 int pool; 561#ifdef PCI_IOV 562 struct ixgbe_vf *vfs; 563#endif 564#ifdef DEV_NETMAP 565 void (*init_locked)(struct adapter *); 566 void (*stop_locked)(void *); 567#endif 568 569 /* Misc stats maintained by the driver */ 570 unsigned long dropped_pkts; 571 unsigned long mbuf_defrag_failed; 572 unsigned long mbuf_header_failed; 573 unsigned long mbuf_packet_failed; 574 unsigned long watchdog_events; 575 unsigned long link_irq; 576 union { 577 struct ixgbe_hw_stats pf; 578 struct ixgbevf_hw_stats vf; 579 } stats; 580#if __FreeBSD_version >= 1100036 581 /* counter(9) stats */ 582 u64 ipackets; 583 u64 ierrors; 584 u64 opackets; 585 u64 oerrors; 586 u64 ibytes; 587 u64 obytes; 588 u64 imcasts; 589 u64 omcasts; 590 u64 iqdrops; 591 u64 noproto; 592#endif 593}; 594 595 596/* Precision Time Sync (IEEE 1588) defines */ 597#define ETHERTYPE_IEEE1588 0x88F7 598#define PICOSECS_PER_TICK 20833 599#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 600#define IXGBE_ADVTXD_TSTAMP 0x00080000 601 602 603#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 604 mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 605#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 606#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 607#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 608#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 609#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 610#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 611#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 612#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 613#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 614#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 615#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 616#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 617 618/* For backward compatibility */ 619#if !defined(PCIER_LINK_STA) 620#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 621#endif 622 623/* Stats macros */ 624#if __FreeBSD_version >= 1100036 625#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 626#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 627#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 628#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 629#define IXGBE_SET_COLLISIONS(sc, count) 630#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 631#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 632#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 633#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 634#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 635#else 636#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 637#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 638#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 639#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 640#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 641#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 642#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 643#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 644#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 645#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 646#endif 647 648/* External PHY register addresses */ 649#define IXGBE_PHY_CURRENT_TEMP 0xC820 650#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 651 652/* Sysctl help messages; displayed with sysctl -d */ 653#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 654 "\nControl advertised link speed using these flags:\n" \ 655 "\t0x1 - advertise 100M\n" \ 656 "\t0x2 - advertise 1G\n" \ 657 "\t0x4 - advertise 10G\n\n" \ 658 "\t100M is only supported on certain 10GBaseT adapters.\n" 659 660#define IXGBE_SYSCTL_DESC_SET_FC \ 661 "\nSet flow control mode using these values:\n" \ 662 "\t0 - off\n" \ 663 "\t1 - rx pause\n" \ 664 "\t2 - tx pause\n" \ 665 "\t3 - tx and rx pause" 666 667static inline bool 668ixgbe_is_sfp(struct ixgbe_hw *hw) 669{ 670 switch (hw->phy.type) { 671 case ixgbe_phy_sfp_avago: 672 case ixgbe_phy_sfp_ftl: 673 case ixgbe_phy_sfp_intel: 674 case ixgbe_phy_sfp_unknown: 675 case ixgbe_phy_sfp_passive_tyco: 676 case ixgbe_phy_sfp_passive_unknown: 677 case ixgbe_phy_qsfp_passive_unknown: 678 case ixgbe_phy_qsfp_active_unknown: 679 case ixgbe_phy_qsfp_intel: 680 case ixgbe_phy_qsfp_unknown: 681 return TRUE; 682 default: 683 return FALSE; 684 } 685} 686 687/* Workaround to make 8.0 buildable */ 688#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 689static __inline int 690drbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 691{ 692#ifdef ALTQ 693 if (ALTQ_IS_ENABLED(&ifp->if_snd)) 694 return (1); 695#endif 696 return (!buf_ring_empty(br)); 697} 698#endif 699 700/* 701** Find the number of unrefreshed RX descriptors 702*/ 703static inline u16 704ixgbe_rx_unrefreshed(struct rx_ring *rxr) 705{ 706 if (rxr->next_to_check > rxr->next_to_refresh) 707 return (rxr->next_to_check - rxr->next_to_refresh - 1); 708 else 709 return ((rxr->num_desc + rxr->next_to_check) - 710 rxr->next_to_refresh - 1); 711} 712 713/* 714** This checks for a zero mac addr, something that will be likely 715** unless the Admin on the Host has created one. 716*/ 717static inline bool 718ixv_check_ether_addr(u8 *addr) 719{ 720 bool status = TRUE; 721 722 if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 723 addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 724 status = FALSE; 725 return (status); 726} 727 728/* Shared Prototypes */ 729 730#ifdef IXGBE_LEGACY_TX 731void ixgbe_start(struct ifnet *); 732void ixgbe_start_locked(struct tx_ring *, struct ifnet *); 733#else /* ! IXGBE_LEGACY_TX */ 734int ixgbe_mq_start(struct ifnet *, struct mbuf *); 735int ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 736void ixgbe_qflush(struct ifnet *); 737void ixgbe_deferred_mq_start(void *, int); 738#endif /* IXGBE_LEGACY_TX */ 739 740int ixgbe_allocate_queues(struct adapter *); 741int ixgbe_allocate_transmit_buffers(struct tx_ring *); 742int ixgbe_setup_transmit_structures(struct adapter *); 743void ixgbe_free_transmit_structures(struct adapter *); 744int ixgbe_allocate_receive_buffers(struct rx_ring *); 745int ixgbe_setup_receive_structures(struct adapter *); 746void ixgbe_free_receive_structures(struct adapter *); 747void ixgbe_txeof(struct tx_ring *); 748bool ixgbe_rxeof(struct ix_queue *); 749 750int ixgbe_dma_malloc(struct adapter *, 751 bus_size_t, struct ixgbe_dma_alloc *, int); 752void ixgbe_dma_free(struct adapter *, struct ixgbe_dma_alloc *); 753 754#ifdef PCI_IOV 755 756static inline boolean_t 757ixgbe_vf_mac_changed(struct ixgbe_vf *vf, const uint8_t *mac) 758{ 759 return (bcmp(mac, vf->ether_addr, ETHER_ADDR_LEN) != 0); 760} 761 762static inline void 763ixgbe_send_vf_msg(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 764{ 765 766 if (vf->flags & IXGBE_VF_CTS) 767 msg |= IXGBE_VT_MSGTYPE_CTS; 768 769 ixgbe_write_mbx(&adapter->hw, &msg, 1, vf->pool); 770} 771 772static inline void 773ixgbe_send_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 774{ 775 msg &= IXGBE_VT_MSG_MASK; 776 ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_ACK); 777} 778 779static inline void 780ixgbe_send_vf_nack(struct adapter *adapter, struct ixgbe_vf *vf, u32 msg) 781{ 782 msg &= IXGBE_VT_MSG_MASK; 783 ixgbe_send_vf_msg(adapter, vf, msg | IXGBE_VT_MSGTYPE_NACK); 784} 785 786static inline void 787ixgbe_process_vf_ack(struct adapter *adapter, struct ixgbe_vf *vf) 788{ 789 if (!(vf->flags & IXGBE_VF_CTS)) 790 ixgbe_send_vf_nack(adapter, vf, 0); 791} 792 793static inline enum ixgbe_iov_mode 794ixgbe_get_iov_mode(struct adapter *adapter) 795{ 796 if (adapter->num_vfs == 0) 797 return (IXGBE_NO_VM); 798 if (adapter->num_queues <= 2) 799 return (IXGBE_64_VM); 800 else if (adapter->num_queues <= 4) 801 return (IXGBE_32_VM); 802 else 803 return (IXGBE_NO_VM); 804} 805 806static inline u16 807ixgbe_max_vfs(enum ixgbe_iov_mode mode) 808{ 809 /* 810 * We return odd numbers below because we 811 * reserve 1 VM's worth of queues for the PF. 812 */ 813 switch (mode) { 814 case IXGBE_64_VM: 815 return (63); 816 case IXGBE_32_VM: 817 return (31); 818 case IXGBE_NO_VM: 819 default: 820 return (0); 821 } 822} 823 824static inline int 825ixgbe_vf_queues(enum ixgbe_iov_mode mode) 826{ 827 switch (mode) { 828 case IXGBE_64_VM: 829 return (2); 830 case IXGBE_32_VM: 831 return (4); 832 case IXGBE_NO_VM: 833 default: 834 return (0); 835 } 836} 837 838static inline int 839ixgbe_vf_que_index(enum ixgbe_iov_mode mode, u32 vfnum, int num) 840{ 841 return ((vfnum * ixgbe_vf_queues(mode)) + num); 842} 843 844static inline int 845ixgbe_pf_que_index(enum ixgbe_iov_mode mode, int num) 846{ 847 return (ixgbe_vf_que_index(mode, ixgbe_max_vfs(mode), num)); 848} 849 850static inline void 851ixgbe_update_max_frame(struct adapter * adapter, int max_frame) 852{ 853 if (adapter->max_frame_size < max_frame) 854 adapter->max_frame_size = max_frame; 855} 856 857static inline u32 858ixgbe_get_mrqc(enum ixgbe_iov_mode mode) 859{ 860 u32 mrqc = 0; 861 switch (mode) { 862 case IXGBE_64_VM: 863 mrqc = IXGBE_MRQC_VMDQRSS64EN; 864 break; 865 case IXGBE_32_VM: 866 mrqc = IXGBE_MRQC_VMDQRSS32EN; 867 break; 868 case IXGBE_NO_VM: 869 mrqc = 0; 870 break; 871 default: 872 panic("Unexpected SR-IOV mode %d", mode); 873 } 874 return(mrqc); 875} 876 877 878static inline u32 879ixgbe_get_mtqc(enum ixgbe_iov_mode mode) 880{ 881 uint32_t mtqc = 0; 882 switch (mode) { 883 case IXGBE_64_VM: 884 mtqc |= IXGBE_MTQC_64VF | IXGBE_MTQC_VT_ENA; 885 break; 886 case IXGBE_32_VM: 887 mtqc |= IXGBE_MTQC_32VF | IXGBE_MTQC_VT_ENA; 888 break; 889 case IXGBE_NO_VM: 890 mtqc = IXGBE_MTQC_64Q_1PB; 891 break; 892 default: 893 panic("Unexpected SR-IOV mode %d", mode); 894 } 895 return(mtqc); 896} 897#endif /* PCI_IOV */ 898 899#endif /* _IXGBE_H_ */ 900