1179055Sjfv/****************************************************************************** 2171384Sjfv 3315333Serj Copyright (c) 2001-2017, Intel Corporation 4179055Sjfv All rights reserved. 5315333Serj 6315333Serj Redistribution and use in source and binary forms, with or without 7179055Sjfv modification, are permitted provided that the following conditions are met: 8315333Serj 9315333Serj 1. Redistributions of source code must retain the above copyright notice, 10179055Sjfv this list of conditions and the following disclaimer. 11315333Serj 12315333Serj 2. Redistributions in binary form must reproduce the above copyright 13315333Serj notice, this list of conditions and the following disclaimer in the 14179055Sjfv documentation and/or other materials provided with the distribution. 15315333Serj 16315333Serj 3. Neither the name of the Intel Corporation nor the names of its 17315333Serj contributors may be used to endorse or promote products derived from 18179055Sjfv this software without specific prior written permission. 19315333Serj 20179055Sjfv THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21315333Serj AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22315333Serj IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23315333Serj ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24315333Serj LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25315333Serj CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26315333Serj SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27315333Serj INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28315333Serj CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29179055Sjfv ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30179055Sjfv POSSIBILITY OF SUCH DAMAGE. 31171384Sjfv 32179055Sjfv******************************************************************************/ 33179055Sjfv/*$FreeBSD: stable/10/sys/dev/ixgbe/ixgbe.h 315434 2017-03-16 23:18:57Z erj $*/ 34171384Sjfv 35185352Sjfv 36171384Sjfv#ifndef _IXGBE_H_ 37171384Sjfv#define _IXGBE_H_ 38171384Sjfv 39171384Sjfv 40171384Sjfv#include <sys/param.h> 41171384Sjfv#include <sys/systm.h> 42194875Sjfv#include <sys/buf_ring.h> 43171384Sjfv#include <sys/mbuf.h> 44171384Sjfv#include <sys/protosw.h> 45171384Sjfv#include <sys/socket.h> 46171384Sjfv#include <sys/malloc.h> 47171384Sjfv#include <sys/kernel.h> 48171384Sjfv#include <sys/module.h> 49171384Sjfv#include <sys/sockio.h> 50295008Ssbruno#include <sys/eventhandler.h> 51171384Sjfv 52171384Sjfv#include <net/if.h> 53295008Ssbruno#include <net/if_var.h> 54171384Sjfv#include <net/if_arp.h> 55171384Sjfv#include <net/bpf.h> 56171384Sjfv#include <net/ethernet.h> 57171384Sjfv#include <net/if_dl.h> 58171384Sjfv#include <net/if_media.h> 59171384Sjfv 60171384Sjfv#include <net/bpf.h> 61171384Sjfv#include <net/if_types.h> 62171384Sjfv#include <net/if_vlan_var.h> 63171384Sjfv 64171384Sjfv#include <netinet/in_systm.h> 65171384Sjfv#include <netinet/in.h> 66171384Sjfv#include <netinet/if_ether.h> 67171384Sjfv#include <netinet/ip.h> 68171384Sjfv#include <netinet/ip6.h> 69171384Sjfv#include <netinet/tcp.h> 70190873Sjfv#include <netinet/tcp_lro.h> 71171384Sjfv#include <netinet/udp.h> 72171384Sjfv 73171384Sjfv#include <machine/in_cksum.h> 74171384Sjfv 75171384Sjfv#include <sys/bus.h> 76171384Sjfv#include <machine/bus.h> 77171384Sjfv#include <sys/rman.h> 78171384Sjfv#include <machine/resource.h> 79171384Sjfv#include <vm/vm.h> 80171384Sjfv#include <vm/pmap.h> 81171384Sjfv#include <machine/clock.h> 82171384Sjfv#include <dev/pci/pcivar.h> 83171384Sjfv#include <dev/pci/pcireg.h> 84171384Sjfv#include <sys/proc.h> 85171384Sjfv#include <sys/sysctl.h> 86171384Sjfv#include <sys/endian.h> 87171384Sjfv#include <sys/taskqueue.h> 88179055Sjfv#include <sys/pcpu.h> 89194875Sjfv#include <sys/smp.h> 90194875Sjfv#include <machine/smp.h> 91283620Serj#include <sys/sbuf.h> 92171384Sjfv 93315333Serj#include "ixgbe_features.h" 94171384Sjfv#include "ixgbe_api.h" 95283620Serj#include "ixgbe_common.h" 96283620Serj#include "ixgbe_phy.h" 97171384Sjfv 98171384Sjfv/* Tunables */ 99171384Sjfv 100171384Sjfv/* 101172043Sjfv * TxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 102171384Sjfv * number of transmit descriptors allocated by the driver. Increasing this 103171384Sjfv * value allows the driver to queue more transmits. Each descriptor is 16 104172043Sjfv * bytes. Performance tests have show the 2K value to be optimal for top 105172043Sjfv * performance. 106171384Sjfv */ 107315333Serj#define DEFAULT_TXD 1024 108315333Serj#define PERFORM_TXD 2048 109315333Serj#define MAX_TXD 4096 110315333Serj#define MIN_TXD 64 111171384Sjfv 112171384Sjfv/* 113172043Sjfv * RxDescriptors Valid Range: 64-4096 Default Value: 256 This value is the 114172043Sjfv * number of receive descriptors allocated for each RX queue. Increasing this 115171384Sjfv * value allows the driver to buffer more incoming packets. Each descriptor 116315333Serj * is 16 bytes. A receive buffer is also allocated for each descriptor. 117315333Serj * 118315333Serj * Note: with 8 rings and a dual port card, it is possible to bump up 119315333Serj * against the system mbuf pool limit, you can tune nmbclusters 120315333Serj * to adjust for this. 121171384Sjfv */ 122315333Serj#define DEFAULT_RXD 1024 123315333Serj#define PERFORM_RXD 2048 124315333Serj#define MAX_RXD 4096 125315333Serj#define MIN_RXD 64 126171384Sjfv 127172043Sjfv/* Alignment for rings */ 128315333Serj#define DBA_ALIGN 128 129172043Sjfv 130171384Sjfv/* 131200239Sjfv * This is the max watchdog interval, ie. the time that can 132200239Sjfv * pass between any two TX clean operations, such only happening 133200239Sjfv * when the TX hardware is functioning. 134171384Sjfv */ 135315333Serj#define IXGBE_WATCHDOG (10 * hz) 136171384Sjfv 137171384Sjfv/* 138171384Sjfv * This parameters control when the driver calls the routine to reclaim 139171384Sjfv * transmit descriptors. 140171384Sjfv */ 141315333Serj#define IXGBE_TX_CLEANUP_THRESHOLD(_a) ((_a)->num_tx_desc / 8) 142315333Serj#define IXGBE_TX_OP_THRESHOLD(_a) ((_a)->num_tx_desc / 32) 143171384Sjfv 144283620Serj/* These defines are used in MTU calculations */ 145315333Serj#define IXGBE_MAX_FRAME_SIZE 9728 146315333Serj#define IXGBE_MTU_HDR (ETHER_HDR_LEN + ETHER_CRC_LEN) 147315333Serj#define IXGBE_MTU_HDR_VLAN (ETHER_HDR_LEN + ETHER_CRC_LEN + \ 148315333Serj ETHER_VLAN_ENCAP_LEN) 149315333Serj#define IXGBE_MAX_MTU (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR) 150315333Serj#define IXGBE_MAX_MTU_VLAN (IXGBE_MAX_FRAME_SIZE - IXGBE_MTU_HDR_VLAN) 151171384Sjfv 152172043Sjfv/* Flow control constants */ 153315333Serj#define IXGBE_FC_PAUSE 0xFFFF 154315333Serj#define IXGBE_FC_HI 0x20000 155315333Serj#define IXGBE_FC_LO 0x10000 156171384Sjfv 157239940Sscottl/* 158239940Sscottl * Used for optimizing small rx mbufs. Effort is made to keep the copy 159239940Sscottl * small and aligned for the CPU L1 cache. 160315333Serj * 161239940Sscottl * MHLEN is typically 168 bytes, giving us 8-byte alignment. Getting 162239940Sscottl * 32 byte alignment needed for the fast bcopy results in 8 bytes being 163239940Sscottl * wasted. Getting 64 byte alignment, which _should_ be ideal for 164239940Sscottl * modern Intel CPUs, results in 40 bytes wasted and a significant drop 165239940Sscottl * in observed efficiency of the optimization, 97.9% -> 81.8%. 166239940Sscottl */ 167295524Ssbruno#if __FreeBSD_version < 1002000 168315333Serj#define MPKTHSIZE (sizeof(struct m_hdr) + sizeof(struct pkthdr)) 169295524Ssbruno#endif 170315333Serj#define IXGBE_RX_COPY_HDR_PADDED ((((MPKTHSIZE - 1) / 32) + 1) * 32) 171315333Serj#define IXGBE_RX_COPY_LEN (MSIZE - IXGBE_RX_COPY_HDR_PADDED) 172315333Serj#define IXGBE_RX_COPY_ALIGN (IXGBE_RX_COPY_HDR_PADDED - MPKTHSIZE) 173239940Sscottl 174221189Sjfv/* Keep older OS drivers building... */ 175221189Sjfv#if !defined(SYSCTL_ADD_UQUAD) 176221189Sjfv#define SYSCTL_ADD_UQUAD SYSCTL_ADD_QUAD 177221189Sjfv#endif 178221189Sjfv 179171384Sjfv/* Defines for printing debug information */ 180171384Sjfv#define DEBUG_INIT 0 181171384Sjfv#define DEBUG_IOCTL 0 182171384Sjfv#define DEBUG_HW 0 183171384Sjfv 184171384Sjfv#define INIT_DEBUGOUT(S) if (DEBUG_INIT) printf(S "\n") 185171384Sjfv#define INIT_DEBUGOUT1(S, A) if (DEBUG_INIT) printf(S "\n", A) 186171384Sjfv#define INIT_DEBUGOUT2(S, A, B) if (DEBUG_INIT) printf(S "\n", A, B) 187171384Sjfv#define IOCTL_DEBUGOUT(S) if (DEBUG_IOCTL) printf(S "\n") 188171384Sjfv#define IOCTL_DEBUGOUT1(S, A) if (DEBUG_IOCTL) printf(S "\n", A) 189171384Sjfv#define IOCTL_DEBUGOUT2(S, A, B) if (DEBUG_IOCTL) printf(S "\n", A, B) 190171384Sjfv#define HW_DEBUGOUT(S) if (DEBUG_HW) printf(S "\n") 191171384Sjfv#define HW_DEBUGOUT1(S, A) if (DEBUG_HW) printf(S "\n", A) 192171384Sjfv#define HW_DEBUGOUT2(S, A, B) if (DEBUG_HW) printf(S "\n", A, B) 193171384Sjfv 194171384Sjfv#define MAX_NUM_MULTICAST_ADDRESSES 128 195315333Serj#define IXGBE_82598_SCATTER 100 196315333Serj#define IXGBE_82599_SCATTER 32 197315333Serj#define MSIX_82598_BAR 3 198315333Serj#define MSIX_82599_BAR 4 199315333Serj#define IXGBE_TSO_SIZE 262140 200315333Serj#define IXGBE_RX_HDR 128 201315333Serj#define IXGBE_VFTA_SIZE 128 202315333Serj#define IXGBE_BR_SIZE 4096 203315333Serj#define IXGBE_QUEUE_MIN_FREE 32 204315333Serj#define IXGBE_MAX_TX_BUSY 10 205315333Serj#define IXGBE_QUEUE_HUNG 0x80000000 206171384Sjfv 207315333Serj#define IXGBE_EITR_DEFAULT 128 208243718Sjfv 209295524Ssbruno/* Supported offload bits in mbuf flag */ 210295524Ssbruno#if __FreeBSD_version >= 1000000 211315333Serj#define CSUM_OFFLOAD (CSUM_IP_TSO|CSUM_IP6_TSO|CSUM_IP| \ 212315333Serj CSUM_IP_UDP|CSUM_IP_TCP|CSUM_IP_SCTP| \ 213315333Serj CSUM_IP6_UDP|CSUM_IP6_TCP|CSUM_IP6_SCTP) 214295524Ssbruno#elif __FreeBSD_version >= 800000 215315333Serj#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP|CSUM_SCTP) 216205904Sjfv#else 217315333Serj#define CSUM_OFFLOAD (CSUM_IP|CSUM_TCP|CSUM_UDP) 218205904Sjfv#endif 219205904Sjfv 220283620Serj/* Backward compatibility items for very old versions */ 221283620Serj#ifndef pci_find_cap 222283620Serj#define pci_find_cap pci_find_extcap 223283620Serj#endif 224283620Serj 225283620Serj#ifndef DEVMETHOD_END 226283620Serj#define DEVMETHOD_END { NULL, NULL } 227283620Serj#endif 228283620Serj 229171384Sjfv/* 230315333Serj * Interrupt Moderation parameters 231171384Sjfv */ 232315333Serj#define IXGBE_LOW_LATENCY 128 233315333Serj#define IXGBE_AVE_LATENCY 400 234315333Serj#define IXGBE_BULK_LATENCY 1200 235171384Sjfv 236295524Ssbruno/* Using 1FF (the max value), the interval is ~1.05ms */ 237315333Serj#define IXGBE_LINK_ITR_QUANTA 0x1FF 238315333Serj#define IXGBE_LINK_ITR ((IXGBE_LINK_ITR_QUANTA << 3) & \ 239315333Serj IXGBE_EITR_ITR_INT_MASK) 240295524Ssbruno 241315333Serj#define IXGBE_IS_VF(_x) 0 242315333Serj#define IXGBE_IS_X550VF(_x) 0 243251964Sjfv 244315333Serj/* Netmap helper macro */ 245315333Serj#define IXGBE_VFTDH IXGBE_TDH 246283620Serj 247315333Serj/************************************************************************ 248171384Sjfv * vendor_info_array 249315333Serj * 250315333Serj * This array contains the list of Subvendor/Subdevice IDs on 251315333Serj * which the driver should load. 252315333Serj ************************************************************************/ 253171384Sjfvtypedef struct _ixgbe_vendor_info_t { 254315333Serj unsigned int vendor_id; 255315333Serj unsigned int device_id; 256315333Serj unsigned int subvendor_id; 257315333Serj unsigned int subdevice_id; 258315333Serj unsigned int index; 259185352Sjfv} ixgbe_vendor_info_t; 260171384Sjfv 261315333Serjstruct ixgbe_bp_data { 262315333Serj u32 low; 263315333Serj u32 high; 264315333Serj u32 log; 265315333Serj}; 266295008Ssbruno 267171384Sjfvstruct ixgbe_tx_buf { 268315333Serj union ixgbe_adv_tx_desc *eop; 269315333Serj struct mbuf *m_head; 270315333Serj bus_dmamap_t map; 271171384Sjfv}; 272171384Sjfv 273171384Sjfvstruct ixgbe_rx_buf { 274315333Serj struct mbuf *buf; 275315333Serj struct mbuf *fmp; 276315333Serj bus_dmamap_t pmap; 277315333Serj u_int flags; 278315333Serj#define IXGBE_RX_COPY 0x01 279315333Serj uint64_t addr; 280171384Sjfv}; 281171384Sjfv 282171384Sjfv/* 283315333Serj * Bus dma allocation structure used by ixgbe_dma_malloc and ixgbe_dma_free 284171384Sjfv */ 285171384Sjfvstruct ixgbe_dma_alloc { 286315333Serj bus_addr_t dma_paddr; 287315333Serj caddr_t dma_vaddr; 288315333Serj bus_dma_tag_t dma_tag; 289315333Serj bus_dmamap_t dma_map; 290315333Serj bus_dma_segment_t dma_seg; 291315333Serj bus_size_t dma_size; 292315333Serj int dma_nseg; 293171384Sjfv}; 294171384Sjfv 295295008Ssbrunostruct ixgbe_mc_addr { 296315333Serj u8 addr[IXGBE_ETH_LENGTH_OF_ADDRESS]; 297295008Ssbruno u32 vmdq; 298295008Ssbruno}; 299295008Ssbruno 300171384Sjfv/* 301315333Serj * Driver queue struct: this is the interrupt container 302315333Serj * for the associated tx and rx ring. 303315333Serj */ 304205720Sjfvstruct ix_queue { 305315333Serj struct adapter *adapter; 306315333Serj u32 msix; /* This queue's MSI-X vector */ 307315333Serj u32 eims; /* This queue's EIMS bit */ 308315333Serj u32 eitr_setting; 309315333Serj u32 me; 310315333Serj struct resource *res; 311315333Serj void *tag; 312315333Serj int busy; 313315333Serj struct tx_ring *txr; 314315333Serj struct rx_ring *rxr; 315315333Serj struct task que_task; 316315333Serj struct taskqueue *tq; 317315333Serj u64 irqs; 318205720Sjfv}; 319205720Sjfv 320205720Sjfv/* 321205720Sjfv * The transmit ring, one per queue 322171384Sjfv */ 323171384Sjfvstruct tx_ring { 324315333Serj struct adapter *adapter; 325315333Serj struct mtx tx_mtx; 326315333Serj u32 me; 327315333Serj u32 tail; 328315333Serj int busy; 329315333Serj union ixgbe_adv_tx_desc *tx_base; 330315333Serj struct ixgbe_tx_buf *tx_buffers; 331315333Serj struct ixgbe_dma_alloc txdma; 332315333Serj volatile u16 tx_avail; 333315333Serj u16 next_avail_desc; 334315333Serj u16 next_to_clean; 335315333Serj u16 num_desc; 336315333Serj u32 txd_cmd; 337315333Serj bus_dma_tag_t txtag; 338315333Serj char mtx_name[16]; 339315333Serj struct buf_ring *br; 340315333Serj struct task txq_task; 341315333Serj 342315333Serj /* Flow Director */ 343315333Serj u16 atr_sample; 344315333Serj u16 atr_count; 345315333Serj 346315333Serj u32 bytes; /* used for AIM */ 347315333Serj u32 packets; 348179055Sjfv /* Soft Stats */ 349315434Serj u64 tso_tx; 350315434Serj u64 no_tx_map_avail; 351315434Serj u64 no_tx_dma_setup; 352315333Serj u64 no_desc_avail; 353315333Serj u64 total_packets; 354171384Sjfv}; 355171384Sjfv 356171384Sjfv 357171384Sjfv/* 358171384Sjfv * The Receive ring, one per rx queue 359171384Sjfv */ 360171384Sjfvstruct rx_ring { 361315333Serj struct adapter *adapter; 362315333Serj struct mtx rx_mtx; 363315333Serj u32 me; 364315333Serj u32 tail; 365315333Serj union ixgbe_adv_rx_desc *rx_base; 366315333Serj struct ixgbe_dma_alloc rxdma; 367315333Serj struct lro_ctrl lro; 368315333Serj bool lro_enabled; 369315333Serj bool hw_rsc; 370315333Serj bool vtag_strip; 371315333Serj u16 next_to_refresh; 372315333Serj u16 next_to_check; 373315333Serj u16 num_desc; 374315333Serj u16 mbuf_sz; 375315333Serj char mtx_name[16]; 376315333Serj struct ixgbe_rx_buf *rx_buffers; 377315333Serj bus_dma_tag_t ptag; 378185352Sjfv 379315333Serj u32 bytes; /* Used for AIM calc */ 380315333Serj u32 packets; 381185352Sjfv 382171384Sjfv /* Soft stats */ 383315333Serj u64 rx_irq; 384315333Serj u64 rx_copies; 385315333Serj u64 rx_packets; 386315333Serj u64 rx_bytes; 387315333Serj u64 rx_discarded; 388315333Serj u64 rsc_num; 389315333Serj 390315333Serj /* Flow Director */ 391315333Serj u64 flm; 392171384Sjfv}; 393171384Sjfv 394295008Ssbruno#define IXGBE_MAX_VF_MC 30 /* Max number of multicast entries */ 395295008Ssbruno 396295008Ssbrunostruct ixgbe_vf { 397315333Serj u_int pool; 398315333Serj u_int rar_index; 399315333Serj u_int max_frame_size; 400315333Serj uint32_t flags; 401315333Serj uint8_t ether_addr[ETHER_ADDR_LEN]; 402315333Serj uint16_t mc_hash[IXGBE_MAX_VF_MC]; 403315333Serj uint16_t num_mc_hashes; 404315333Serj uint16_t default_vlan; 405315333Serj uint16_t vlan_tag; 406315333Serj uint16_t api_ver; 407295008Ssbruno}; 408295008Ssbruno 409171384Sjfv/* Our adapter structure */ 410171384Sjfvstruct adapter { 411315333Serj struct ixgbe_hw hw; 412315333Serj struct ixgbe_osdep osdep; 413171384Sjfv 414315333Serj struct device *dev; 415315333Serj struct ifnet *ifp; 416171384Sjfv 417315333Serj struct resource *pci_mem; 418315333Serj struct resource *msix_mem; 419179055Sjfv 420171384Sjfv /* 421194875Sjfv * Interrupt resources: this set is 422194875Sjfv * either used for legacy, or for Link 423315333Serj * when doing MSI-X 424171384Sjfv */ 425315333Serj void *tag; 426315333Serj struct resource *res; 427171384Sjfv 428315333Serj struct ifmedia media; 429315333Serj struct callout timer; 430315333Serj int link_rid; 431315333Serj int if_flags; 432179055Sjfv 433315333Serj struct mtx core_mtx; 434179055Sjfv 435315333Serj eventhandler_tag vlan_attach; 436315333Serj eventhandler_tag vlan_detach; 437194875Sjfv 438315333Serj u16 num_vlans; 439315333Serj u16 num_queues; 440194875Sjfv 441215911Sjfv /* 442315333Serj * Shadow VFTA table, this is needed because 443315333Serj * the real vlan filter table gets cleared during 444315333Serj * a soft reset and the driver needs to be able 445315333Serj * to repopulate it. 446315333Serj */ 447315333Serj u32 shadow_vfta[IXGBE_VFTA_SIZE]; 448215911Sjfv 449215911Sjfv /* Info about the interface */ 450315333Serj int advertise; /* link speeds */ 451315333Serj bool enable_aim; /* adaptive interrupt moderation */ 452315333Serj bool link_active; 453315333Serj u16 max_frame_size; 454315333Serj u16 num_segs; 455315333Serj u32 link_speed; 456315333Serj bool link_up; 457315333Serj u32 vector; 458315333Serj u16 dmac; 459315333Serj u32 phy_layer; 460171384Sjfv 461283620Serj /* Power management-related */ 462315333Serj bool wol_support; 463315333Serj u32 wufc; 464283620Serj 465185352Sjfv /* Mbuf cluster size */ 466315333Serj u32 rx_mbuf_sz; 467171384Sjfv 468190873Sjfv /* Support for pluggable optics */ 469315333Serj bool sfp_probe; 470315333Serj struct task link_task; /* Link tasklet */ 471315333Serj struct task mod_task; /* SFP tasklet */ 472315333Serj struct task msf_task; /* Multispeed Fiber */ 473315333Serj struct task mbx_task; /* VF -> PF mailbox interrupt */ 474185352Sjfv 475315333Serj /* Flow Director */ 476315333Serj int fdir_reinit; 477315333Serj struct task fdir_task; 478315333Serj 479315333Serj struct task phy_task; /* PHY intr tasklet */ 480315333Serj struct taskqueue *tq; 481315333Serj 482171384Sjfv /* 483315333Serj * Queues: 484315333Serj * This is the irq holder, it has 485315333Serj * and RX/TX pair or rings associated 486315333Serj * with it. 487315333Serj */ 488315333Serj struct ix_queue *queues; 489205720Sjfv 490205720Sjfv /* 491315333Serj * Transmit rings 492315333Serj * Allocated at run time, an array of rings 493171384Sjfv */ 494315333Serj struct tx_ring *tx_rings; 495315333Serj u32 num_tx_desc; 496315333Serj u32 tx_process_limit; 497171384Sjfv 498171384Sjfv /* 499315333Serj * Receive rings 500315333Serj * Allocated at run time, an array of rings 501171384Sjfv */ 502315333Serj struct rx_ring *rx_rings; 503315333Serj u64 active_queues; 504315333Serj u32 num_rx_desc; 505315333Serj u32 rx_process_limit; 506171384Sjfv 507215914Sjfv /* Multicast array memory */ 508315333Serj struct ixgbe_mc_addr *mta; 509215914Sjfv 510315333Serj /* SR-IOV */ 511315333Serj int iov_mode; 512315333Serj int num_vfs; 513315333Serj int pool; 514315333Serj struct ixgbe_vf *vfs; 515315333Serj 516315333Serj /* Bypass */ 517315333Serj struct ixgbe_bp_data bypass; 518315333Serj 519315333Serj /* Netmap */ 520315333Serj void (*init_locked)(struct adapter *); 521315333Serj void (*stop_locked)(void *); 522315333Serj 523171384Sjfv /* Misc stats maintained by the driver */ 524315333Serj unsigned long dropped_pkts; 525315333Serj unsigned long mbuf_defrag_failed; 526315333Serj unsigned long mbuf_header_failed; 527315333Serj unsigned long mbuf_packet_failed; 528315333Serj unsigned long watchdog_events; 529315333Serj unsigned long link_irq; 530315333Serj struct ixgbe_hw_stats stats_pf; 531283620Serj#if __FreeBSD_version >= 1100036 532283620Serj /* counter(9) stats */ 533315333Serj u64 ipackets; 534315333Serj u64 ierrors; 535315333Serj u64 opackets; 536315333Serj u64 oerrors; 537315333Serj u64 ibytes; 538315333Serj u64 obytes; 539315333Serj u64 imcasts; 540315333Serj u64 omcasts; 541315333Serj u64 iqdrops; 542315333Serj u64 noproto; 543283620Serj#endif 544315333Serj /* Feature capable/enabled flags. See ixgbe_features.h */ 545315333Serj u32 feat_cap; 546315333Serj u32 feat_en; 547171384Sjfv}; 548171384Sjfv 549251964Sjfv 550190873Sjfv/* Precision Time Sync (IEEE 1588) defines */ 551190873Sjfv#define ETHERTYPE_IEEE1588 0x88F7 552190873Sjfv#define PICOSECS_PER_TICK 20833 553190873Sjfv#define TSYNC_UDP_PORT 319 /* UDP port for the protocol */ 554315333Serj#define IXGBE_ADVTXD_TSTAMP 0x00080000 555190873Sjfv 556190873Sjfv 557179055Sjfv#define IXGBE_CORE_LOCK_INIT(_sc, _name) \ 558179055Sjfv mtx_init(&(_sc)->core_mtx, _name, "IXGBE Core Lock", MTX_DEF) 559179055Sjfv#define IXGBE_CORE_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->core_mtx) 560200239Sjfv#define IXGBE_TX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->tx_mtx) 561200239Sjfv#define IXGBE_RX_LOCK_DESTROY(_sc) mtx_destroy(&(_sc)->rx_mtx) 562179055Sjfv#define IXGBE_CORE_LOCK(_sc) mtx_lock(&(_sc)->core_mtx) 563200239Sjfv#define IXGBE_TX_LOCK(_sc) mtx_lock(&(_sc)->tx_mtx) 564200239Sjfv#define IXGBE_TX_TRYLOCK(_sc) mtx_trylock(&(_sc)->tx_mtx) 565200239Sjfv#define IXGBE_RX_LOCK(_sc) mtx_lock(&(_sc)->rx_mtx) 566179055Sjfv#define IXGBE_CORE_UNLOCK(_sc) mtx_unlock(&(_sc)->core_mtx) 567179055Sjfv#define IXGBE_TX_UNLOCK(_sc) mtx_unlock(&(_sc)->tx_mtx) 568179055Sjfv#define IXGBE_RX_UNLOCK(_sc) mtx_unlock(&(_sc)->rx_mtx) 569179055Sjfv#define IXGBE_CORE_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->core_mtx, MA_OWNED) 570179055Sjfv#define IXGBE_TX_LOCK_ASSERT(_sc) mtx_assert(&(_sc)->tx_mtx, MA_OWNED) 571179055Sjfv 572251964Sjfv/* For backward compatibility */ 573251964Sjfv#if !defined(PCIER_LINK_STA) 574251964Sjfv#define PCIER_LINK_STA PCIR_EXPRESS_LINK_STA 575251964Sjfv#endif 576179055Sjfv 577283620Serj/* Stats macros */ 578283620Serj#if __FreeBSD_version >= 1100036 579283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ipackets = (count) 580283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ierrors = (count) 581283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->opackets = (count) 582283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->oerrors = (count) 583283620Serj#define IXGBE_SET_COLLISIONS(sc, count) 584283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ibytes = (count) 585283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->obytes = (count) 586283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->imcasts = (count) 587283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->omcasts = (count) 588283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->iqdrops = (count) 589283620Serj#else 590283620Serj#define IXGBE_SET_IPACKETS(sc, count) (sc)->ifp->if_ipackets = (count) 591283620Serj#define IXGBE_SET_IERRORS(sc, count) (sc)->ifp->if_ierrors = (count) 592283620Serj#define IXGBE_SET_OPACKETS(sc, count) (sc)->ifp->if_opackets = (count) 593283620Serj#define IXGBE_SET_OERRORS(sc, count) (sc)->ifp->if_oerrors = (count) 594283620Serj#define IXGBE_SET_COLLISIONS(sc, count) (sc)->ifp->if_collisions = (count) 595283620Serj#define IXGBE_SET_IBYTES(sc, count) (sc)->ifp->if_ibytes = (count) 596283620Serj#define IXGBE_SET_OBYTES(sc, count) (sc)->ifp->if_obytes = (count) 597283620Serj#define IXGBE_SET_IMCASTS(sc, count) (sc)->ifp->if_imcasts = (count) 598283620Serj#define IXGBE_SET_OMCASTS(sc, count) (sc)->ifp->if_omcasts = (count) 599283620Serj#define IXGBE_SET_IQDROPS(sc, count) (sc)->ifp->if_iqdrops = (count) 600283620Serj#endif 601283620Serj 602283620Serj/* External PHY register addresses */ 603315333Serj#define IXGBE_PHY_CURRENT_TEMP 0xC820 604315333Serj#define IXGBE_PHY_OVERTEMP_STATUS 0xC830 605283620Serj 606283620Serj/* Sysctl help messages; displayed with sysctl -d */ 607283620Serj#define IXGBE_SYSCTL_DESC_ADV_SPEED \ 608315333Serj "\nControl advertised link speed using these flags:\n" \ 609315333Serj "\t0x1 - advertise 100M\n" \ 610315333Serj "\t0x2 - advertise 1G\n" \ 611315333Serj "\t0x4 - advertise 10G\n" \ 612315333Serj "\t0x8 - advertise 10M\n\n" \ 613315333Serj "\t100M and 10M are only supported on certain adapters.\n" 614283620Serj 615283620Serj#define IXGBE_SYSCTL_DESC_SET_FC \ 616315333Serj "\nSet flow control mode using these values:\n" \ 617315333Serj "\t0 - off\n" \ 618315333Serj "\t1 - rx pause\n" \ 619315333Serj "\t2 - tx pause\n" \ 620315333Serj "\t3 - tx and rx pause" 621283620Serj 622208762Sjfv/* Workaround to make 8.0 buildable */ 623217129Sjfv#if __FreeBSD_version >= 800000 && __FreeBSD_version < 800504 624208762Sjfvstatic __inline int 625208762Sjfvdrbr_needs_enqueue(struct ifnet *ifp, struct buf_ring *br) 626208762Sjfv{ 627208762Sjfv#ifdef ALTQ 628208762Sjfv if (ALTQ_IS_ENABLED(&ifp->if_snd)) 629208762Sjfv return (1); 630208762Sjfv#endif 631208762Sjfv return (!buf_ring_empty(br)); 632208762Sjfv} 633208762Sjfv#endif 634208762Sjfv 635221041Sjfv/* 636315333Serj * Find the number of unrefreshed RX descriptors 637315333Serj */ 638221041Sjfvstatic inline u16 639221041Sjfvixgbe_rx_unrefreshed(struct rx_ring *rxr) 640315333Serj{ 641221041Sjfv if (rxr->next_to_check > rxr->next_to_refresh) 642221041Sjfv return (rxr->next_to_check - rxr->next_to_refresh - 1); 643221041Sjfv else 644243729Sjfv return ((rxr->num_desc + rxr->next_to_check) - 645221041Sjfv rxr->next_to_refresh - 1); 646315333Serj} 647221041Sjfv 648315333Serjstatic inline int 649315333Serjixgbe_legacy_ring_empty(struct ifnet *ifp, struct buf_ring *dummy) 650315333Serj{ 651315333Serj UNREFERENCED_1PARAMETER(dummy); 652315333Serj 653315333Serj return IFQ_DRV_IS_EMPTY(&ifp->if_snd); 654315333Serj} 655315333Serj 656283620Serj/* 657315333Serj * This checks for a zero mac addr, something that will be likely 658315333Serj * unless the Admin on the Host has created one. 659315333Serj */ 660283620Serjstatic inline bool 661283620Serjixv_check_ether_addr(u8 *addr) 662283620Serj{ 663283620Serj bool status = TRUE; 664283620Serj 665283620Serj if ((addr[0] == 0 && addr[1]== 0 && addr[2] == 0 && 666283620Serj addr[3] == 0 && addr[4]== 0 && addr[5] == 0)) 667283620Serj status = FALSE; 668315333Serj 669283620Serj return (status); 670283620Serj} 671283620Serj 672283620Serj/* Shared Prototypes */ 673315333Serjvoid ixgbe_legacy_start(struct ifnet *); 674315333Serjint ixgbe_legacy_start_locked(struct ifnet *, struct tx_ring *); 675315333Serjint ixgbe_mq_start(struct ifnet *, struct mbuf *); 676315333Serjint ixgbe_mq_start_locked(struct ifnet *, struct tx_ring *); 677315333Serjvoid ixgbe_qflush(struct ifnet *); 678315333Serjvoid ixgbe_deferred_mq_start(void *, int); 679315333Serjvoid ixgbe_init_locked(struct adapter *); 680283620Serj 681315333Serjint ixgbe_allocate_queues(struct adapter *); 682315333Serjint ixgbe_setup_transmit_structures(struct adapter *); 683315333Serjvoid ixgbe_free_transmit_structures(struct adapter *); 684315333Serjint ixgbe_setup_receive_structures(struct adapter *); 685315333Serjvoid ixgbe_free_receive_structures(struct adapter *); 686315333Serjvoid ixgbe_txeof(struct tx_ring *); 687315333Serjbool ixgbe_rxeof(struct ix_queue *); 688283620Serj 689315333Serj#include "ixgbe_sriov.h" 690315333Serj#include "ixgbe_bypass.h" 691315333Serj#include "ixgbe_fdir.h" 692315333Serj#include "ixgbe_rss.h" 693315333Serj#include "ixgbe_netmap.h" 694283620Serj 695171384Sjfv#endif /* _IXGBE_H_ */ 696