1129794Stackerman/******************************************************************************* 2129794Stackerman 3129794Stackerman Copyright (c) 2001-2004, Intel Corporation 4129794Stackerman All rights reserved. 5129794Stackerman 6129794Stackerman Redistribution and use in source and binary forms, with or without 7129794Stackerman modification, are permitted provided that the following conditions are met: 8129794Stackerman 9129794Stackerman 1. Redistributions of source code must retain the above copyright notice, 10129794Stackerman this list of conditions and the following disclaimer. 11129794Stackerman 12129794Stackerman 2. Redistributions in binary form must reproduce the above copyright 13129794Stackerman notice, this list of conditions and the following disclaimer in the 14129794Stackerman documentation and/or other materials provided with the distribution. 15129794Stackerman 16129794Stackerman 3. Neither the name of the Intel Corporation nor the names of its 17129794Stackerman contributors may be used to endorse or promote products derived from 18129794Stackerman this software without specific prior written permission. 19129794Stackerman 20129794Stackerman THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" 21129794Stackerman AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE 22129794Stackerman IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE 23129794Stackerman ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE 24129794Stackerman LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR 25129794Stackerman CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF 26129794Stackerman SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS 27129794Stackerman INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN 28129794Stackerman CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) 29129794Stackerman ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE 30129794Stackerman POSSIBILITY OF SUCH DAMAGE. 31129794Stackerman 32129794Stackerman*******************************************************************************/ 33129794Stackerman 34129794Stackerman/*$FreeBSD$*/ 35129794Stackerman#ifndef _IXGB_HW_H_ 36129794Stackerman#define _IXGB_HW_H_ 37129794Stackerman 38129794Stackerman#include <dev/ixgb/if_ixgb_osdep.h> 39129794Stackerman 40129794Stackerman/* Enums */ 41129794Stackermantypedef enum { 42129794Stackerman ixgb_mac_unknown = 0, 43129794Stackerman ixgb_82597, 44129794Stackerman ixgb_num_macs 45129794Stackerman} ixgb_mac_type; 46129794Stackerman 47129794Stackerman/* Types of physical layer modules */ 48129794Stackermantypedef enum { 49129794Stackerman ixgb_phy_type_unknown = 0, 50129794Stackerman ixgb_phy_type_g6005, /* 850nm, MM fiber, XPAK transceiver */ 51129794Stackerman ixgb_phy_type_g6104, /* 1310nm, SM fiber, XPAK transceiver */ 52129794Stackerman ixgb_phy_type_txn17201, /* 850nm, MM fiber, XPAK transceiver */ 53129794Stackerman ixgb_phy_type_txn17401 /* 1310nm, SM fiber, XENPAK transceiver */ 54129794Stackerman} ixgb_phy_type; 55129794Stackerman 56129794Stackerman/* XPAK transceiver vendors, for the SR adapters */ 57129794Stackermantypedef enum { 58129794Stackerman ixgb_xpak_vendor_intel, 59129794Stackerman ixgb_xpak_vendor_infineon 60129794Stackerman} ixgb_xpak_vendor; 61129794Stackerman 62129794Stackerman/* Media Types */ 63129794Stackermantypedef enum { 64129794Stackerman ixgb_media_type_unknown = 0, 65129794Stackerman ixgb_media_type_fiber = 1, 66129794Stackerman ixgb_num_media_types 67129794Stackerman} ixgb_media_type; 68129794Stackerman 69129794Stackerman/* Flow Control Settings */ 70129794Stackermantypedef enum { 71129794Stackerman ixgb_fc_none = 0, 72129794Stackerman ixgb_fc_rx_pause = 1, 73129794Stackerman ixgb_fc_tx_pause = 2, 74129794Stackerman ixgb_fc_full = 3, 75129794Stackerman ixgb_fc_default = 0xFF 76129794Stackerman} ixgb_fc_type; 77129794Stackerman 78129794Stackerman/* PCI bus types */ 79129794Stackermantypedef enum { 80129794Stackerman ixgb_bus_type_unknown = 0, 81129794Stackerman ixgb_bus_type_pci, 82129794Stackerman ixgb_bus_type_pcix 83129794Stackerman} ixgb_bus_type; 84129794Stackerman 85129794Stackerman/* PCI bus speeds */ 86129794Stackermantypedef enum { 87129794Stackerman ixgb_bus_speed_unknown = 0, 88129794Stackerman ixgb_bus_speed_33, 89129794Stackerman ixgb_bus_speed_66, 90129794Stackerman ixgb_bus_speed_100, 91129794Stackerman ixgb_bus_speed_133, 92129794Stackerman ixgb_bus_speed_reserved 93129794Stackerman} ixgb_bus_speed; 94129794Stackerman 95129794Stackerman/* PCI bus widths */ 96129794Stackermantypedef enum { 97129794Stackerman ixgb_bus_width_unknown = 0, 98129794Stackerman ixgb_bus_width_32, 99129794Stackerman ixgb_bus_width_64 100129794Stackerman} ixgb_bus_width; 101129794Stackerman 102129794Stackerman 103129794Stackerman#define IXGB_ETH_LENGTH_OF_ADDRESS 6 104129794Stackerman 105129794Stackerman#define IXGB_EEPROM_SIZE 64 /* Size in words */ 106129794Stackerman 107129794Stackerman#define SPEED_10000 10000 108129794Stackerman#define FULL_DUPLEX 2 109129794Stackerman 110129794Stackerman#define MIN_NUMBER_OF_DESCRIPTORS 8 111129794Stackerman#define MAX_NUMBER_OF_DESCRIPTORS 0xFFF8 /* 13 bits in RDLEN/TDLEN, 128B aligned */ 112129794Stackerman 113129794Stackerman#define IXGB_DELAY_BEFORE_RESET 10 /* allow 10ms after idling rx/tx units */ 114129794Stackerman#define IXGB_DELAY_AFTER_RESET 1 /* allow 1ms after the reset */ 115129794Stackerman#define IXGB_DELAY_AFTER_EE_RESET 10 /* allow 10ms after the EEPROM reset */ 116129794Stackerman 117129794Stackerman#define IXGB_DELAY_USECS_AFTER_LINK_RESET 13 /* allow 13 microseconds after the reset */ 118129794Stackerman /* NOTE: this is MICROSECONDS */ 119129794Stackerman#define MAX_RESET_ITERATIONS 8 /* number of iterations to get things right */ 120129794Stackerman 121129794Stackerman/* General Registers */ 122129794Stackerman#define IXGB_CTRL0 0x00000 /* Device Control Register 0 - RW */ 123129794Stackerman#define IXGB_CTRL1 0x00008 /* Device Control Register 1 - RW */ 124129794Stackerman#define IXGB_STATUS 0x00010 /* Device Status Register - RO */ 125129794Stackerman#define IXGB_EECD 0x00018 /* EEPROM/Flash Control/Data Register - RW */ 126129794Stackerman#define IXGB_MFS 0x00020 /* Maximum Frame Size - RW */ 127129794Stackerman 128129794Stackerman/* Interrupt */ 129129794Stackerman#define IXGB_ICR 0x00080 /* Interrupt Cause Read - R/clr */ 130129794Stackerman#define IXGB_ICS 0x00088 /* Interrupt Cause Set - RW */ 131129794Stackerman#define IXGB_IMS 0x00090 /* Interrupt Mask Set/Read - RW */ 132129794Stackerman#define IXGB_IMC 0x00098 /* Interrupt Mask Clear - WO */ 133129794Stackerman 134129794Stackerman/* Receive */ 135129794Stackerman#define IXGB_RCTL 0x00100 /* RX Control - RW */ 136129794Stackerman#define IXGB_FCRTL 0x00108 /* Flow Control Receive Threshold Low - RW */ 137129794Stackerman#define IXGB_FCRTH 0x00110 /* Flow Control Receive Threshold High - RW */ 138129794Stackerman#define IXGB_RDBAL 0x00118 /* RX Descriptor Base Low - RW */ 139129794Stackerman#define IXGB_RDBAH 0x0011C /* RX Descriptor Base High - RW */ 140129794Stackerman#define IXGB_RDLEN 0x00120 /* RX Descriptor Length - RW */ 141129794Stackerman#define IXGB_RDH 0x00128 /* RX Descriptor Head - RW */ 142129794Stackerman#define IXGB_RDT 0x00130 /* RX Descriptor Tail - RW */ 143129794Stackerman#define IXGB_RDTR 0x00138 /* RX Delay Timer Ring - RW */ 144129794Stackerman#define IXGB_RXDCTL 0x00140 /* Receive Descriptor Control - RW */ 145129794Stackerman#define IXGB_RAIDC 0x00148 /* Receive Adaptive Interrupt Delay Control - RW */ 146129794Stackerman#define IXGB_RXCSUM 0x00158 /* Receive Checksum Control - RW */ 147129794Stackerman#define IXGB_RA 0x00180 /* Receive Address Array Base - RW */ 148129794Stackerman#define IXGB_RAL 0x00180 /* Receive Address Low [0:15] - RW */ 149129794Stackerman#define IXGB_RAH 0x00184 /* Receive Address High [0:15] - RW */ 150129794Stackerman#define IXGB_MTA 0x00200 /* Multicast Table Array [0:127] - RW */ 151129794Stackerman#define IXGB_VFTA 0x00400 /* VLAN Filter Table Array [0:127] - RW */ 152129794Stackerman#define IXGB_REQ_RX_DESCRIPTOR_MULTIPLE 8 153129794Stackerman 154129794Stackerman/* Transmit */ 155129794Stackerman#define IXGB_TCTL 0x00600 /* TX Control - RW */ 156129794Stackerman#define IXGB_TDBAL 0x00608 /* TX Descriptor Base Low - RW */ 157129794Stackerman#define IXGB_TDBAH 0x0060C /* TX Descriptor Base High - RW */ 158129794Stackerman#define IXGB_TDLEN 0x00610 /* TX Descriptor Length - RW */ 159129794Stackerman#define IXGB_TDH 0x00618 /* TX Descriptor Head - RW */ 160129794Stackerman#define IXGB_TDT 0x00620 /* TX Descriptor Tail - RW */ 161129794Stackerman#define IXGB_TIDV 0x00628 /* TX Interrupt Delay Value - RW */ 162129794Stackerman#define IXGB_TXDCTL 0x00630 /* Transmit Descriptor Control - RW */ 163129794Stackerman#define IXGB_TSPMT 0x00638 /* TCP Segmentation PAD & Min Threshold - RW */ 164129794Stackerman#define IXGB_PAP 0x00640 /* Pause and Pace - RW */ 165129794Stackerman#define IXGB_REQ_TX_DESCRIPTOR_MULTIPLE 8 166129794Stackerman 167129794Stackerman/* Physical */ 168129794Stackerman#define IXGB_PCSC1 0x00700 /* PCS Control 1 - RW */ 169129794Stackerman#define IXGB_PCSC2 0x00708 /* PCS Control 2 - RW */ 170129794Stackerman#define IXGB_PCSS1 0x00710 /* PCS Status 1 - RO */ 171129794Stackerman#define IXGB_PCSS2 0x00718 /* PCS Status 2 - RO */ 172129794Stackerman#define IXGB_XPCSS 0x00720 /* 10GBASE-X PCS Status (or XGXS Lane Status) - RO */ 173129794Stackerman#define IXGB_UCCR 0x00728 /* Unilink Circuit Control Register */ 174129794Stackerman#define IXGB_XPCSTC 0x00730 /* 10GBASE-X PCS Test Control */ 175129794Stackerman#define IXGB_MACA 0x00738 /* MDI Autoscan Command and Address - RW */ 176129794Stackerman#define IXGB_APAE 0x00740 /* Autoscan PHY Address Enable - RW */ 177129794Stackerman#define IXGB_ARD 0x00748 /* Autoscan Read Data - RO */ 178129794Stackerman#define IXGB_AIS 0x00750 /* Autoscan Interrupt Status - RO */ 179129794Stackerman#define IXGB_MSCA 0x00758 /* MDI Single Command and Address - RW */ 180129794Stackerman#define IXGB_MSRWD 0x00760 /* MDI Single Read and Write Data - RW, RO */ 181129794Stackerman 182129794Stackerman/* Wake-up */ 183129794Stackerman#define IXGB_WUFC 0x00808 /* Wake Up Filter Control - RW */ 184129794Stackerman#define IXGB_WUS 0x00810 /* Wake Up Status - RO */ 185129794Stackerman#define IXGB_FFLT 0x01000 /* Flexible Filter Length Table - RW */ 186129794Stackerman#define IXGB_FFMT 0x01020 /* Flexible Filter Mask Table - RW */ 187129794Stackerman#define IXGB_FTVT 0x01420 /* Flexible Filter Value Table - RW */ 188129794Stackerman 189129794Stackerman/* Statistics */ 190129794Stackerman#define IXGB_TPRL 0x02000 /* Total Packets Received (Low) */ 191129794Stackerman#define IXGB_TPRH 0x02004 /* Total Packets Received (High) */ 192129794Stackerman#define IXGB_GPRCL 0x02008 /* Good Packets Received Count (Low) */ 193129794Stackerman#define IXGB_GPRCH 0x0200C /* Good Packets Received Count (High) */ 194129794Stackerman#define IXGB_BPRCL 0x02010 /* Broadcast Packets Received Count (Low) */ 195129794Stackerman#define IXGB_BPRCH 0x02014 /* Broadcast Packets Received Count (High) */ 196129794Stackerman#define IXGB_MPRCL 0x02018 /* Multicast Packets Received Count (Low) */ 197129794Stackerman#define IXGB_MPRCH 0x0201C /* Multicast Packets Received Count (High) */ 198129794Stackerman#define IXGB_UPRCL 0x02020 /* Unicast Packets Received Count (Low) */ 199129794Stackerman#define IXGB_UPRCH 0x02024 /* Unicast Packets Received Count (High) */ 200129794Stackerman#define IXGB_VPRCL 0x02028 /* VLAN Packets Received Count (Low) */ 201129794Stackerman#define IXGB_VPRCH 0x0202C /* VLAN Packets Received Count (High) */ 202129794Stackerman#define IXGB_JPRCL 0x02030 /* Jumbo Packets Received Count (Low) */ 203129794Stackerman#define IXGB_JPRCH 0x02034 /* Jumbo Packets Received Count (High) */ 204129794Stackerman#define IXGB_GORCL 0x02038 /* Good Octets Received Count (Low) */ 205129794Stackerman#define IXGB_GORCH 0x0203C /* Good Octets Received Count (High) */ 206129794Stackerman#define IXGB_TORL 0x02040 /* Total Octets Received (Low) */ 207129794Stackerman#define IXGB_TORH 0x02044 /* Total Octets Received (High) */ 208129794Stackerman#define IXGB_RNBC 0x02048 /* Receive No Buffers Count */ 209129794Stackerman#define IXGB_RUC 0x02050 /* Receive Undersize Count */ 210129794Stackerman#define IXGB_ROC 0x02058 /* Receive Oversize Count */ 211129794Stackerman#define IXGB_RLEC 0x02060 /* Receive Length Error Count */ 212129794Stackerman#define IXGB_CRCERRS 0x02068 /* CRC Error Count */ 213129794Stackerman#define IXGB_ICBC 0x02070 /* Illegal control byte in mid-packet Count */ 214129794Stackerman#define IXGB_ECBC 0x02078 /* Error Control byte in mid-packet Count */ 215129794Stackerman#define IXGB_MPC 0x02080 /* Missed Packets Count */ 216129794Stackerman#define IXGB_TPTL 0x02100 /* Total Packets Transmitted (Low) */ 217129794Stackerman#define IXGB_TPTH 0x02104 /* Total Packets Transmitted (High) */ 218129794Stackerman#define IXGB_GPTCL 0x02108 /* Good Packets Transmitted Count (Low) */ 219129794Stackerman#define IXGB_GPTCH 0x0210C /* Good Packets Transmitted Count (High) */ 220129794Stackerman#define IXGB_BPTCL 0x02110 /* Broadcast Packets Transmitted Count (Low) */ 221129794Stackerman#define IXGB_BPTCH 0x02114 /* Broadcast Packets Transmitted Count (High) */ 222129794Stackerman#define IXGB_MPTCL 0x02118 /* Multicast Packets Transmitted Count (Low) */ 223129794Stackerman#define IXGB_MPTCH 0x0211C /* Multicast Packets Transmitted Count (High) */ 224129794Stackerman#define IXGB_UPTCL 0x02120 /* Unicast Packets Transmitted Count (Low) */ 225129794Stackerman#define IXGB_UPTCH 0x02124 /* Unicast Packets Transmitted Count (High) */ 226129794Stackerman#define IXGB_VPTCL 0x02128 /* VLAN Packets Transmitted Count (Low) */ 227129794Stackerman#define IXGB_VPTCH 0x0212C /* VLAN Packets Transmitted Count (High) */ 228129794Stackerman#define IXGB_JPTCL 0x02130 /* Jumbo Packets Transmitted Count (Low) */ 229129794Stackerman#define IXGB_JPTCH 0x02134 /* Jumbo Packets Transmitted Count (High) */ 230129794Stackerman#define IXGB_GOTCL 0x02138 /* Good Octets Transmitted Count (Low) */ 231129794Stackerman#define IXGB_GOTCH 0x0213C /* Good Octets Transmitted Count (High) */ 232129794Stackerman#define IXGB_TOTL 0x02140 /* Total Octets Transmitted Count (Low) */ 233129794Stackerman#define IXGB_TOTH 0x02144 /* Total Octets Transmitted Count (High) */ 234129794Stackerman#define IXGB_DC 0x02148 /* Defer Count */ 235129794Stackerman#define IXGB_PLT64C 0x02150 /* Packet Transmitted was less than 64 bytes Count */ 236129794Stackerman#define IXGB_TSCTC 0x02170 /* TCP Segmentation Context Transmitted Count */ 237129794Stackerman#define IXGB_TSCTFC 0x02178 /* TCP Segmentation Context Tx Fail Count */ 238129794Stackerman#define IXGB_IBIC 0x02180 /* Illegal byte during Idle stream count */ 239129794Stackerman#define IXGB_RFC 0x02188 /* Remote Fault Count */ 240129794Stackerman#define IXGB_LFC 0x02190 /* Local Fault Count */ 241129794Stackerman#define IXGB_PFRC 0x02198 /* Pause Frame Receive Count */ 242129794Stackerman#define IXGB_PFTC 0x021A0 /* Pause Frame Transmit Count */ 243129794Stackerman#define IXGB_MCFRC 0x021A8 /* MAC Control Frames (non-Pause) Received Count */ 244129794Stackerman#define IXGB_MCFTC 0x021B0 /* MAC Control Frames (non-Pause) Transmitted Count */ 245129794Stackerman#define IXGB_XONRXC 0x021B8 /* XON Received Count */ 246129794Stackerman#define IXGB_XONTXC 0x021C0 /* XON Transmitted Count */ 247129794Stackerman#define IXGB_XOFFRXC 0x021C8 /* XOFF Received Count */ 248129794Stackerman#define IXGB_XOFFTXC 0x021D0 /* XOFF Transmitted Count */ 249129794Stackerman#define IXGB_RJC 0x021D8 /* Receive Jabber Count */ 250129794Stackerman 251129794Stackerman 252129794Stackerman/* CTRL0 Bit Masks */ 253129794Stackerman#define IXGB_CTRL0_LRST 0x00000008 254129794Stackerman#define IXGB_CTRL0_JFE 0x00000010 255129794Stackerman#define IXGB_CTRL0_XLE 0x00000020 256129794Stackerman#define IXGB_CTRL0_MDCS 0x00000040 257129794Stackerman#define IXGB_CTRL0_CMDC 0x00000080 258129794Stackerman#define IXGB_CTRL0_SDP0 0x00040000 259129794Stackerman#define IXGB_CTRL0_SDP1 0x00080000 260129794Stackerman#define IXGB_CTRL0_SDP2 0x00100000 261129794Stackerman#define IXGB_CTRL0_SDP3 0x00200000 262129794Stackerman#define IXGB_CTRL0_SDP0_DIR 0x00400000 263129794Stackerman#define IXGB_CTRL0_SDP1_DIR 0x00800000 264129794Stackerman#define IXGB_CTRL0_SDP2_DIR 0x01000000 265129794Stackerman#define IXGB_CTRL0_SDP3_DIR 0x02000000 266129794Stackerman#define IXGB_CTRL0_RST 0x04000000 267129794Stackerman#define IXGB_CTRL0_RPE 0x08000000 268129794Stackerman#define IXGB_CTRL0_TPE 0x10000000 269129794Stackerman#define IXGB_CTRL0_VME 0x40000000 270129794Stackerman 271129794Stackerman/* CTRL1 Bit Masks */ 272129794Stackerman#define IXGB_CTRL1_GPI0_EN 0x00000001 273129794Stackerman#define IXGB_CTRL1_GPI1_EN 0x00000002 274129794Stackerman#define IXGB_CTRL1_GPI2_EN 0x00000004 275129794Stackerman#define IXGB_CTRL1_GPI3_EN 0x00000008 276129794Stackerman#define IXGB_CTRL1_SDP4 0x00000010 277129794Stackerman#define IXGB_CTRL1_SDP5 0x00000020 278129794Stackerman#define IXGB_CTRL1_SDP6 0x00000040 279129794Stackerman#define IXGB_CTRL1_SDP7 0x00000080 280129794Stackerman#define IXGB_CTRL1_SDP4_DIR 0x00000100 281129794Stackerman#define IXGB_CTRL1_SDP5_DIR 0x00000200 282129794Stackerman#define IXGB_CTRL1_SDP6_DIR 0x00000400 283129794Stackerman#define IXGB_CTRL1_SDP7_DIR 0x00000800 284129794Stackerman#define IXGB_CTRL1_EE_RST 0x00002000 285129794Stackerman#define IXGB_CTRL1_RO_DIS 0x00020000 286129794Stackerman#define IXGB_CTRL1_PCIXHM_MASK 0x00C00000 287129794Stackerman#define IXGB_CTRL1_PCIXHM_1_2 0x00000000 288129794Stackerman#define IXGB_CTRL1_PCIXHM_5_8 0x00400000 289129794Stackerman#define IXGB_CTRL1_PCIXHM_3_4 0x00800000 290129794Stackerman#define IXGB_CTRL1_PCIXHM_7_8 0x00C00000 291129794Stackerman 292129794Stackerman/* STATUS Bit Masks */ 293129794Stackerman#define IXGB_STATUS_LU 0x00000002 294129794Stackerman#define IXGB_STATUS_AIP 0x00000004 295129794Stackerman#define IXGB_STATUS_TXOFF 0x00000010 296129794Stackerman#define IXGB_STATUS_XAUIME 0x00000020 297129794Stackerman#define IXGB_STATUS_RES 0x00000040 298129794Stackerman#define IXGB_STATUS_RIS 0x00000080 299129794Stackerman#define IXGB_STATUS_RIE 0x00000100 300129794Stackerman#define IXGB_STATUS_RLF 0x00000200 301129794Stackerman#define IXGB_STATUS_RRF 0x00000400 302129794Stackerman#define IXGB_STATUS_PCI_SPD 0x00000800 303129794Stackerman#define IXGB_STATUS_BUS64 0x00001000 304129794Stackerman#define IXGB_STATUS_PCIX_MODE 0x00002000 305129794Stackerman#define IXGB_STATUS_PCIX_SPD_MASK 0x0000C000 306129794Stackerman#define IXGB_STATUS_PCIX_SPD_66 0x00000000 307129794Stackerman#define IXGB_STATUS_PCIX_SPD_100 0x00004000 308129794Stackerman#define IXGB_STATUS_PCIX_SPD_133 0x00008000 309129794Stackerman#define IXGB_STATUS_REV_ID_MASK 0x000F0000 310129794Stackerman#define IXGB_STATUS_REV_ID_SHIFT 16 311129794Stackerman 312129794Stackerman/* EECD Bit Masks */ 313129794Stackerman#define IXGB_EECD_SK 0x00000001 314129794Stackerman#define IXGB_EECD_CS 0x00000002 315129794Stackerman#define IXGB_EECD_DI 0x00000004 316129794Stackerman#define IXGB_EECD_DO 0x00000008 317129794Stackerman#define IXGB_EECD_FWE_MASK 0x00000030 318129794Stackerman#define IXGB_EECD_FWE_DIS 0x00000010 319129794Stackerman#define IXGB_EECD_FWE_EN 0x00000020 320129794Stackerman 321129794Stackerman/* MFS */ 322129794Stackerman#define IXGB_MFS_SHIFT 16 323129794Stackerman 324129794Stackerman/* Interrupt Register Bit Masks (used for ICR, ICS, IMS, and IMC) */ 325129794Stackerman#define IXGB_INT_TXDW 0x00000001 326129794Stackerman#define IXGB_INT_TXQE 0x00000002 327129794Stackerman#define IXGB_INT_LSC 0x00000004 328129794Stackerman#define IXGB_INT_RXSEQ 0x00000008 329129794Stackerman#define IXGB_INT_RXDMT0 0x00000010 330129794Stackerman#define IXGB_INT_RXO 0x00000040 331129794Stackerman#define IXGB_INT_RXT0 0x00000080 332129794Stackerman#define IXGB_INT_AUTOSCAN 0x00000200 333129794Stackerman#define IXGB_INT_GPI0 0x00000800 334129794Stackerman#define IXGB_INT_GPI1 0x00001000 335129794Stackerman#define IXGB_INT_GPI2 0x00002000 336129794Stackerman#define IXGB_INT_GPI3 0x00004000 337129794Stackerman 338129794Stackerman/* RCTL Bit Masks */ 339129794Stackerman#define IXGB_RCTL_RXEN 0x00000002 340129794Stackerman#define IXGB_RCTL_SBP 0x00000004 341129794Stackerman#define IXGB_RCTL_UPE 0x00000008 342129794Stackerman#define IXGB_RCTL_MPE 0x00000010 343129794Stackerman#define IXGB_RCTL_RDMTS_MASK 0x00000300 344129794Stackerman#define IXGB_RCTL_RDMTS_1_2 0x00000000 345129794Stackerman#define IXGB_RCTL_RDMTS_1_4 0x00000100 346129794Stackerman#define IXGB_RCTL_RDMTS_1_8 0x00000200 347129794Stackerman#define IXGB_RCTL_MO_MASK 0x00003000 348129794Stackerman#define IXGB_RCTL_MO_47_36 0x00000000 349129794Stackerman#define IXGB_RCTL_MO_46_35 0x00001000 350129794Stackerman#define IXGB_RCTL_MO_45_34 0x00002000 351129794Stackerman#define IXGB_RCTL_MO_43_32 0x00003000 352129794Stackerman#define IXGB_RCTL_MO_SHIFT 12 353129794Stackerman#define IXGB_RCTL_BAM 0x00008000 354129794Stackerman#define IXGB_RCTL_BSIZE_MASK 0x00030000 355129794Stackerman#define IXGB_RCTL_BSIZE_2048 0x00000000 356129794Stackerman#define IXGB_RCTL_BSIZE_4096 0x00010000 357129794Stackerman#define IXGB_RCTL_BSIZE_8192 0x00020000 358129794Stackerman#define IXGB_RCTL_BSIZE_16384 0x00030000 359129794Stackerman#define IXGB_RCTL_VFE 0x00040000 360129794Stackerman#define IXGB_RCTL_CFIEN 0x00080000 361129794Stackerman#define IXGB_RCTL_CFI 0x00100000 362129794Stackerman#define IXGB_RCTL_RPDA_MASK 0x00600000 363129794Stackerman#define IXGB_RCTL_RPDA_MC_MAC 0x00000000 364129794Stackerman#define IXGB_RCTL_MC_ONLY 0x00400000 365129794Stackerman#define IXGB_RCTL_CFF 0x00800000 366129794Stackerman#define IXGB_RCTL_SECRC 0x04000000 367129794Stackerman#define IXGB_RDT_FPDB 0x80000000 368129794Stackerman 369129794Stackerman#define IXGB_RCTL_IDLE_RX_UNIT 0 370129794Stackerman 371129794Stackerman/* FCRTL Bit Masks */ 372129794Stackerman#define IXGB_FCRTL_XONE 0x80000000 373129794Stackerman 374129794Stackerman/* RXDCTL Bit Masks */ 375129794Stackerman#define IXGB_RXDCTL_PTHRESH_MASK 0x000001FF 376129794Stackerman#define IXGB_RXDCTL_PTHRESH_SHIFT 0 377129794Stackerman#define IXGB_RXDCTL_HTHRESH_MASK 0x0003FE00 378129794Stackerman#define IXGB_RXDCTL_HTHRESH_SHIFT 9 379129794Stackerman#define IXGB_RXDCTL_WTHRESH_MASK 0x07FC0000 380129794Stackerman#define IXGB_RXDCTL_WTHRESH_SHIFT 18 381129794Stackerman 382129794Stackerman/* RAIDC Bit Masks */ 383129794Stackerman#define IXGB_RAIDC_HIGHTHRS_MASK 0x0000003F 384129794Stackerman#define IXGB_RAIDC_DELAY_MASK 0x000FF800 385129794Stackerman#define IXGB_RAIDC_DELAY_SHIFT 11 386129794Stackerman#define IXGB_RAIDC_POLL_MASK 0x1FF00000 387129794Stackerman#define IXGB_RAIDC_POLL_SHIFT 20 388129794Stackerman#define IXGB_RAIDC_RXT_GATE 0x40000000 389129794Stackerman#define IXGB_RAIDC_EN 0x80000000 390129794Stackerman 391129794Stackerman#define IXGB_RAIDC_POLL_1000_INTERRUPTS_PER_SECOND 1220 392129794Stackerman#define IXGB_RAIDC_POLL_5000_INTERRUPTS_PER_SECOND 244 393129794Stackerman#define IXGB_RAIDC_POLL_10000_INTERRUPTS_PER_SECOND 122 394129794Stackerman#define IXGB_RAIDC_POLL_20000_INTERRUPTS_PER_SECOND 61 395129794Stackerman 396129794Stackerman/* RXCSUM Bit Masks */ 397129794Stackerman#define IXGB_RXCSUM_IPOFL 0x00000100 398129794Stackerman#define IXGB_RXCSUM_TUOFL 0x00000200 399129794Stackerman 400129794Stackerman/* RAH Bit Masks */ 401129794Stackerman#define IXGB_RAH_ASEL_MASK 0x00030000 402129794Stackerman#define IXGB_RAH_ASEL_DEST 0x00000000 403129794Stackerman#define IXGB_RAH_ASEL_SRC 0x00010000 404129794Stackerman#define IXGB_RAH_AV 0x80000000 405129794Stackerman 406129794Stackerman/* TCTL Bit Masks */ 407129794Stackerman#define IXGB_TCTL_TCE 0x00000001 408129794Stackerman#define IXGB_TCTL_TXEN 0x00000002 409129794Stackerman#define IXGB_TCTL_TPDE 0x00000004 410129794Stackerman 411129794Stackerman#define IXGB_TCTL_IDLE_TX_UNIT 0 412129794Stackerman 413129794Stackerman/* TXDCTL Bit Masks */ 414129794Stackerman#define IXGB_TXDCTL_PTHRESH_MASK 0x0000007F 415129794Stackerman#define IXGB_TXDCTL_HTHRESH_MASK 0x00007F00 416129794Stackerman#define IXGB_TXDCTL_HTHRESH_SHIFT 8 417129794Stackerman#define IXGB_TXDCTL_WTHRESH_MASK 0x007F0000 418129794Stackerman#define IXGB_TXDCTL_WTHRESH_SHIFT 16 419129794Stackerman 420129794Stackerman/* TSPMT Bit Masks */ 421129794Stackerman#define IXGB_TSPMT_TSMT_MASK 0x0000FFFF 422129794Stackerman#define IXGB_TSPMT_TSPBP_MASK 0xFFFF0000 423129794Stackerman#define IXGB_TSPMT_TSPBP_SHIFT 16 424129794Stackerman 425129794Stackerman/* PAP Bit Masks */ 426129794Stackerman#define IXGB_PAP_TXPC_MASK 0x0000FFFF 427129794Stackerman#define IXGB_PAP_TXPV_MASK 0x000F0000 428129794Stackerman#define IXGB_PAP_TXPV_10G 0x00000000 429129794Stackerman#define IXGB_PAP_TXPV_1G 0x00010000 430129794Stackerman#define IXGB_PAP_TXPV_2G 0x00020000 431129794Stackerman#define IXGB_PAP_TXPV_3G 0x00030000 432129794Stackerman#define IXGB_PAP_TXPV_4G 0x00040000 433129794Stackerman#define IXGB_PAP_TXPV_5G 0x00050000 434129794Stackerman#define IXGB_PAP_TXPV_6G 0x00060000 435129794Stackerman#define IXGB_PAP_TXPV_7G 0x00070000 436129794Stackerman#define IXGB_PAP_TXPV_8G 0x00080000 437129794Stackerman#define IXGB_PAP_TXPV_9G 0x00090000 438129794Stackerman#define IXGB_PAP_TXPV_WAN 0x000F0000 439129794Stackerman 440129794Stackerman/* PCSC1 Bit Masks */ 441129794Stackerman#define IXGB_PCSC1_LOOPBACK 0x00004000 442129794Stackerman 443129794Stackerman/* PCSC2 Bit Masks */ 444129794Stackerman#define IXGB_PCSC2_PCS_TYPE_MASK 0x00000003 445129794Stackerman#define IXGB_PCSC2_PCS_TYPE_10GBX 0x00000001 446129794Stackerman 447129794Stackerman/* PCSS1 Bit Masks */ 448129794Stackerman#define IXGB_PCSS1_LOCAL_FAULT 0x00000080 449129794Stackerman#define IXGB_PCSS1_RX_LINK_STATUS 0x00000004 450129794Stackerman 451129794Stackerman/* PCSS2 Bit Masks */ 452129794Stackerman#define IXGB_PCSS2_DEV_PRES_MASK 0x0000C000 453129794Stackerman#define IXGB_PCSS2_DEV_PRES 0x00004000 454129794Stackerman#define IXGB_PCSS2_TX_LF 0x00000800 455129794Stackerman#define IXGB_PCSS2_RX_LF 0x00000400 456129794Stackerman#define IXGB_PCSS2_10GBW 0x00000004 457129794Stackerman#define IXGB_PCSS2_10GBX 0x00000002 458129794Stackerman#define IXGB_PCSS2_10GBR 0x00000001 459129794Stackerman 460129794Stackerman/* XPCSS Bit Masks */ 461129794Stackerman#define IXGB_XPCSS_ALIGN_STATUS 0x00001000 462129794Stackerman#define IXGB_XPCSS_PATTERN_TEST 0x00000800 463129794Stackerman#define IXGB_XPCSS_LANE_3_SYNC 0x00000008 464129794Stackerman#define IXGB_XPCSS_LANE_2_SYNC 0x00000004 465129794Stackerman#define IXGB_XPCSS_LANE_1_SYNC 0x00000002 466129794Stackerman#define IXGB_XPCSS_LANE_0_SYNC 0x00000001 467129794Stackerman 468129794Stackerman/* XPCSTC Bit Masks */ 469129794Stackerman#define IXGB_XPCSTC_BERT_TRIG 0x00200000 470129794Stackerman#define IXGB_XPCSTC_BERT_SST 0x00100000 471129794Stackerman#define IXGB_XPCSTC_BERT_PSZ_MASK 0x000C0000 472129794Stackerman#define IXGB_XPCSTC_BERT_PSZ_SHIFT 17 473129794Stackerman#define IXGB_XPCSTC_BERT_PSZ_INF 0x00000003 474129794Stackerman#define IXGB_XPCSTC_BERT_PSZ_68 0x00000001 475129794Stackerman#define IXGB_XPCSTC_BERT_PSZ_1028 0x00000000 476129794Stackerman 477129794Stackerman/* MSCA bit Masks */ 478129794Stackerman/* New Protocol Address */ 479129794Stackerman#define IXGB_MSCA_NP_ADDR_MASK 0x0000FFFF 480129794Stackerman#define IXGB_MSCA_NP_ADDR_SHIFT 0 481129794Stackerman/* Either Device Type or Register Address,depending on ST_CODE */ 482129794Stackerman#define IXGB_MSCA_DEV_TYPE_MASK 0x001F0000 483129794Stackerman#define IXGB_MSCA_DEV_TYPE_SHIFT 16 484129794Stackerman#define IXGB_MSCA_PHY_ADDR_MASK 0x03E00000 485129794Stackerman#define IXGB_MSCA_PHY_ADDR_SHIFT 21 486129794Stackerman#define IXGB_MSCA_OP_CODE_MASK 0x0C000000 487129794Stackerman/* OP_CODE == 00, Address cycle, New Protocol */ 488129794Stackerman/* OP_CODE == 01, Write operation */ 489129794Stackerman/* OP_CODE == 10, Read operation */ 490129794Stackerman/* OP_CODE == 11, Read, auto increment, New Protocol */ 491129794Stackerman#define IXGB_MSCA_ADDR_CYCLE 0x00000000 492129794Stackerman#define IXGB_MSCA_WRITE 0x04000000 493129794Stackerman#define IXGB_MSCA_READ 0x08000000 494129794Stackerman#define IXGB_MSCA_READ_AUTOINC 0x0C000000 495129794Stackerman#define IXGB_MSCA_OP_CODE_SHIFT 26 496129794Stackerman#define IXGB_MSCA_ST_CODE_MASK 0x30000000 497129794Stackerman/* ST_CODE == 00, New Protocol */ 498129794Stackerman/* ST_CODE == 01, Old Protocol */ 499129794Stackerman#define IXGB_MSCA_NEW_PROTOCOL 0x00000000 500129794Stackerman#define IXGB_MSCA_OLD_PROTOCOL 0x10000000 501129794Stackerman#define IXGB_MSCA_ST_CODE_SHIFT 28 502129794Stackerman/* Initiate command, self-clearing when command completes */ 503129794Stackerman#define IXGB_MSCA_MDI_COMMAND 0x40000000 504129794Stackerman/*MDI In Progress Enable. */ 505129794Stackerman#define IXGB_MSCA_MDI_IN_PROG_EN 0x80000000 506129794Stackerman 507129794Stackerman/* MSRWD bit masks */ 508129794Stackerman#define IXGB_MSRWD_WRITE_DATA_MASK 0x0000FFFF 509129794Stackerman#define IXGB_MSRWD_WRITE_DATA_SHIFT 0 510129794Stackerman#define IXGB_MSRWD_READ_DATA_MASK 0xFFFF0000 511129794Stackerman#define IXGB_MSRWD_READ_DATA_SHIFT 16 512129794Stackerman 513129794Stackerman/* Definitions for the optics devices on the MDIO bus. */ 514129794Stackerman#define IXGB_PHY_ADDRESS 0x0 /* Single PHY, multiple "Devices" */ 515129794Stackerman 516129794Stackerman/* Standard five-bit Device IDs. See IEEE 802.3ae, clause 45 */ 517129794Stackerman#define MDIO_PMA_PMD_DID 0x01 518129794Stackerman#define MDIO_WIS_DID 0x02 519129794Stackerman#define MDIO_PCS_DID 0x03 520129794Stackerman#define MDIO_XGXS_DID 0x04 521129794Stackerman 522129794Stackerman/* Standard PMA/PMD registers and bit definitions. */ 523129794Stackerman/* Note: This is a very limited set of definitions, */ 524129794Stackerman/* only implemented features are defined. */ 525129794Stackerman#define MDIO_PMA_PMD_CR1 0x0000 526129794Stackerman#define MDIO_PMA_PMD_CR1_RESET 0x8000 527129794Stackerman 528129794Stackerman#define MDIO_PMA_PMD_XPAK_VENDOR_NAME 0x803A /* XPAK/XENPAK devices only */ 529129794Stackerman 530129794Stackerman/* Vendor-specific MDIO registers */ 531129794Stackerman#define G6XXX_PMA_PMD_VS1 0xC001 /* Vendor-specific register */ 532129794Stackerman#define G6XXX_XGXS_XAUI_VS2 0x18 /* Vendor-specific register */ 533129794Stackerman 534129794Stackerman#define G6XXX_PMA_PMD_VS1_PLL_RESET 0x80 535129794Stackerman#define G6XXX_PMA_PMD_VS1_REMOVE_PLL_RESET 0x00 536129794Stackerman#define G6XXX_XGXS_XAUI_VS2_INPUT_MASK 0x0F /* XAUI lanes synchronized */ 537129794Stackerman 538129794Stackerman/* Layout of a single receive descriptor. The controller assumes that this 539129794Stackerman * structure is packed into 16 bytes, which is a safe assumption with most 540129794Stackerman * compilers. However, some compilers may insert padding between the fields, 541129794Stackerman * in which case the structure must be packed in some compiler-specific 542129794Stackerman * manner. */ 543129794Stackermanstruct ixgb_rx_desc { 544129794Stackerman uint64_t buff_addr; 545129794Stackerman uint16_t length; 546129794Stackerman uint16_t reserved; 547129794Stackerman uint8_t status; 548129794Stackerman uint8_t errors; 549129794Stackerman uint16_t special; 550129794Stackerman}; 551129794Stackerman 552129794Stackerman#define IXGB_RX_DESC_STATUS_DD 0x01 553129794Stackerman#define IXGB_RX_DESC_STATUS_EOP 0x02 554129794Stackerman#define IXGB_RX_DESC_STATUS_IXSM 0x04 555129794Stackerman#define IXGB_RX_DESC_STATUS_VP 0x08 556129794Stackerman#define IXGB_RX_DESC_STATUS_TCPCS 0x20 557129794Stackerman#define IXGB_RX_DESC_STATUS_IPCS 0x40 558129794Stackerman#define IXGB_RX_DESC_STATUS_PIF 0x80 559129794Stackerman 560129794Stackerman#define IXGB_RX_DESC_ERRORS_CE 0x01 561129794Stackerman#define IXGB_RX_DESC_ERRORS_SE 0x02 562129794Stackerman#define IXGB_RX_DESC_ERRORS_P 0x08 563129794Stackerman#define IXGB_RX_DESC_ERRORS_TCPE 0x20 564129794Stackerman#define IXGB_RX_DESC_ERRORS_IPE 0x40 565129794Stackerman#define IXGB_RX_DESC_ERRORS_RXE 0x80 566129794Stackerman 567129794Stackerman#define IXGB_RX_DESC_SPECIAL_VLAN_MASK 0x0FFF /* VLAN ID is in lower 12 bits */ 568129794Stackerman#define IXGB_RX_DESC_SPECIAL_PRI_MASK 0xE000 /* Priority is in upper 3 bits */ 569129794Stackerman#define IXGB_RX_DESC_SPECIAL_PRI_SHIFT 0x000D /* Priority is in upper 3 of 16 */ 570129794Stackerman 571129794Stackerman/* Layout of a single transmit descriptor. The controller assumes that this 572129794Stackerman * structure is packed into 16 bytes, which is a safe assumption with most 573129794Stackerman * compilers. However, some compilers may insert padding between the fields, 574129794Stackerman * in which case the structure must be packed in some compiler-specific 575129794Stackerman * manner. */ 576129794Stackermanstruct ixgb_tx_desc { 577129794Stackerman uint64_t buff_addr; 578129794Stackerman uint32_t cmd_type_len; 579129794Stackerman uint8_t status; 580129794Stackerman uint8_t popts; 581129794Stackerman uint16_t vlan; 582129794Stackerman}; 583129794Stackerman 584129794Stackerman#define IXGB_TX_DESC_LENGTH_MASK 0x000FFFFF 585129794Stackerman#define IXGB_TX_DESC_TYPE_MASK 0x00F00000 586129794Stackerman#define IXGB_TX_DESC_TYPE_SHIFT 20 587129794Stackerman#define IXGB_TX_DESC_CMD_MASK 0xFF000000 588129794Stackerman#define IXGB_TX_DESC_CMD_SHIFT 24 589129794Stackerman#define IXGB_TX_DESC_CMD_EOP 0x01000000 590129794Stackerman#define IXGB_TX_DESC_CMD_TSE 0x04000000 591129794Stackerman#define IXGB_TX_DESC_CMD_RS 0x08000000 592129794Stackerman#define IXGB_TX_DESC_CMD_VLE 0x40000000 593129794Stackerman#define IXGB_TX_DESC_CMD_IDE 0x80000000 594129794Stackerman 595129794Stackerman#define IXGB_TX_DESC_TYPE 0x00100000 596129794Stackerman 597129794Stackerman#define IXGB_TX_DESC_STATUS_DD 0x01 598129794Stackerman 599129794Stackerman#define IXGB_TX_DESC_POPTS_IXSM 0x01 600129794Stackerman#define IXGB_TX_DESC_POPTS_TXSM 0x02 601129794Stackerman#define IXGB_TX_DESC_SPECIAL_PRI_SHIFT IXGB_RX_DESC_SPECIAL_PRI_SHIFT /* Priority is in upper 3 of 16 */ 602129794Stackerman 603129794Stackermanstruct ixgb_context_desc { 604129794Stackerman uint8_t ipcss; 605129794Stackerman uint8_t ipcso; 606129794Stackerman uint16_t ipcse; 607129794Stackerman uint8_t tucss; 608129794Stackerman uint8_t tucso; 609129794Stackerman uint16_t tucse; 610129794Stackerman uint32_t cmd_type_len; 611129794Stackerman uint8_t status; 612129794Stackerman uint8_t hdr_len; 613129794Stackerman uint16_t mss; 614129794Stackerman}; 615129794Stackerman 616129794Stackerman#define IXGB_CONTEXT_DESC_CMD_TCP 0x01000000 617129794Stackerman#define IXGB_CONTEXT_DESC_CMD_IP 0x02000000 618129794Stackerman#define IXGB_CONTEXT_DESC_CMD_TSE 0x04000000 619129794Stackerman#define IXGB_CONTEXT_DESC_CMD_RS 0x08000000 620129794Stackerman#define IXGB_CONTEXT_DESC_CMD_IDE 0x80000000 621129794Stackerman 622129794Stackerman#define IXGB_CONTEXT_DESC_TYPE 0x00000000 623129794Stackerman 624129794Stackerman#define IXGB_CONTEXT_DESC_STATUS_DD 0x01 625129794Stackerman 626129794Stackerman/* Filters */ 627129794Stackerman#define IXGB_RAR_ENTRIES 16 /* Number of entries in Rx Address array */ 628129794Stackerman#define IXGB_MC_TBL_SIZE 128 /* Multicast Filter Table (4096 bits) */ 629129794Stackerman#define IXGB_VLAN_FILTER_TBL_SIZE 128 /* VLAN Filter Table (4096 bits) */ 630129794Stackerman 631129794Stackerman#define IXGB_MEMORY_REGISTER_BASE_ADDRESS 0 632129794Stackerman#define ENET_HEADER_SIZE 14 633129794Stackerman#define ENET_FCS_LENGTH 4 634129794Stackerman#define IXGB_MAX_NUM_MULTICAST_ADDRESSES 128 635129794Stackerman#define IXGB_MIN_ENET_FRAME_SIZE_WITHOUT_FCS 60 636129794Stackerman#define IXGB_MAX_ENET_FRAME_SIZE_WITHOUT_FCS 1514 637129794Stackerman#define IXGB_MAX_JUMBO_FRAME_SIZE 0x3F00 638129794Stackerman 639129794Stackerman/* Phy Addresses */ 640129794Stackerman#define IXGB_OPTICAL_PHY_ADDR 0x0 /* Optical Module phy address*/ 641129794Stackerman#define IXGB_XAUII_PHY_ADDR 0x1 /* Xauii transceiver phy address*/ 642129794Stackerman#define IXGB_DIAG_PHY_ADDR 0x1F/* Diagnostic Device phy address*/ 643129794Stackerman 644129794Stackerman/* This structure takes a 64k flash and maps it for identification commands */ 645129794Stackermanstruct ixgb_flash_buffer { 646129794Stackerman uint8_t manufacturer_id; 647129794Stackerman uint8_t device_id; 648129794Stackerman uint8_t filler1[0x2AA8]; 649129794Stackerman uint8_t cmd2; 650129794Stackerman uint8_t filler2[0x2AAA]; 651129794Stackerman uint8_t cmd1; 652129794Stackerman uint8_t filler3[0xAAAA]; 653129794Stackerman}; 654129794Stackerman 655129794Stackerman/* 656129794Stackerman * This is a little-endian specific check. 657129794Stackerman */ 658129794Stackerman#define IS_MULTICAST(Address) \ 659129794Stackerman (boolean_t)(((uint8_t *)(Address))[0] & ((uint8_t)0x01)) 660129794Stackerman 661129794Stackerman 662129794Stackerman/* 663129794Stackerman * Check whether an address is broadcast. 664129794Stackerman */ 665129794Stackerman#define IS_BROADCAST(Address) \ 666129794Stackerman ((((uint8_t *)(Address))[0] == ((uint8_t)0xff)) && (((uint8_t *)(Address))[1] == ((uint8_t)0xff))) 667129794Stackerman 668129794Stackerman/* Flow control parameters */ 669129794Stackermanstruct ixgb_fc { 670129794Stackerman uint32_t high_water; /* Flow Control High-water */ 671129794Stackerman uint32_t low_water; /* Flow Control Low-water */ 672129794Stackerman uint16_t pause_time; /* Flow Control Pause timer */ 673129794Stackerman boolean_t send_xon; /* Flow control send XON */ 674129794Stackerman ixgb_fc_type type; /* Type of flow control */ 675129794Stackerman}; 676129794Stackerman 677129794Stackerman/* The historical defaults for the flow control values are given below. */ 678129794Stackerman#define FC_DEFAULT_HI_THRESH (0x8000) /* 32KB */ 679129794Stackerman#define FC_DEFAULT_LO_THRESH (0x4000) /* 16KB */ 680129794Stackerman#define FC_DEFAULT_TX_TIMER (0x100) /* ~130 us */ 681129794Stackerman 682129794Stackerman/* Phy definitions */ 683129794Stackerman#define IXGB_MAX_PHY_REG_ADDRESS 0xFFFF 684129794Stackerman#define IXGB_MAX_PHY_ADDRESS 31 685129794Stackerman#define IXGB_MAX_PHY_DEV_TYPE 31 686129794Stackerman 687129794Stackerman/* Bus parameters */ 688129794Stackermanstruct ixgb_bus { 689129794Stackerman ixgb_bus_speed speed; 690129794Stackerman ixgb_bus_width width; 691129794Stackerman ixgb_bus_type type; 692129794Stackerman}; 693129794Stackerman 694129794Stackermanstruct ixgb_hw { 695129794Stackerman uint8_t *hw_addr; /* Base Address of the hardware */ 696129794Stackerman void *back; /* Pointer to OS-dependent struct */ 697129794Stackerman struct ixgb_fc fc; /* Flow control parameters */ 698129794Stackerman struct ixgb_bus bus; /* Bus parameters */ 699129794Stackerman uint32_t phy_id; /* Phy Identifier */ 700129794Stackerman uint32_t phy_addr; /* XGMII address of Phy */ 701129794Stackerman ixgb_mac_type mac_type; /* Identifier for MAC controller */ 702129794Stackerman ixgb_phy_type phy_type; /* Transceiver/phy identifier */ 703129794Stackerman uint32_t max_frame_size; /* Maximum frame size supported */ 704129794Stackerman uint32_t mc_filter_type; /* Multicast filter hash type */ 705129794Stackerman uint32_t num_mc_addrs; /* Number of current Multicast addrs*/ 706129794Stackerman uint8_t curr_mac_addr[IXGB_ETH_LENGTH_OF_ADDRESS]; /* Individual address currently programmed in MAC */ 707129794Stackerman uint32_t num_tx_desc; /* Number of Transmit descriptors */ 708129794Stackerman uint32_t num_rx_desc; /* Number of Receive descriptors */ 709129794Stackerman uint32_t rx_buffer_size; /* Size of Receive buffer */ 710129794Stackerman boolean_t link_up; /* TRUE if link is valid */ 711129794Stackerman boolean_t adapter_stopped; /* State of adapter */ 712129794Stackerman uint16_t device_id; /* device id from PCI configuration space */ 713129794Stackerman uint16_t vendor_id; /* vendor id from PCI configuration space */ 714129794Stackerman uint8_t revision_id; /* revision id from PCI configuration space */ 715129794Stackerman uint16_t subsystem_vendor_id;/* subsystem vendor id from PCI configuration space */ 716129794Stackerman uint16_t subsystem_id; /* subsystem id from PCI configuration space */ 717129794Stackerman uint32_t bar0; /* Base Address registers */ 718129794Stackerman uint32_t bar1; 719129794Stackerman uint32_t bar2; 720129794Stackerman uint32_t bar3; 721129794Stackerman uint16_t pci_cmd_word; /* PCI command register id from PCI configuration space */ 722129794Stackerman uint16_t eeprom[IXGB_EEPROM_SIZE]; /* EEPROM contents read at init time */ 723129794Stackerman unsigned long io_base; /* Our I/O mapped location */ 724129794Stackerman uint32_t lastLFC; 725129794Stackerman uint32_t lastRFC; 726129794Stackerman}; 727129794Stackerman 728129794Stackerman/* Statistics reported by the hardware */ 729129794Stackermanstruct ixgb_hw_stats { 730129794Stackerman uint64_t tprl; 731129794Stackerman uint64_t tprh; 732129794Stackerman uint64_t gprcl; 733129794Stackerman uint64_t gprch; 734129794Stackerman uint64_t bprcl; 735129794Stackerman uint64_t bprch; 736129794Stackerman uint64_t mprcl; 737129794Stackerman uint64_t mprch; 738129794Stackerman uint64_t uprcl; 739129794Stackerman uint64_t uprch; 740129794Stackerman uint64_t vprcl; 741129794Stackerman uint64_t vprch; 742129794Stackerman uint64_t jprcl; 743129794Stackerman uint64_t jprch; 744129794Stackerman uint64_t gorcl; 745129794Stackerman uint64_t gorch; 746129794Stackerman uint64_t torl; 747129794Stackerman uint64_t torh; 748129794Stackerman uint64_t rnbc; 749129794Stackerman uint64_t ruc; 750129794Stackerman uint64_t roc; 751129794Stackerman uint64_t rlec; 752129794Stackerman uint64_t crcerrs; 753129794Stackerman uint64_t icbc; 754129794Stackerman uint64_t ecbc; 755129794Stackerman uint64_t mpc; 756129794Stackerman uint64_t tptl; 757129794Stackerman uint64_t tpth; 758129794Stackerman uint64_t gptcl; 759129794Stackerman uint64_t gptch; 760129794Stackerman uint64_t bptcl; 761129794Stackerman uint64_t bptch; 762129794Stackerman uint64_t mptcl; 763129794Stackerman uint64_t mptch; 764129794Stackerman uint64_t uptcl; 765129794Stackerman uint64_t uptch; 766129794Stackerman uint64_t vptcl; 767129794Stackerman uint64_t vptch; 768129794Stackerman uint64_t jptcl; 769129794Stackerman uint64_t jptch; 770129794Stackerman uint64_t gotcl; 771129794Stackerman uint64_t gotch; 772129794Stackerman uint64_t totl; 773129794Stackerman uint64_t toth; 774129794Stackerman uint64_t dc; 775129794Stackerman uint64_t plt64c; 776129794Stackerman uint64_t tsctc; 777129794Stackerman uint64_t tsctfc; 778129794Stackerman uint64_t ibic; 779129794Stackerman uint64_t rfc; 780129794Stackerman uint64_t lfc; 781129794Stackerman uint64_t pfrc; 782129794Stackerman uint64_t pftc; 783129794Stackerman uint64_t mcfrc; 784129794Stackerman uint64_t mcftc; 785129794Stackerman uint64_t xonrxc; 786129794Stackerman uint64_t xontxc; 787129794Stackerman uint64_t xoffrxc; 788129794Stackerman uint64_t xofftxc; 789129794Stackerman uint64_t rjc; 790129794Stackerman}; 791129794Stackerman 792129794Stackerman/* Function Prototypes */ 793129794Stackermanextern boolean_t ixgb_adapter_stop(struct ixgb_hw *hw); 794129794Stackermanextern boolean_t ixgb_init_hw(struct ixgb_hw *hw); 795129794Stackermanextern boolean_t ixgb_adapter_start(struct ixgb_hw *hw); 796129794Stackermanextern void ixgb_init_rx_addrs(struct ixgb_hw *hw); 797129794Stackermanextern void ixgb_check_for_link(struct ixgb_hw *hw); 798129794Stackermanextern boolean_t ixgb_check_for_bad_link(struct ixgb_hw *hw); 799129794Stackermanextern boolean_t ixgb_setup_fc(struct ixgb_hw *hw); 800129794Stackermanextern void ixgb_clear_hw_cntrs(struct ixgb_hw *hw); 801129794Stackermanextern boolean_t mac_addr_valid(uint8_t *mac_addr); 802129794Stackerman 803129794Stackermanextern uint16_t ixgb_read_phy_reg(struct ixgb_hw *hw, 804129794Stackerman uint32_t reg_addr, 805129794Stackerman uint32_t phy_addr, 806129794Stackerman uint32_t device_type); 807129794Stackerman 808129794Stackermanextern void ixgb_write_phy_reg(struct ixgb_hw *hw, 809129794Stackerman uint32_t reg_addr, 810129794Stackerman uint32_t phy_addr, 811129794Stackerman uint32_t device_type, 812129794Stackerman uint16_t data); 813129794Stackerman 814129794Stackermanextern void ixgb_rar_set(struct ixgb_hw *hw, 815129794Stackerman uint8_t *addr, 816129794Stackerman uint32_t index); 817129794Stackerman 818129794Stackerman 819129794Stackerman/* Filters (multicast, vlan, receive) */ 820129794Stackermanextern void ixgb_mc_addr_list_update(struct ixgb_hw *hw, 821129794Stackerman uint8_t * mc_addr_list, 822129794Stackerman uint32_t mc_addr_count, 823129794Stackerman uint32_t pad); 824129794Stackerman 825129794Stackerman/* Vfta functions */ 826129794Stackermanextern void ixgb_write_vfta(struct ixgb_hw *hw, 827129794Stackerman uint32_t offset, 828129794Stackerman uint32_t value); 829129794Stackerman 830129794Stackermanextern void ixgb_clear_vfta(struct ixgb_hw *hw); 831129794Stackerman 832129794Stackerman 833129794Stackerman/* Access functions to eeprom data */ 834129794Stackermanvoid ixgb_get_ee_mac_addr(struct ixgb_hw *hw, uint8_t *mac_addr); 835129794Stackermanuint16_t ixgb_get_ee_compatibility(struct ixgb_hw *hw); 836129794Stackermanuint32_t ixgb_get_ee_pba_number(struct ixgb_hw *hw); 837129794Stackermanuint16_t ixgb_get_ee_init_ctrl_reg_1(struct ixgb_hw *hw); 838129794Stackermanuint16_t ixgb_get_ee_init_ctrl_reg_2(struct ixgb_hw *hw); 839129794Stackermanuint16_t ixgb_get_ee_subsystem_id(struct ixgb_hw *hw); 840129794Stackermanuint16_t ixgb_get_ee_subvendor_id(struct ixgb_hw *hw); 841129794Stackermanuint16_t ixgb_get_ee_device_id(struct ixgb_hw *hw); 842129794Stackermanuint16_t ixgb_get_ee_vendor_id(struct ixgb_hw *hw); 843129794Stackermanuint16_t ixgb_get_ee_swdpins_reg(struct ixgb_hw *hw); 844129794Stackermanuint8_t ixgb_get_ee_d3_power(struct ixgb_hw *hw); 845129794Stackermanuint8_t ixgb_get_ee_d0_power(struct ixgb_hw *hw); 846129794Stackermanboolean_t ixgb_get_eeprom_data(struct ixgb_hw *hw); 847129794Stackermanuint16_t ixgb_get_eeprom_word(struct ixgb_hw *hw, uint16_t index); 848129794Stackerman 849129794Stackerman/* Everything else */ 850129794Stackermanvoid ixgb_led_on(struct ixgb_hw *hw); 851129794Stackermanvoid ixgb_led_off(struct ixgb_hw *hw); 852129794Stackermanvoid ixgb_write_pci_cfg(struct ixgb_hw *hw, 853129794Stackerman uint32_t reg, 854129794Stackerman uint16_t * value); 855129794Stackerman 856129794Stackerman 857129794Stackerman#endif /* _IXGB_HW_H_ */ 858